Breakpoint debugging method, breakpoint debugging apparatus, and readable medium

Abstract

The present disclosure provides a breakpoint debugging method, comprising: performing trigger checking for each cycle, to determine trigger matching information of the cycle, the trigger matching information being information of a trigger matching an instruction; performing priority arbitration on the trigger matching information of different cycles, to obtain information of a target trigger; and, when an instruction matching the target trigger reaches a submission stage and it is determined that the target trigger is triggered, on the basis of the information of the target trigger, determining an execution action, so that a processing core executes the execution action.

Description

Breakpoint debugging method, breakpoint debugging device and readable medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to Chinese patent application 202311455879.4 filed with the State Intellectual Property Office of China on November 3, 2023, and the disclosure of this Chinese patent application is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to the field of computer technology, and in particular to a breakpoint debugging method, a breakpoint debugging device, and a readable medium. Background Art

[0004] The RISCV instruction set architecture has technical characteristics such as simplicity, modularity, scalability and open source. As an emerging instruction set, the RISCV instruction set can build microprocessors suitable for any field through the combination and expansion of limited instruction sets.

[0005] Due to the high licensing fees and royalties, as well as technology embargoes, of mainstream instruction sets like ARM, numerous research institutions, tech giants, and startups have joined the competition and development of the RISC-V instruction set, seeking to break the monopoly of ARM and other mainstream instruction sets in the mobile and server sectors. This has led to the emergence of numerous commercial IP and SoC (System on Chip) products based on the RISC-V core. Hardware breakpoints and hardware watchpoints are essential features and debugging tools within the RISC-V core, and must be implemented at the hardware level.

[0006] Summary of the Invention

[0007] The present disclosure provides a breakpoint debugging method, a breakpoint debugging device, and a readable medium.

[0008] In a first aspect, an embodiment of the present disclosure provides a breakpoint debugging method, comprising:

[0009] Perform trigger detection for each cycle to determine trigger matching information for the cycle, where the trigger matching information is information about the trigger that matches the instruction;

[0010] Performing priority arbitration on the trigger matching information of different cycles to obtain information of a target trigger;

[0011] When the instruction matching the target trigger reaches the commit stage and it is determined that the target trigger is triggered, an execution action is determined according to information of the target trigger, so that the processing core executes the execution action.

[0012] In another aspect, the present disclosure further provides a breakpoint debugging device, comprising:

[0013] A trigger detection module, configured to perform trigger detection on each cycle and determine trigger matching information of the cycle, wherein the trigger matching information is information of the trigger matching the instruction;

[0014] A trigger detection information synchronization module is used to perform priority arbitration on the trigger matching information of different periods to obtain information of the target trigger;

[0015] The trigger submission module is used to determine an execution action according to the information of the target trigger when the instruction matched by the target trigger reaches the submission stage and the target trigger is determined to be triggered, so that the processing core can execute the execution action.

[0016] On the other hand, an embodiment of the present disclosure also provides a breakpoint debugging device, comprising: one or more processors; a storage device on which one or more programs are stored; when the one or more programs are executed by the one or more processors, the one or more processors implement the breakpoint debugging method as described above; one or more I / O interfaces, connected between the processor and the storage device, configured to implement information interaction between the processor and the storage device.

[0017] On the other hand, an embodiment of the present disclosure further provides a computer-readable medium having a computer program stored thereon, wherein the program implements the breakpoint debugging method as described above when executed.

[0018] The breakpoint debugging method provided by the embodiment of the present disclosure includes: performing trigger detection on each cycle to determine the trigger matching information of the cycle, where the trigger matching information is the information of the trigger matching the instruction; performing priority arbitration on the trigger matching information of different cycles to obtain the information of the target trigger; when the instruction matching the target trigger reaches the submission stage and it is determined that the target trigger is triggered, determining the execution action according to the information of the target trigger, so that the processing core can execute the execution action; the breakpoint debugging method of the embodiment of the present disclosure provides an implementation scheme for RISCV hardware breakpoints and hardware observation points, wherein the trigger detection logic and the trigger detection information synchronization logic have a low degree of coupling with the mainstream pipeline. When the trigger scheme is expanded, only a small modification needs to be made to the trigger detection logic and the trigger detection information synchronization logic while keeping them unchanged; and the trigger submission logic, which has a high degree of coupling with the mainstream pipeline, has no correlation with the type and number of triggers, and the embodiment of the present disclosure is based on a superscalar out-of-order pipeline design, has good scalability, and can reduce the difficulty of secondary development for developers on different microarchitectures. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] FIG1 is a schematic diagram of a process of a breakpoint debugging method according to an embodiment of the present disclosure;

[0020] FIG2 is a schematic diagram showing the principle of a breakpoint debugging method according to an embodiment of the present disclosure;

[0021] FIG3 is a schematic diagram of instruction address trigger detection according to an embodiment of the present disclosure;

[0022] FIG4 is a schematic diagram of memory access address trigger detection according to an embodiment of the present disclosure;

[0023] FIG5 is a schematic structural diagram of a breakpoint debugging device according to an embodiment of the present disclosure;

[0024] FIG6 is a schematic structural diagram of a breakpoint debugging device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] Example embodiments will be described more fully hereinafter with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art.

[0026] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0027] The terms used herein are used only to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements, and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof is not excluded.

[0028] The embodiments described herein may be described with reference to plan views and / or cross-sectional views, with the aid of idealized schematic diagrams of the present disclosure. Thus, the example illustrations may be modified based on manufacturing techniques and / or tolerances. Therefore, the embodiments are not limited to the embodiments shown in the accompanying drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the accompanying drawings are schematic in nature, and the shapes of the regions shown in the drawings illustrate specific shapes of the regions of the elements, but are not intended to be limiting.

[0029] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined as such herein.

[0030] As an emerging instruction set architecture, the RISCV instruction set is still evolving and developing. Currently, its core commercial applications are primarily concentrated in areas such as the Internet of Things and artificial intelligence. Currently, RISCV hardware breakpoints and watchpoints are mostly designed based on sequential pipelines, tightly coupled with the main pipeline. These implementations are relatively simple, lacking trigger chains and other features. These solutions lack scalability and are not considered valuable references. Furthermore, there are currently no RISCV hardware breakpoint and watchpoint debugging solutions based on superscalar, out-of-order main pipelines.

[0031] An embodiment of the present disclosure provides a breakpoint debugging method, which is applied to a breakpoint debugging device. The breakpoint debugging device may include a trigger detection (Trigger Match) module, a trigger detection information synchronization (Trigger Match Information Synchronization / Trig Syndr) module, a trigger control status register (Trigger CSR) and a trigger commit (Trigger Commit) module.

[0032] The trigger detection module includes the instruction address trigger detection (PC Trigger Match / PC Trig Match) submodule and the memory access address trigger detection (LS Trigger Match / LS Trigger Match) submodule, which perform trigger detection in the instruction decoding stage and the memory access execution stage respectively.

[0033] The trigger detection information synchronization module synchronizes and caches different triggers that match the same instruction or triggers that match different instructions, collected at different pipeline stages / time points, and caches the information of the oldest and second-oldest triggers (chains) in the main pipeline. The oldest trigger (chain) in the main pipeline means that in a superscalar out-of-order processor, the life cycle of an instruction ends at commit, that is, it will go through the processes of instruction fetch, decoding, renaming, distribution, emission, execution, and commit. Therefore, in the main pipeline, there will be multiple instructions in their life cycle. Among these instructions, triggers (chains) will match on some instructions. The triggers (chains) that match the instructions are distinguished by the age information of the instructions. That is, among the instructions that match the trigger (chain), the trigger (chain) that matches the oldest instruction is called the oldest trigger (chain).

[0034] The trigger control status register primarily implements read and write operations on the trigger-related status register, sending its value in real time to the two trigger detection modules. Depending on the type of trigger being implemented, the control status register implementation will vary. This disclosed embodiment involves the trigger select (tselect) register, trigger data1 (tdata1) register, and trigger data1 (tdata2) register.

[0035] During the instruction submission phase, the trigger submission module determines whether the trigger is finally triggered and the execution action after the trigger is triggered based on the priority between the trigger and the abnormal event in the processor core.

[0036] Figure 1 is a flow chart of a breakpoint debugging method according to an embodiment of the present disclosure, and Figure 2 is a schematic diagram of the principle of the breakpoint debugging method according to an embodiment of the present disclosure. As shown in Figure 2, the present disclosure provides a design scheme for RISC-V hardware breakpoints and hardware watchpoints based on a superscalar out-of-order pipeline architecture with three main pipelines and two memory access pipelines. Figure 2 only illustrates the pipeline stages related to trigger implementation, namely the decode, rename, dispatch, issue, execute (only the memory access execution unit (LSU) is shown), and the instruction commit and retire (IRU) pipeline stages. Each pipeline stage may include logic for processing instruction information, including information about whether the instruction has a trigger hit, such as Trig Logic 1 in the rename pipeline stage and Trig Logic 2 in the IRU pipeline stage. Trig Logic 1 is primarily responsible for processing instruction address trigger detection information and sending it to the dispatch pipeline stage. The dispatch pipeline stage records the information processed by Trig Logic 1 along with other instruction information into the reorder cache. Trig logic 2 is primarily used to flush and stall the memory access pipeline based on memory address trigger detection information from load instructions, store instructions, atomic operation instructions, and instruction address trigger detection information from the reorder cache. This disclosed embodiment uses the implementation of four triggers as an example to illustrate its design principles.

[0037] 1 and 2 , the breakpoint debugging method includes steps S11 to S13 .

[0038] In step S11 , trigger detection is performed for each cycle to determine trigger matching information of the cycle, wherein the trigger matching information is information of a trigger that matches an instruction.

[0039] Trigger match information varies for different cycles. This information can include instruction address trigger match information and memory address trigger match information. The value of the trigger control status register (Trig CSR) is output to the trigger detection module in real time. In the program flow executed in the processor core, the instruction address trigger detection submodule matches the instruction address on the multi-issue channel during the instruction decoding phase and outputs instruction address trigger match information. The memory address trigger detection submodule matches the memory access address on the first stage of the memory access pipeline and outputs memory address trigger match information.

[0040] In step S12, priority arbitration is performed on trigger matching information of different cycles to obtain information of the target trigger.

[0041] During the time interval from trigger matching to triggering, the trigger matching information needs to be cached. For the instruction address trigger matching information output by the instruction address trigger detection submodule, it needs to flow along with the main pipeline to the distribution stage before it is output to the trigger detection information synchronization module for arbitration and storage. For the memory access address trigger matching information output by the memory access address trigger detection submodule, it is directly output to the trigger detection information synchronization module at the second stage of the memory access pipeline for arbitration and storage. It should be noted that in addition to the cached trigger information, the trigger detection information synchronization module also stores the matching instruction address and the reordering cache number corresponding to the instruction.

[0042] In step S13 , when the instruction matching the target trigger reaches the commit stage and it is determined that the target trigger is triggered, an execution action is determined according to information of the target trigger, so that the processing core can execute the execution action.

[0043] When an instruction matching a target trigger reaches the commit stage and the target trigger is determined to have been triggered, the first submodule of the trigger commit module (Trig Commit1) determines whether the target trigger has ultimately been triggered based on the priority of the target trigger and other exceptions associated with the instruction. If it is determined to have been triggered, the target trigger information, such as the instruction address that matched the target trigger and the configured execution action, is output to the second submodule of the trigger commit module (Trig Commit2).

[0044] After the trigger submission module determines that the target trigger has been triggered, the processor core determines the action to be taken based on the action field in the trigger control status register. If the action field is 1, the processor core enters debug mode. If the action field is 0, the processor core enters the corresponding exception service routine.

[0045] It should be noted that, before step S11, the following steps need to be performed: initialization, processor entering debug mode, configuring trigger CSR, processor returning from debug and executing program flow, etc.

[0046] (1) Initialization

[0047] Initialization refers to the system initialization of the processor core, which involves configuring system registers, loading programs and data, and so on, so that the processor core can begin executing programs. This initialization step also includes initializing the registers and storage queues used in the hardware breakpoint and watchpoint schemes described above. For example, it initializes the two sets of registers in the trigger detection information synchronization module (which can be viewed as queues with a depth of 2) to 0 and initializes the configuration enable field of the trigger control status register to invalid.

[0048] (2) The processor enters debug mode

[0049] The debugger initiates a debug halt request through the debug module. The processor core responds to the debug halt request after draining the pipeline and enters debug mode.

[0050] (3)Configure trigger CSR

[0051] The debugger configures the trigger control status register in the processor core through the debug module, and configures the trigger select (tselect) register, the trigger data1 (tdata1) register, and the trigger data1 (tdata2) register in sequence.

[0052] (4) The processor returns from debugging and executes the program flow

[0053] The debugger initiates a resume request to the processor core through the debug module. The processor core returns from the debug mode to the previous execution mode and resumes to the previous debug interrupt site or starts from the instruction fetch address specified by the debugger and continues to execute the program flow.

[0054] The breakpoint debugging method provided by the embodiment of the present disclosure includes: performing trigger detection for each cycle to determine the trigger matching information of the cycle, where the trigger matching information is the information of the trigger that matches the instruction; performing priority arbitration on the trigger matching information of different cycles to obtain the information of the target trigger; when the instruction that matches the target trigger reaches the submission stage and it is determined that the target trigger is triggered, determining the execution action based on the information of the target trigger, so that the processing core can execute the execution action. The breakpoint debugging method of the embodiment of the present disclosure provides an implementation scheme for RISCV hardware breakpoints and hardware observation points, wherein the trigger detection logic and the trigger detection information synchronization logic are less coupled with the mainstream pipeline. When the trigger scheme is expanded, only a small modification needs to be made to the trigger detection logic and the trigger detection information synchronization logic while the trigger detection logic and the trigger detection information synchronization logic remain unchanged. The trigger submission logic, which has a greater degree of coupling with the mainstream pipeline, is not related to the type and number of triggers. In addition, the embodiment of the present disclosure is based on a superscalar out-of-order pipeline design, has good scalability, and can reduce the difficulty of secondary development for developers on different microarchitectures.

[0055] In some embodiments, a trigger detection is performed for each cycle to determine the trigger matching information of the cycle (i.e., step S11), including the following steps: for each first cycle, an instruction address trigger detection is performed in the instruction decoding stage to determine the instruction address trigger matching information of the first cycle; for each second cycle, a memory access address trigger detection is performed in the memory access execution stage to determine the memory access address trigger matching information of the second cycle.

[0056] In some embodiments, the instruction address trigger matching information of the first cycle may include information about the instruction address trigger corresponding to the oldest instruction matched with the trigger in the first cycle, or information about the instruction address trigger corresponding to the oldest instruction matched with the trigger in the first cycle and information about the instruction address trigger corresponding to the second oldest instruction matched with the trigger in the first cycle. The memory address trigger matching information of the second cycle may include information about the memory address trigger corresponding to the oldest instruction matched with the trigger in the second cycle, or information about the memory address trigger corresponding to the oldest instruction matched with the trigger in the second cycle and information about the memory address trigger corresponding to the second oldest instruction matched with the trigger in the second cycle.

[0057] In some embodiments, determining instruction address trigger matching information for the first cycle includes the following steps: determining instruction address trigger matching information for the first cycle based on a trigger chain membership attribute of the instruction address trigger and the age and type of the instruction in the first cycle. In the disclosed embodiments, the trigger chain membership attribute is used to indicate whether the trigger is a trigger in a trigger chain, that is, whether the trigger belongs to the trigger chain.

[0058] The following describes in detail various situations of determining instruction address trigger matching information of the first cycle in conjunction with Figure 3. Figure 3 is a schematic diagram of instruction address trigger detection according to an embodiment of the present disclosure.

[0059] The instruction address trigger detection (PC Trigger Match) submodule is located in the same pipeline stage as the decode module. In the instruction address trigger detection submodule, during the first cycle, each trigger is compared with the instruction on each issue channel of the processor core. The instruction address trigger match information for the first cycle is determined and output.

[0060] As shown in FIG3 , determining the instruction address trigger matching information of the first cycle includes the following situations.

[0061] (1) In the case where the trigger that matches the instruction in the first cycle is not a trigger in the trigger chain, the instruction address trigger matching information for the first cycle is determined to be the information of the instruction address trigger corresponding to the oldest instruction among the instructions matched by the instruction address trigger in the first cycle. In other words, the output priority of the trigger that matches on the older instruction is higher. In the case where there is no trigger chain in the matched trigger, only the matching information of the oldest trigger among all the matched triggers in the current cycle (i.e., the first cycle) is output (the oldest here refers to the trigger corresponding to the oldest instruction).

[0062] As shown in case (a) in Figure 3, in the first cycle, if the triggers Trigger1 and Trigger2 that match the instruction are not triggers in the trigger chain, since the instruction C0 that matches the trigger Trigger2 is older than the instruction C1 that matches the trigger Trigger1, the instruction address trigger matching information of the first cycle is the information of the oldest trigger (Trigger2) among all the matching triggers in the first cycle, that is, only the information of Trigger2 is output.

[0063] (2) When the oldest trigger that matches the instruction in the first cycle is a trigger in the trigger chain, and the instruction matched by the oldest trigger is a memory access instruction, and there are other instruction address triggers that match the instruction in the first cycle, the instruction address trigger matching information of the first cycle is determined to be the information of the trigger chain and the information of the instruction address trigger corresponding to the second oldest instruction among the instructions matched by the instruction address trigger in the first cycle. That is, when there is a trigger chain among the matched triggers, if the instruction address trigger that matches between the two triggers in the trigger chain is the oldest trigger among all the matched triggers in this cycle (i.e., the first cycle) and the instruction that matches the trigger is a memory access instruction, then the matching information of the trigger chain is output, and if the second-oldest trigger also matches, then the matching information of the second-oldest trigger needs to be output.

[0064] As shown in case (b) in Figure 3, in the first cycle, the triggers that match the instruction include triggers Trigger0 and Trigger3 that are not in the trigger chain and trigger Trigger1 in the trigger chain, among which the oldest trigger is Trigger1, and the instruction C0 matched by Trigger1 is a memory access instruction. In the first cycle, triggers Trigger0 and Trigger3 also match the instruction. Then, the instruction address trigger matching information of the first cycle is the information of the trigger chain (i.e., Trigger1 (chain)) and the information of the trigger Trigger0 corresponding to the second oldest instruction (C1) among the instructions matched in the first cycle.

[0065] (3) When the oldest trigger that matches the instruction in the first cycle is not a trigger in the trigger chain, the instruction address trigger matching information of the first cycle is determined to be the information of the oldest trigger that matches the instruction in the first cycle. In other words, if the oldest trigger among all the matching triggers in the current cycle (i.e., the first cycle) is not a trigger in the trigger chain, then referring to the above situation (1), only the information of the oldest trigger needs to be output.

[0066] As shown in case (c) in Figure 3, the oldest trigger that matches the instruction in the first cycle is Trigger0, and Trigger0 is not a trigger in the trigger chain. Then the instruction address trigger matching information of the first cycle is the information that the oldest trigger that matches the instruction is Trigger0.

[0067] (4) When the instruction in the first cycle is an ebreak instruction and the ebreak_en field in the debug register is valid, the instruction address trigger matching information of the first cycle is not generated.

[0068] For a trigger with the action "raise a breakpoint exception" (see RISC-V External Debug Support Version 0.13.2), when determining whether it matches an instruction in the first cycle, a special case needs to be handled. That is, the instruction is an ebreak instruction and the ebreak_en field in the dcsr (debug csr register) is configured to be valid. In this case, the priority of ebreak is higher than the priority of the trigger with the action "raise a breakpoint exception", so the trigger does not trigger.

[0069] The trigger chain mentioned above is defined as: starting from the trigger with the value of 1 in the first chain field (configuration field in the tselect register) and ending with the trigger with the value of 0 in the first chain field behind it, this is a trigger chain. For a trigger chain, only when all the triggers in the trigger chain are matched on the same instruction, the trigger chain meets the trigger condition, and the execution action of the last trigger in the trigger chain (action field in tselect) is used as the execution action of the entire trigger chain. The length of the trigger chain in the embodiment of the present disclosure is 2 because the embodiment of the present disclosure only involves two types of triggers (instruction address triggers and memory address triggers). If the solution is expanded based on the embodiment of the present disclosure to implement other types of triggers, the maximum length of the trigger chain will also change accordingly.

[0070] In some embodiments, determining the memory access address trigger matching information of the second cycle includes the following steps: in the presence of a trigger chain, determining the memory access address trigger matching information of the second cycle based on the matching result between the instruction in the second cycle and the memory access address trigger, the matching result of the instruction address trigger in the trigger chain in the first cycle, the trigger chain affiliation of the memory access address trigger, the age of the instruction in the second cycle, and the age of the instruction in the trigger chain that matches the instruction address trigger.

[0071] The following, combined with Figure 4, details various scenarios for determining the memory access address trigger match information for the second cycle. The LS Trigger Match submodule, located in the same pipeline stage as the first stage of the Memory Execution Unit (LSU), determines and outputs the memory access address trigger match information for the second cycle.

[0072] Figure 4 is a schematic diagram of memory access address trigger detection according to an embodiment of the present disclosure. As shown in Figure 4, determining the memory access address trigger matching information of the second cycle includes the following situations.

[0073] (1) When there is no trigger chain match in the second cycle and there is no trigger chain in the trigger that has no instruction match in the second cycle, or when there is a trigger chain in the trigger that has no trigger chain match in the second cycle and there is no instruction match in the second cycle, but the instruction address trigger matched in the trigger chain in the first cycle is younger than the oldest trigger in the memory access address trigger matched in the second cycle, the memory access address trigger matching information of the second cycle is determined to be the information of the oldest trigger in the memory access address trigger matched in the second cycle.

[0074] As shown in case (a) in Figure 4, since the LSU trigger in the trigger chain does not match the instruction in the second cycle, the trigger chain is unmatched, meaning no trigger chain matches in the second cycle. In the second cycle, the triggers that match the instruction include Trigger2 and Trigger3, where Trigger2 is older than Trigger3, meaning Trigger2 is the oldest trigger among the matched LSU triggers in the second cycle. If the instruction address trigger (PC trigger) Trigger0 in the trigger chain that matched in the first cycle is younger than Trigger2, the oldest trigger among the matched LSU triggers in the second cycle, then the matching information for the matched LSU trigger in the second cycle is Trigger2's information. In other words, if there is no trigger chain among the matched triggers and no trigger chain among the unmatched triggers, or if there is a trigger chain among the unmatched triggers but the instruction corresponding to the instruction address trigger in the trigger chain that matches is younger than the instruction corresponding to the oldest trigger that matched in the current cycle (i.e., the second cycle), only the information for the oldest trigger among all matched triggers in the current cycle is output.

[0075] (2) If no memory access trigger matches the instruction in the second cycle, or if only the memory access address trigger in the trigger chain matches the instruction in the second cycle and the instruction address trigger in the trigger chain did not match the instruction in the first cycle, the memory access address trigger matching information for the second cycle is not generated. In other words, if the instruction address trigger in the trigger chain has not matched the instruction in the first cycle before, the memory access address trigger in the trigger chain will not output whether it matches or not.

[0076] As shown in case (b) in Figure 4, in the second cycle, only the memory address trigger Trigger0 in the trigger chain matches the instruction, but the instruction address trigger Trigger1 in the trigger chain does not match the instruction in the first cycle. This situation indicates that the trigger chain does not match, and the memory address trigger matching information of the second cycle is not output.

[0077] (3) When the instruction matched by the instruction address trigger in the trigger chain is older than the target instruction, and the memory address trigger in the trigger chain matches in the second cycle, the memory address trigger matching information of the second cycle is determined to be the information of the memory address trigger in the trigger chain. The target instruction is the oldest instruction matched by the memory address triggers other than the memory address trigger in the trigger chain in the second cycle.

[0078] For example, in case (c) of Figure 4, the target instruction is the instruction (i7) that matches Trigger2, and the instruction (i2) that matches instruction address trigger Trigger0 in the trigger chain is older than the target instruction (i7). Therefore, the memory access address trigger matching information for the second cycle is the information of memory access address trigger Trigger1 in the trigger chain. It should be noted that regardless of whether the memory access address triggers in the trigger chain match, the information of the memory access address triggers in that trigger chain must be output.

[0079] (4) When the instruction matched by the instruction address trigger in the trigger chain is older than the target instruction, and the memory address trigger in the trigger chain does not match the instruction in the second cycle, and the other memory address triggers other than the trigger chain match the instruction in the second cycle, the memory address trigger matching information of the second cycle is determined to be the information of the memory address triggers in the trigger chain that do not match and the information of the oldest trigger among the other memory address triggers other than the trigger chain that match the instruction in the second cycle. The target instruction is the oldest instruction matched by the other memory address triggers other than the memory address trigger in the trigger chain in the second cycle.

[0080] As shown in case (d) in Figure 4, the target instruction is the instruction (i4) that matches Trigger3, the instruction (i2) that matches the instruction address trigger Trigger0 in the trigger chain is older than the target instruction (i4), and the memory address trigger Trigger1 in the trigger chain does not match the instruction in the second cycle, and the other memory address triggers Trigger2 and Trigger3 except the trigger chain all match the instruction in the second cycle, then the memory address trigger matching information of the second cycle is the information that the memory address trigger Trigger1 in the trigger chain does not match, and the information of the oldest trigger Trigger3 among the other memory address triggers except the trigger chain.

[0081] (5) When the instruction matched by the instruction address trigger in the trigger chain is older than the target instruction, and the memory address trigger in the trigger chain does not match the instruction in the second cycle, and the memory address triggers in other trigger chains other than the trigger chain match the instruction in the second cycle, the memory address trigger matching information of the second cycle is determined to be the information of the memory address triggers in the trigger chain that do not match and the information of the memory address triggers in other trigger chains other than the trigger chain that match the instruction in the second cycle. The target instruction is the oldest instruction matched by other memory address triggers other than the memory address trigger in the trigger chain (regardless of whether in other trigger chains) in the second cycle.

[0082] For example, in case (e) of Figure 4 , taking trigger chain 1 (i.e., the first trigger chain shown in Figure 4e ) as an example, the target instruction is the instruction (i4) matched by Trigger2, the instruction (i2) matched by the instruction address trigger in trigger chain 1 is older than the target instruction (i4), and the memory address trigger Trigger1 in trigger chain 1 does not match the instruction in the second cycle, and the memory address trigger Trigger2 in trigger chain 2 (i.e., the second trigger chain shown in Figure 4e ) does match the instruction in the second cycle, then the memory address trigger matching information for the second cycle is the mismatch information of the memory address trigger Trigger1 in trigger chain 1, and the information of Trigger2 in trigger chain 2. In other words, in addition to outputting the mismatch information of the memory address triggers in the trigger chain, it is also necessary to output the information of the oldest trigger among the other matching memory address triggers in this cycle.

[0083] From the above cases (3)-(5), it can be seen that if the instruction address trigger in the trigger chain has matched before, and the instruction corresponding to the matched trigger is older than the instruction corresponding to the trigger in other non-trigger chains that matched in this cycle (i.e., the second cycle), then regardless of whether the memory access address trigger in the trigger chain matches, the information of the memory access address trigger needs to be output. If the memory access address trigger in the trigger chain does not match, and there are other memory access address triggers that match in this cycle (i.e., the second cycle), then the information of the oldest trigger among the other matching memory access address triggers also needs to be output.

[0084] In some embodiments, priority arbitration is performed on trigger matching information of different cycles to obtain target trigger information (i.e., step S12), including the following steps: according to a preset first rule and a preset second rule, priority arbitration is performed on the instruction address trigger matching information of the first cycle and the memory access address trigger matching information of the second cycle to obtain target trigger information; wherein the first rule is a rule based on the trigger chain affiliation attribute, and the second rule is a rule based on the instruction age relationship corresponding to the currently input memory access address trigger matching information and the saved trigger matching information.

[0085] Because there's a certain time interval between trigger matching and triggering (the actual triggering decision isn't made until the instruction submission phase, based on trigger matching information and the priorities of other system events and triggers), multiple triggers may match on different instructions during this time. Therefore, the trigger matching information output by the two trigger detection submodules needs to be cached. The most direct and effective approach is to add some hardware resources to each entry in the reorder cache to record the trigger matching information for the instruction stored in that entry. However, this requires adding hardware resources to each reorder cache entry, resulting in high hardware overhead. Therefore, using a dedicated queue to cache matching trigger information is a relatively better approach. However, directly storing all trigger matching information without processing it also incurs significant hardware overhead. In practice, we only need to record the oldest matching trigger in the current pipeline. An exception to this is for a trigger chain where the instruction address trigger matches but the memory access trigger does not, and because the instruction address trigger detection logic for the same instruction executes before the memory access trigger detection logic, the instruction address trigger detection submodule may output both the oldest and second-oldest matching trigger information. Therefore, the trigger detection information synchronization module can follow the above ideas to perform priority arbitration on the trigger matching information from the two trigger detection submodules and record the information of the two oldest triggers (chains). This information can include the trigger action, the trigger time point (the timing field in the tselect register), the matching instruction address, and its corresponding reordering cache sequence number. It should be noted that since the minimum length of the trigger chain is 2, when the solution is expanded, more triggers can be implemented, such as 6, in which case the information of the three oldest triggers (chains) needs to be recorded in the trigger detection information synchronization module, and so on.

[0086] Therefore, in some embodiments, the target trigger information may include information about the oldest trigger (chain); the target trigger information may also include information about the oldest trigger (chain) and information about the second oldest trigger (chain). In other words, after synchronous processing based on trigger detection information, only the information of the oldest one or two triggers (chains) in the pipeline can be cached, which can significantly reduce the hardware overhead of its implementation in a superscalar out-of-order processor.

[0087] In an embodiment of the present disclosure, the oldest trigger matching information in the current pipeline is recorded through the first array, and the second oldest trigger matching information in the current pipeline is recorded through the second array, wherein the oldest trigger matching information in the current pipeline refers to: the information of the oldest trigger that matches the instruction in the current pipeline; the second oldest trigger matching information in the current pipeline refers to the information of the second oldest trigger that matches the instruction in the current pipeline.

[0088] The first rule includes at least one of the following:

[0089] (1) If the trigger matching information of the first array is not the information of the trigger in the trigger chain, the second array is invalidated.

[0090] (2) If the trigger match information in the first array is information about triggers in a trigger chain, the trigger match information in the second array may include information about the trigger chain or information about triggers not in the trigger chain. In other words, if the first array records trigger matches for a trigger chain, the second array may record information about either the trigger chain or a single trigger.

[0091] (3) If the trigger matching information of the first array is the information of the trigger in the trigger chain, and both the instruction address trigger and the memory address trigger in the trigger chain match the instruction, the second array is invalidated. That is, for the first array, if the current record is the information of the trigger chain, and the instruction address trigger therein matches, and if the memory address trigger detection submodule outputs the matching memory address trigger in the trigger chain, the second array is invalidated, that is, only the first array is retained.

[0092] (4) For any one of the first and second arrays, if the trigger matching information of the array is the information of the trigger in the trigger chain, and the instruction address trigger in the trigger chain matches the instruction, and the memory address trigger in the trigger chain does not match the instruction, the array is invalidated; wherein, if the array is the first array, the second array is marked as the first array in this cycle. That is to say, for each of the two arrays, if the array currently records the information of the trigger chain and the instruction address trigger therein is matched, at this time, if the memory address trigger detection submodule outputs that the memory address trigger in the trigger chain does not match, then the array is invalidated; if the invalidated array is the first array, then the original second array is marked as the first array in the current cycle.

[0093] For each of the two arrays, the local information recorded in the trigger detection information synchronization module and the input information from the two trigger detection submodules need to be updated according to the second rule.

[0094] The second rule includes at least one of the following:

[0095] (1) When the first array is stored locally but the second array is not stored, and the information in the first array is the matching information of the instruction address trigger in the trigger chain, if the instruction matched by the currently input memory address trigger is the same age as the instruction matched by the instruction address trigger, then the trigger chain of the first array is matched; if the instruction matched by the currently input memory address trigger is older than the instruction matched by the instruction address trigger in the trigger chain of the first array, then the first array is updated to the matching information of the currently input memory address trigger; if the instruction matched by the currently input memory address trigger is younger than the instruction matched by the instruction address trigger, then the second array is updated to the matching information of the currently input memory address trigger.

[0096] That is to say, only the first array is recorded locally and the first array is a trigger chain, that is, the instruction address trigger in the trigger chain of the first array has been matched. If the instruction of the memory address trigger currently matched by the input is the same age as the instruction corresponding to the trigger of the first array recorded locally, it means that the memory address trigger in this trigger chain is also matched, then the current trigger chain of the first array is matched; if the instruction of the memory address trigger currently matched by the input is older than the instruction age corresponding to the trigger of the first array recorded locally, the memory address trigger currently matched by the input has a higher priority, then the trigger chain recorded in the first array will be invalidated, and the memory address trigger information currently matched by the input will be updated to the first array; if the instruction of the memory address trigger currently matched by the input is younger than the instruction age corresponding to the trigger of the first array recorded locally, then the memory address trigger information currently matched by the input will be updated to the second array.

[0097] (2) When the first array is stored locally but the second array is not stored, and the information in the first array is not the matching information of the trigger in the trigger chain, if the age of the instruction matched by the currently input memory access address trigger is different from the age of the instruction matched by the instruction address trigger, the first array is updated to the matching information of the trigger corresponding to the older instruction of the two; if the age of the instruction matched by the currently input memory access address trigger is the same as the age of the instruction matched by the instruction address trigger, the execution action of the currently input memory access address trigger and the execution action of the instruction address trigger are judged; if the execution actions are inconsistent, the execution action is determined to be the first preset action, and the first array is updated to the first target trigger matching information corresponding to the first preset action.

[0098] That is to say, if only the first array is recorded locally and the first array is not a trigger chain, then the trigger of the first array and the memory address trigger that matches the current input, the older one has a higher priority; if the two are of the same age, the execution actions of the two are further judged. If the execution actions of the two are consistent, it can be determined that the trigger type of the locally recorded first array is an instruction address trigger, so the locally recorded first array has a higher priority. If the execution actions of the two are inconsistent, the one with the execution action of "entry debug mode" has a higher priority; this set of trigger information with a higher priority is used to update the locally recorded first array in the next cycle.

[0099] (3) When the first array and the second array are stored locally, and the information in the first array is the matching information of the trigger in the trigger chain, and the information in the second array is the matching information of the trigger in the trigger chain or the matching information of the trigger in the non-trigger chain, if the instruction matched by the currently input memory access address trigger is the same age as the instruction matched by the instruction address trigger in the first array, the second array is invalidated; if the instruction matched by the currently input memory access address trigger is older than the instruction matched by the instruction address trigger in the first array, the second array is invalidated, and the first array is updated to the matching information of the previously input memory access address trigger; if the instruction matched by the currently input memory access address trigger is older than the instruction matched by the instruction address trigger in the first array, the second array is invalidated, and the first array is updated to the matching information of the previously input memory access address trigger; If the instruction matched by the memory access address trigger is younger and older than the instruction matched by the instruction address trigger in the second array, the second array is updated to the matching information of the currently input memory address trigger; if the instruction matched by the currently input memory address trigger is younger than the instruction matched by the instruction address trigger in the first array and is the same age as the instruction matched by the instruction address trigger in the second array, and the information in the second array is not the matching information of the trigger in the trigger chain, then the execution action of the currently input memory address trigger is judged to be the execution action of the instruction address trigger in the second array; if the execution actions are inconsistent, the execution action is determined to be the second preset action, and the second array is updated to the second target trigger matching information corresponding to the second preset action.

[0100] That is to say, if two groups of first numbers and second numbers are recorded locally, that is, the first array is the matching information of the trigger chain, and the second array is the matching information of the trigger chain or a single trigger, if the instruction of the memory address trigger currently matched by the input is the same age as the instruction corresponding to the first number recorded locally, it means that the memory address trigger in this trigger chain also matches, then the current trigger chain of the first array matches, and the second array is invalidated at this time; if the memory address trigger currently matched by the input is older than the instruction age corresponding to the first and second arrays recorded locally, and the memory address trigger currently matched by the input has a higher priority, then the first and second arrays will be invalidated, and the memory address trigger information of the current input match will be updated to the first array; if the instruction of the memory address trigger currently matched by the input is younger than the instruction age of the locally recorded first array and older than the instruction corresponding to the locally recorded second array, then the first array remains unchanged and the second array is invalidated. array, and updates the memory address trigger information of the current input match to the second array; if the instruction of the memory address trigger of the current input match is younger than the instructions corresponding to the two arrays recorded locally, the two arrays recorded locally remain unchanged; if the instruction of the memory address trigger of the current input match is younger than the instruction age corresponding to the first array recorded locally and is the same as the instruction age corresponding to the second array recorded locally, if the second array is a trigger chain, it means that the memory address trigger of the current input match is the trigger in the trigger chain, and the trigger chain matches; if the second array is not a trigger chain, further judge the execution actions of the two. If the execution actions of the two are consistent, it can be determined that the trigger type of the second array recorded locally is an instruction address trigger, so the priority of the second array recorded locally is higher than the priority of the memory address trigger of the current input match; if the execution actions of the two are inconsistent, the priority of the one with the execution action of "entry debug mode" is higher, and this set of trigger matching information with a high priority is used to update the second array of the local record in the next cycle.

[0101] It should be noted that the trigger detection information synchronization module records the trigger matching information with high priority, updates the local information recorded by the trigger detection information synchronization module in this cycle according to the above second rule, and sends the information of the first array to the trigger submission module in real time.

[0102] In some embodiments, determining whether a target trigger is triggered includes the following steps: determining whether the target trigger is triggered according to the exception priority of the instruction.

[0103] The exception priority of the instruction is shown in Table 1:

[0104] Table 1

[0105] In some embodiments, determining the execution action according to the information of the target trigger (step S13) includes the following steps: determining the execution action according to the information of the target trigger and the priority of the flushing pipeline.

[0106] In some embodiments, the priority of a debug request is higher than the priority of an interrupt, the priority of an interrupt is higher than the priority of an exception in debug mode, and the priority of an exception in debug mode is higher than the priority of an exception in non-debug mode; wherein, among the priorities of debug requests, the priority of a trigger execution action is higher than the priority of a software breakpoint, the priority of a software breakpoint is higher than the priority of a debug interrupt request, and the priority of a debug interrupt request is higher than the priority of a single-step debugging request.

[0107] The trigger submission module consists of two parts: the first submodule (Trig Commit1) and the second submodule (Trig Commit2). The first submodule is the logic under the reorder cache. In the first submodule, when the instruction matched by the trigger is submitted, the exception priority of the instruction is used to determine whether the trigger is finally triggered. The exception priority is shown in Table 1. For triggers that are judged to be triggered, the information of the trigger (such as the instruction address matched by the trigger, the execution action configured by the trigger, etc.) is output to the second submodule configured in the instruction reset module (IRU). In the second submodule, further processing is performed based on the execution action after the trigger is triggered and the priority of interrupts, exceptions, and debug requests, and ultimately the next execution action and state of the processor core are determined. The priority judgment of this part follows the definition of the RISCV manual. The priority definition of flushing the pipeline is as follows:

[0108] Debug Request > Break > Exception in debug mode > Exception in non-debug mode > Other;

[0109] The priority of debug request is defined as follows: trigger (action == 1) > software breakpoint > debug module halt request > single-step debugging.

[0110] The trigger submission module is the most highly coupled to the mainstream water in the embodiment of this disclosure, but this part is related to the microarchitecture of the processor core, and the expansion design of the number and types of triggers based on the embodiment of this disclosure does not involve modifications to this part, so this part will not be elaborated in detail.

[0111] The disclosed embodiments provide a solution for RISCV hardware breakpoints and hardware watchpoints based on a superscalar out-of-order main pipeline. The solution can be expanded by simple adjustments based on a specific superscalar out-of-order main pipeline architecture. Compared with a solution that temporarily stores breakpoint detection information based on a reorder buffer (Reorder Buffer) or other dedicated queues, the disclosed embodiments have lower hardware overhead and power consumption for processing breakpoint detection information. In the RISCV instruction set manual, hardware breakpoints and hardware watchpoints are implemented based on debug logic and trigger logic, and the core of the implementation of hardware breakpoints and hardware watchpoints is mainly the implementation of triggers. Therefore, the disclosed embodiments focus on the design and implementation of triggers based on a superscalar out-of-order pipeline, which mainly consists of a trigger detection module, a trigger detection information synchronization module, a trigger control register, and a trigger submission module.

[0112] The disclosed embodiments offer excellent scalability. Expanding the solution requires only minor modifications to the trigger detection strategy and the trigger detection information synchronization rules. Furthermore, when caching trigger matching information, the disclosed embodiments utilize only a single queue with a depth of two. This reduces hardware overhead compared to solutions that directly store the information in the reordering cache or directly store it in a dedicated queue without trigger detection and information synchronization.

[0113] The embodiments of the present disclosure are applicable to any device that uses a processor, especially a high-performance processor, such as a CPU / SOC chip, a mobile phone, a computer, a data center server, etc.

[0114] The present disclosure also provides a breakpoint debugging device. FIG5 is a schematic structural diagram of a breakpoint debugging device according to an embodiment of the present disclosure.

[0115] As shown in FIG5 , the breakpoint debugging device includes: a trigger detection module 501 , a trigger detection information synchronization module 502 and a trigger submission module 503 .

[0116] The trigger detection module 50 is configured to perform trigger detection for each cycle and determine trigger matching information of the cycle, where the trigger matching information is information of a trigger that matches an instruction.

[0117] The trigger detection information synchronization module 502 is configured to perform priority arbitration on the trigger matching information of different cycles to obtain information of a target trigger.

[0118] The trigger submission module 503 is configured to determine an execution action according to information of the target trigger when the instruction matched by the target trigger reaches the submission stage and the target trigger is determined to be triggered, so that the processing core can execute the execution action.

[0119] The present disclosure also provides a breakpoint debugging device. FIG6 is a schematic structural diagram of a breakpoint debugging device according to an embodiment of the present disclosure.

[0120] As shown in Figure 6, the breakpoint debugging device includes one or more processors 601, a storage device 602, and one or more I / O interfaces 603. The storage device 602 stores one or more programs. When executed by the one or more processors 601, these programs enable the one or more processors 601 to implement the breakpoint debugging method described above. The I / O interface 603 is connected between the processor 601 and the storage device 602 and is configured to facilitate information exchange between the processor 601 and the storage device 602.

[0121] Processor 601 is a device with data processing capabilities, including but not limited to a central processing unit (CPU). Storage device 602 is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically, SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and flash memory (FLASH). I / O interface (read / write interface) 603 is connected between processor 601 and storage device 602 to enable information exchange between processor 601 and storage device 602, including but not limited to a data bus.

[0122] An embodiment of the present disclosure further provides a computer-readable medium having a computer program stored thereon, wherein the computer program implements the breakpoint debugging method as described above when executed.

[0123] It will be appreciated by those skilled in the art that all or some of the steps in the method disclosed above, and the functional modules / units in the device can be implemented as software, firmware, hardware, and appropriate combinations thereof. In a hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media generally embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0124] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A breakpoint debugging method, comprising: Perform trigger detection for each cycle to determine trigger matching information of the cycle, where the trigger matching information is information of a trigger that matches an instruction; Perform priority arbitration on trigger matching information of different cycles to obtain information of the target trigger; When the instruction matching the target trigger reaches the commit stage and it is determined that the target trigger is triggered, an execution action is determined according to information of the target trigger, so that the processing core executes the execution action.

2. The method of claim 1, wherein: Perform trigger detection for each cycle to determine trigger matching information of the cycle, including: For each first cycle, performing instruction address trigger detection in the instruction decoding stage to determine instruction address trigger matching information of the first cycle; For each second cycle, a memory access address trigger detection is performed in the memory access execution phase to determine the memory access address trigger matching information of the second cycle.

3. The method of claim 2, wherein: The instruction address trigger matching information of the first cycle includes information of the instruction address trigger corresponding to the oldest instruction matched with the trigger in the first cycle, or information of the instruction address trigger corresponding to the oldest instruction matched with the trigger in the first cycle and information of the instruction address trigger corresponding to the second oldest instruction matched with the trigger in the first cycle; The memory access address trigger matching information of the second cycle includes information of the memory access address trigger corresponding to the oldest instruction that matches the trigger in the second cycle, or information of the memory access address trigger corresponding to the oldest instruction that matches the trigger in the second cycle and information of the memory access address trigger corresponding to the second oldest instruction that matches the trigger in the second cycle.

4. The method of claim 3, wherein: Determining instruction address trigger matching information of the first cycle includes: Instruction address trigger matching information of the first cycle is determined based on the trigger chain membership attribute of the instruction address trigger and the age and type of the instruction in the first cycle.

5. The method of claim 4, wherein: Determining instruction address trigger matching information of the first cycle according to the trigger chain membership attribute of the instruction address trigger and the age and type of the instruction in the first cycle, including: In the case where the trigger matched with the instruction in the first cycle is not a trigger in the trigger chain, determining that the instruction address trigger matching information of the first cycle is information of the instruction address trigger corresponding to the oldest instruction among the instructions matched by the instruction address trigger in the first cycle; In the case where the oldest trigger that matches the instruction in the first cycle is a trigger in a trigger chain, and the instruction matched by the oldest trigger is a memory access instruction, and in the case where other instruction address triggers match the instruction in the first cycle, determining that the instruction address trigger matching information of the first cycle is information of the trigger chain and information of the instruction address trigger corresponding to the second oldest instruction among the instructions matched by the instruction address trigger in the first cycle; When the oldest trigger that matches the instruction in the first cycle is not a trigger in the trigger chain, the instruction address trigger matching information of the first cycle is determined to be the information of the oldest trigger that matches the instruction in the first cycle.

6. The method of claim 3, wherein: Determining the memory access address trigger matching information of the second cycle includes: In the case where there is a trigger chain, the memory address trigger matching information of the second cycle is determined based on the matching result between the instruction in the second cycle and the memory address trigger, the matching result of the instruction address trigger in the trigger chain in the first cycle, the trigger chain affiliation of the memory address trigger, the age of the instruction in the second cycle, and the age of the instruction in the trigger chain that matches the instruction address trigger.

7. The method of claim 6, wherein: According to the matching result between the instruction in the second cycle and the memory address trigger, the matching result of the instruction address trigger in the trigger chain in the first cycle, the trigger chain affiliation of the memory address trigger, the age of the instruction in the second cycle, and the age of the instruction in the trigger chain that matches the instruction address trigger, the memory address trigger matching information of the second cycle is determined, including: In the case where there is no trigger chain match in the second cycle and there is no trigger chain in the trigger that has no instruction match in the second cycle, or in the case where there is no trigger chain match in the second cycle and there is a trigger chain in the trigger that has no instruction match in the second cycle, but the instruction address trigger in the trigger chain that matches in the first cycle is younger than the oldest trigger in the memory access address triggers that match in the second cycle, determine that the memory access address trigger matching information of the second cycle is the information of the oldest trigger in the memory access address triggers that match in the second cycle; If no memory access trigger matches the instruction in the second cycle, or if only the memory access address trigger in the trigger chain matches the instruction in the second cycle and the instruction address trigger in the trigger chain does not match the instruction in the first cycle, the memory access address trigger matching information of the second cycle is not generated; When the instruction matched by the instruction address trigger in the trigger chain is older than the target instruction and the memory access address trigger in the trigger chain is matched in the second cycle, determining the memory access address trigger matching information of the second cycle as the information of the memory access address trigger in the trigger chain; In the trigger chain, when the instruction matched by the instruction address trigger is older than the target instruction, and the memory address trigger in the trigger chain does not match the instruction in the second cycle, and other memory address triggers except the trigger chain match the instruction in the second cycle, determine the memory address trigger matching information of the second cycle as the information that the memory address trigger in the trigger chain does not match and the information of the oldest trigger among other memory address triggers except the trigger chain that match the instruction in the second cycle; In the case where the instruction matched by the instruction address trigger in the trigger chain is older than the target instruction, and the memory address trigger in the trigger chain does not match the instruction in the second cycle, and the memory address triggers in other trigger chains except the trigger chain match the instruction in the second cycle, determining the memory address trigger matching information of the second cycle as the information of the memory address triggers in the trigger chain that do not match and the information of the memory address triggers in other trigger chains except the trigger chain that match the instruction in the second cycle; The target instruction is the oldest instruction matched by other memory access address triggers except the memory access address trigger in the trigger chain in the second cycle.

8. The method of claim 2, wherein: Priority arbitration is performed on trigger matching information of different cycles to obtain information of the target trigger, including: According to the preset first rule and the preset second rule, priority arbitration is performed on the instruction address trigger matching information of the first cycle and the memory address trigger matching information of the second cycle to obtain the information of the target trigger; the first rule is a rule based on the trigger chain affiliation attribute, and the second rule is a rule based on the instruction age relationship corresponding to the currently input memory address trigger matching information and the saved trigger matching information.

9. The method of claim 8, wherein: The oldest trigger matching information in the current pipeline is recorded through the first array, and the second oldest trigger matching information in the current pipeline is recorded through the second array, and The first rule includes at least one of the following: In the case that the trigger matching information of the first array is not the information of the trigger in the trigger chain, invalidating the second array; In the case where the trigger matching information of the first array is information of a trigger in a trigger chain, the trigger matching information of the second array includes information of a trigger chain or information of a trigger in a non-trigger chain; In the case where the trigger matching information of the first array is information of a trigger in a trigger chain, and both the instruction address trigger and the memory access address trigger in the trigger chain match the instruction, invalidating the second array; and For any one of the first array and the second array, when the trigger matching information of the array is the information of the trigger in the trigger chain, and the instruction address trigger in the trigger chain matches the instruction, and the memory address trigger in the trigger chain does not match the instruction, the array is invalid; wherein, if the array is the first array, the second array is marked as the first array in this cycle.

10. The method of claim 8, wherein: The oldest trigger matching information in the current pipeline is recorded through the first array, and the second oldest trigger matching information in the current pipeline is recorded through the second array, and The second rule includes at least one of the following: In the case where the first array is stored locally but the second array is not stored, and the information in the first array is the matching information of the instruction address trigger in the trigger chain, if the instruction matched by the currently input memory access address trigger is the same age as the instruction matched by the instruction address trigger, then the trigger chain of the first array is matched; if the instruction matched by the currently input memory access address trigger is older than the instruction matched by the instruction address trigger in the trigger chain of the first array, then the first array is updated to the matching information of the currently input memory access address trigger; if the instruction matched by the currently input memory access address trigger is younger than the instruction matched by the instruction address trigger, then the second array is updated to the matching information of the currently input memory access address trigger; In the case where the first array is stored locally but the second array is not stored, and the information in the first array is not the matching information of the trigger in the trigger chain, if the age of the instruction matched by the currently input memory access address trigger is different from the age of the instruction matched by the instruction address trigger, then the first array is updated to the matching information of the trigger corresponding to the older instruction of the two; if the age of the instruction matched by the currently input memory access address trigger is the same as the age of the instruction matched by the instruction address trigger, then the execution action of the currently input memory access address trigger and the execution action of the instruction address trigger are determined, and if the execution actions are inconsistent, the execution action is determined to be a first preset action, and the first array is updated to the first target trigger matching information corresponding to the first preset action; and In the case where the first array and the second array are stored locally, and the information in the first array is the matching information of the trigger in the trigger chain, and the information in the second array is the matching information of the trigger in the trigger chain or the matching information of the trigger in the non-trigger chain, if the instruction matched by the currently input memory access address trigger is the same age as the instruction matched by the instruction address trigger in the first array, the second array is invalid; if the instruction matched by the currently input memory access address trigger is older than the instruction matched by the instruction address trigger in the first array, the second array is invalid, and the first array is updated to the matching information of the previously input memory access address trigger; if the instruction matched by the currently input memory access address trigger is older than the instruction matched by the instruction address trigger in the first array, the second array is invalid, and the first array is updated to the matching information of the previously input memory access address trigger; If the instruction matched by the memory access address trigger is younger and older than the instruction matched by the instruction address trigger in the second array, the second array is updated to the matching information of the currently input memory access address trigger; if the instruction matched by the currently input memory access address trigger is younger than the instruction matched by the instruction address trigger in the first array and is the same age as the instruction matched by the instruction address trigger in the second array, and the information in the second array is not the matching information of the trigger in the trigger chain, then the execution action of the currently input memory access address trigger is judged to be the execution action of the instruction address trigger in the second array; if the execution actions are inconsistent, the execution action is determined to be the second preset action, and the second array is updated to the second target trigger matching information corresponding to the second preset action.

11. The method of claim 1, wherein: Determining that the target trigger is triggered includes: Whether the target trigger is triggered is determined according to the exception priority of the instruction.

12. The method of claim 1, wherein: Determining an execution action according to information of the target trigger includes: The execution action is determined according to the information of the target trigger and the priority of the flushing pipeline.

13. The method of claim 12, wherein: In the priority of the flush pipeline, the priority of the debug request is higher than the priority of the interrupt, the priority of the interrupt is higher than the priority of the exception in the debug mode, the priority of the exception in the debug mode is higher than the priority of the exception in the non-debug mode, and Among them, in the priority of the debugging request, the priority of the trigger execution action is higher than the priority of the software breakpoint, the priority of the software breakpoint is higher than the priority of the debugging interrupt request, and the priority of the debugging interrupt request is higher than the priority of the single-step debugging request.

14. A breakpoint debugging device, comprising: A trigger detection module, configured to perform trigger detection for each cycle and determine trigger matching information of the cycle, wherein the trigger matching information is information of a trigger matching an instruction; A trigger detection information synchronization module, which is configured to perform priority arbitration on the trigger matching information of different cycles to obtain information of a target trigger; as well as A trigger submission module is configured to determine an execution action according to information of the target trigger when the instruction matched by the target trigger reaches the submission stage and the target trigger is determined to be triggered, so that the processing core can execute the execution action.

15. A breakpoint debugging device, comprising: one or more processors; a storage device having one or more programs stored thereon; When the one or more programs are executed by the one or more processors, the one or more processors implement the breakpoint debugging method according to any one of claims 1 to 13; One or more I / O interfaces are connected between the processor and the storage device and are configured to implement information interaction between the processor and the storage device.

16. A computer readable medium having a computer program stored thereon, wherein: When the program is executed, the breakpoint debugging method according to any one of claims 1 to 13 is implemented.

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