Driving method for pixel circuit, and display panel

Abstract

A driving method for a pixel circuit, and a display panel. The pixel circuit comprises a data writing module (11), a driving module (12), and a first reset module (13). The data writing module (11) is connected to the driving module (12), and the first reset module (13) is connected to a control end of the driving module (12). In one display frame, the driving method for the pixel circuit comprises: in a first reset stage, controlling the first reset module (13) to reset the control end of the driving module (12) at least once; in a second reset stage, controlling the first reset module (13) to reset the control end of the driving module (12) at least once; and in a first data writing stage, controlling the data writing module (11) to write a first data voltage into the control end of the driving module (12) at least once.

Description

Pixel circuit driving method and display panel

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on October 31, 2023 with application number 202311434931.8, and the Chinese patent application filed with the China Patent Office on June 19, 2024 with application number 202410796535.8. The entire contents of the above applications are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of display technology, for example, to a driving method for a pixel circuit and a display panel. Background Art

[0003] Organic Light Emitting Display (OLED) flat panel display devices are widely used in various electronic products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, power saving, thin body and wide application range.

[0004] However, the display effect of current display products needs to be improved, that is, the display products have the problem of poor display effect.

[0005] Summary of the Invention

[0006] The present application provides a driving method for a pixel circuit and a display panel to solve the problem of poor display effect of display products.

[0007] According to one aspect of the present application, a method for driving a pixel circuit is provided. The pixel circuit includes a data writing module, a driving module, and a first reset module. The data writing module is connected to the driving module, and the first reset module is connected to a control terminal of the driving module. Within a display frame, the method includes:

[0008] In a first reset phase, controlling the first reset module to reset the control end of the driving module at least once;

[0009] In a second reset phase, controlling the first reset module to reset the control end of the driving module at least once;

[0010] In a first data writing phase, the data writing module is controlled to write a first data voltage into the control terminal of the driving module at least once.

[0011] According to another aspect of the present application, a method for driving a pixel circuit is provided. The pixel circuit includes a data writing module, a driving module, and a first reset module. The data writing module is connected to the driving module, and the first reset module is connected to a control terminal of the driving module. Within a display frame, the method includes:

[0012] In a first reset phase, controlling the first reset module to reset the control end of the driving module at least once;

[0013] In the second data writing phase, controlling the data writing module to write the second data voltage to the control terminal of the driving module at least once;

[0014] In a first data writing phase, the data writing module is controlled to write a first data voltage into the control terminal of the driving module at least once.

[0015] According to another aspect of the present application, a method for driving a pixel circuit is provided. The pixel circuit includes a data writing module, a driving module, a first reset module, and a storage module. The data writing module is connected to the driving module, and the first reset module is connected to a control terminal of the driving module. A first terminal of the storage module is connected to a DC signal, and a second terminal of the storage module is connected to the control terminal of the driving module. Within a display frame, the method includes:

[0016] In a first reset phase, controlling the first reset module to reset the control end of the driving module at least once;

[0017] During a reset and maintain phase, controlling the first reset module and the data writing module to be turned off so that the storage module maintains the potential of the control terminal of the driving module; or, during a portion of the reset and maintain phase, controlling the first reset module to reset the control terminal of the driving module at least once, and controlling the first reset module and the data writing module to be turned off during another portion of the reset and maintain phase;

[0018] In a first data writing phase, controlling the data writing module to write a first data voltage to the control terminal of the driving module at least once;

[0019] The other part of the reset maintaining phase is the period from the last time the first reset module resets the control terminal of the driving module to the start of the first data writing phase during the reset maintaining phase.

[0020] According to another aspect of the present application, a display panel is provided, comprising a plurality of first gate driving circuits, a plurality of second gate driving circuits, and a plurality of pixel circuits; the pixel circuits comprising a data writing module, a driving module, and a first reset module; the data writing module is connected to the driving module, and the first reset module is connected to a control terminal of the driving module;

[0021] The first gate driving circuit is connected to the first reset modules of the k rows of pixel circuits, and the first gate driving circuit is configured to transmit a first gate driving signal to the first reset modules corresponding to the k rows of pixel circuits;

[0022] The second gate driving circuit is connected to the data writing module of a row of pixel circuits, and the second gate driving circuit is configured to transmit a second gate driving signal to the data writing module of the corresponding row of pixel circuits;

[0023] The single effective pulse width of the first gate driving signal is n times the single effective pulse width of the second gate driving signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] FIG1 is a schematic structural diagram of a pixel circuit provided in an embodiment of the present application;

[0025] FIG2 is a flow chart of a driving method of a pixel circuit provided in an embodiment of the present application;

[0026] FIG3 is a driving timing diagram of a pixel circuit provided in an embodiment of the present application;

[0027] FIG4 is a flowchart of another pixel circuit driving method provided in an embodiment of the present application;

[0028] FIG5 is a driving timing diagram of another pixel circuit provided in an embodiment of the present application;

[0029] FIG6 is a driving timing diagram of another pixel circuit provided in an embodiment of the present application;

[0030] FIG7 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present application;

[0031] FIG8 is a flowchart of another method for driving a pixel circuit provided in an embodiment of the present application;

[0032] FIG9 is a driving timing diagram of another pixel circuit provided in an embodiment of the present application;

[0033] FIG10 is a flowchart of another pixel circuit driving method provided in an embodiment of the present application;

[0034] FIG11 is a driving timing diagram of another pixel circuit provided in an embodiment of the present application;

[0035] FIG12 is a driving timing diagram of another pixel circuit provided in an embodiment of the present application;

[0036] FIG13 is a driving timing diagram of another pixel circuit provided in an embodiment of the present application;

[0037] FIG14 is a driving timing diagram of another pixel circuit provided in an embodiment of the present application;

[0038] FIG15 is a flowchart of another method for driving a pixel circuit provided in an embodiment of the present application;

[0039] FIG16 is a driving timing diagram of another pixel circuit provided in an embodiment of the present application;

[0040] FIG17 is a flowchart of another pixel circuit driving method provided in an embodiment of the present application;

[0041] FIG18 is a driving timing diagram of another pixel circuit provided in an embodiment of the present application;

[0042] FIG19 is a flowchart of another method for driving a pixel circuit according to an embodiment of the present application;

[0043] FIG20 is a driving timing diagram of another pixel circuit provided in an embodiment of the present application;

[0044] FIG21 is a flowchart of another pixel circuit driving method provided in an embodiment of the present application;

[0045] FIG22 is a driving timing diagram of another pixel circuit provided in an embodiment of the present application;

[0046] FIG23 is a flowchart of another pixel circuit driving method provided in an embodiment of the present application;

[0047] FIG24 is a driving timing diagram of another pixel circuit provided in an embodiment of the present application;

[0048] FIG25 is a driving timing diagram of another pixel circuit provided in an embodiment of the present application;

[0049] FIG26 is a schematic structural diagram of a display panel provided in an embodiment of the present application;

[0050] FIG27 is a schematic structural diagram of another display panel provided in an embodiment of the present application;

[0051] FIG28 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0052] The terms "first", "second" etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, in addition to comprising the process, method, system, product or equipment of a series of steps or units shown in the embodiments of the present application, other processes, methods, systems, products and equipment of this series of steps or units that may not be listed, or other steps or units inherent to these processes, methods, systems, products or equipment.

[0053] Organic light-emitting diode (OLED) display panels emit light through current-driven operation. The display panel includes multiple pixel circuits and organic light-emitting diodes (OLEDs), which can be arranged in an array. The pixel circuits include driver transistors connected to the OLEDs. The driver transistors in the pixel circuits generate a drive current based on a data voltage, causing the OLEDs to emit light in response to the drive current. However, when displaying an image, the driver transistors are turned on, subjecting the driver transistors to forward voltage stress. Prolonged exposure to forward voltage stress can cause the driver transistor's characteristics to shift, resulting in brightness deviation when switching to the next grayscale. When displaying an image, OLEDs at different locations have different target brightnesses. Consequently, different driver transistors receive different target data voltages, subjecting the different driver transistors to different forward voltage stresses. This leads to different changes in the characteristics of the different driver transistors, resulting in different drive currents generated by the different driver transistors at the same grayscale, resulting in different display brightnesses for the different OLEDs. Therefore, when switching from a display with different grayscales to a display with the same grayscale, the brightness deviations of the OLEDs corresponding to each driver transistor vary, resulting in image sticking, poor display uniformity across the display panel, and poor display quality.

[0054] To address the above issues, an embodiment of the present application provides a method for driving a pixel circuit. FIG1 is a schematic diagram of the structure of a pixel circuit provided by an embodiment of the present application. Referring to FIG1 , the pixel circuit includes a data writing module 11, a driving module 12, and a first reset module 13. The data writing module 11 is connected to the driving module 12, and the first reset module 13 is connected to the control terminal of the driving module 12.

[0055] The data writing module 11 can be connected to the control terminal of the driving module 12. The data writing module 11 is connected to the data line Data and transmits the data voltage on the data line Data to the control terminal of the driving module 12. The data writing module 11 can also be connected to the first terminal of the driving module 12 and write the data voltage from the first terminal of the driving module 12 to the control terminal of the driving module 12. Figure 1 shows the connection between the data writing module 11 and the control terminal of the driving module 12.

[0056] The first reset module 13 is connected to the control end of the driving module 12. The first reset module 13 is connected to the first reset voltage Vref1, so that the first reset module 13 can transmit the first reset voltage Vref1 to the control end of the driving module 12 to reset the control end of the driving module 12. The first end of the driving module 12 can be connected to the first power supply VDD. The pixel circuit can also include a light-emitting module 14. The second end of the driving module 12 can be connected to the first end of the light-emitting module 14, and the second end of the light-emitting module 14 is connected to the second power supply VSS. The voltage of the first power supply VDD can be a positive voltage, and the voltage of the second power supply VSS can be zero or a negative voltage. In this way, a current loop can be formed between the first power supply VDD, the driving module 12, the light-emitting module 14, and the second power supply VSS. The driving module 12 can generate a driving current according to the data voltage, and the light-emitting module 14 can emit light in response to the driving current.

[0057] The pixel circuit can be connected to a gate drive circuit, which provides a gate drive signal to the pixel circuit. The gate drive signal can control whether the first reset module 13 is turned on and whether the data write module 11 is turned on. The gate drive signals written to the first reset module 13 and the data write module 11 are different. For example, the control end of the first reset module 13 is connected to the first gate drive line S1, which provides the first gate drive signal to the first reset module 13. The control end of the data write module 11 is connected to the second gate drive line S2, which provides the second gate drive signal to the data write module 11.

[0058] FIG2 is a flow chart of a method for driving a pixel circuit according to an embodiment of the present application. Referring to FIG2 , within a display frame, the method for driving a pixel circuit includes:

[0059] S101 : In a first reset phase, controlling a first reset module to reset a control terminal of a driving module at least once.

[0060] For example, FIG3 is a driving timing diagram of a pixel circuit provided by an embodiment of the present application. As shown in FIG1 and FIG3, in the first reset phase t01, the first gate drive signal Scan1 transmitted by the first gate drive line S1 is at an effective level, and the first reset module 13 is controlled to be turned on at least once, so that the first reset module 13 transmits the first reset voltage Vref1 to the control terminal of the drive module 12 at least once, and resets the control terminal of the drive module 12 at least once. In this way, the residual charge of the previous frame can be cleared, and a reverse voltage stress (opposite to the voltage stress when the drive module 12 is turned on) can be applied to the drive module 12, thereby reducing the degree of characteristic deviation caused by the long-term conduction of the drive module 12, improving the characteristics of the drive module 12, and avoiding the ghosting problem caused by the change in the characteristics of the drive module 12 when it was turned on in the previous frame, which is conducive to improving the display effect of the display panel where the pixel circuit is located.

[0061] During the first reset phase, the first reset module 13 can reset the control terminal of the driver module 12 multiple times, thereby applying reverse voltage stress to the driver module 12 multiple times, further improving the characteristics of the driver module 12. Even driver modules 12 with large characteristic deviations can effectively restore their characteristics, allowing each driver module 12 to effectively restore its characteristics before generating a driving current. The upper limit of the number of times the first reset module 13 is turned on during the first reset phase can be determined based on actual conditions, for example, based on the proportion of the non-light-emitting phase in a driving cycle.

[0062] When the first reset module 13 resets the control end of the driving module 12 in the first reset phase, the reset can be performed multiple times continuously or multiple times intermittently.

[0063] S102 : In a second reset phase, controlling the first reset module to reset the control end of the driving module at least once.

[0064] For example, as shown in Figures 1 and 3, in the second reset phase t02, the first gate drive signal Scan1 transmitted by the first gate drive line S1 is at an active level, controlling the first reset module 13 to be turned on at least once, so that the first reset module 13 transmits the first reset voltage Vref1 to the control terminal of the driver module 12 at least once, resetting the control terminal of the driver module 12 at least once. In this way, the control terminal of the driver module 12 can be continuously reset, increasing the number and duration of reverse voltage stress applied to the driver module 12, thereby improving the characteristics of the driver module 12 and providing time for the driver module 12 to recover its characteristics. This can ensure that the characteristics are well restored when the driver module 12 generates a driving current. Therefore, even a driver module 12 with a large characteristic deviation can still recover its characteristics well, ensuring that the characteristics of each driver module 12 are well restored. This ensures that the driving current generated by the driver module 12 is consistent under the same grayscale, and the luminance of the light-emitting modules 14 is consistent, thereby improving the display uniformity of the display panel and improving the display effect of the display panel. Furthermore, it can avoid the problem of sliding color deviation caused by the characteristics of the driving module 12 not being restored after the screen is switched, resulting in different driving currents generated by different driving modules 12 when the first frame is displayed, and large differences in the luminous efficiency of the light-emitting modules 14 of different luminous colors. This can avoid the ghosting phenomenon.

[0065] When the first reset module 13 resets the control end of the driving module 12 in the second reset phase, the reset can be performed multiple times continuously or multiple times intermittently.

[0066] S103 , in a first data writing phase, controlling the data writing module to write the first data voltage into the control terminal of the driving module at least once.

[0067] For example, as shown in FIG1 , in the first data writing phase t03 , the second gate drive signal Scan2 on the second gate drive line S2 is at an active level, controlling the data writing module 11 to be turned on, causing the data writing module 11 to transmit the first data voltage on the data line Data to the control terminal of the driving module 12 , so that the driving module 12 generates a driving current based on the first data voltage, and the light-emitting module 14 emits light in response to the driving current. The first data voltage is the data voltage corresponding to the pixel circuit of the current row.

[0068] The second gate drive signal corresponding to the data writing module 11 is a shift of the first gate drive signal corresponding to the first reset module 13, that is, the second gate drive signal is a next-level signal of the first gate drive signal. In the technical solution of this embodiment, the first gate drive signal is independent of the second gate drive signal. The number and duration of the effective level of the first gate drive signal can be adjusted according to actual needs (such as the degree of image sticking). Therefore, the first gate drive signal can be adjusted for different operating states (such as different images displayed on the display panel), thereby better restoring the characteristics of the driver module 12.

[0069] The above-mentioned effective level can be a high level or a low level, that is, the data writing module 11 and the first reset module 13 can be turned on in response to a high level or a low level. FIG3 illustrates the case where the effective level is a low level.

[0070] The technical solution of this embodiment controls the first reset module to reset the control terminal of the driver module at least once in the first reset phase, and controls the second reset module to reset the control terminal of the driver module at least once in the second reset phase. This allows the control terminal of the driver module to be reset at least twice, thereby increasing the duration and number of times reverse voltage stress is applied to the driver module. Even driver modules with large characteristic deviations can effectively recover their characteristics, allowing each driver module to effectively recover its characteristics. At the same grayscale, the driving currents generated by different driver modules tend to be consistent, resulting in consistent luminance of different light-emitting modules. This improves the display uniformity of the display panel, avoids ghosting, and enhances the display quality of the display panel.

[0071] Based on the above technical solution, the following describes the stages that the driving method may further include.

[0072] FIG4 is a flowchart of another method for driving a pixel circuit provided in an embodiment of the present application. Optionally, referring to FIG4 , within a display frame, the method for driving a pixel circuit includes:

[0073] S201 : In a first reset phase, controlling a first reset module to reset a control terminal of a driving module at least once.

[0074] Exemplarily, Figure 5 is a driving timing diagram of another pixel circuit provided in an embodiment of the present application. As shown in Figure 5, in the first reset stage t11, the first gate drive signal Scan1 on the first gate drive line S1 is at a valid level, and the first reset module 13 is controlled to reset the control end of the drive module 12.

[0075] S202 , executing a second data writing phase; wherein, in the second data writing phase, the data writing module writes the second data voltage to the control terminal of the driving module at least once.

[0076] The second data voltage is the first data voltage corresponding to the pixel circuits in the preceding rows of the current row. For example, the current row is row a, and the preceding rows are rows ab, where b can be a positive integer greater than or equal to 1. Because when the current row executes the second data write phase, the preceding rows have already or are in the first data write phase, the second data write phase can write the first data voltages of the preceding rows to perform data pre-charging. When the image to be displayed is a solid color image, the first data voltage is equal to the second data voltage, that is, the data voltages corresponding to the preceding rows are the same as the data voltages corresponding to the current row. When the image to be displayed is not a solid color image, the first data voltage is different from the second data voltage.

[0077] For example, as shown in Figures 1 and 5, in the second data writing phase t12, the second gate drive signal Scan2 on the second gate drive line S2 is at an active level at least once, controlling the data writing module 11 to be turned on at least once, so that the data writing module 11 transmits the second data voltage to the control terminal of the driving module 12 at least once. The voltage at the first terminal of the driving module 12 is the first power supply voltage, the first power supply voltage can be a positive voltage, and the second data voltage can be a negative voltage. Then, current stress can be applied to the driving module 12, so that all driving modules 12 are unified in advance under the input of the first data voltage, thereby avoiding large differences in the driving current generated by the driving module 12 at the same grayscale, thereby improving display uniformity. By applying current stress to the driving module 12, the characteristics of the driving module 12 are improved, and the driving current generated by the driving module 12 in the first frame after switching the screen can be avoided to be large different from the driving current corresponding to the target brightness, thereby avoiding large differences in the brightness of the first frame after switching the screen and the target brightness, thereby improving the display effect of the display panel.

[0078] Exemplarily, FIG5 shows a situation in which the data writing module 11 is turned on once in the second data writing phase t12.

[0079] S203 : In the second reset phase, control the first reset module to reset the control end of the driving module at least once.

[0080] Exemplarily, as shown in FIG. 5 , in the second reset stage t13 , the first gate driving signal Scan1 on the first gate driving line S1 is at an active level, and the first reset module 13 is controlled to reset the control terminal of the driving module 12 .

[0081] S204 , in a first data writing phase, controlling the data writing module to write the first data voltage into the control terminal of the driving module at least once.

[0082] For example, as shown in FIG5 , in the first data writing phase t14, the second gate drive signal Scan2 on the second gate drive line S2 is at a valid level, and the data writing module 11 is controlled to be turned on, so that the data writing module 11 transmits the first data voltage on the data line Data to the control end of the driving module 12.

[0083] By executing the second reset phase and the first data writing phase, after data pre-charging (the second data writing phase), the charge can be cleared, and when the first data voltage is written in the first data writing phase, that is, when the characteristics of the driving module 12 are restored, the first data voltage is written, which can ensure that the driving module 12 better generates a driving current according to the written first data voltage.

[0084] In some embodiments, optionally, in the second data writing phase, the data writing module 11 writes the second data voltage to the control terminal of the driving module 12 at least twice.

[0085] FIG6 is a driving timing diagram of another pixel circuit provided in an embodiment of the present application. As shown in FIG6 , during the second data writing phase t12, the second gate drive signal Scan2 on the second gate drive line S2 has an active level twice, controlling the data writing module 11 to be turned on twice, so that the data writing module 11 transmits the second data voltage twice to the control terminal of the driving module 12. In this way, the duration and number of times the current stress is applied to the driving module 12 can be increased, which can better improve the characteristics of the driving module 12, reduce the difference between the driving current generated by the driving module 12 and the driving current corresponding to the target brightness, avoid a large difference between the brightness of the first frame after switching the screen and the target brightness, and improve the display effect of the display panel.

[0086] In other embodiments, the data writing module 11 may be controlled to be turned on multiple times during the second data writing phase t12 to increase the duration and number of times the current stress is applied to the driving module 12, thereby further improving the characteristics of the driving module 12. This embodiment does not limit the number of valid levels during the second data writing phase t12.

[0087] The technical solution of this embodiment, by setting the first data writing stage and the second data writing stage, can not only apply current stress to the driving module, but also unify the states of each driving module in advance, so that the driving current generated by all driving modules in the first frame after switching the screen is close to the current corresponding to the target brightness, thereby making the brightness of the display panel in the first frame after switching the screen close to the target brightness.

[0088] Based on the above technical solution, the following describes the stages that the driving method may further include.

[0089] FIG7 is a structural diagram of another pixel circuit provided in an embodiment of the present application. Optionally, as shown in FIG7 , the pixel circuit further includes a light-emitting module 14 , and the driving module 12 is connected to the light-emitting module 14 .

[0090] Optionally, as shown in Figure 7, the pixel circuit also includes a light-emitting control module 15, which is connected between the first power supply VDD and the light-emitting module 14. The control end of the light-emitting control module 15 is connected to the third gate drive line Em. The third gate drive signal EM provided by the third gate drive line Em is used to control the conduction and shutdown of the light-emitting control module 15.

[0091] Optionally, within a display frame, the driving method of the pixel circuit further includes:

[0092] In the light emitting stage, the driving module generates a driving current so that the light emitting module emits light in response to the driving current.

[0093] As shown in FIG6 , in the light-emitting stage t15 , the third gate signal EM is at an effective level, controlling the light-emitting control module 15 to be turned on, so that the first power supply VDD, the driving module 12, the light-emitting control module 15, the light-emitting module 14 and the second power supply VSS form a current loop, the driving module 12 generates a driving current, and the light-emitting module 14 emits light in response to the driving current.

[0094] Optionally, as shown in FIG. 7 , the pixel circuit further includes a threshold compensation module 16 , the control end of which is connected to the second gate drive line S2 , and the threshold compensation module 16 is connected between the second end of the driving module 12 and the control end of the driving module 12 .

[0095] Figure 7 shows the situation where the data writing module 11 is connected to the first end of the driving module 12. When the second gate driving signal Scan2 provided by the second gate driving line S2 is at a valid level, the data writing module 11 and the threshold compensation module 16 are turned on, and the data writing module 11 transmits the data voltage (the first data voltage or the second data voltage) to the control end of the driving module 12 through the driving module 12 and the threshold compensation module 16, thereby writing the data voltage (the first data voltage or the second data voltage) to the control end of the driving module 12.

[0096] Optionally, as shown in FIG7 , the pixel circuit further includes a storage module 17. A first terminal of the storage module 17 is connected to a DC signal, and a second terminal of the storage module 17 is connected to the control terminal of the driver module 12. For example, the first terminal of the storage module 17 is connected to a first power supply VDD. If the potential of the first terminal of the storage module 17 remains unchanged, the potential of the control terminal of the driver module 12 can be maintained.

[0097] FIG8 is a flowchart of another method for driving a pixel circuit provided in an embodiment of the present application. Optionally, referring to FIG8 , within a display frame, the method for driving a pixel circuit includes:

[0098] S301 : In a first reset phase, control a first reset module to reset a control terminal of a driving module at least once.

[0099] FIG9 is a driving timing diagram of another pixel circuit provided in an embodiment of the present application. As shown in FIG9 , in the first reset stage t21 , the first gate drive signal Scan1 on the first gate drive line S1 is at a valid level, the first reset module 13 is turned on, and the control end of the drive module 12 is reset.

[0100] S302 : In the reset maintenance phase, the first reset module and the data writing module are controlled to be turned off, so that the storage module maintains the potential of the control terminal of the driving module.

[0101] For example, as shown in FIG9 , during the reset maintenance phase t22 , the first gate drive signal Scan1 and the second gate drive signal Scan2 are both at an inactive level, and the first reset module 13 and the data writing module 11 are turned off. Because the first reset voltage is written to the control terminal of the driver module 12 during the first reset phase t21 , the storage module 17 can maintain the potential of the control terminal of the driver module 12 , thereby continuously applying a positive voltage stress to the driver module 12 . This allows the driver module 12 to better restore its characteristics. Even if the characteristics of the driver module 12 are significantly offset, the characteristics can be restored well, allowing the driver module 12 to generate a drive current close to or equal to the current corresponding to the target brightness, thereby improving the display effect of the display panel.

[0102] The duration of the reset maintenance phase can be adjusted according to actual needs, for example, according to the degree of afterimage of the display panel or the degree of characteristic deviation of the driving module 12, so that it can be applied to different working states and improve the applicability of the driving method of the pixel circuit.

[0103] S303 , executing a second data writing phase; wherein, in the second data writing phase, the data writing module writes the second data voltage to the control terminal of the driving module at least once.

[0104] As shown in FIG9 , in the second data writing phase t23 , the second gate driving signal Scan2 on the second gate driving line S2 has a valid level twice, controlling the data writing module 11 to be turned on twice, so that the data writing module 11 transmits the second data voltage to the control end of the driving module 12 twice.

[0105] S304 : In the second reset phase, control the first reset module to reset the control end of the driving module at least once.

[0106] As shown in FIG. 9 , in the second reset stage t24 , the first gate driving signal Scan1 on the first gate driving line S1 is at an active level, the first reset module 13 is turned on, and the control terminal of the driving module 12 is reset.

[0107] S305 , in the first data writing phase, controlling the data writing module to write the first data voltage into the control terminal of the driving module at least once.

[0108] As shown in FIG9 , in the first data writing phase t25 , the second gate driving signal Scan2 on the second gate driving line S2 is at an effective level, controlling the data writing module 11 to be turned on, so that the data writing module 11 transmits the first data voltage on the data line Data to the control end of the driving module 12 .

[0109] S306 , in the light-emitting stage, the driving module generates a driving current, so that the light-emitting module emits light in response to the driving current.

[0110] As shown in FIG9 , in the light-emitting stage t26 , the third gate signal EM is at a valid level, controlling the light-emitting control module 15 to be turned on, so that the first power supply VDD, the driving module 12, the light-emitting control module 15, the light-emitting module 14 and the second power supply VSS form a current loop. The driving module 12 generates a driving current according to the first data voltage, and the light-emitting module 14 emits light in response to the driving current.

[0111] In another embodiment, FIG10 is a flowchart of another method for driving a pixel circuit provided in an embodiment of the present application. Optionally, referring to FIG10 , within a display frame, the method for driving a pixel circuit includes:

[0112] S401 : In a first reset phase, control a first reset module to reset a control terminal of a driving module at least once.

[0113] S402. During a portion of the reset maintenance phase, control the first reset module to reset the control end of the driver module at least once, and during another portion of the reset maintenance phase, control the first reset module and the data writing module to be turned off; wherein the other portion of the time period is the period from the end of the last reset of the control end of the driver module by the first reset module to the beginning of the second data writing phase during the reset maintenance phase.

[0114] For example, by controlling the first reset module 13 to reset the control terminal of the driver module 12 at least once during a portion of the reset and maintain phase, the number of times reverse voltage stress is applied to the driver module 12 can be increased, thereby preventing the storage module 17 from being unable to effectively maintain the potential of the control terminal of the driver module 12, resulting in poor characteristic recovery. Furthermore, when the gate drive circuit cannot output an inactive level for a long period of time, the duration of the reset and maintain phase can be guaranteed, ensuring that the characteristics of all driver modules 12 are restored.

[0115] For example, FIG11 is a driving timing diagram of another pixel circuit provided in an embodiment of the present application. As shown in FIG11 , the difference between FIG11 and FIG9 is that, in FIG11 , during a partial period t221 of the reset and maintenance phase t22, the first gate drive signal Scan1 is at an active level, controlling the first reset module 13 to reset the control terminal of the drive module 12 at least once; during the remaining period of the reset phase t22, the first gate drive signal Scan1 and the second gate drive signal Scan2 are both at an inactive level, and the first reset module 13 and the data writing module 11 are turned off. Another partial period t222 is the period between the partial period t221 and the second data writing phase t23. The period during the reset phase t22 when the first gate drive signal Scan1 is at an active level can be the beginning of the reset and maintenance phase t22, the middle of the reset and maintenance phase t22, or the portion before the end of the reset and maintenance phase t22.

[0116] S403 , executing a second data writing phase; wherein, in the second data writing phase, the data writing module writes the second data voltage to the control terminal of the driving module at least once.

[0117] S404 : In the second reset phase, control the first reset module to reset the control end of the driving module at least once.

[0118] S405 , in the first data writing phase, controlling the data writing module to write the first data voltage into the control terminal of the driving module at least once.

[0119] S406 , in the light-emitting stage, the driving module generates a driving current, so that the light-emitting module emits light in response to the driving current.

[0120] The technical solution of this embodiment, by providing a reset-hold phase after the first reset phase, can increase the duration of the reverse voltage stress applied to the driver module, ensuring that the characteristics of the driver module are restored. Furthermore, the duration of the reset-hold phase can be adjusted based on the degree of image sticking on the display panel, thereby improving the applicability of the pixel circuit driving method.

[0121] In some other implementations, the various stages in the driving sequence of the pixel circuit may be executed in another order. Another possible execution order is described below.

[0122] Optionally, the first data writing phase may also be located before the first reset phase; wherein the second reset phase is located before the first data writing phase; in the first data writing phase, the data writing module 11 writes the second data voltage to the control terminal of the driving module 12 at least once; in the second data writing phase, the data writing module 11 writes the first data voltage to the control terminal of the driving module 12 at least once. For example, FIG12 is a driving timing diagram of another pixel circuit provided in an embodiment of the present application. As shown in FIG12 , the difference between FIG12 and FIG9 is that in FIG12 , the first data writing phase t25 is located before the first reset phase t21.

[0123] Exemplarily, when the first data writing phase t25 precedes the first reset phase t21, the driving method is executed in the following order: the second reset phase t24, the first data writing phase t25, the first reset phase t21, the reset maintenance phase t22, the second data writing phase t23, and the light-emitting phase t26. Thus, in the second reset phase t24, the control terminal of the driver module 12 can be reset, and a reverse voltage stress can be applied to the driver module 12 to improve the characteristics of the driver module 12. Then, in the first data writing phase t25, the second data voltage is transmitted to the control terminal of the driver module 12, and a current stress is applied to the driver module 12 to improve the characteristics of the driver module 12. The first reset phase t21 and the reset maintenance phase t22 are then executed to improve the characteristics of the driver module 12, so that the characteristics of all driver modules 12 can be restored. In the second data writing phase t23, the first data voltage is written to the driver module 12 after the characteristics have been restored, so that the driving current generated by the driver module 12 according to the first data voltage can be the same as the current corresponding to the target brightness, thereby improving the display effect of the display panel.

[0124] Based on the above technical solutions, optionally, before the reset and maintenance phase, the driving method of the pixel circuit further includes:

[0125] The duration of the reset maintenance phase is determined according to a test parameter value of the display panel where the pixel circuit is located; wherein the test parameter value at least includes an afterimage value of the display panel.

[0126] Exemplarily, by measuring the brightness difference of the display panel before and after the display panel switches from a non-pure color picture to a pure color picture, the afterimage value of the display panel can be determined. During the test, the duration of the corresponding reset maintenance phase can be tested when the afterimage value is improved well, and the correspondence between the afterimage value and the duration of the reset maintenance phase is stored. When driving the pixel circuit, if the display panel switches from a non-pure color picture to a pure color picture, the brightness value of the display panel can be obtained, and then the afterimage value of the display panel can be determined. According to the correspondence between the afterimage value and the duration of the reset maintenance phase, the duration of the reset maintenance phase can be determined. In this way, the duration of the reset maintenance phase determined according to the afterimage value can better improve the characteristics of the driving module. Regardless of the working conditions, the degree of afterimage can be reduced to a greater extent, so that when switching to the next picture, the brightness of the first frame can be better improved, and the brightness of the first frame is closer to the target brightness.

[0127] Based on the above technical solutions, the following describes the stages that may be included in the driving method. Optionally, as shown in FIG6 , FIG9 or FIG11 , between the second reset stage and the first data writing stage, the driving method of the pixel circuit further includes:

[0128] During the transition phase, the data writing module 11 and the first reset module 13 are controlled to be turned off; wherein, the duration of the reset maintaining phase is longer than the duration of the transition phase.

[0129] For example, as shown in FIG6, FIG9 or FIG11, in the transition phase ty, the first gate drive signal Scan1 and the second gate drive signal Scan2 are both at an invalid level. Because reverse voltage stress has been applied to the driver module 12 for a long time in the first reset phase, the reset maintenance phase and the second reset phase, the bias state of the driver module 12 can be improved. There is no need to perform a long reset maintenance in the transition phase ty, which can avoid a long non-light-emitting phase. In addition, by setting the duration of the reset maintenance phase to be longer than the duration of the transition phase, for example, the duration of the reset maintenance phase is much longer than the duration of the transition phase, that is, the duration of the reset maintenance phase is longer, ensuring that the reset maintenance phase can improve the characteristics of all driver modules 12, and even driver modules 12 with larger characteristic deviations can better recover their characteristics.

[0130] Optionally, as shown in FIG11 , the duration of the other period t222 is longer than the duration of the transition period ty. This ensures that the reset period of the driver module 12 is maintained for a longer period during the reset and maintenance phase, thereby improving the bias state of the driver module 12. Furthermore, the reset and maintenance period does not need to be extended during the transition period ty, thereby avoiding a prolonged non-luminous period.

[0131] Based on the above technical solutions, in some embodiments, the pixel circuit driving method optionally further includes executing at least one first reset phase between the first reset phase and the reset maintenance phase. This can increase the number and duration of reverse voltage stress applied to the driver module 12, improving the characteristics of the driver module 12. This allows even driver modules 12 with significant characteristic deviations to recover their characteristics, thereby ensuring consistent characteristic recovery across all driver modules 12, thereby improving display uniformity across the display panel.

[0132] In some embodiments, between the reset and hold phase and the second data writing phase, the pixel circuit driving method further includes executing at least one first reset phase and at least one reset and hold phase. This can significantly improve the characteristics of the driver modules 12, allowing even driver modules 12 with significant characteristic deviations to recover their characteristics, thereby ensuring consistent characteristic recovery across all driver modules 12 and improving display uniformity across the display panel.

[0133] Based on the above technical solution, the following describes the stages that the driving method may further include.

[0134] Optionally, as shown in Figure 7, the pixel circuit also includes a second reset module 18, which is connected to the light-emitting module 14; for example, the control end of the second reset module 18 is connected to the first gate drive line S1, the first end of the second reset module 18 is connected to the second reset voltage Vref2, and the second end of the second reset module 18 is connected to the first end of the light-emitting module 14.

[0135] Optionally, the pixel circuit driving method further includes:

[0136] In the first reset stage, controlling the second reset module to reset the light emitting module 14 at least once;

[0137] In the second reset stage, the second reset module is controlled to reset the light emitting module 14 at least once.

[0138] For example, in the first reset phase, the first gate drive signal Scan1 is at an active level, controlling the second reset module 18 to conduct, and the second reset module 18 transmits the second reset voltage Vref2 to the first terminal of the light-emitting module 14, thereby resetting the light-emitting module 14 at least once. In the second reset phase, the first gate drive signal Scan1 is at an active level, controlling the second reset module 18 to conduct, and the second reset module 18 resets the light-emitting module 14 at least once. Thus, the residual charge on the first terminal of the light-emitting module 14 can be cleared, allowing the light-emitting module 14 to more accurately display the target brightness.

[0139] A voltage difference between the second reset voltage Vref2 and the voltage of the second end of the light emitting module 14 (the voltage of the second power supply VSS) is smaller than the turn-on voltage of the light emitting module 14 .

[0140] On the basis of the above technical solutions, optionally, the single effective pulse widths of the control signals of the first reset module 13 are all the same;

[0141] The single effective pulse width of the control signal of the first reset module 13 is n times the single effective pulse width of the control signal of the data write module.

[0142] The control signal of the first reset module 13 is the first gate drive signal. The control signal of the first reset module 13 is the same control signal, and the single effective pulse width on the same control signal is the same. The control signal of the data writing module 11 is the second gate drive signal.

[0143] Exemplarily, in both the first reset phase and the second reset phase, the first reset module operates in response to the first gate drive signal, so the single effective pulse width in the first reset phase and the second reset phase is the same. Because the multiple pixel circuits are arranged in an array, data is written row by row. Therefore, the single effective pulse width of the control signal of the data write module 11 is at most one row time, that is, the single effective pulse width of the control signal of the data write module 11 is less than or equal to one row time. When resetting the control end of the driver module 12, the reset can be performed row by row, or at least two rows can be reset simultaneously. That is, the single effective pulse width of the control signal (first gate drive signal) of the first reset module can be one row time, two row times, or multiple row times. Therefore, the single effective pulse width of the control signal of the first reset module 13 is n times the single effective pulse width of the control signal of the data write module 11. When the single effective pulse width of the control signal of the data write module 11 is equal to one row time, n is an integer. When the single effective pulse width of the control signal of the data write module 11 is less than one row time, n may not be an integer. In this way, the number of first gate driving signals can be reduced, the number of gate driving circuits can be reduced, and space can be reduced.

[0144] Optionally, n is an integer greater than or equal to 1. In this case, the single effective pulse width of the control signal of the data writing module 11 is equal to one line time, which can achieve sufficient data writing and ensure that the data voltage (the first data voltage or the second data voltage) is completely written to the driving module 12.

[0145] Optionally, n is 1 or 2.

[0146] In one embodiment, Figure 13 is a driving timing diagram of another pixel circuit provided in an embodiment of the present application. As shown in Figure 13, the single effective pulse width of the control signal (first gate drive signal Scan1) of the first reset module 13 is the same as the single effective pulse width of the control signal (second gate drive signal Scan2) of the data write module 11, that is, the single effective pulse width of the control signal (first gate drive signal Scan1) of the first reset module 13 is 1 times the single effective pulse width of the control signal (second gate drive signal Scan2) of the data write module 11.

[0147] In another embodiment, Figure 14 is a driving timing diagram of another pixel circuit provided in an embodiment of the present application. As shown in Figure 14, the single effective pulse width of the control signal (first gate drive signal Scan1) of the first reset module 13 is twice the single effective pulse width of the control signal (second gate drive signal Scan2) of the data writing module 11, so that the first gate drive signal Scan1 can simultaneously drive the first reset modules 13 in two rows of pixel circuits to turn on, which can reduce the number of gate drive circuits and save space.

[0148] In some other implementations, n may also be an integer greater than or equal to 3, and the first gate driving signal may simultaneously drive the first reset modules in multiple rows of pixel circuits to turn on, thereby reducing the number of gate driving circuits.

[0149] As shown in FIG14 , when n is 2, one first gate drive signal Scan1 corresponds to two rows of pixel circuits, and one second gate drive signal Scan2 corresponds to one row of pixel circuits. Thus, the 2m-1th row of pixel circuits and the 2mth row of pixel circuits correspond to the mth first gate drive signal Scan1(m), the 2m-1th row of pixel circuits correspond to the 2m-1th second gate drive signal Scan2(2m-1), and the 2mth row of pixel circuits correspond to the 2mth second gate drive signal Scan2(2m). During the first data writing phase t24, the 2m-1th second gate drive signal Scan2(2m-1) and the 2mth second gate drive signal Scan2(2m) sequentially output valid levels. During the second data writing phase t23, if the second data voltage is written only once to the control terminal of the driver module 12, the 2m-1th second gate drive signal Scan2(2m-1) and the 2mth second gate drive signal Scan2(2m) sequentially output valid levels. During the second data writing phase t23, if the second data voltage is written at least twice to the control terminal of the driver module 12, the 2m-1th second gate driving signal Scan2(2m-1) and the 2mth second gate driving signal Scan2(2m) alternately output an active level. That is, when the data voltage (the first data voltage or the second data voltage) is written at least twice, the data voltage (the first data voltage or the second data voltage) is alternately written to two adjacent rows of pixel circuits, thereby implementing data writing to the two adjacent rows of pixel circuits. Here, m is an integer greater than or equal to 1.

[0150] In another embodiment, FIG15 is a flowchart of another method for driving a pixel circuit provided in an embodiment of the present application. Referring to FIG15 , within a display frame, the method for driving a pixel circuit includes:

[0151] S501 : In a first reset phase, control a first reset module to reset a control terminal of a driving module at least once.

[0152] For example, FIG16 is a driving timing diagram of another pixel circuit provided in an embodiment of the present application. As shown in FIG16 , in the first reset phase t31, the first gate drive signal Scan1 on the first gate drive line S1 is at an effective level, controlling the first reset module 13 to be turned on at least once, so that the first reset module 13 transmits the first reset voltage Vref1 to the control terminal of the drive module 12 at least once, resetting the control terminal of the drive module 12 at least once. In this way, the residual charge of the previous frame can be cleared, and a reverse voltage stress (opposite to the voltage stress when the drive module 12 is turned on) can be applied to the drive module 12, thereby improving the characteristics of the drive module 12 and avoiding the ghosting problem caused by the change in the characteristics of the drive module 12 when the previous frame was turned on, which is conducive to improving the display effect of the display panel where the pixel circuit is located. Furthermore, in the first reset phase, the first reset module 13 can reset the control end of the driving module 12 multiple times, thereby applying reverse voltage stress to the driving module 12 multiple times, thereby better improving the characteristics of the driving module 12. Even if the driving module 12 has a large characteristic deviation, the characteristics can be well restored, so that each driving module 12 can better restore the characteristics before generating a driving current.

[0153] S502 : In the second data writing phase, controlling the data writing module to write the second data voltage into the control terminal of the driving module at least once.

[0154] For example, as shown in FIG16 , during the second data writing phase t32 , the second gate drive signal Scan2 on the second gate drive line S2 is at an active level at least once, controlling the data writing module 11 to be turned on at least once, so that the data writing module 11 transmits the second data voltage to the control terminal of the driving module 12 at least once. The voltage at the first terminal of the driving module 12 is the first power supply voltage, which may be a positive voltage, and the second data voltage is a negative voltage. Current stress can be applied to the driving module 12, so that all driving modules 12 are unified in advance under the input of the first data voltage, thereby avoiding large differences in the driving current generated by the driving module 12 at the same grayscale, thereby improving display uniformity. By applying current stress to the driving module 12, the characteristics of the driving module 12 are improved, and the driving current generated by the driving module 12 in the first frame after switching the screen is prevented from being significantly different from the driving current corresponding to the target brightness, thereby avoiding a large difference in the brightness of the first frame after switching the screen from being significantly different from the target brightness, thereby improving the display effect of the display panel.

[0155] S503 : In the first data writing phase, control the data writing module to write the first data voltage into the control terminal of the driving module at least once.

[0156] For example, as shown in FIG16 , in the first data writing phase t33, the second gate driving signal Scan2 on the second gate driving line S2 is at a valid level, and the data writing module 11 is controlled to be turned on, so that the data writing module 11 transmits the first data voltage on the data line Data to the control end of the driving module 12, so that the driving module 12 generates a driving current according to the first data voltage, and the light-emitting module 14 emits light in response to the driving current.

[0157] The technical solution of this embodiment, by setting the first data writing stage and the second data writing stage, can not only apply current stress to the driving module, but also unify the states of each driving module in advance, so that the driving current generated by all driving modules in the first frame after switching the screen is close to the current corresponding to the target brightness, thereby making the brightness of the display panel in the first frame after switching the screen close to the target brightness.

[0158] Based on the above technical solution, FIG17 is a flowchart of another pixel circuit driving method provided in an embodiment of the present application. Optionally, referring to FIG17 , within a display frame, the pixel circuit driving method includes:

[0159] S601 : In a first reset phase, control a first reset module to reset a control terminal of a driving module.

[0160] Figure 18 is a driving timing diagram of another pixel circuit provided in an embodiment of the present application. As shown in Figure 18, in the first reset stage t41, the first gate drive signal Scan1 on the first gate drive line S1 is at a valid level, controlling the first reset module 13 to be turned on at least once, so that the first reset module 13 transmits the first reset voltage Vref1 to the control end of the drive module 12 at least once, and resets the control end of the drive module 12 at least once.

[0161] S602 : In the reset maintenance phase, the first reset module and the data writing module are controlled to be turned off, so that the storage module maintains the potential of the control terminal of the driving module.

[0162] For example, as shown in FIG18 , during the reset maintenance phase t42 , the first gate drive signal Scan1 and the second gate drive signal Scan2 are both at an inactive level, and the first reset module 13 and the data writing module 11 are turned off. Because the first reset voltage is written to the control terminal of the driver module 12 during the first reset phase t41 , the storage module 17 can maintain the potential of the control terminal of the driver module 12 , thereby continuously applying a positive voltage stress to the driver module 12 . This allows the driver module 12 to better recover its characteristics. Even if the characteristics of the driver module 12 are significantly offset, the characteristics can still be well recovered, allowing the driver module 12 to generate a drive current close to or equal to the current corresponding to the target brightness, thereby improving the display effect of the display panel.

[0163] The duration of the reset maintenance phase can be adjusted according to actual needs, for example, according to the degree of afterimage of the display panel or the offset degree of the driving module 12, so that it can be applied to different working states and improve the applicability of the driving method of the pixel circuit.

[0164] S603 : In the second data writing phase, control the data writing module to write the second data voltage into the control terminal of the driving module at least once.

[0165] For example, as shown in FIG18 , in the second data writing phase t43, the second gate drive signal Scan2 on the second gate drive line S2 has a valid level twice, controlling the data writing module 11 to be turned on twice, so that the data writing module 11 transmits the second data voltage to the control end of the driving module 12 twice.

[0166] S604 : In the first data writing phase, control the data writing module to write the first data voltage to the control terminal of the driving module at least once.

[0167] For example, as shown in Figure 18, in the first data writing stage t44, the second gate drive signal Scan2 on the second gate drive line S2 is at a valid level, controlling the data writing module 11 to be turned on, so that the data writing module 11 transmits the first data voltage on the data line Data to the control end of the driving module 12.

[0168] The technical solution of this embodiment, by providing a reset-hold phase after the first reset phase, can increase the duration of the reverse voltage stress applied to the driver module, ensuring that the characteristics of the driver module are restored. Furthermore, the duration of the reset-hold phase can be adjusted based on the degree of image sticking on the display panel, thereby improving the applicability of the pixel circuit driving method.

[0169] In another embodiment, FIG19 is a flowchart of another method for driving a pixel circuit provided in an embodiment of the present application. Optionally, referring to FIG19 , within a display frame, the method for driving a pixel circuit includes:

[0170] S701 : In a first reset phase, control a first reset module to reset a control terminal of a driving module.

[0171] S702. During a portion of the reset maintenance phase, control the first reset module to reset the control end of the driver module at least once, and during another portion of the reset maintenance phase, control the first reset module and the data writing module to be turned off; wherein the other portion of the time period is the period from the end of the last reset of the control end of the driver module by the first reset module in the reset maintenance phase to the beginning of the second data writing phase.

[0172] For example, FIG20 is a driving timing diagram of another pixel circuit provided in an embodiment of the present application. As shown in FIG20 , the difference between FIG20 and FIG18 is that in FIG20 , during a partial period t421 of the reset and maintenance phase t42, the first gate drive signal Scan1 is at an active level, controlling the first reset module 13 to reset the control terminal of the driver module 12 at least once; during the remaining period of the reset phase t42, the first gate drive signal Scan1 and the second gate drive signal Scan2 are both at an inactive level, and the first reset module 13 and the data writing module 11 are turned off. Another partial period t422 is the period between the partial period t421 and the second data writing phase t43. The period during the reset phase t42 when the first gate drive signal Scan1 is at an active level can be the beginning of the reset and maintenance phase t42, the middle of the reset and maintenance phase t42, or the portion before the end of the reset and maintenance phase t42.

[0173] By increasing the number of times reverse voltage stress is applied to the driver module 12, the problem of poor characteristic recovery caused by the inability of the storage module 17 to properly maintain the potential of the control terminal of the driver module 12 can be avoided. Furthermore, when the gate drive circuit cannot output an inactive level for a long period of time, the duration of the reset maintenance phase can be guaranteed, ensuring that the characteristics of all driver modules 12 are restored.

[0174] S703 : In the second data writing phase, control the data writing module to write the second data voltage into the control terminal of the driving module at least once.

[0175] S704 , in the first data writing phase, controlling the data writing module to write the first data voltage to the control terminal of the driving module at least once.

[0176] In another embodiment, FIG21 is a flowchart of another method for driving a pixel circuit provided in an embodiment of the present application. Referring to FIG21 , within a display frame, the method for driving a pixel circuit includes:

[0177] S801 : In a first reset phase, control a first reset module to reset a control terminal of a driving module.

[0178] Figure 22 is a driving timing diagram of another pixel circuit provided in an embodiment of the present application. As shown in Figure 12, in the first reset stage t51, the first gate drive signal Scan1 on the first gate drive line S1 is at a valid level, controlling the first reset module 13 to be turned on at least once, so that the first reset module 13 transmits the first reset voltage Vref1 to the control end of the drive module 12 at least once, and resets the control end of the drive module 12 at least once.

[0179] S802 : In the reset maintenance phase, the first reset module and the data writing module are controlled to be turned off, so that the storage module maintains the potential of the control terminal of the driving module.

[0180] For example, as shown in FIG22 , during the reset maintenance phase t52 , the first gate drive signal Scan1 and the second gate drive signal Scan2 are both at an inactive level, and the first reset module 13 and the data writing module 11 are turned off. Because the first reset voltage is written to the control terminal of the driver module 12 during the first reset phase t51 , the storage module 17 can maintain the potential of the control terminal of the driver module 12, thereby continuously applying a positive voltage stress to the driver module 12. This allows the driver module 12 to better restore its characteristics. Even if the characteristics of the driver module 12 are significantly offset, the characteristics can still be restored well, so that the driving current generated by the driver module 12 is close to or equal to the current corresponding to the target brightness, thereby improving the display effect of the display panel.

[0181] The duration of the reset maintenance phase can be adjusted according to actual needs, for example, according to the degree of afterimage of the display panel or the offset degree of the driving module 12, so that it can be applied to different working states and improve the applicability of the driving method of the pixel circuit.

[0182] S803 : In the first data writing phase, control the data writing module to write the first data voltage into the control terminal of the driving module at least once.

[0183] As shown in Figure 22, in the first data writing stage t53, the second gate driving signal Scan2 on the second gate driving line S2 is at a valid level, controlling the data writing module 11 to be turned on, so that the data writing module 11 transmits the first data voltage on the data line Data to the control end of the driving module 12.

[0184] In another embodiment, FIG23 is a flowchart of another method for driving a pixel circuit provided in an embodiment of the present application. Referring to FIG23 , within a display frame, the method for driving a pixel circuit includes:

[0185] S901 : In a first reset phase, control a first reset module to reset a control terminal of a driving module.

[0186] S902. During a portion of the reset maintenance phase, control the first reset module to reset the control end of the driver module at least once, and during another portion of the reset maintenance phase, control the first reset module and the data writing module to be turned off; wherein the other portion of the time period is the period from the end of the last reset of the control end of the driver module by the first reset module in the reset maintenance phase to the beginning of the first data writing phase.

[0187] For example, FIG24 is a driving timing diagram of another pixel circuit provided in an embodiment of the present application. As shown in FIG24 , the difference between FIG24 and FIG22 is that, in FIG24 , during a partial period t521 of the reset and maintenance phase t52, the first gate drive signal Scan1 is at an active level, controlling the first reset module 13 to reset the control terminal of the driver module 12 at least once; during the remaining period of the reset phase t52, the first gate drive signal Scan1 and the second gate drive signal Scan2 are both at an inactive level, and the first reset module 13 and the data writing module 11 are turned off. Another partial period t522 is the period between the partial period t521 and the first data writing phase t53. The period during the reset phase t52 when the first gate drive signal Scan1 is at an active level can be the beginning of the reset and maintenance phase t52, the middle of the reset and maintenance phase t52, or the portion before the end of the reset and maintenance phase t52.

[0188] By increasing the number of times reverse voltage stress is applied to the driver module 12, the problem of poor characteristic recovery caused by the inability of the storage module 17 to properly maintain the potential of the control terminal of the driver module 12 can be avoided. Furthermore, when the gate drive circuit cannot output an inactive level for a long period of time, the duration of the reset maintenance phase can be guaranteed, ensuring that the characteristics of all driver modules 12 are restored.

[0189] S903 , in a first data writing phase, controlling the data writing module to write the first data voltage to the control terminal of the driving module at least once.

[0190] In some embodiments, FIG25 is a driving timing diagram of another pixel circuit provided by an embodiment of the present application. As shown in FIG25 , the single effective pulse width of the first gate drive signal Scan1 is the same as the single effective pulse width of the second gate drive signal Scan2. As shown in FIG25 , within a display frame, the driving timing of the pixel circuit includes the following stages.

[0191] In the first reset phase t61 , the first gate driving signal Scan1 transmits a valid level three times to the first reset module 13 , and controls the first reset module 13 to reset the control terminal of the driving module 12 three times.

[0192] In the reset maintaining phase t62 , the first gate driving signal Scan1 and the second gate driving signal Scan2 are both at an invalid level, and the first reset module 13 and the data writing module 11 are controlled to be turned off.

[0193] In the second reset phase t63 , the first gate driving signal Scan1 transmits a valid level three times to the first reset module 13 , and controls the first reset module 13 to reset the control terminal of the driving module 12 three times.

[0194] During the first data writing phase t64, the second gate drive signal Scan2 transmits an active level three times to the data writing module 11, controlling the data writing module 11 to write the first data voltage three times to the control terminal of the driving module 12. Furthermore, when the second reset phase t63 and the first data writing phase t64 both include multiple active levels, the second reset phase t63 and the first data writing phase t64 can be performed alternately, i.e., during the second reset phase t63 and the first data writing phase t64, the first gate drive signal Scan1 and the second gate drive signal Scan2 alternately output active levels.

[0195] In the light-emitting stage t65, the third gate signal EM is at an effective level, controlling the light-emitting control module 15 to be turned on, so that the first power supply VDD, the driving module 12, the light-emitting control module 15, the light-emitting module 14 and the second power supply VSS form a current loop, the driving module 12 generates a driving current, and the light-emitting module 14 emits light in response to the driving current.

[0196] During the first reset phase t61 and the second reset phase t63, the control terminal of the driver module 12 is reset multiple times. During the reset maintenance phase t62, the electrical stress applied to the driver module 12 is maintained, thereby subjecting the control terminal of the driver module 12 to negative gate bias stress (NBS) for a prolonged period of time. This reduces the impact of positive gate bias stress (PBS) caused by the driver module 12 being on for a long time during the previous display frame. This allows the characteristics of the driver module 12 to be restored before the light-emitting phase, thereby improving the display quality of the display panel. Furthermore, the reset process of the control terminal of the driver module 12 is separated from the data writing process to avoid invalid resets.

[0197] In the timing diagrams provided in the embodiments of the present application, the effective level is a low level and the ineffective level is a high level. In other embodiments, the effective level may also be a high level and the ineffective level may also be a low level.

[0198] An embodiment of the present application also provides a display panel, which includes multiple first gate driving circuits 21, multiple second gate driving circuits 22 and multiple pixel circuits 10; the pixel circuit 10 includes a data writing module 11, a driving module 12 and a first reset module 13; the data writing module 11 is connected to the driving module 12, and the first reset module 13 is connected to the control end of the driving module 12.

[0199] FIG26 is a schematic structural diagram of a display panel provided in an embodiment of the present application. Referring to FIG26 , a first gate driving circuit 21 is connected to the first reset module 13 of k rows of pixel circuits 10. The first gate driving circuit 21 is configured to transmit a first gate driving signal Scan1 to the first reset module 13 of the corresponding k rows of pixel circuits 10.

[0200] A second gate driving circuit 22 is connected to the data writing module 11 of a row of pixel circuits 10, and the second gate driving circuit 22 is used to transmit a second gate driving signal Scan2 to the data writing module 11 of the corresponding row of pixel circuits 10;

[0201] The single effective pulse width of the first gate driving signal Scan1 is n times the single effective pulse width of the second gate driving signal Scan2 .

[0202] Exemplarily, a second gate driver circuit 22 is connected to the data write module 11 of a row of pixel circuits 10, so that the second gate drive signal output by the second gate driver circuit 22 drives the data write module 11 in the row of pixel circuits 10, thereby realizing row-by-row writing of the data voltage (first data voltage or second data voltage). The first gate driver circuit 21 is connected to the first reset module 13 of k rows of pixel circuits 10, and can simultaneously transmit the first gate drive signal Scan1 to k rows of pixel circuits 10, thereby reducing the number of first gate drive signals Scan1 and the number of first gate driver circuits 21, which is conducive to reducing the occupied area. The second gate driver circuit 22 is connected to the data write module 11 of a row of pixel circuits 10, and the second gate drive signal Scan2 can be the same as or less than the row time, that is, the single effective pulse width of the second gate drive signal Scan2 is less than or equal to the row time. If the single effective pulse width of the first gate drive signal Scan1 is k times the row time, then when the single effective pulse width of the second gate drive signal Scan2 is equal to the row time, n is the same as k. When the single effective pulse width of the second gate driving signal Scan2 is less than one line time, n is greater than k, and n is not an integer.

[0203] In one embodiment, optionally, k=n=2. As shown in FIG14 , the single effective pulse width of the first gate drive signal Scan1 is twice the single effective pulse width of the second gate drive signal Scan2, so that the first gate drive signal can simultaneously drive the first reset modules in two rows of pixel circuits to conduct, which can reduce the number of gate drive circuits and save space. Furthermore, k=n, that is, the single effective pulse width of the second gate drive signal Scan2 is equal to a row time, which can fully write the data voltage (the first data voltage or the second data voltage) and ensure the integrity of the written data voltage (the first data voltage or the second data voltage).

[0204] In another embodiment, optionally, k=n=1. FIG27 is a schematic structural diagram of another display panel provided by an embodiment of the present application. Referring to FIG27 , a first gate driving circuit 21 is connected to a first reset module of a row of pixel circuits 10. The first gate driving circuit 21 is used to transmit a first gate driving signal Scan1 to the first reset module 13 of the corresponding row of pixel circuits 10.

[0205] A second gate driving circuit 22 is connected to the data writing module 11 of a row of pixel circuits 10, and the second gate driving circuit 22 is used to transmit a second gate driving signal Scan2 to the data writing module 11 of the corresponding row of pixel circuits 10;

[0206] The single effective pulse width of the first gate driving signal Scan1 is the same as the single effective pulse width of the second gate driving signal Scan2 .

[0207] Exemplarily, the single effective pulse width of the first gate drive signal is the same as the single effective pulse width of the second gate drive signal, that is, the single effective pulse width of the first gate drive signal is 1 times the single effective pulse width of the second gate drive signal. In this way, the drive module can be reset row by row, and the data voltage (first data voltage or second data voltage) can be written to the control terminal of the drive module 12 row by row, facilitating row-by-row control. Furthermore, k=n, that is, the single effective pulse width of the second gate drive signal Scan2 is equal to a row time, which can fully write the data voltage (first data voltage or second data voltage) and ensure the integrity of the written data voltage (first data voltage or second data voltage).

[0208] Optionally, as shown in Figures 26 and 27, the display panel further includes a third gate driver circuit 23, which is connected to the light-emitting control modules 15 of two rows of pixel circuits 10 to provide light-emitting control signals to the light-emitting control modules 15. In this way, the number of third gate driver circuits 23 can be reduced, saving space. In other embodiments, one third gate driver circuit 23 can also be connected to one row of pixel circuits 10.

[0209] Optionally, as shown in Figures 26 and 27 , the pixel circuit 10 may be located in the display area AA of the display panel, and the first gate circuit 21, the second gate circuit 22, and the third electrode circuit 23 may be located in the non-display area NA of the display panel. Figures 26 and 27 illustrate the non-display area NA as larger to illustrate the first gate circuit 21, the second gate circuit 22, and the third electrode circuit 23. However, these figures do not limit the size of the non-display area NA, nor do they limit the proportional relationship between the size of the display area AA and the size of the non-display area NA.

[0210] Due to limited space, the pixel circuit 10 in Figures 26 and 27 only shows the first reset module 13, the data writing module 11, and the light control module 15, and does not show other modules or the connections between them. The structure of the pixel circuit 10 can be referred to Figure 1 or Figure 7. The following describes the possible structure of the pixel circuit 10 in conjunction with the components that each module in Figure 7 may include.

[0211] FIG28 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present application. As shown in FIG28 , the data writing module 11 includes a data writing transistor T1. The control electrode of the data writing transistor T1 is connected to the second gate driving line S2. The first electrode of the data writing transistor T1 is connected to the data line Data. The second electrode of the data writing transistor T1 is connected to the first end of the driving module 12.

[0212] The driving module 12 includes a driving transistor T2;

[0213] The first reset module 13 includes a first reset transistor T3, a control electrode of the first reset transistor T3 is connected to the first gate drive line S1, a first electrode of the first reset transistor T3 is connected to the first reset voltage Vref1, and a second electrode of the first reset transistor T3 is connected to the control electrode of the drive transistor T2; the first reset transistor T3 can be a dual-gate transistor;

[0214] The light emitting module 14 includes a light emitting diode D1;

[0215] The light control module 15 includes a first light control transistor T4 and a second light control transistor T5. The first light control transistor T4 is connected between the first power supply VDD and the first electrode of the driving transistor T2. The second light control transistor T5 is connected between the second electrode of the driving transistor T2 and the first electrode of the light emitting diode D1. The control electrodes of the first light control transistor T4 and the second light control transistor T5 are connected to the third gate drive line Em. The second electrode of the light emitting diode D1 is connected to the second power supply VSS.

[0216] The threshold compensation module 16 includes a threshold compensation transistor T6, which is connected between the first electrode of the driving transistor T2 and the control electrode of the driving transistor T2, and the control electrode of the threshold compensation transistor T6 is connected to the second gate driving line S2; the threshold compensation transistor T6 can be a dual-gate transistor;

[0217] The storage module 17 includes a storage capacitor C1, a first electrode of the storage capacitor C1 is connected to the first power supply VDD, and a second electrode of the storage capacitor C1 is connected to the control electrode of the driving transistor T2;

[0218] The second reset module 18 includes a second reset transistor T7 , a control electrode of the second reset transistor T7 connected to the first gate drive line S1 , a first electrode of the second reset transistor T7 connected to the second reset voltage Vref2 , and a second electrode of the second reset transistor T7 connected to the first electrode of the light emitting diode D1 .

[0219] Illustratively, in the first reset phase, the first gate drive signal provided by the first gate drive line S1 is at an active level at least once, thereby controlling the first reset transistor T1 to be turned on at least once, and controlling the second reset transistor T7 to be turned on at least once, so that the first reset transistor T1 resets the control electrode of the driving transistor T2 at least once, and the second reset transistor T7 can reset the first electrode of the light-emitting diode D1 at least once. In the second reset phase, the first gate drive signal provided by the first gate drive line S1 is at an active level at least once, thereby controlling the first reset transistor T1 to be turned on at least once, and controlling the second reset transistor T7 to be turned on at least once, so that the first reset transistor T1 resets the control electrode of the driving transistor T2 at least once, and the second reset transistor T7 can reset the first electrode of the light-emitting diode D1 at least once. This allows the control electrode of the driving transistor T2 to be reset at least twice, which can increase the duration and number of times the reverse voltage stress is applied to the driving transistor T2. Even when the driving transistor T2 has a large characteristic deviation, the characteristics can be well restored, so that each driving transistor T2 can have a good recovery characteristic. At the same grayscale, the driving currents generated by different driving transistors T2 tend to be consistent, so that the luminous brightness of different light-emitting diodes D1 tends to be consistent, which can improve the display uniformity of the display panel, avoid ghosting, and improve the display effect of the display panel.

[0220] In the first data writing stage, the second gate driving signal provided by the second gate driving line S2 is at an effective level at least once, which can control the data writing transistor T1 and the threshold compensation transistor T6 to be turned on at least once, so that the data writing transistor T1 transmits the data voltage (first data voltage or second data voltage) on the data line Data through the driving transistor T2 and the threshold compensation transistor T6 to the control electrode of the driving transistor T2 at least once.

[0221] In the light-emitting stage, the third gate driving signal provided by the third gate driving line Em is at an effective level, the first light-emitting control transistor T4 and the second light-emitting control transistor T5 are turned on, so that the driving transistor T2 generates a driving current, and the light-emitting diode D1 emits light in response to the driving transistor T2.

[0222] Figure 28 shows a case where all transistors are P-type transistors. In other embodiments, all transistors in the pixel circuit may be N-type transistors, or some transistors may be N-type transistors and the other may be P-type transistors.

[0223] The various forms of processes shown above can be used to reorder, add, or delete steps. For example, the multiple steps described in this application can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of this application can be achieved.

Claims

1. A driving method for a pixel circuit, the pixel circuit comprising a data writing module, a driving module and a first reset module; the data writing module is connected to the driving module, and the first reset module is connected to a control end of the driving module; In one display frame, the method comprises: In a first reset stage, controlling the first reset module to reset the control end of the driving module at least once; In the second resetting stage, controlling the first resetting module to reset the control end of the driving module at least once; In the first data writing phase, the data writing module is controlled to write the first data voltage to the control terminal of the driving module at least once.

2. The method according to claim 1, further comprising: Between the first reset phase and the second reset phase, a second data writing phase is performed: In the second data writing stage, the data writing module is controlled to write the second data voltage to the control end of the driving module at least once; or, in the second data writing stage, the data writing module is controlled to write the second data voltage to the control end of the driving module at least twice; Wherein, the pixel circuit further includes a light emitting module, and the driving module is connected to the light emitting module; and the method further includes: In the light-emitting stage, the driving module is controlled to generate a driving current, so that the light-emitting module emits light in response to the driving current.

3. The method according to claim 2, wherein: The pixel circuit further includes a storage module, a first end of the storage module is connected to a DC signal, and a second end of the storage module is connected to a control end of the driving module; Between the first resetting phase and the second data writing phase, the method further includes: In the reset and maintenance phase, the first reset module and the data writing module are controlled to be turned off so that the storage module maintains the potential of the control end of the driving module; or, in a part of the reset and maintenance phase, the first reset module is controlled to reset the control end of the driving module at least once, and in another part of the reset and maintenance phase, the first reset module and the data writing module are controlled to be turned off; wherein the other part of the reset and maintenance phase is the period from the end of the last reset of the control end of the driving module by the first reset module in the reset and maintenance phase to the beginning of the second data writing phase; Alternatively, the first data writing phase is located before the first resetting phase; in the first data writing phase, the data writing module is controlled to write the second data voltage to the control end of the driving module at least once; in the second data writing phase, the data writing module is controlled to write the first data voltage to the control end of the driving module at least once; wherein the second resetting phase is located before the first resetting phase; Before the first data writing phase.

4. The method according to claim 3, before the reset maintenance phase, the method further comprises: The duration of the reset maintenance phase is determined according to a test parameter value of the display panel where the pixel circuit is located; wherein the test parameter value at least includes an afterimage value of the display panel.

5. The method according to claim 3, between the second resetting phase and the first data writing phase, the method further comprises: In the transition phase, controlling the data writing module and the first reset module to be turned off; The duration of the reset maintenance phase is longer than the duration of the transition phase, or the duration of another part of the reset maintenance phase is longer than the duration of the transition phase.

6. The method according to claim 3, between the first reset phase and the reset maintenance phase, the method further comprises performing at least one of the first reset phases; Alternatively, between the reset maintenance phase and the second data writing phase, the method further comprises executing at least one of the first reset phase and at least one of the reset maintenance phase; in, The pixel circuit further includes a second reset module, and the second reset module is connected to the light emitting module; the method further includes: In the first resetting stage, controlling the second resetting module to reset the light emitting module at least once; In the second resetting stage, the second resetting module is controlled to reset the light emitting module at least once.

7. The method according to claim 1, wherein: The single effective pulse widths of the control signals of the first reset modules are all the same; The single effective pulse width of the control signal of the first reset module is n times the single effective pulse width of the control signal of the data writing module; Wherein, n is an integer greater than or equal to 1; or, n is 1 or 2.

8. A driving method for a pixel circuit, the pixel circuit comprising a data writing module, a driving module and a first reset module; the data writing module is connected to the driving module, and the first reset module is connected to a control end of the driving module; In one display frame, the method comprises: In a first reset stage, controlling the first reset module to reset the control end of the driving module at least once; In the second data writing phase, controlling the data writing module to write the second data voltage to the control end of the driving module at least once; In the first data writing phase, the data writing module is controlled to write the first data voltage to the control terminal of the driving module at least once.

9. The method according to claim 8, wherein: The pixel circuit further includes a storage module, a first end of the storage module is connected to a DC signal, and a second end of the storage module is connected to a control end of the driving module; between the first reset phase and the second data writing phase; the method further includes: In the reset maintenance phase, the first reset module and the data writing module are controlled to be turned off, so that the storage module maintains the potential of the control end of the driving module; Alternatively, during a partial period of the reset maintenance phase, the first reset module is controlled to reset the control end of the driving module at least once, and during another partial period of the reset maintenance phase, the first reset module and the data writing module are controlled to be turned off; wherein the other partial period of the reset maintenance phase is the period from the end of the last time the first reset module resets the control end of the driving module during the reset maintenance phase to the beginning of the second data writing phase.

10. The method according to claim 9, between the second data writing phase and the first data writing phase, the method further comprises: In the second resetting stage, controlling the first resetting module to reset the control end of the driving module at least once; Alternatively, in the second data writing phase, controlling the data writing module to write the second data voltage to the control end of the driving module at least twice; Alternatively, the first data writing stage is located before the first resetting stage; in the first data writing stage, the data writing module is controlled to write the second data voltage to the control end of the driving module at least once; in the second data writing stage, the data writing module is controlled to write the first data voltage to the control end of the driving module at least once; wherein the second resetting stage is located before the first data writing stage; Alternatively, the pixel circuit further includes a light emitting module, and the driving module is connected to the light emitting module; and the method further includes: In the light-emitting stage, controlling the driving module to generate a driving current so that the light-emitting module emits light in response to the driving current; Alternatively, the pixel circuit further includes a second reset module, and the second reset module is connected to the light emitting module; and the method further includes: In the first resetting stage, controlling the second resetting module to reset the light emitting module at least once; In the second reset stage, the second reset module is controlled to perform at least one Reset again.

11. The method according to claim 10, between the second resetting phase and the first data writing phase, the method further comprises: In the transition phase, controlling the data writing module and the first reset module to be turned off; The duration of the reset maintenance phase is longer than the duration of the transition phase; or the duration of another part of the reset maintenance phase is longer than the duration of the transition phase.

12. The method according to claim 9, before the reset maintenance phase, the method further comprises: The duration of the reset maintenance phase is determined according to a test parameter value of the display panel where the pixel circuit is located; wherein the test parameter value at least includes an afterimage value of the display panel.

13. The method according to claim 9, between the first reset phase and the reset maintenance phase, the method further comprises performing at least one of the first reset phases; Alternatively, between the reset and maintenance phase and the second data writing phase, the method further comprises executing at least one of the first reset phase and at least one of the reset and maintenance phases.

14. The method according to claim 10, wherein: The single effective pulse widths of the control signals of the first reset modules are all the same; The single effective pulse width of the control signal of the first reset module is n times the single effective pulse width of the control signal of the data writing module; Wherein, n is an integer greater than or equal to 1; or, n is 1 or 2.

15. A driving method for a pixel circuit, the pixel circuit comprising a data writing module, a driving module, a first resetting module and a storage module; the data writing module is connected to the driving module, and the first resetting module is connected to a control terminal of the driving module; The first end of the storage module is connected to a DC signal, and the second end of the storage module is connected to the control end of the driving module; In one display frame, the method comprises: In a first reset stage, controlling the first reset module to reset the control end of the driving module at least once; In the reset maintenance phase, the first reset module and the data writing module are controlled to be turned off so that the storage module maintains the potential of the control end of the driving module; or, in a part of the reset maintenance phase, the first reset module is controlled to reset the control end of the driving module at least once, and in another part of the reset maintenance phase, the first reset module and the data writing module are controlled to be turned off; In the first data writing phase, the data writing module is controlled to write the first data voltage at least once. input to the control end of the driving module; Another part of the reset maintenance phase is the period from the end of the last reset of the control end of the driving module by the first reset module to the start of the first data writing phase in the reset maintenance phase.

16. The method according to claim 15, between the reset maintenance phase and the first data writing phase, the method further comprises: In the second data writing phase, the data writing module is controlled to write the second data voltage to the control end of the driving module at least once; wherein the other part of the period of the reset maintenance phase is the period from the end of the last reset of the control end of the driving module by the first reset module in the reset maintenance phase to the beginning of the second data writing phase; In the second resetting stage, controlling the first resetting module to reset the control end of the driving module at least once; Alternatively, the first data writing stage is located before the first resetting stage; in the first data writing stage, the data writing module is controlled to write the second data voltage to the control end of the driving module at least once; in the second data writing stage, the data writing module is controlled to write the first data voltage to the control end of the driving module at least once; wherein the second resetting stage is located before the first data writing stage; or, in the second data writing stage, the data writing module is controlled to write the second data voltage to the control end of the driving module at least twice; Alternatively, the pixel circuit further includes a light emitting module, and the driving module is connected to the light emitting module; and the method further includes: In the light-emitting stage, the driving module is controlled to generate a driving current, so that the light-emitting module emits light in response to the driving current.

17. The method according to claim 15, before the reset maintenance phase, the method further comprises: The duration of the reset maintenance phase is determined according to a test parameter value of the display panel where the pixel circuit is located; wherein the test parameter value at least includes an afterimage value of the display panel.

18. The method according to claim 16, between the second resetting phase and the first data writing phase, the method further comprises: In the transition phase, controlling the data writing module and the first reset module to be turned off; The duration of the reset maintenance phase is longer than the duration of the transition phase; or the duration of another part of the reset maintenance phase is longer than the duration of the transition phase; Alternatively, between the first reset phase and the reset maintenance phase, the method further comprises executing Perform at least one of the first reset stages; Alternatively, between the reset maintenance phase and the second data writing phase, the method further comprises executing at least one of the first reset phase and at least one of the reset maintenance phase; Wherein, the pixel circuit further includes a second reset module, and the second reset module is connected to the light emitting module; the method further includes: In the first resetting stage, controlling the second resetting module to reset the light emitting module at least once; In the second resetting stage, controlling the second resetting module to reset the light emitting module at least once; Alternatively, the single effective pulse widths of the control signals of the first reset modules are all the same; The single effective pulse width of the control signal of the first reset module is n times the single effective pulse width of the control signal of the data writing module; Wherein, n is an integer greater than or equal to 1; or, n is 1 or 2.

19. A display panel, comprising a plurality of first gate driving circuits, a plurality of second gate driving circuits and a plurality of pixel circuits; the pixel circuit comprises a data writing module, a driving module and a first reset module; the data writing module is connected to the driving module, and the first reset module is connected to a control end of the driving module; The first gate driving circuit is connected to the first reset modules of the k rows of pixel circuits, and the first gate driving circuit is configured to transmit a first gate driving signal to the first reset modules corresponding to the k rows of pixel circuits; The second gate driving circuit is connected to a data writing module of a row of pixel circuits, and the second gate driving circuit is configured to transmit a second gate driving signal to the data writing module corresponding to the row of pixel circuits; The single effective pulse width of the first gate driving signal is n times the single effective pulse width of the second gate driving signal.

20. The display panel according to claim 19, wherein: The k is an integer greater than or equal to 1, and the n is an integer greater than or equal to 1; Wherein, the k is equal to the n; or, k=n=2; or, k=n=1.

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