Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device that improves reliability by reducing positional deviation of an electrode terminal and the occurrence of a gap between a circuit pattern and the electrode terminal in an electrode terminal bonding process. The semiconductor device includes a circuit pattern, a fixing wire pattern, and an electrode terminal. The circuit pattern is electrically connected to the semiconductor element. Both ends of the fixing wire pattern are joined to the circuit pattern, and the fixing wire pattern stands out from the circuit pattern between both ends to form a loop shape. The electrode terminal includes a joint section inserted into the loop shape and joined to the circuit pattern. The joint section is pressed toward the circuit pattern by the fixing wire pattern.

Description

Semiconductor device and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] In a semiconductor device manufacturing method, electrode terminals are ultrasonically bonded to a circuit pattern on an insulating substrate. Patent Document 1 discloses a semiconductor device including a buffer member inserted between the surface electrode of an IGBT and the electrode terminal. The buffer member is provided on the surface electrode of the IGBT before ultrasonic bonding, and the electrode terminal is positioned by the buffer member.

[0003] Japanese Patent Application Laid-Open No. 2014-056917

[0004] If ultrasonic bonding is performed with a gap between the electrode terminal and the circuit pattern, various defects can occur due to factors such as uneven pressure during bonding, uneven bonding area, and uneven contact of the ultrasonic bonding tool, resulting in reduced reliability of the semiconductor device. For example, cracks can be induced on the underside of the insulating substrate.

[0005] In order to solve the above-mentioned problems, the present disclosure aims to provide a semiconductor device that improves reliability by reducing the occurrence of misalignment of electrode terminals and gaps between circuit patterns and electrode terminals during the electrode terminal bonding process.

[0006] The semiconductor device according to the present disclosure includes a circuit pattern, a fixing wire pattern, and an electrode terminal. The circuit pattern is electrically connected to a semiconductor element. The fixing wire pattern has both ends bonded to the circuit pattern and is raised above the circuit pattern between the ends, forming a loop shape. The electrode terminal includes a bonding portion inserted into the loop shape and bonded to the circuit pattern. The bonding portion is pressed toward the circuit pattern by the fixing wire pattern.

[0007] According to the present disclosure, a semiconductor device is provided that improves reliability by reducing the occurrence of misalignment of electrode terminals and gaps between circuit patterns and electrode terminals during the bonding process of the electrode terminals.

[0008] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings.

[0009] 1 is a front view showing the configuration of a semiconductor device in a first embodiment; FIG. 2 is a plan view showing the configuration of a semiconductor device; FIG. 3 is a perspective view showing the configuration of a semiconductor device; FIG. 4 is a flowchart showing a method for manufacturing a semiconductor device in an embodiment; FIG. 5 is a front view showing a state in which a fixing wire pattern has been formed; FIG. 6 is a plan view showing a state in which a fixing wire pattern has been formed; FIG. 7 is a front view showing a state in which an electrode terminal has been inserted; FIG. 8 is a front view showing a state in which an electrode terminal is pressed by a fixing wire pattern; FIG. 9 is a plan view showing a state in which an electrode terminal is pressed by a fixing wire pattern; FIG. 10 is a front view showing the configuration of a semiconductor device in a second embodiment; FIG. 11 is a plan view showing the configuration of a semiconductor device; FIG. 12 is a perspective view showing the configuration of a semiconductor device;

[0010] <First Embodiment> Fig. 1 is a front view showing the configuration of a semiconductor device 101 in a first embodiment. Fig. 2 is a plan view showing the configuration of the semiconductor device 101. Fig. 3 is a perspective view showing the configuration of the semiconductor device 101 (heat sink 1 is not shown). The semiconductor device 101 includes a heat sink 1, an insulating substrate 2, a semiconductor element (not shown), electrode terminals 3, and a fixing wire pattern 4.

[0011] The heat sink 1 is a plate made of a metal such as copper (Cu) or aluminum (Al), or an AlSiC composite material, and has the function of transferring heat generated by electronic components such as semiconductor elements included in the semiconductor device 101 to the outside.

[0012] The insulating substrate 2 is provided on the heat sink 1 via a bonding material 5. The bonding material 5 is, for example, solder, brazing material, or sintered material. The insulating substrate 2 includes a ceramic substrate 2A and a circuit pattern 2B. The ceramic substrate 2A is, for example, alumina (Al ２ O ３ ), aluminum nitride (AlN), silicon nitride (Si ３ N ４The circuit pattern 2B is formed on the upper surface of the ceramic substrate 2A. The circuit pattern 2B is formed from a conductive material such as aluminum (Al), copper (Cu), or an alloy thereof.

[0013] The semiconductor element is electrically connected to the circuit pattern 2B of the insulating substrate 2. The semiconductor element is held to the circuit pattern 2B via, for example, a conductive adhesive (not shown). ２ O ３ , GeO ２ The semiconductor element is preferably a so-called wide bandgap semiconductor such as diamond. The semiconductor element is a power semiconductor element, a control IC (Integrated Circuit) for controlling the power semiconductor element, or the like. The semiconductor element includes, for example, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a Schottky barrier diode, or the like. The semiconductor element may also include an RC-IGBT (Reverse-Conducting IGBT) in which an IGBT and a free wheel diode are formed within a single semiconductor substrate.

[0014] The electrode terminal 3 is, for example, a conductor configured to be connectable to an external circuit provided outside the semiconductor device 101. The electrode terminal 3 is, for example, a metal frame formed by processing a metal plate into a predetermined shape. The electrode terminal 3 includes a joint 3A. The joint 3A is joined to the circuit pattern 2B. For example, the joint 3A is directly joined to the circuit pattern 2B by ultrasonic bonding. The electrode terminal 3 is formed of, for example, aluminum (Al), copper (Cu), or the like. The joint 3A in contact with the circuit pattern 2B may be plated with nickel (Ni).

[0015] The fixing wire pattern 4 has a loop shape. Both ends of the fixing wire pattern 4 are bonded to the circuit pattern 2B. The fixing wire pattern 4 is raised above the circuit pattern 2B between the ends, thereby forming a loop shape relative to the circuit pattern 2B. The fixing wire pattern 4 extends in a direction intersecting the extension direction of the electrode terminal 3. The fixing wire pattern 4 is provided so as to straddle the joint 3A. In the first embodiment, two fixing wire patterns 4 are provided so as to straddle the tip and base of the joint 3A, respectively. The joint 3A is pressed toward the circuit pattern 2B by the fixing wire patterns 4. The lower surface of the joint 3A is in surface contact with the circuit pattern 2B. The fixing wire pattern 4 is formed, for example, of an aluminum wire (Al wire). The fixing wire pattern 4 is formed, for example, by wire bonding.

[0016] FIG. 4 is a flowchart showing a method for manufacturing the semiconductor device 101 according to the embodiment.

[0017] In step S1, a circuit pattern 2B is prepared. Here, an insulating substrate 2 is prepared, which is held by a heat sink 1. A semiconductor element may be bonded to the circuit pattern 2B in advance, or may be bonded later.

[0018] In step S2, a fixing wire pattern 4 having a loop shape is formed. Fig. 5 is a front view showing the state in which the fixing wire pattern 4 has been formed. Fig. 6 is a plan view showing the state in which the fixing wire pattern 4 has been formed. Both ends of the fixing wire pattern 4 are bonded to the circuit pattern 2B. The fixing wire pattern 4 is formed by wire bonding. The fixing wire pattern 4 is formed, for example, so as to extend in the vibration direction of ultrasonic waves in the step of bonding the bonding portion 3A described below.

[0019] In step S3, the electrode terminal 3 is inserted inside the loop shape of the fixing wire pattern 4. Fig. 7 is a front view showing the inserted state of the electrode terminal 3. Fig. 3 shows the state after the insertion of the electrode terminal 3 is completed. Here, the electrode terminal 3 is inserted in a direction perpendicular to the extending direction of the fixing wire pattern 4.

[0020] In step S4, the bonding portion 3A is pressed against the circuit pattern 2B by the fixing wire pattern 4. For example, the fixing wire pattern 4 is pressed from above and deformed, and this deformation presses the bonding portion 3A against the circuit pattern 2B. Fig. 8 is a front view showing the state in which the electrode terminal 3 is pressed by the fixing wire pattern 4. Fig. 9 is a plan view showing the state in which the electrode terminal 3 is pressed by the fixing wire pattern 4. By this step S4, the bonding portion 3A is held in surface contact with the circuit pattern 2B.

[0021] In step S5, the bonding portion 3A held down by the fixing wire pattern 4 and the circuit pattern 2B are ultrasonically bonded together. At this time, the ultrasonic tool applies ultrasonic waves to the upper surface of the bonding portion 3A. Thereafter, predetermined components such as semiconductor elements are encapsulated with an encapsulant, and the semiconductor device 101 is completed.

[0022] Steps S2 and S3 described above determine the placement position of the electrode terminal 3 relative to the circuit pattern 2B. This prevents misalignment of the electrode terminal 3. Steps S4 and S5 ensure that the lower surface of the joining portion 3A of the electrode terminal 3 comes into surface contact with the circuit pattern 2B. This prevents gaps from forming between the circuit pattern 2B and the electrode terminal 3. This reduces defects such as cracks on the lower surface of the insulating substrate 2 during ultrasonic bonding.

[0023] To summarize the above, the semiconductor device 101 in the first embodiment includes a circuit pattern 2B, a fixing wire pattern 4, and an electrode terminal 3. The circuit pattern 2B is electrically connected to the semiconductor element. The fixing wire pattern 4 has both ends bonded to the circuit pattern 2B and is raised above the circuit pattern 2B between the ends, thereby forming a loop shape. The electrode terminal 3 includes a bonding portion 3A inserted into the loop shape and bonded to the circuit pattern 2B. The bonding portion 3A is pressed toward the circuit pattern 2B by the fixing wire pattern 4.

[0024] Such a semiconductor device 101 suppresses misalignment of the electrode terminals 3 with respect to the circuit pattern 2B and the occurrence of gaps between the circuit pattern 2B and the electrode terminals 3. As a result, the reliability of the semiconductor device 101 is improved.

[0025] In the first embodiment, the insulating substrate 2 is held to the heat sink 1 via a bonding material 5, and the electrode terminals 3 are bonded to a circuit pattern 2B formed on a ceramic substrate 2A of the insulating substrate 2. However, the configuration of the circuit pattern 2B is not limited to the above. An insulating film may be formed on the upper surface of the heat sink 1, and the circuit pattern 2B may be provided on the insulating film. In this case, the insulating film may be made of resin.

[0026] Second Embodiment In a second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0027] Fig. 10 is a front view showing the configuration of a semiconductor device 102 in embodiment 2. Fig. 11 is a plan view showing the configuration of the semiconductor device 102. Fig. 12 is a perspective view showing the configuration of the semiconductor device 102 (heat sink 1 is not shown). The semiconductor device 102 includes a heat sink 1, an insulating substrate 2, a semiconductor element (not shown), electrode terminals 3, fixing wire patterns 4, and misalignment prevention wire patterns 6.

[0028] In the second embodiment, a portion of the fixing wire pattern 4 is bonded to the upper surface of the joint 3A. The portion of the fixing wire pattern 4 bonded to the upper surface of the joint 3A is any portion of the fixing wire pattern 4 excluding both ends. The joint 3A is pressed toward the circuit pattern 2B by the fixing wire pattern 4. As a result, the lower surface of the joint 3A is in surface contact with the circuit pattern 2B.

[0029] The misalignment prevention wire pattern 6 has a loop shape. Both ends of the misalignment prevention wire pattern 6 are bonded to the circuit pattern 2B, and the portion between the ends is raised from the circuit pattern 2B. The misalignment prevention wire pattern 6 is provided along the periphery of the joint 3A. In the second embodiment, two misalignment prevention wire patterns 6 are provided along both sides of the base of the joint 3A. The misalignment prevention wire pattern 6 is formed of, for example, aluminum wire (Al wire). The misalignment prevention wire pattern 6 is formed by wire bonding.

[0030] The fixing wire pattern 4 ensures that the lower surface of the joint portion 3A of the electrode terminal 3 is in surface contact with the circuit pattern 2B, thereby reducing the occurrence of gaps between the circuit pattern 2B and the electrode terminal 3.

[0031] The joining portion 3A of the electrode terminal 3 is held in a predetermined position by the fixing wire pattern 4 and the misalignment prevention wire pattern 6. Therefore, the electrode terminal 3 is prevented from being misaligned.

[0032] Although this disclosure has been described in detail, the above description is illustrative in all respects and is not restrictive. It is understood that countless variations not illustrated can be envisioned.

[0033] In the present disclosure, the embodiments can be freely combined, and the embodiments can be modified or omitted as appropriate.

[0034] REFERENCE SIGNS LIST 1 heat sink, 2 insulating substrate, 2A ceramic substrate, 2B circuit pattern, 3 electrode terminal, 3A joint, 4 fixing wire pattern, 5 joining material, 6 misalignment prevention wire pattern, 101 semiconductor device, 102 semiconductor device.

Claims

1. A semiconductor device comprising: a circuit pattern electrically connected to a semiconductor element; a fixing wire pattern having both ends bonded to the circuit pattern and raised from the circuit pattern between the ends to form a loop shape; and an electrode terminal including a joint inserted into the loop shape and bonded to the circuit pattern, wherein the joint is pressed toward the circuit pattern by the fixing wire pattern.

2. The semiconductor device according to claim 1, wherein said fixing wire pattern extends in a direction intersecting with the extension direction of said electrode terminal and is provided so as to straddle said joint portion.

3. The semiconductor device according to claim 1 or 2, wherein a portion of said fixing wire pattern is joined to an upper surface of said joint portion.

4. A semiconductor device according to any one of claims 1 to 3, further comprising a wire pattern for preventing misalignment, the wire pattern having a loop shape, arranged along the periphery of the joint, and both ends of which are joined to the circuit pattern.

5. A method for manufacturing a semiconductor device, comprising: a step of preparing a circuit pattern; a step of forming a fixing wire pattern having both ends bonded to the circuit pattern and raised from the circuit pattern between the ends to form a loop shape; and a step of inserting a bonding portion of an electrode terminal into the loop shape and bonding it to the circuit pattern, wherein the step of bonding the bonding portion includes a step of pressing the bonding portion against the circuit pattern with the fixing wire pattern.

6. The method for manufacturing a semiconductor device according to claim 5, wherein in the step of forming the fixing wire pattern, the fixing wire pattern is formed so as to extend in the vibration direction of ultrasonic waves in the step of joining the joints.

7. A method for manufacturing a semiconductor device as described in claim 5 or claim 6, wherein the step of joining the joint further includes the steps of: inserting the electrode terminal inside the loop shape of the fixing wire pattern; and ultrasonically joining the joint held down by the fixing wire pattern to the circuit pattern.

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