Memory device and semiconductor device

Abstract

The present invention reduces connection defects between a magnetoresistive effect element and wiring. This memory device includes: a memory cell including a magnetoresistive effect element disposed in a wiring region and a cell transistor disposed on a semiconductor substrate; first lower layer wiring disposed in the wiring region and connecting a terminal of the cell transistor and one end of the magnetoresistive effect element; second lower layer wiring disposed in the wiring region and configured to have substantially the same height as the first lower layer wiring, the second lower layer wiring being connected to another terminal different from the terminal of the cell transistor; first upper layer wiring disposed in the wiring region and connected to another end of the magnetoresistive effect element; second upper layer wiring arranged in the same layer as the first upper layer wiring in the wiring region and connected to the second lower layer wiring; a first connection part which is columnar wiring connecting the second lower layer wiring and the second upper layer wiring; and a second connection part which is columnar wiring connecting another end different from the one end of the magnetoresistive effect element and the first upper layer wiring and is smaller in diameter than the first connection part.

Description

Memory device and semiconductor device

[0001] The present disclosure relates to memory devices and semiconductor devices.

[0002] Memory devices are being used that employ magnetoresistive elements, whose resistance values ​​change in response to an applied voltage, as nonvolatile memory elements. To increase capacity, memory cells containing magnetoresistive elements are being miniaturized, and magnetoresistive elements are being miniaturized. As a result, the connection between the magnetoresistive elements and wiring becomes an issue. A magnetic device has been proposed in which miniaturized magnetoresistive elements are connected to wiring by metal connection studs (see, for example, Patent Document 1).

[0003] In this magnetic device, two dielectric layers, an upper layer and a lower layer, are disposed so as to cover the magnetoresistive element, and the upper layer is etched near the top of the magnetoresistive element to form a trench. The lower layer is then further etched at the bottom of the trench to form a trench shaped to reach the magnetoresistive element, and the trench is filled with metal to form a metal contact stud.

[0004] Special Publication No. 2009-506531

[0005] However, the above-mentioned prior art has a problem in that variations in etching depth during trench formation can cause poor connections between the metal connection stud and the magnetoresistive element.

[0006] Therefore, the present disclosure proposes a memory device that reduces connection failures between magnetoresistive elements and wiring, and a semiconductor device that uses the memory device.

[0007] The memory device according to the present disclosure has a memory cell including a magnetoresistive element arranged in a wiring region formed on a semiconductor substrate and a cell transistor arranged on the semiconductor substrate and connected to the magnetoresistive element; a first lower layer wiring arranged in the wiring region and connecting a terminal of the cell transistor to one end of the magnetoresistive element; a second lower layer wiring arranged in the wiring region and configured at approximately the same height as the first lower layer wiring and connected to another terminal different from the terminal of the cell transistor; a first upper layer wiring arranged in the wiring region and connected to another end of the magnetoresistive element different from the one end; a second upper layer wiring arranged in the same layer as the first upper layer wiring in the wiring region and connected to the second lower layer wiring; a first connection portion which is a pillar-shaped wiring connecting the second lower layer wiring and the second upper layer wiring; and a second connection portion which is a pillar-shaped wiring connecting the other end different from the one end of the magnetoresistive element and the first upper layer wiring and configured with a smaller diameter than the first connection portion.

[0008] FIG. 1 is a diagram illustrating an example configuration of a memory system according to an embodiment of the present disclosure. FIG. 2 is a diagram illustrating an example configuration of a memory cell according to a first embodiment of the present disclosure. FIG. 3 is a diagram illustrating an example configuration of a second connection unit and a first connection unit according to the first embodiment of the present disclosure. FIG. 4 is a diagram illustrating an example configuration of a second connection unit according to the first embodiment of the present disclosure. FIG. 5 is a diagram illustrating an example manufacturing method of a memory cell according to the first embodiment of the present disclosure. FIG. 6 is a diagram illustrating an example manufacturing method of a memory cell according to the first embodiment of the present disclosure. FIG. 7 is a diagram illustrating an example manufacturing method of a memory cell according to the first embodiment of the present disclosure. FIG. 8 is a diagram illustrating an example manufacturing method of a memory cell according to the first embodiment of the present disclosure. FIG. 9 is a diagram illustrating an example manufacturing method of a memory cell according to the first embodiment of the present disclosure. FIG. 10 is a diagram illustrating an example manufacturing method of a memory cell according to the first embodiment of the present disclosure.

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be given in the following order. Note that in the following embodiments, the same components are designated by the same reference numerals, and redundant description will be omitted. 1. First embodiment 2. Second embodiment 3. Third embodiment

[0010] 1. First Embodiment [Configuration of Memory System] FIG. 1 is a diagram illustrating an example configuration of a memory system according to an embodiment of the present disclosure. This figure is a block diagram illustrating an example configuration of a memory system 1. The memory system 1 includes an interface unit 2, a memory control unit 3, a memory cell array 10, a word line address decoder 60, a word line control circuit 20, a bit line address decoder 50, a bit line control circuit 30, and a sense amplifier 40. The memory system 1 also includes a voltage generation circuit 70. Note that this embodiment describes an example having a memory interface connected to a host system. Alternatively, the memory system 1 can be applied to an embedded memory, an integrated memory, or an integrated storage having an I / O that connects to an internal bus or logic circuit integrated in a SoC (System on a Chip). Note that the memory system 1 is an example of a "semiconductor device" according to the present disclosure. The memory cell array 10 , word line address decoder 60 , word line control circuit 20 , bit line address decoder 50 , bit line control circuit 30 and sense amplifier 40 of the memory system 1 constitute a memory device 4 .

[0011] The interface unit 2 is used to communicate with a host system or the like that uses the memory system 1 .

[0012] The memory control unit 3 communicates with a host system or the like. The memory control unit 3 receives commands from the host system or the like and controls the writing and reading of data based on the received commands. The memory control unit 3 in FIG. 1 outputs write and read addresses to the word line address decoder 60 and the bit line address decoder 50. The memory control unit 3 also outputs control signals to the word line control circuit 20 and the voltage generation circuit 70. The memory control unit 3 also sends write data to the sense amplifier 40 and obtains read data from the sense amplifier 40. The memory control unit 3 is an example of a "control unit" in the present disclosure.

[0013] The memory cell array 10 is configured by arranging memory cells 100 for storing data in a two-dimensional matrix. Each memory cell 100 includes a magnetoresistive element 120 and a cell transistor 110.

[0014] The magnetoresistive element 120 has a magnetic tunnel junction (MTJ) structure in which a tunnel barrier layer is sandwiched between two magnetic layers (a memory layer and a reference layer). The resistance value of the magnetoresistive element 120 changes depending on the magnetization directions of these two magnetic layers. Specifically, the magnetoresistive element 120 is in a high-resistance state when the magnetization directions of these two ferromagnetic layers are different, and in a low-resistance state when the magnetization directions are the same. The state in which the magnetization directions are the same is called a parallel state, and the state in which the magnetization directions are different is called an anti-parallel state. This magnetization direction can be changed by applying a write voltage to the MTJ element. For example, values ​​"0" and "1" can be associated with the low-resistance state and the high-resistance state of the MTJ element to store one bit of data. The values ​​"0" and "1" can also be called low-level voltage (L) and high-level voltage (H).

[0015] The cell transistor 110 is an element connected to one end of the magnetoresistive element 120 and controls the application of voltage to the magnetoresistive element 120. For example, an n-channel MOS transistor can be used for this cell transistor 110.

[0016] In the memory cell 100, word lines 11, bit lines 12, and source lines 13 are arranged. The word lines 11 are made up of a plurality of word lines WL. The bit lines 12 are made up of a plurality of bit lines BL. The source lines 13 are made up of a plurality of source lines SL. The word lines WL and bit lines BL transmit control signals. The source lines SL transmit signals from the memory elements 120. In the memory cell array 10, a plurality of word lines WL are wired in the row direction, and a plurality of bit lines BL and source lines SL are wired in the column direction.

[0017] The word line address decoder 60 selects a word line WL of the memory cell array 10 based on a control signal from the memory control unit 3 .

[0018] The word line control circuit 20 outputs a control signal to the word line WL selected by the word line address decoder 60 .

[0019] The bit line address decoder 50 selects a bit line BL of the memory cell array 10 based on a control signal from the memory control unit 3 .

[0020] The bit line control circuit 30 outputs a control signal to the bit line BL selected by the bit line address decoder 50 .

[0021] The sense amplifier 40 reads data by detecting the current flowing through the memory cell 100 during reading. The read data is output to the memory control unit 3. The sense amplifier 40 also applies a write voltage to the memory cell 100 during writing.

[0022] The voltage generating circuit 70 is a circuit that generates a voltage to be applied when writing to and reading from the memory cell 100 .

[0023] Writing to the memory cell 100 is performed when the data stored in the memory cell 100 differs from the write data. That is, data is read from the memory cell 100 and the read data is compared with the write data. If the comparison shows that the two data differ, writing is performed. In this case, writing can be performed by inverting the data stored in the memory cell 100. That is, writing can be performed by inverting the memory state of the magnetoresistive element 120. The memory state of the magnetoresistive element 120 can be inverted by applying a predetermined write voltage to the magnetoresistive element 120.

[0024] Reading can be performed by applying a predetermined read voltage to the magnetoresistive element 120 of the memory cell 100 and detecting the current flowing through the memory cell 100. The read voltage is preferably set to a lower voltage than the write voltage.

[0025] 2 is a diagram showing a configuration example of a memory cell according to the first embodiment of the present disclosure. The diagram is a schematic cross-sectional view showing a configuration example of the memory cell 100. As described above, the memory cell 100 includes a cell transistor 110 and a magnetoresistive element 120.

[0026] The memory cell 100 is formed on a semiconductor substrate 130. This semiconductor substrate 130 is a semiconductor substrate on which the cell transistor 110 and the like are formed. A wiring region 140 is arranged on the semiconductor substrate 130. This wiring region 140 is an area where wiring and the like of elements are arranged. The wiring region 140 is arranged, for example, adjacent to the semiconductor substrate 130. The wiring region 140 includes insulating layers (insulating layers 141 to 143) and wiring. The wiring transmits signals and the like to the elements of the semiconductor substrate 130. In the wiring region 140 in FIG. 2, a first upper layer wiring 161 and a second upper layer wiring 162 are shown as examples of wiring. The wiring can be made of, for example, copper (Cu). The insulating layer insulates the wiring and the like. This insulating layer can be made of, for example, silicon oxide (SiO ２ ) The insulating layer can be formed in multiple layers. In FIG. 2, insulating layers 141 to 143 are shown stacked in order.

[0027] The cell transistor 110 is formed on a semiconductor substrate 130. Specifically, the cell transistor 110 is composed of semiconductor regions 131 and 132 formed on the semiconductor substrate 130 and a gate electrode 133 arranged with a gate insulating film 134 interposed therebetween. The semiconductor region 131 corresponds to one of the drain region and the source region, and the semiconductor region 132 corresponds to the other of the drain region and the source region. For convenience, the semiconductor region 131 is considered to be the source, and the semiconductor region 132 is considered to be the drain.

[0028] The magnetoresistive element 120 is disposed in a wiring region 140 formed on a semiconductor substrate 130. The magnetoresistive element 120 in FIG. 2 is disposed on an insulating layer 142. A lower electrode 128 and an upper electrode 129 are disposed on the magnetoresistive element 120. The lower electrode 128 can be made of, for example, titanium nitride (TiN) and tantalum nitride (TaN). The upper electrode 129 can be made of, for example, tantalum (Ta), titanium nitride (TiN), and tantalum nitride (TaN).

[0029] The drain of the cell transistor 110 and the magnetoresistive element 120 are connected by a first lower layer interconnect 150. The first lower layer interconnect 150 in FIG. 2 is connected to the lower electrode 128 of the magnetoresistive element 120. This first lower layer interconnect 150 can be configured as a contact plug formed in a region of the insulating layer 141. This contact plug is a pillar-shaped interconnect connected to a semiconductor region of the semiconductor substrate 130. A second lower layer interconnect 151 is connected to the source of the cell transistor 110. Like the first lower layer interconnect 150, this second lower layer interconnect 151 can be configured as a contact plug and is disposed in a region of the insulating layer 141. As shown in FIG. 2, the second lower layer interconnect 151 can be configured to have approximately the same height as the first lower layer interconnect 150. Furthermore, the first lower layer interconnect 150 and the second lower layer interconnect 151 can be configured to have approximately the same diameter.

[0030] A first upper layer interconnect 161 and a second upper layer interconnect 162 are arranged above the memory cell 100. The first upper layer interconnect 161 and the second upper layer interconnect 162 are formed in the region of the insulating layer 143. The first upper layer interconnect 161 is an interconnect connected to the magnetoresistive element 120 of the memory cell 100. The second upper layer interconnect 162 is an interconnect connected to the cell transistor 110 of the memory cell 100. The first upper layer interconnect 161 corresponds to the bit line in FIG. 1. The second upper layer interconnect 162 corresponds to the source line in FIG. 1. It is assumed that the first upper layer interconnect 161 and the second upper layer interconnect 162 in FIG. 2 are interconnects included in the lowest wiring layer of multiple wiring layers in the wiring region 140.

[0031] The second lower layer wiring 151 and the second upper layer wiring 162 are connected by a first connection portion 153. This first connection portion 153 can be formed of a via plug. This via plug is a pillar-shaped wiring that connects wirings and the like arranged on different layers. The first connection portion 153 can be formed of a metal such as tungsten (W) or Cu.

[0032] The magnetoresistive effect element 120 and the first upper layer wiring 161 are connected by a second connection portion 152. This second connection portion 152 can be configured by a via plug, similar to the first connection portion 153. The second connection portion 152 is configured to have a smaller diameter than the first connection portion 153. The second connection portion 152 can be configured by a metal such as tungsten (W) or Cu.

[0033] A protective film 147 is disposed adjacent to the magnetoresistive element 120. This protective film 147 can be made of, for example, silicon nitride (SiN).

[0034] [Configuration of Second Connection Portion and First Connection Portion] FIG. 3 is a diagram illustrating an example configuration of the second connection portion and the first connection portion according to the first embodiment of the present disclosure. This figure is a schematic cross-sectional view illustrating an example configuration of the second connection portion 152 and the first connection portion 153. As described above, the second connection portion 152 can be configured to have a smaller diameter than the first connection portion 153. The height from the surface of the semiconductor substrate 130 at the same level as the bottom where the second connection portion 152 contacts the upper electrode 129 of the magnetoresistive effect element 120 is referred to as the reference height. The dotted line in FIG. 3 represents this reference height. Also, "d1" in FIG. 3 represents the diameter of the second connection portion 152 at this reference height. Also, "d2" in FIG. 3 represents the diameter of the first connection portion 153 at the reference height. Also, "d3" in FIG. 3 represents the diameter of the tunnel barrier layer portion of the magnetoresistive effect element 120.

[0035] As shown in FIG. 3, d1 can be made smaller than d2. This makes it possible to prevent defects such as short circuits even if the second connection portion 152 is misaligned. Specifically, the second connection portion 152 and the first connection portion 153 can be configured as follows: d2-d1≧10 nm. In other words, the second connection portion 152 can be configured to have a diameter that is 10 nm or more smaller than the diameter of the first connection portion 153 at the reference height. By reducing the diameter of the second connection portion 152, the overlay margin between the magnetoresistive element 120 and the second connection portion 152 can be increased, and the occurrence of low resistance defects can be reduced even in chips with large overlay misalignment.

[0036] The second connecting portion 152 can be configured to have a size that satisfies the following formula: 30 nm≦d1≦60 nm In other words, the second connecting portion 152 can be configured to have a diameter that is 30 nm or more and 60 nm or less.

[0037] However, when not only the second connecting portion 152 but also the magnetoresistive element 120 is reduced in size, low resistance defects due to misalignment are confirmed. In this case, low resistance defects do not occur if the diameter (d3) of the tunnel barrier layer portion of the magnetoresistive element 120 is 15 nm or more larger than the diameter d1 of the second connecting portion 152. The second connecting portion 152 can be configured to have a size satisfying the following formula: d3 - d1 ≧ 15 nm In other words, the second connecting portion 152 can be configured to have a diameter that is 15 nm or more smaller than the diameter of the tunnel barrier layer portion of the magnetoresistive element 120.

[0038] It is preferable that the diameter (d3) of the tunnel barrier layer portion of the magnetoresistive element 120 is set to a size of 45 nm to 75 nm. This is because, while increasing the diameter of the magnetoresistive element 120 can lengthen the recording retention time, it also increases the current required for rewriting.

[0039] 4 is a diagram showing an example of the configuration of the second connector 152 according to the first embodiment of the present disclosure. This diagram illustrates an example in which the second connector 152 is misaligned. The magnetoresistive element 120 in this diagram includes a tunnel barrier layer 121. The region of the magnetoresistive element 120 enclosed by a dashed-dotted line represents the region of the tunnel barrier layer 121. Note that the second connector 152 in this diagram illustrates a case in which the second connector 152 is formed with a shift toward the left of the diagram. By reducing the diameter of the second connector 152, the second connector 152 is configured to remain in the region of the upper electrode 129 even in the case of misalignment.

[0040] 4 represents the case where the second connection portion 152 is configured to have the same diameter as the first connection portion 153. Due to misalignment, the end of the second connection portion 152 comes close to the tunnel barrier layer 121 of the magnetoresistive element 120. This causes a low resistance defect.

[0041] In this way, by reducing the diameter of the second connection portion 152, the influence of misalignment can be reduced. Furthermore, since the second connection portion 152 is connected to the magnetoresistive element 120, which has a relatively high resistance, the influence of an increase in resistance due to size reduction is reduced. In contrast, the first connection portion 153 is configured to a size based on the rules of the manufacturing process of the memory cell 100. Furthermore, since the first connection portion 153 is connected to the cell transistor 110, if the resistance increases due to size reduction, the operation of the logic circuit for driving the memory cell 100 will become unstable. For this reason, there is a limit to how much the size of the first connection portion 153 can be reduced. Therefore, the diameter of the second connection portion 152 can be determined using the first connection portion 153 as a comparison target.

[0042] 5A to 5L are diagrams illustrating an example of a method for manufacturing a memory cell according to the first embodiment of the present disclosure, showing a manufacturing process for a region of the memory cell 100 near the magnetoresistive element 120.

[0043] First, an insulating layer 141, a first lower layer wiring 150, etc. are disposed on a semiconductor substrate 130 (not shown) (FIG. 5A).

[0044] Next, a titanium nitride film 400 is disposed on the surface of the insulating layer 141 (FIG. 5B). Next, a magnetoresistive element film 401 is laminated on this titanium nitride film 400 (FIG. 5C).

[0045] Next, a tantalum film 402 is laminated on the magnetoresistive element film 401 (FIG. 5D).

[0046] Next, the SiN film 403 and SiO ２ A membrane 404 is then laminated (FIG. 5E).

[0047] Next, SiO ２ The film 404 is processed to the size of the magnetoresistive element 120. This can be done by etching using a photoresist mask (FIG. 5F).

[0048] Next, SiO ２ Using the film 404 as a mask, the SiN film 403 and the tantalum film 402 are etched (FIG. 5G).

[0049] Next, the magnetoresistive element film 401 and the titanium nitride film 400 are etched (FIG. 5H). This can be performed by, for example, ion beam etching. As a result, the magnetoresistive element 120, the lower electrode 128, and the upper electrode 129 can be formed.

[0050] Next, a protective film 147 is disposed (FIG. 5I). Next, an insulating layer 142 is disposed, and the surface is ground and flattened (FIG. 5J).

[0051] Next, an opening 405 is formed in the insulating layer 142 in a region where the second connection portion 152 is to be disposed (FIG. 5K).

[0052] Next, the second connection portion 152 is formed. This can be done by disposing a metal film that will be the material for the second connection portion 152 on the surface of the insulating layer 142, including the opening 405, and then grinding away unnecessary areas (FIG. 5L). Through the above steps, the first lower layer wiring 150, the magnetoresistive element 120, and the second connection portion 152 can be formed.

[0053] In this way, the memory device 4 according to the first embodiment of the present disclosure can reduce the influence of misalignment of the second connection portion 152 by making the diameter of the second connection portion 152 of the memory cell 100 smaller than that of the first connection portion 153. This can reduce poor connection between the magnetoresistive element 120 and the wiring.

[0054] (2. Second Embodiment) In the memory device 4 of the first embodiment described above, the first lower layer wiring 150 and the second lower layer wiring 151 are connected to the semiconductor region 131 of the semiconductor substrate 130, etc. In contrast, the memory device 4 of the second embodiment of the present disclosure differs from the first embodiment described above in that the first lower layer wiring 150 and the second lower layer wiring 151 are connected to wiring.

[0055] [Configuration of Memory Cell] Fig. 6 is a diagram showing a configuration example of a memory cell according to a second embodiment of the present disclosure. Similar to Fig. 2, this figure is a schematic cross-sectional view showing a configuration example of a memory cell 100. The memory cell 100 in this figure differs from the memory cell 100 in Fig. 2 in that the first lower layer wiring 150 and the second lower layer wiring 151 are connected to wiring 163 and wiring 164, respectively.

[0056] 6 shows insulating layers 143 to 146 stacked in order in the wiring region 140. Wiring 163 and 164 are arranged in the region of insulating layer 143. Furthermore, first lower layer wiring 150 and second lower layer wiring 151 are arranged in insulating layer 144. Furthermore, magnetoresistive effect element 120, second connection portion 152, and first connection portion 153 are arranged in the region of insulating layer 145. Furthermore, first upper layer wiring 161 and second upper layer wiring 162 are arranged in the region of insulating layer 146.

[0057] 6 are configured by via plugs, and the wirings 163 and 164 are connected to the cell transistor 110 via contact plugs or the like.

[0058] In the memory cell 100 of FIG. 6 as well, the diameter of the second connecting portion 152 can be made smaller than that of the first connecting portion 153 .

[0059] The configuration of the memory device 4 other than that described above is the same as the configuration of the memory device 4 in the first embodiment of the present disclosure, and therefore description thereof will be omitted.

[0060] In this way, the memory device 4 of the second embodiment of the present disclosure can reduce the effect of misalignment of the second connection portion 152 by making the diameter of the second connection portion 152 of the memory cell 100 smaller than that of the first connection portion 153.

[0061] (3. Third Embodiment) The memory device 4 of the first embodiment described above includes memory cells 100 having the same size of magnetoresistive effect elements 120. In contrast, the memory device 4 of the third embodiment of the present disclosure differs from the first embodiment described above in that it includes a plurality of memory cells 100 having magnetoresistive effect elements 120 of different sizes.

[0062] [Memory Cell Configuration] Fig. 7 is a diagram showing a configuration example of a memory cell array according to a third embodiment of the present disclosure. The same figure is a diagram showing a configuration example of a memory cell array 10 according to the third embodiment of the present disclosure. The memory cell array 10 in the same figure includes a memory cell 100a and a memory cell 100b. Note that the memory cell 100b is an example of a "second memory cell" of the present disclosure. Also, the magnetoresistive effect element 120b is an example of a "second magnetoresistive effect element" of the present disclosure.

[0063] The memory cell 100a includes a magnetoresistive element 120a, a second connecting portion 152a, and a first connecting portion 153a, which are configured to have the same sizes as the magnetoresistive element 120, the second connecting portion 152a, and the first connecting portion 153a of the memory cell 100 in FIG.

[0064] In contrast, the memory cell 100b includes a magnetoresistive element 120b, a second connection portion 152b, and a first connection portion 153b. The magnetoresistive element 120b represents an example in which it is configured to have a larger diameter than the magnetoresistive element 120a. The second connection portion 152b can be configured to a size corresponding to the size of the magnetoresistive element 120b. Specifically, the second connection portion 152b can be configured to have the same diameter as the first connection portion 153b. The first connection portion 153b can be configured to have the same size as the first connection portion 153a.

[0065] The configuration of the memory device 4 other than that described above is the same as the configuration of the memory device 4 in the first embodiment of the present disclosure, and therefore description thereof will be omitted.

[0066] In this way, the memory device 4 of the third embodiment of the present disclosure has magnetoresistive effect elements 120 of different sizes arranged therein, and second connection portions 152 of sizes corresponding to the sizes of these magnetoresistive effect elements 120 arranged therein.

[0067] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0068] The present technology can also be configured as follows: (1) A memory device having: a memory cell including a magnetoresistive element arranged in a wiring region formed on a semiconductor substrate and a cell transistor arranged on the semiconductor substrate and connected to the magnetoresistive element; a first lower layer wiring arranged in the wiring region and connecting a terminal of the cell transistor to one end of the magnetoresistive element; a second lower layer wiring arranged in the wiring region and configured to be at approximately the same height as the first lower layer wiring and connected to another terminal different from the terminal of the cell transistor; a first upper layer wiring arranged in the wiring region and connected to another end of the magnetoresistive element different from the one end; a second upper layer wiring arranged in the same layer as the first upper layer wiring in the wiring region and connected to the second lower layer wiring; a first connecting portion which is a pillar-shaped wiring connecting the second lower layer wiring and the second upper layer wiring; and a second connecting portion which is a pillar-shaped wiring connecting the other end different from the one end of the magnetoresistive element and the first upper layer wiring and configured with a diameter smaller than that of the first connecting portion. (2) The memory device according to (1), wherein the first lower layer wiring is formed of a pillar-shaped wiring, and the second lower layer wiring is formed of a pillar-shaped wiring. (3) The memory device according to (2), wherein the first lower layer wiring is formed to have approximately the same diameter as the second lower layer wiring. (4) The memory device according to any of (1) to (3), wherein the second connection portion has a bottom portion formed to have a diameter smaller than the diameter of the first connection portion at a reference height, which is the same height from the surface of the semiconductor substrate as the bottom portion that contacts the electrode of the magnetoresistive effect element. (5) The memory device according to (4), wherein the second connection portion has a bottom portion formed to have a diameter smaller than the diameter of the first connection portion at the reference height by 10 nm or more. (6) The memory device according to (4), wherein the second connection portion has a bottom portion formed to have a diameter greater than or equal to 30 nm and less than 60 nm. (7) The memory device according to (4), wherein the second connection portion has the bottom portion configured to have a diameter that is 15 nm or more smaller than the diameter of the tunnel barrier layer of the magnetoresistive effect element.(8) The memory device according to any one of (1) to (7), further comprising a second memory cell including a second magnetoresistive element and a cell transistor configured to have a diameter larger than that of the magnetoresistive element, wherein a second connection portion corresponding to the second magnetoresistive element is configured to have a diameter corresponding to the second magnetoresistive element. (9) The memory device according to any one of (1) to (8), wherein the second connection portion is configured from a metal, and the first connection portion is configured from a metal. (10) The memory device according to (9), wherein the second connection portion is configured from either tungsten or copper, and the first connection portion is configured from either tungsten or copper. (11) A semiconductor device having: a memory cell including a magnetoresistive element arranged in a wiring region formed on a semiconductor substrate, and a cell transistor arranged on the semiconductor substrate and connected to the magnetoresistive element; a first lower layer wiring arranged in the wiring region and connecting a terminal of the cell transistor to one end of the magnetoresistive element; a second lower layer wiring arranged in the wiring region and configured to be at approximately the same height as the first lower layer wiring and connected to another terminal different from the terminal of the cell transistor; a first upper layer wiring arranged in the wiring region and connected to another end of the magnetoresistive element different from the one end; a second upper layer wiring arranged in the same layer as the first upper layer wiring in the wiring region and connected to the second lower layer wiring; a first connecting portion which is a pillar-shaped wiring connecting the second lower layer wiring and the second upper layer wiring; and a second connecting portion which is a pillar-shaped wiring connecting the other end different from the one end of the magnetoresistive element and the first upper layer wiring, the pillar-shaped wiring having a diameter smaller than that of the first connecting portion; and a control unit for controlling the memory device.

[0069] REFERENCE SIGNS LIST 1 memory system 3 memory control unit 4 memory device 100, 100a, 100b memory cell 110 cell transistor 120, 120b, 120a magnetoresistive effect element 121 tunnel barrier layer 128 lower electrode 129 upper electrode 130 semiconductor substrate 140 wiring region 150 first lower layer wiring 151 second lower layer wiring 152, 152a, 152b second connection portion 153, 153a, 153b first connection portion 161 first upper layer wiring 162 second upper layer wiring 163, 164 wiring

Claims

1. A memory device having: a memory cell including a magnetoresistive element arranged in a wiring region formed on a semiconductor substrate, and a cell transistor arranged on the semiconductor substrate and connected to the magnetoresistive element; a first lower layer wiring arranged in the wiring region and connecting a terminal of the cell transistor to one end of the magnetoresistive element; a second lower layer wiring arranged in the wiring region, configured to be at approximately the same height as the first lower layer wiring, and connected to another terminal different from the terminal of the cell transistor; a first upper layer wiring arranged in the wiring region and connected to another end of the magnetoresistive element different from the one end; a second upper layer wiring arranged in the same layer as the first upper layer wiring in the wiring region and connected to the second lower layer wiring; a first connection portion which is a pillar-shaped wiring connecting the second lower layer wiring and the second upper layer wiring; and a second connection portion which is a pillar-shaped wiring connecting the other end different from the one end of the magnetoresistive element and the first upper layer wiring, the pillar-shaped wiring being configured to have a smaller diameter than the first connection portion.

2. The memory device according to claim 1, wherein the first lower layer wiring is composed of pillar-shaped wiring, and the second lower layer wiring is composed of pillar-shaped wiring.

3. The memory device according to claim 2, wherein the first lower layer wiring is configured to have approximately the same diameter as the second lower layer wiring.

4. A memory device as described in claim 1, wherein the second connection portion has a bottom portion configured to have a diameter smaller than the diameter of the first connection portion at a reference height, which is the same height from the surface of the semiconductor substrate as the bottom portion that contacts the electrode of the magnetoresistive element.

5. The memory device according to claim 4, wherein said second connection portion has a bottom portion configured to have a diameter that is 10 nm or more smaller than the diameter of said first connection portion at said reference height.

6. The memory device according to claim 4, wherein the second connection portion has a bottom portion configured to have a diameter of 30 nm or more and 60 nm or less.

7. The memory device according to claim 4, wherein said second connection portion has a bottom portion configured to have a diameter 15 nm or more smaller than a diameter of the tunnel barrier layer of said magnetoresistive element.

8. The memory device according to claim 1, further comprising a second memory cell including a second magnetoresistance effect element and a cell transistor configured to have a larger diameter than the magnetoresistance effect element, and a second connection portion corresponding to the second magnetoresistance effect element is configured to have a diameter corresponding to the second magnetoresistance effect element.

9. The memory device according to claim 1, wherein the second connection portion is made of a metal, and the first connection portion is made of a metal.

10. The memory device according to claim 9, wherein the second connection portion is made of either tungsten or copper, and the first connection portion is made of either tungsten or copper.

11. A semiconductor device having: a memory device comprising: a memory cell including a magnetoresistive element arranged in a wiring region formed on a semiconductor substrate, and a cell transistor arranged on the semiconductor substrate and connected to the magnetoresistive element; a first lower layer wiring arranged in the wiring region and connecting a terminal of the cell transistor to one end of the magnetoresistive element; a second lower layer wiring arranged in the wiring region, configured to be at approximately the same height as the first lower layer wiring, and connected to another terminal different from the terminal of the cell transistor; a first upper layer wiring arranged in the wiring region and connected to another end of the magnetoresistive element different from the one end; a second upper layer wiring arranged in the same layer as the first upper layer wiring in the wiring region and connected to the second lower layer wiring; a first connection portion which is a pillar-shaped wiring connecting the second lower layer wiring and the second upper layer wiring; and a second connection portion which is a pillar-shaped wiring connecting the other end different from the one end of the magnetoresistive element and the first upper layer wiring, the pillar-shaped wiring being configured with a diameter smaller than that of the first connection portion; and a control portion which controls the memory device.

Images