Solid-state imaging device

Abstract

A solid-state imaging device (1) is provided with a sample-and-hold circuit (10). The sample-and-hold circuit (10) is provided with: a first capacitor (11); a second capacitor (12); a first buffer (21) having an output connected to an AD conversion circuit (90); a first input switch (31) disposed between a vertical signal line (80) and the first capacitor (11); a second input switch (32) disposed between the vertical signal line (80) and the second capacitor (12); a first output switch (41) disposed between the first capacitor (11) and the input of the first buffer (21); and a second output switch (42) disposed between the second capacitor (12) and the input of the first buffer (21). In a plan view, the first output switch (41) and the first buffer (21) are adjacent to each other, and the second output switch (42) and the first buffer (21) are adjacent to each other in the column direction of a pixel array (70).

Description

solid-state imaging device

[0001] The present disclosure relates to a solid-state imaging device.

[0002] 2. Description of the Related Art A solid-state imaging device including a sample-and-hold circuit is known.

[0003] JP 2008-125046 A International Publication No. 2023 / 063024

[0004] Among conventional solid-state imaging devices, there are known ones that include a sample-and-hold circuit having multiple capacitors arranged in parallel to achieve high-speed imaging operation through pipeline control for reading out pixel signals from pixels (see, for example, Patent Documents 1 and 2).

[0005] On the other hand, it is desirable for solid-state imaging devices to capture images with higher quality.

[0006] Therefore, an object of the present disclosure is to provide a solid-state imaging device that can achieve high-speed imaging operation and also achieve high image quality in captured images.

[0007] A solid-state imaging device according to one aspect of the present disclosure includes a pixel array in which a plurality of pixels are arranged in a matrix, a vertical signal line extending in a column direction of the pixel array and transmitting a pixel signal output from at least one of the plurality of pixels, a sample-and-hold circuit that holds the pixel signal transmitted by the vertical signal line, and an AD conversion circuit that performs AD conversion on the pixel signal held by the sample-and-hold circuit, wherein the sample-and-hold circuit includes a first capacitor, a second capacitor having a capacitance equal to that of the first capacitor, a first buffer whose output is connected to the AD conversion circuit, and a signal line connected to the vertical signal line. and the first capacitor, a second input switch arranged on the electrical path between the vertical signal line and the second capacitor, a first output switch arranged on the electrical path between the first capacitor and the input of the first buffer, and a second output switch arranged on the electrical path between the second capacitor and the input of the first buffer, wherein, in a planar view of the pixel array, the first output switch and the first buffer are adjacent to each other in the column direction, and the second output switch and the first buffer are adjacent to each other in the column direction.

[0008] a first input switch disposed on an electrical path between the vertical signal line and the first capacitor; a second input switch disposed on an electrical path between the vertical signal line and the second capacitor; a second input switch disposed on an electrical path between the vertical signal line and the second capacitor; a sample-and-hold circuit configured to hold the pixel signal transmitted by the vertical signal line; and an AD conversion circuit configured to AD convert the pixel signal held by the sample-and-hold circuit. a third input switch arranged on an electrical path between the vertical signal line and the third capacitor, a first output switch arranged on an electrical path between the first capacitor and the input of the first buffer, a second output switch arranged on an electrical path between the second capacitor and the input of the first buffer, a third output switch arranged on an electrical path between the second capacitor and the input of the second buffer, and a fourth output switch arranged on an electrical path between the third capacitor and the input of the second buffer, wherein, in a planar view of the pixel array, the first output switch and the first buffer are adjacent to each other in the column direction, the second output switch and the first buffer are adjacent to each other in the column direction, the third output switch and the second buffer are adjacent to each other in the column direction, and the fourth output switch and the second buffer are adjacent to each other in the column direction.

[0009] A solid-state imaging device according to an aspect of the present disclosure includes: a pixel array in which a plurality of pixels are arranged in a matrix; a first vertical signal line extending in a column direction of the pixel array and transmitting a first pixel signal output from at least one of the plurality of pixels; a second vertical signal line extending in the column direction and transmitting a second pixel signal output from at least one of the plurality of pixels and having a higher gain than the first pixel signal; a sample-and-hold circuit holding the first pixel signal transmitted by the first vertical signal line and the second pixel signal transmitted by the second vertical signal line; and an AD conversion circuit performing AD conversion on the first pixel signal and the second pixel signal held in the sample-and-hold circuit, wherein the sample-and-hold circuit includes a first capacitor and a second capacitor. a second capacitor; a buffer having an output connected to the AD conversion circuit; a first input switch arranged on an electrical path between the first vertical signal line and the first capacitor; a second input switch arranged on an electrical path between the second vertical signal line and the second capacitor; a first output switch arranged on an electrical path between the first capacitor and an input of the buffer; and a second output switch arranged on an electrical path between the second capacitor and an input of the buffer, wherein, in a planar view of the pixel array, the distance between the first output switch and the buffer in the column direction is shorter than the distance between the second output switch and the buffer in the column direction, and the capacitance of the first capacitor is smaller than the capacitance of the second capacitor.

[0010] A solid-state imaging device according to an aspect of the present disclosure can achieve high-speed imaging operation while also achieving high image quality.

[0011] FIG. 1 is a block diagram showing a configuration of a solid-state imaging device according to a first embodiment. FIG. 2 is a circuit diagram showing an example of a circuit configuration of a sample and hold circuit according to the first embodiment. FIG. 3 is a schematic plan view showing an example of a physical configuration of the sample and hold circuit according to the first embodiment. FIG. 4 is a circuit diagram showing an example of a circuit configuration of the sample and hold circuit according to the first embodiment. FIG. 5 is a circuit diagram showing an example of a circuit configuration of the sample and hold circuit according to the first embodiment. FIG. 6 is a schematic plan view showing an example of a physical configuration of the sample and hold circuit according to the first embodiment. FIG. 7 is a circuit diagram showing an example of a circuit configuration of the sample and hold circuit according to the first embodiment. FIG. 8 is a circuit diagram showing an example of a circuit configuration of the sample and hold circuit according to the first embodiment. FIG. 9 is a schematic plan view showing an example of a physical configuration of the sample and hold circuit according to the first embodiment. FIG. 10 is a circuit diagram showing an example of a circuit configuration of the sample and hold circuit according to the first embodiment. FIG. 11 is a circuit diagram showing an example of a circuit configuration of the sample and hold circuit according to the first embodiment. FIG. 12 is a schematic plan view showing an example of a physical configuration of the sample and hold circuit according to the first embodiment. FIG. 13 is a circuit diagram showing an example of a circuit configuration of the sample and hold circuit according to the first embodiment. FIG. 14 is a timing chart of a first read pipeline control process according to the first embodiment. FIG. 15 is a circuit diagram showing an example of a circuit configuration of a sample and hold circuit according to the first modification. FIG. 16 is a circuit diagram showing an example of a circuit configuration of a sample and hold circuit according to the second modification. FIG. 17 is a timing chart showing an example of an operation performed by a solid-state imaging device according to the second modification. FIG. 18 is a block diagram showing a configuration of a solid-state imaging device according to the second embodiment. FIG. 19 is a circuit diagram showing an example of a circuit configuration of a sample and hold circuit according to the second embodiment. FIG. 20 is a schematic plan view showing an example of a physical configuration of a sample and hold circuit according to the second embodiment. FIG. 21 is a circuit diagram showing an example of a circuit configuration of a sample and hold circuit according to the second embodiment. FIG. 22 is a circuit diagram showing an example of a circuit configuration of a sample and hold circuit according to the second embodiment. FIG. 23 is a schematic plan view showing an example of a physical configuration of a sample and hold circuit according to the second embodiment.FIG. 24 is a timing chart showing an example of an operation performed by the solid-state imaging device according to the second embodiment. FIG. 25 is a circuit diagram showing an example of a circuit configuration of a sample and hold circuit according to the second embodiment. FIG. 26 is a circuit diagram showing an example of a circuit configuration of a sample and hold circuit according to the second embodiment. FIG. 27 is a schematic plan view showing an example of a physical configuration of a sample and hold circuit according to the second embodiment. FIG. 28 is a schematic plan view showing an example of a physical configuration of a sample and hold circuit according to the second embodiment. FIG. 29 is a timing chart of a second read pipeline control process according to the second embodiment. FIG. 30 is a circuit diagram showing an example of a circuit configuration of a sample and hold circuit according to a modification. FIG. 31 is a circuit diagram showing an example of a circuit configuration of a sample and hold circuit according to a modification.

[0012] (How one aspect of the present disclosure was achieved) Conventionally, a solid-state imaging device has been known that is capable of realizing high-speed imaging operations through pipeline control for reading out pixel signals from pixels by including a sample-and-hold circuit having a plurality of capacitors arranged in parallel to each other and holding pixel signals read out from pixels, a plurality of switches that exclusively select one of the plurality of capacitors, and a buffer that outputs a voltage corresponding to the pixel signal held in the selected capacitor to an AD conversion circuit.

[0013] The inventors have conducted extensive experiments and studies to improve the quality of images captured by a solid-state imaging device having such a configuration, and as a result, have gained knowledge about factors that hinder the improvement of the quality of images captured by a solid-state imaging device having such a configuration.

[0014] That is, the inventors discovered that (1) the image quality of the captured image deteriorates due to the presence of parasitic capacitance in the electrical path between the capacitor and the buffer via the switch, which causes charge redistribution due to the capacitance of the capacitor and the parasitic capacitance as the switch operates, and (2) the image quality of the captured image deteriorates due to variations in the parasitic capacitance present in each of the electrical paths between multiple capacitors and the buffer.

[0015] The inventors also discovered that when multiple capacitors include capacitors with larger capacitances and capacitors with smaller capacitances, the smaller capacitance capacitors have a greater adverse effect on the degradation of the image quality of the captured image due to the parasitic capacitance present in the electrical path between the capacitors and the buffer than the larger capacitance capacitors.

[0016] Based on these findings, the inventors further conducted experimental studies, and as a result, arrived at the following solid-state imaging device according to one aspect of the present disclosure.

[0017] A solid-state imaging device according to one aspect of the present disclosure includes a pixel array in which a plurality of pixels are arranged in a matrix, a vertical signal line extending in a column direction of the pixel array and transmitting a pixel signal output from at least one of the plurality of pixels, a sample-and-hold circuit that holds the pixel signal transmitted by the vertical signal line, and an AD conversion circuit that performs AD conversion on the pixel signal held by the sample-and-hold circuit, wherein the sample-and-hold circuit includes a first capacitor, a second capacitor having a capacitance equal to that of the first capacitor, a first buffer whose output is connected to the AD conversion circuit, and a signal line connected to the vertical signal line. and the first capacitor, a second input switch arranged on the electrical path between the vertical signal line and the second capacitor, a first output switch arranged on the electrical path between the first capacitor and the input of the first buffer, and a second output switch arranged on the electrical path between the second capacitor and the input of the first buffer, wherein, in a planar view of the pixel array, the first output switch and the first buffer are adjacent to each other in the column direction, and the second output switch and the first buffer are adjacent to each other in the column direction.

[0018] According to the solid-state imaging device having the above configuration, the parasitic capacitance present on the electrical path between the first output switch and the input of the first buffer, and the parasitic capacitance present on the electrical path between the second output switch and the input of the first buffer can be minimized.

[0019] Furthermore, with the solid-state imaging device having the above configuration, it is possible to suppress the relative variation between the parasitic capacitance present on the electrical path between the first input switch and the first output switch and the parasitic capacitance present on the electrical path between the second input switch and the second output switch.

[0020] The solid-state imaging device having the above configuration also includes a sample-and-hold circuit having a first capacitor and a second capacitor arranged in parallel with each other.

[0021] Therefore, the solid-state imaging device having the above configuration can realize high-speed imaging operation and also realize high-quality images.

[0022] The sample and hold circuit may further include a third capacitor having a capacitance equal to that of the first capacitor, a fourth capacitor having a capacitance equal to that of the first capacitor, a second buffer having an output connected to the AD conversion circuit, a third input switch arranged on an electrical path between the vertical signal line and the third capacitor, a fourth input switch arranged on an electrical path between the vertical signal line and the fourth capacitor, a third output switch arranged on an electrical path between the third capacitor and an input of the second buffer, and a fourth output switch arranged on an electrical path between the fourth capacitor and an input of the second buffer, wherein the third output switch and the second buffer are adjacent to each other in the column direction, and the fourth output switch and the second buffer are adjacent to each other in the column direction in a plan view of the pixel array.

[0023] According to the solid-state imaging device having the above configuration, the parasitic capacitance present on the electrical path between the third output switch and the input of the second buffer and the parasitic capacitance present on the electrical path between the fourth output switch and the input of the second buffer can be minimized.

[0024] Furthermore, with the solid-state imaging device having the above configuration, it is possible to suppress the relative variations in the parasitic capacitance present on the electrical path between the first input switch and the first output switch, the parasitic capacitance present on the electrical path between the second input switch and the second output switch, the parasitic capacitance present on the electrical path between the third input switch and the third output switch, and the parasitic capacitance present on the electrical path between the fourth input switch and the fourth output switch.

[0025] The solid-state imaging device having the above configuration also includes a sample-and-hold circuit having a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor arranged in parallel with each other.

[0026] Therefore, the solid-state imaging device having the above configuration can realize high-speed imaging operation and also realize high-quality images.

[0027] A solid-state imaging device according to one aspect of the present disclosure is a solid-state imaging device including a pixel array in which a plurality of pixels are arranged in a matrix, a vertical signal line extending in a column direction of the pixel array and transmitting a pixel signal output from at least one of the plurality of pixels, a sample-and-hold circuit that holds the pixel signal transmitted by the vertical signal line, and an AD conversion circuit that performs AD conversion of the pixel signal held by the sample-and-hold circuit, wherein the sample-and-hold circuit includes a first capacitor, a second capacitor having a capacitance equal to that of the first capacitor, a third capacitor having a capacitance equal to that of the first capacitor, a first buffer having an output connected to the AD conversion circuit, a second buffer having an output connected to the AD conversion circuit, a first input switch arranged on an electrical path between the vertical signal line and the first capacitor, a second input switch arranged on an electrical path between the vertical signal line and the second capacitor, and a front a third input switch arranged on an electrical path between the vertical signal line and the third capacitor, a first output switch arranged on an electrical path between the first capacitor and an input of the first buffer, a second output switch arranged on an electrical path between the second capacitor and an input of the first buffer, a third output switch arranged on an electrical path between the second capacitor and an input of the second buffer, and a fourth output switch arranged on an electrical path between the third capacitor and an input of the second buffer, wherein, in a planar view of the pixel array, the first output switch and the first buffer are adjacent to each other in the column direction, the second output switch and the first buffer are adjacent to each other in the column direction, the third output switch and the second buffer are adjacent to each other in the column direction, and the fourth output switch and the second buffer are adjacent to each other in the column direction.

[0028] According to the solid-state imaging device having the above configuration, it is possible to minimize the parasitic capacitance present on the electrical path between the first output switch and the input of the first buffer, the parasitic capacitance present on the electrical path between the second output switch and the input of the first buffer, the parasitic capacitance present on the electrical path between the third output switch and the input of the second buffer, and the parasitic capacitance present on the electrical path between the fourth output switch and the input of the second buffer.

[0029] Furthermore, with the solid-state imaging device having the above configuration, it is possible to suppress the relative variations in the parasitic capacitance present on the electrical path between the first input switch and the first output switch, the parasitic capacitance present on the electrical path between the second input switch and the second output switch, the parasitic capacitance present on the electrical path between the second input switch and the third output switch, and the parasitic capacitance present on the electrical path between the third input switch and the fourth output switch.

[0030] The solid-state imaging device having the above configuration also includes a sample-and-hold circuit having a first capacitor, a second capacitor, and a third capacitor arranged in parallel with each other.

[0031] Therefore, the solid-state imaging device having the above configuration can realize high-speed imaging operation and also realize high-quality images.

[0032] The sample and hold circuit may further include a fourth capacitor having a capacitance equal to that of the first capacitor, a fifth capacitor having a capacitance equal to that of the first capacitor, a third buffer having an output connected to the AD conversion circuit, a fourth input switch arranged on an electrical path between the vertical signal line and the fourth capacitor, a fifth input switch arranged on an electrical path between the vertical signal line and the fifth capacitor, a fifth output switch arranged on an electrical path between the fourth capacitor and an input of the third buffer, and a sixth output switch arranged on an electrical path between the fifth capacitor and an input of the third buffer, wherein the fifth output switch and the third buffer are adjacent to each other in the column direction, and the sixth output switch and the third buffer are adjacent to each other in the column direction in a plan view of the pixel array.

[0033] According to the solid-state imaging device having the above configuration, the parasitic capacitance present on the electrical path between the fifth output switch and the input of the third buffer and the parasitic capacitance present on the electrical path between the sixth output switch and the input of the third buffer can be minimized.

[0034] Furthermore, with the solid-state imaging device having the above configuration, it is possible to suppress relative variations in the parasitic capacitance present on the electrical path between the first input switch and the first output switch, the parasitic capacitance present on the electrical path between the second input switch and the second output switch, the parasitic capacitance present on the electrical path between the second input switch and the third output switch, the parasitic capacitance present on the electrical path between the third input switch and the fourth output switch, the parasitic capacitance present on the electrical path between the fourth input switch and the fifth output switch, and the parasitic capacitance present on the electrical path between the fifth input switch and the sixth output switch.

[0035] The solid-state imaging device having the above configuration also includes a sample-and-hold circuit having a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, and a fifth capacitor arranged in parallel with each other.

[0036] Therefore, the solid-state imaging device having the above configuration can realize high-speed imaging operation and also realize high-quality images.

[0037] A solid-state imaging device according to one aspect of the present disclosure includes a pixel array in which a plurality of pixels are arranged in a matrix, a first vertical signal line extending in a column direction of the pixel array and transmitting a first pixel signal output from at least one of the plurality of pixels, a second vertical signal line extending in the column direction and transmitting a second pixel signal output from at least one of the plurality of pixels and having a higher gain than the first pixel signal, a sample-and-hold circuit holding the first pixel signal transmitted by the first vertical signal line and the second pixel signal transmitted by the second vertical signal line, and an AD conversion circuit performing AD conversion on the first pixel signal and the second pixel signal held in the sample-and-hold circuit, wherein the sample-and-hold circuit includes a first capacitor and a a second capacitor, a buffer having an output connected to the AD conversion circuit, a first input switch arranged on an electrical path between the first vertical signal line and the first capacitor, a second input switch arranged on an electrical path between the second vertical signal line and the second capacitor, a first output switch arranged on an electrical path between the first capacitor and an input of the buffer, and a second output switch arranged on an electrical path between the second capacitor and an input of the buffer, wherein, in a plan view of the pixel array, the distance between the first output switch and the buffer in the column direction is shorter than the distance between the second output switch and the buffer in the column direction, and the capacitance of the first capacitor is smaller than the capacitance of the second capacitor.

[0038] In the solid-state imaging device having the above configuration, the parasitic capacitance between the first output switch and the input of the buffer, which exists on the electrical path between the first capacitor having a smaller capacitance and the input of the buffer, can be made smaller than the parasitic capacitance between the second output switch and the input of the buffer, which exists on the electrical path between the second capacitor having a larger capacitance and the input of the buffer, thereby suppressing the influence of charge redistribution accompanying the operation of the first output switch and / or the second output switch.

[0039] The solid-state imaging device having the above configuration also includes a sample-and-hold circuit having a first capacitor and a second capacitor arranged in parallel with each other.

[0040] Therefore, the solid-state imaging device having the above configuration can realize high-speed imaging operation and also realize high-quality images.

[0041] The sample and hold circuit may further include a third capacitor having a capacitance equal to that of the first capacitor, a fourth capacitor having a capacitance equal to that of the second capacitor, a third input switch arranged on an electrical path between the first vertical signal line and the third capacitor, a fourth input switch arranged on an electrical path between the second vertical signal line and the fourth capacitor, a third output switch arranged on an electrical path between the third capacitor and an input of the buffer, and a fourth output switch arranged on an electrical path between the fourth capacitor and an input of the buffer, and in a plan view of the pixel array, a distance in the column direction between the third output switch and the buffer may be shorter than a distance in the column direction between the fourth output switch and the buffer.

[0042] In the solid-state imaging device having the above configuration, the parasitic capacitance between the third output switch and the input of the buffer, which exists on the electrical path between the third capacitor having a smaller capacitance and the input of the buffer, can be made smaller than the parasitic capacitance between the fourth output switch and the input of the buffer, which exists on the electrical path between the fourth capacitor having a larger capacitance and the input of the buffer, thereby suppressing the influence of charge redistribution accompanying the operation of the third output switch and / or the fourth output switch.

[0043] The solid-state imaging device having the above configuration also includes a sample-and-hold circuit having a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor arranged in parallel with each other.

[0044] Therefore, the solid-state imaging device having the above configuration can realize high-speed imaging operation and also realize high-quality images.

[0045] The sample and hold circuit may further include a first selection switch arranged on an electrical path between the first output switch and the second output switch and an input of the buffer, and a second selection switch arranged on an electrical path between the third output switch and the fourth output switch and an input of the buffer, and in a planar view of the pixel array, the first selection switch and the buffer may be adjacent to each other in the column direction, and the second selection switch and the buffer may be adjacent to each other in the column direction.

[0046] This makes it possible to suppress the parasitic capacitance present on the electrical paths between the first output switch and the second output switch and the input of the buffer, as well as the parasitic capacitance present on the electrical paths between the third output switch and the fourth output switch and the input of the buffer, compared to a configuration that does not have the first selection switch and the second selection switch.

[0047] Therefore, the solid-state imaging device having the above configuration can realize high-speed imaging operation and also realize high-quality images.

[0048] The sample-and-hold circuit may further include a fixed voltage output circuit that outputs an operating voltage of a fixed potential to the first buffer to operate the first buffer, and a reset switch that is arranged on an electrical path between the output of the fixed voltage output circuit and the input of the first buffer.

[0049] This makes the operating voltage of the first buffer a fixed potential, thereby making it possible to further stabilize the operation of the first buffer.

[0050] This also allows the input of the first buffer to be stably reset to a fixed voltage.

[0051] Therefore, it is possible to achieve even higher image quality for the captured image.

[0052] The sample-and-hold circuit may further include a fixed voltage output circuit that outputs an operating voltage of a fixed potential to the first buffer and the second buffer, causing the first buffer and the second buffer to operate; a first reset switch that is arranged on an electrical path between the output of the fixed voltage output circuit and the input of the first buffer; and a second reset switch that is arranged on an electrical path between the output of the fixed voltage output circuit and the input of the second buffer.

[0053] As a result, the operating voltage of the first buffer and the operating voltage of the second buffer are fixed potentials, so that the operation of the first buffer and the operation of the second buffer can be made more stable.

[0054] This also makes it possible to stably reset the input of the first buffer and the input of the second buffer to a fixed voltage.

[0055] Therefore, it is possible to achieve even higher image quality for the captured image.

[0056] The sample-and-hold circuit may further include a fixed voltage output circuit that outputs an operating voltage of a fixed potential to the buffer to operate the buffer, and a reset switch that is arranged on an electrical path between the output of the fixed voltage output circuit and the input of the buffer.

[0057] This makes the operating voltage of the buffer a fixed potential, thereby making the operation of the buffer more stable.

[0058] This also allows the input of the buffer to be reset to a stable fixed voltage.

[0059] Therefore, it is possible to achieve even higher image quality for the captured image.

[0060] The fixed voltage output circuit may also include a transistor having a drain connected to a power supply wiring and a source connected to the output of the fixed voltage output circuit, a potential holding capacitor connected to the gate of the transistor, and a potential holding switch arranged on an electrical path between the power supply wiring and the potential holding capacitor.

[0061] This allows the fixed voltage output circuit to be realized with a relatively simple configuration.

[0062] The sample-and-hold circuit may further include a pull-up switch that pulls up or pulls down the output of the fixed voltage output circuit.

[0063] This allows each buffer to operate at the pulled-up potential, thereby widening the dynamic range of each buffer.

[0064] This makes it possible to improve the linearity of each buffer.

[0065] Therefore, it is possible to achieve even higher image quality for the captured image.

[0066] Specific examples of solid-state imaging devices according to an aspect of the present disclosure will be described below with reference to the drawings. Each of the embodiments shown here illustrates a specific example of the present disclosure. Therefore, the numerical values, shapes, components, component arrangements and connection configurations, steps (processes), and step sequences shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. In each figure, substantially identical components are assigned the same reference numerals, and redundant explanations are omitted or simplified.

[0067] First Embodiment [1.1. Configuration of Solid-State Imaging Device] FIG. 1 is a block diagram showing the configuration of a solid-state imaging device 1 according to a first embodiment.

[0068] As shown in FIG. 1, the solid-state imaging device 1 includes a pixel array 70, a vertical scanning circuit 71, a reference signal generating unit 72, a control unit 73, a horizontal scanning circuit 74, a signal processing unit 75, a plurality of vertical signal lines 80, a plurality of sample-and-hold circuits 10, and a plurality of AD conversion circuits 90.

[0069] The pixel array 70 is configured by arranging a plurality of pixels 3 in a matrix of m (m is an integer of 2 or more) rows and n (n is an integer of 2 or more) columns.

[0070] The pixel 3 has a photoelectric conversion unit that converts exposed light into a signal charge, and a signal charge holding unit that holds the signal charge converted by the photoelectric conversion unit, and outputs a pixel signal corresponding to the signal charge held in the signal charge holding unit.

[0071] Each of the multiple vertical signal lines 80 extends in the column direction of the pixel array 70 (the X-axis direction in Figure 1), is connected to m pixels 3 arranged in the column direction of the pixel array 70, and transmits a pixel signal output from at least one of the connected pixels 3.

[0072] That is, the number of vertical signal lines 80 included in the solid-state imaging device 1 is n, which is the same as the number of columns in the pixel array 70 .

[0073] There are also cases where the number of columns of the column circuits is an integer multiple, such as two, three, or four times, of the number of columns of the pixel array 70. In such cases, the number of the vertical signal lines 80 is an integer multiple of the number n of columns of the pixel array 70. However, in this description, the number of the vertical signal lines 80 is assumed to be n, which is the same as the number of columns of the pixel array 70.

[0074] The vertical scanning circuit 71 sequentially selects and scans the multiple pixels 3 that make up the pixel array 70 row by row, thereby simultaneously outputting pixel signals from each of the n pixels 3 belonging to the row to be scanned to each of the n vertical signal lines 80.

[0075] The reference signal generating unit 72 generates a reference ramp signal that is used as a reference for voltage comparison by a voltage comparator 91 (described later).

[0076] The control unit 73 controls the operation timing of each component that constitutes the solid-state imaging device 1 .

[0077] The horizontal scanning circuit 74 sequentially selects and scans n memories 93 (described later) to sequentially output pixel data (described later) stored in the memories 93 to the signal processing unit 75 .

[0078] The signal processing unit 75 performs various signal processes on the pixel data sequentially output from the horizontal scanning circuit 74 .

[0079] Each of the plurality of sample-and-hold circuits 10 corresponds one-to-one to each of the plurality of vertical signal lines 80 , and holds the pixel signal transmitted by the corresponding vertical signal line 80 .

[0080] That is, the number of the sample-and-hold circuits 10 included in the solid-state imaging device 1 is n, which is the same as the number of columns in the pixel array 70 .

[0081] There are also cases where the number of columns of the column circuits is an integer multiple, such as two, three, or four times, of the number of columns of the pixel array 70. In such cases, the number of the plurality of sample and hold circuits 10 is an integer multiple of the number n of columns of the pixel array 70. However, in this description, the number of the plurality of sample and hold circuits 10 is assumed to be n, which is the same as the number of columns of the pixel array 70.

[0082] The sample and hold circuit 10 has a plurality of capacitors arranged in parallel to each other for holding pixel signals. That is, the sample and hold circuit 10 can hold a plurality of pixel signals. The sample and hold circuit 10 also has one or more buffers for buffering the pixel signals held by the plurality of capacitors. The sample and hold circuit 10 then outputs a signal corresponding to one of the plurality of pixel signals it holds.

[0083] The specific configuration of the sample-and-hold circuit 10 will be described later.

[0084] Each of the plurality of AD conversion circuits 90 corresponds to each of the plurality of sample and hold circuits 10 on a one-to-one basis, and performs AD conversion on the signal output from the corresponding sample and hold circuit 10 .

[0085] That is, the number of AD conversion circuits 90 included in the solid-state imaging device 1 is n, which is the same as the number of columns in the pixel array 70 .

[0086] There are also cases where the number of columns of the column circuits is an integer multiple, such as two, three, or four times, of the number of columns of the pixel array 70. In such cases, the number of the plurality of AD conversion circuits 90 is an integer multiple of the number n of columns of the pixel array 70. However, in this description, the number of the plurality of AD conversion circuits 90 is assumed to be n, which is the same as the number of columns of the pixel array 70.

[0087] As shown in FIG. 1, the AD conversion circuit 90 includes a voltage comparator 91 , a counter circuit 92 , and a memory 93 .

[0088] The voltage comparator 91 compares the voltage of the reference ramp signal generated by the reference signal generator 72 with the voltage of the signal output from the sample-and-hold circuit 10 .

[0089] The counter circuit 92 detects the count value at the time when the comparison by the voltage comparator 91 results in a match.

[0090] The count value detected by the counter circuit 92 is determined according to the value of the pixel signal held by the corresponding sample and hold circuit 10. Therefore, the count value detected by the counter circuit 92 is the value of the digitized pixel signal. Note that this digitized pixel signal value is also referred to as "pixel data."

[0091] The memory 93 stores the count value detected by the counter circuit 92, that is, stores pixel data.

[0092] During the AD conversion, a digital correlated double sampling (digital CDS) process is also performed to remove reset noise in the pixel 3, specific pattern noise unique to each pixel 3, noise caused by the AD conversion circuit 90, etc., by calculating the difference between the AD conversion result of the pixel signal output from the pixel 3 in the reset state and the AD conversion result of the pixel signal output from the pixel 3 in the exposed state.

[0093] [1.2. Configuration of Sample-and-Hold Circuit] A specific configuration of the sample-and-hold circuit 10 will now be described.

[0094] As described above, the sample and hold circuit 10 has a plurality of capacitors arranged in parallel to each other for holding pixel signals.

[0095] First, the configuration of the sample-and-hold circuit 10 having two capacitors will be described.

[0096] [1.2. A. Configuration of Sample-and-Hold Circuit Having Two Capacitors] FIG. 2 is a circuit diagram showing an example of the circuit configuration of the sample-and-hold circuit 10 having two capacitors.

[0097] As shown in FIG. 2, the sample-and-hold circuit 10 has a first capacitor 11, a second capacitor 12, a first buffer 21, a first input switch 31, a second input switch 32, a first output switch 41, a second output switch 42, an input 51, and an output 52.

[0098] The input 51 is connected to a vertical signal line 80 .

[0099] The output 52 is connected to an AD conversion circuit 90 .

[0100] The first capacitor 11 is a capacitor for holding a pixel signal, and is indicated as C1 in FIG. 2 and in circuit diagrams, plan views, and the like described below.

[0101] The second capacitor 12 is a capacitor for holding a pixel signal, and its capacitance is equal to that of the first capacitor 11. The second capacitor 12 is indicated as C2 in FIG. 2 and in circuit diagrams, plan views, etc. described later.

[0102] The first buffer 21 is a buffer whose output is connected to the output 52, i.e., whose output is connected to the AD conversion circuit 90, and which buffers the pixel signal held in the first capacitor 11 or the pixel signal held in the second capacitor 12. The first buffer 21 is indicated as buf1 in FIG. 2 and in circuit diagrams, plan views, etc. described later.

[0103] The first input switch 31 is a switch connected to the input 51 and the first capacitor 11, and switches between a conductive state and a non-conductive state between the input 51 and the first capacitor 11. That is, the first input switch 31 is a switch disposed on an electrical path between the vertical signal line 80 and the first capacitor 11, and switches between a conductive state and a non-conductive state between the vertical signal line 80 and the first capacitor 11. The first input switch 31 is indicated as SW11 in FIG. 2 and in circuit diagrams, plan views, etc. described later.

[0104] The second input switch 32 is a switch connected to the input 51 and the second capacitor 12, and switches between a conductive state and a non-conductive state between the input 51 and the second capacitor 12. That is, the second input switch 32 is a switch disposed on the electrical path between the vertical signal line 80 and the second capacitor 12, and switches between a conductive state and a non-conductive state between the vertical signal line 80 and the second capacitor 12. The second input switch 32 is indicated as SW21 in FIG. 2 and in circuit diagrams, plan views, etc. described below.

[0105] The first output switch 41 is a switch connected to the first capacitor 11 and the input of the first buffer 21, and switches between a conductive state and a non-conductive state between the first capacitor 11 and the input of the first buffer 21. That is, the first output switch 41 is a switch disposed on an electrical path between the first capacitor 11 and the input of the first buffer 21, and switches between a conductive state and a non-conductive state between the first capacitor 11 and the input of the first buffer 21. The first output switch 41 is indicated as SW12 in FIG. 2 and in circuit diagrams, plan views, etc. described later.

[0106] The second output switch 42 is a switch connected to the second capacitor 12 and the input of the first buffer 21, and switches between a conductive state and a non-conductive state between the second capacitor 12 and the input of the first buffer 21. That is, the second output switch 42 is a switch disposed on the electrical path between the second capacitor 12 and the input of the first buffer 21, and switches between a conductive state and a non-conductive state between the second capacitor 12 and the input of the first buffer 21. The second output switch 42 is indicated as SW22 in FIG. 2 and in circuit diagrams, plan views, etc. described below.

[0107] As shown in FIG. 2, in the sample-and-hold circuit 10 shown in FIG. 2, a parasitic capacitance 111 (indicated as Cp1 in FIG. 2) exists on the electrical path between the first input switch 31 and the first output switch 41, a parasitic capacitance 112 (indicated as Cp2 in FIG. 2) exists on the electrical path between the second input switch 32 and the second output switch 42, and a parasitic capacitance 113 (indicated as Cpcom in FIG. 2) exists on the electrical path between the first output switch 41 and the second output switch 42 and the input of the first buffer 21.

[0108] Although similar parasitic capacitances exist in the sample-and-hold circuit 10 and other circuits exemplified in the following description, these parasitic capacitances will be omitted from the following drawings to avoid unnecessarily complicating the drawings.

[0109] FIG. 3 is a schematic plan view showing an example of the physical configuration of the sample-and-hold circuit 10 shown in FIG.

[0110] 3, the X-axis direction is the column direction of the pixel array 70, and the Y-axis direction is the row direction of the pixel array 70. Therefore, FIG. 3 is a schematic plan view of the sample and hold circuit 10 in the plan view of the pixel array 70.

[0111] As shown in FIG. 3 , in a planar view of the sample and hold circuit 10, that is, in a planar view of the pixel array 70, the first output switch 41 and the first buffer 21 are adjacent to each other in the column direction of the pixel array 70 (the X-axis direction in FIG. 3 ), and the second output switch 42 and the first buffer 21 are adjacent to each other in the column direction of the pixel array 70.

[0112] According to the solid-state imaging device 1 equipped with the sample-and-hold circuit 10 having the above-described configuration, the parasitic capacitance present on the electrical path between the first output switch 41 and the input of the first buffer 21 and the parasitic capacitance present on the electrical path between the second output switch 42 and the input of the first buffer 21 can be minimized.

[0113] Furthermore, according to the solid-state imaging device 1 equipped with the sample-and-hold circuit 10 having the above-described configuration, the relative variation between the parasitic capacitance present on the electrical path between the first input switch 31 and the first output switch 41 and the parasitic capacitance present on the electrical path between the second input switch 32 and the second output switch 42 can be suppressed.

[0114] The solid-state imaging device 1 including the sample-and-hold circuit 10 configured as described above includes the sample-and-hold circuit 10 having the first capacitor 11 and the second capacitor 12 arranged in parallel with each other.

[0115] Therefore, the solid-state imaging device 1 including the sample-and-hold circuit 10 having the above configuration can realize high-speed imaging operation and also realize high-quality images.

[0116] The sample and hold circuit 10 may further include one or more buffer inputs and one or more reset switches for resetting the capacitors.

[0117] FIG. 4 is a circuit diagram showing an example of the circuit configuration of the sample-and-hold circuit 10 shown in FIG. 2 when the sample-and-hold circuit 10 further includes a first reset switch 61 for resetting the input of the first buffer 21 with the initialization voltage Vinit.

[0118] The first reset switch 61 is connected to the output of an initialization power supply that supplies the initialization voltage Vinit and to the input of the first buffer 21, and switches between a conductive state and a non-conductive state between the output of the initialization power supply and the input of the first buffer 21. That is, the first reset switch 61 is disposed on the electrical path between the output of the initialization power supply and the input of the first buffer 21, and switches between a conductive state and a non-conductive state between the output of the initialization power supply and the input of the first buffer 21. The first reset switch 61 is indicated as SW61 in FIG. 4 and in circuit diagrams, plan views, etc. described below.

[0119] The solid-state imaging device 1 including the sample-and-hold circuit 10 configured as described above can reset the input of the first buffer 21 to the initialization voltage Vinit by turning on the first reset switch 61 .

[0120] Next, the configuration of the sample-and-hold circuit 10 having three capacitors will be described.

[0121] [1.2. B. Configuration of Sample-and-Hold Circuit Having Three Capacitors] FIG. 5 is a circuit diagram showing an example of the circuit configuration of the sample-and-hold circuit 10 having three capacitors.

[0122] As shown in FIG. 5, the sample and hold circuit 10 has a first capacitor 11A, a second capacitor 12A, a third capacitor 13A, a first buffer 21A, a second buffer 22A, a first input switch 31A, a second input switch 32A, a third input switch 33A, a first output switch 41A, a second output switch 42A, a third output switch 43A, a fourth output switch 44A, an input 51, and an output 52.

[0123] The first capacitor 11A is a capacitor for holding a pixel signal, and is indicated as C1 in FIG. 5 and in circuit diagrams, plan views, and the like described below.

[0124] The second capacitor 12A is a capacitor for holding a pixel signal, and its capacitance is equal to that of the first capacitor 11A. The second capacitor 12A is indicated as C2 in FIG. 5 and in circuit diagrams, plan views, etc. described later.

[0125] The third capacitor 13A is a capacitor for holding a pixel signal, and its capacitance is equal to that of the first capacitor 11A. The third capacitor 13A is indicated as C3 in FIG. 5 and in circuit diagrams, plan views, etc. described later.

[0126] The first buffer 21A is a buffer that buffers the pixel signal held in the first capacitor 11A or the pixel signal held in the second capacitor 12A, the output of which is connected to the output 52, i.e., the output of which is connected to the AD conversion circuit 90. The first buffer 21A is indicated as buf1 in FIG. 5 and in circuit diagrams, plan views, etc. described later.

[0127] The second buffer 22A is a buffer that buffers the pixel signal held in the second capacitor 12A or the pixel signal held in the third capacitor 13A, the output of which is connected to the output 52, i.e., the output of which is connected to the AD conversion circuit 90. The second buffer 22A is indicated as buf2 in FIG. 5 and in the circuit diagrams, plan views, etc. described below.

[0128] Here, it is assumed that the characteristics of the first buffer 21A and the characteristics of the second buffer 22A are equal.

[0129] The first input switch 31A is connected to the input 51 and the first capacitor 11A and switches between a conductive state and a non-conductive state between the input 51 and the first capacitor 11A. That is, the first input switch 31A is disposed on the electrical path between the vertical signal line 80 and the first capacitor 11A and switches between a conductive state and a non-conductive state between the vertical signal line 80 and the first capacitor 11A. The first input switch 31A is indicated as SW11 in FIG. 5 and in circuit diagrams, plan views, etc. described below.

[0130] The second input switch 32A is connected to the input 51 and the second capacitor 12A and switches the input 51 and the second capacitor 12A between a conductive state and a non-conductive state. That is, the second input switch 32A is disposed on the electrical path between the vertical signal line 80 and the second capacitor 12A and switches the vertical signal line 80 and the second capacitor 12A between a conductive state and a non-conductive state. The second input switch 32A is indicated as SW21 in FIG. 5 and in circuit diagrams, plan views, etc. described below.

[0131] The third input switch 33A is connected to the input 51 and the third capacitor 13A and switches the input 51 and the third capacitor 13A between a conductive state and a non-conductive state. That is, the third input switch 33A is disposed on the electrical path between the vertical signal line 80 and the third capacitor 13A and switches the vertical signal line 80 and the third capacitor 13A between a conductive state and a non-conductive state. The third input switch 33A is indicated as SW31 in FIG. 5 and in circuit diagrams, plan views, etc. described below.

[0132] The first output switch 41A is a switch connected to the first capacitor 11A and the input of the first buffer 21A, and switches between a conductive state and a non-conductive state between the first capacitor 11A and the input of the first buffer 21A. That is, the first output switch 41A is disposed on the electrical path between the first capacitor 11A and the input of the first buffer 21A, and switches between a conductive state and a non-conductive state between the first capacitor 11A and the input of the first buffer 21A. The first output switch 41A is indicated as SW12 in FIG. 5 and in circuit diagrams, plan views, etc. described below.

[0133] The second output switch 42A is connected to the second capacitor 12A and the input of the first buffer 21A, and switches between a conductive state and a non-conductive state between the second capacitor 12A and the input of the first buffer 21A. That is, the second output switch 42A is disposed on the electrical path between the second capacitor 12A and the input of the first buffer 21A, and switches between a conductive state and a non-conductive state between the second capacitor 12A and the input of the first buffer 21A. The second output switch 42A is indicated as SW22 in FIG. 5 and in circuit diagrams, plan views, etc. described below.

[0134] The third output switch 43A is connected to the second capacitor 12A and the input of the second buffer 22A, and switches between a conductive state and a non-conductive state between the second capacitor 12A and the input of the second buffer 22A. That is, the third output switch 43A is disposed on the electrical path between the second capacitor 12A and the input of the second buffer 22A, and switches between a conductive state and a non-conductive state between the second capacitor 12A and the input of the second buffer 22A. The third output switch 43A is indicated as SW32 in FIG. 5 and in the circuit diagrams, plan views, etc. described below.

[0135] The fourth output switch 44A is connected to the third capacitor 13A and the input of the second buffer 22A and switches between a conductive state and a non-conductive state between the third capacitor 13A and the input of the second buffer 22A. That is, the fourth output switch 44A is disposed on the electrical path between the third capacitor 13A and the input of the second buffer 22A and switches between a conductive state and a non-conductive state between the third capacitor 13A and the input of the second buffer 22A. The fourth output switch 44A is indicated as SW42 in FIG. 5 and in circuit diagrams, plan views, etc. described below.

[0136] FIG. 6 is a schematic plan view showing an example of the physical configuration of the sample-and-hold circuit 10 shown in FIG.

[0137] 6, the X-axis direction is the column direction of the pixel array 70, and the Y-axis direction is the row direction of the pixel array 70. Therefore, FIG. 6 is a schematic plan view of the sample and hold circuit 10 in a plan view of the pixel array 70.

[0138] As shown in FIG. 6 , in a planar view of the sample and hold circuit 10, that is, in a planar view of the pixel array 70, the first output switch 41A and the first buffer 21A are adjacent to each other in the column direction of the pixel array 70 (the X-axis direction in FIG. 6 ), the second output switch 42A and the first buffer 21A are adjacent to each other in the column direction of the pixel array 70, the third output switch 43A and the second buffer 22A are adjacent to each other in the column direction of the pixel array 70, and the fourth output switch 44A and the second buffer 22A are adjacent to each other in the column direction of the pixel array 70.

[0139] According to the solid-state imaging device 1 including the sample-and-hold circuit 10 having the above-described configuration, it is possible to minimize the parasitic capacitance present on the electrical path between the first output switch 41A and the input of the first buffer 21A, the parasitic capacitance present on the electrical path between the second output switch 42A and the input of the first buffer 21A, the parasitic capacitance present on the electrical path between the third output switch 43A and the input of the second buffer 22A, and the parasitic capacitance present on the electrical path between the fourth output switch 44A and the input of the second buffer 22A.

[0140] Furthermore, according to the solid-state imaging device 1 equipped with the sample-and-hold circuit 10 having the above-described configuration, it is possible to suppress the relative variations in the parasitic capacitance present on the electrical path between the first input switch 31A and the first output switch 41A, the parasitic capacitance present on the electrical path between the second input switch 32A and the second output switch 42A, the parasitic capacitance present on the electrical path between the second input switch 32A and the third output switch 43A, and the parasitic capacitance present on the electrical path between the third input switch 33A and the input of the fourth output switch 44A.

[0141] Furthermore, the solid-state imaging device 1 including the sample-and-hold circuit 10 configured as described above includes the sample-and-hold circuit 10 having the first capacitor 11A, the second capacitor 12A, and the third capacitor 13A arranged in parallel with each other.

[0142] Therefore, the solid-state imaging device 1 including the sample-and-hold circuit 10 having the above configuration can realize high-speed imaging operation and also realize high-quality images.

[0143] As mentioned above, the sample and hold circuit 10 may further include one or more buffer inputs and one or more reset switches for resetting the capacitors.

[0144] FIG. 7 is a circuit diagram showing an example of the circuit configuration of the sample and hold circuit 10 shown in FIG. 5 when the sample and hold circuit 10 further includes a first reset switch 61A for resetting the input of the first buffer 21A with the initialization voltage Vinit, and a second reset switch 62A for resetting the input of the second buffer 22A with the initialization voltage Vinit.

[0145] The first reset switch 61A is connected to the output of an initialization power supply that supplies the initialization voltage Vinit and to the input of the first buffer 21A, and is a switch that switches between a conductive state and a non-conductive state between the output of the initialization power supply and the input of the first buffer 21A. That is, the first reset switch 61A is disposed on the electrical path between the output of the initialization power supply and the input of the first buffer 21A, and is a switch that switches between a conductive state and a non-conductive state between the output of the initialization power supply and the input of the first buffer 21A. The first reset switch 61A is indicated as SW61 in FIG. 7 and in circuit diagrams, plan views, etc. described below.

[0146] The second reset switch 62A is connected to the output of an initialization power supply that supplies the initialization voltage Vinit and to the input of the second buffer 22A, and switches between a conductive state and a non-conductive state between the output of the initialization power supply and the input of the second buffer 22A. That is, the second reset switch 62A is disposed on the electrical path between the output of the initialization power supply and the input of the second buffer 22A, and switches between a conductive state and a non-conductive state between the output of the initialization power supply and the input of the second buffer 22A. The second reset switch 62A is indicated as SW62 in FIG. 7 and in circuit diagrams, plan views, etc. described below.

[0147] The solid-state imaging device 1 including the sample-and-hold circuit 10 configured as described above can reset the input of the first buffer 21A to the initialization voltage Vinit by turning on the first reset switch 61A.

[0148] Furthermore, the solid-state imaging device 1 including the sample-and-hold circuit 10 configured as described above can reset the input of the second buffer 22A to the initialization voltage Vinit by turning on the second reset switch 62A.

[0149] Next, the configuration of the sample-and-hold circuit 10 having four capacitors will be described.

[0150] [1.2. C. Configuration of Sample-and-Hold Circuit Having Four Capacitors] FIG. 8 is a circuit diagram showing an example of the circuit configuration of the sample-and-hold circuit 10 having four capacitors.

[0151] As shown in FIG. 8, the sample and hold circuit 10 is configured by adding a third capacitor 13B, a fourth capacitor 14B, a second buffer 22B, a third input switch 33B, a fourth input switch 34B, a third output switch 43B, and a fourth output switch 44B to the sample and hold circuit 10 having two capacitors shown in FIG. 2.

[0152] The third capacitor 13B is a capacitor for holding a pixel signal, and its capacitance is equal to that of the first capacitor 11. The third capacitor 13B is indicated as C3 in FIG. 8 and in circuit diagrams, plan views, etc. described later.

[0153] The fourth capacitor 14B is a capacitor for holding a pixel signal, and its capacitance is equal to that of the first capacitor 11. The fourth capacitor 14B is indicated as C4 in FIG. 8 and in circuit diagrams, plan views, etc. described later.

[0154] The second buffer 22B is a buffer that buffers the pixel signal held in the third capacitor 13B or the pixel signal held in the fourth capacitor 14B, the output of which is connected to the output 52, i.e., the output of which is connected to the AD conversion circuit 90. The second buffer 22B is indicated as buf2 in FIG. 8 and in circuit diagrams, plan views, etc. described later.

[0155] Here, it is assumed that the characteristics of the first buffer 21 and the characteristics of the second buffer 22B are equal.

[0156] The third input switch 33B is a switch connected to the input 51 and the third capacitor 13B, and switches the input 51 and the third capacitor 13B between a conductive state and a non-conductive state. That is, the third input switch 33B is a switch disposed on the electrical path between the vertical signal line 80 and the third capacitor 13B, and switches the vertical signal line 80 and the third capacitor 13B between a conductive state and a non-conductive state. The third input switch 33B is indicated as SW31 in FIG. 8 and in circuit diagrams, plan views, etc. described below.

[0157] The fourth input switch 34B is a switch connected to the input 51 and the fourth capacitor 14B, and switches the input 51 and the fourth capacitor 14B between a conductive state and a non-conductive state. That is, the fourth input switch 34B is a switch disposed on the electrical path between the vertical signal line 80 and the fourth capacitor 14B, and switches the vertical signal line 80 and the fourth capacitor 14B between a conductive state and a non-conductive state. The fourth input switch 34B is indicated as SW41 in FIG. 8 and in circuit diagrams, plan views, etc. described below.

[0158] The third output switch 43B is connected to the third capacitor 13B and the input of the second buffer 22B, and switches between a conductive state and a non-conductive state between the third capacitor 13B and the input of the second buffer 22B. That is, the third output switch 43B is disposed on the electrical path between the third capacitor 13B and the input of the second buffer 22B, and switches between a conductive state and a non-conductive state between the third capacitor 13B and the input of the second buffer 22B. The third output switch 43B is indicated as SW32 in FIG. 8 and in circuit diagrams, plan views, etc. described below.

[0159] The fourth output switch 44B is connected to the fourth capacitor 14B and the input of the second buffer 22B and switches between a conductive state and a non-conductive state between the fourth capacitor 14B and the input of the second buffer 22B. That is, the fourth output switch 44B is disposed on the electrical path between the fourth capacitor 14B and the input of the second buffer 22B and switches between a conductive state and a non-conductive state between the fourth capacitor 14B and the input of the second buffer 22B. The fourth output switch 44B is indicated as SW42 in FIG. 8 and in circuit diagrams, plan views, etc. described below.

[0160] FIG. 9 is a schematic plan view showing an example of the physical configuration of the sample-and-hold circuit 10 having four capacitors.

[0161] 9, the X-axis direction is the column direction of the pixel array 70, and the Y-axis direction is the row direction of the pixel array 70. Therefore, FIG. 9 is a schematic plan view of the sample and hold circuit 10 in the plan view of the pixel array 70.

[0162] As shown in FIG. 9 , in a planar view of the sample and hold circuit 10, that is, in a planar view of the pixel array 70, the first output switch 41 and the first buffer 21 are adjacent to each other in the column direction of the pixel array 70 (the X-axis direction in FIG. 9 ), the second output switch 42 and the first buffer 21 are adjacent to each other in the column direction of the pixel array 70, the third output switch 43B and the second buffer 22B are adjacent to each other in the column direction of the pixel array 70, and the fourth output switch 44B and the second buffer 22B are adjacent to each other in the column direction of the pixel array 70.

[0163] According to the solid-state imaging device 1 having the sample-and-hold circuit 10 of the above configuration, it is possible to minimize the parasitic capacitance present on the electrical path between the first output switch 41 and the input of the first buffer 21, the parasitic capacitance present on the electrical path between the second output switch 42 and the input of the first buffer 21, the parasitic capacitance present on the electrical path between the third output switch 43B and the input of the second buffer 22B, and the parasitic capacitance present on the electrical path between the fourth output switch 44B and the input of the second buffer 22B.

[0164] Furthermore, according to the solid-state imaging device 1 equipped with the sample-and-hold circuit 10 having the above-described configuration, it is possible to suppress the relative variations in the parasitic capacitance present on the electrical path between the first input switch 31 and the first output switch 41, the parasitic capacitance present on the electrical path between the second input switch 32 and the second output switch 42, the parasitic capacitance present on the electrical path between the third input switch 33B and the third output switch 43B, and the parasitic capacitance present on the electrical path between the fourth input switch 34B and the fourth output switch 44B.

[0165] Furthermore, the solid-state imaging device 1 having the sample-and-hold circuit 10 configured as described above has a sample-and-hold circuit 10 having a first capacitor 11, a second capacitor 12, a third capacitor 13B, and a fourth capacitor 14B arranged in parallel with each other.

[0166] Therefore, the solid-state imaging device 1 including the sample-and-hold circuit 10 having the above configuration can realize high-speed imaging operation and also realize high-quality images.

[0167] As mentioned above, the sample and hold circuit 10 may further include one or more buffer inputs and one or more reset switches for resetting the capacitors.

[0168] FIG. 10 is a circuit diagram showing an example of the circuit configuration of the sample and hold circuit 10 shown in FIG. 8 when the sample and hold circuit 10 further includes a first reset switch 61 for resetting the input of the first buffer 21 with the initialization voltage Vinit, and a second reset switch 62B for resetting the input of the second buffer 22B with the initialization voltage Vinit.

[0169] The second reset switch 62B is connected to the output of an initialization power supply that supplies the initialization voltage Vinit and to the input of the second buffer 22B, and switches between a conductive state and a non-conductive state between the output of the initialization power supply and the input of the second buffer 22B. That is, the second reset switch 62B is disposed on the electrical path between the output of the initialization power supply and the input of the second buffer 22B, and switches between a conductive state and a non-conductive state between the output of the initialization power supply and the input of the second buffer 22B. The second reset switch 62B is indicated as SW62 in FIG. 10 .

[0170] The solid-state imaging device 1 including the sample-and-hold circuit 10 configured as described above can reset the input of the first buffer 21 to the initialization voltage Vinit by turning on the first reset switch 61 .

[0171] Next, the configuration of the sample-and-hold circuit 10 having five capacitors will be described.

[0172] [1.2. D. Configuration of Sample-and-Hold Circuit Having Five Capacitors] FIG. 11 is a circuit diagram showing an example of the circuit configuration of the sample-and-hold circuit 10 having five capacitors.

[0173] As shown in FIG. 11, the sample and hold circuit 10 is configured by adding a fourth capacitor 14C, a fifth capacitor 15C, a third buffer 23C, a fourth input switch 34C, a fifth input switch 35C, a fifth output switch 45C, and a sixth output switch 46C to the sample and hold circuit 10 having three capacitors shown in FIG. 5.

[0174] The fourth capacitor 14C is a capacitor for holding a pixel signal, and its capacitance is equal to that of the first capacitor 11A. The fourth capacitor 14C is indicated as C4 in FIG. 11 and in circuit diagrams, plan views, etc. described later.

[0175] The fifth capacitor 15C is a capacitor for holding a pixel signal, and its capacitance is equal to that of the first capacitor 11A. The fifth capacitor 15C is indicated as C5 in FIG. 11 and in circuit diagrams, plan views, etc. described later.

[0176] The third buffer 23C is a buffer that buffers the pixel signal held in the fourth capacitor 14C or the pixel signal held in the fifth capacitor 15C, and has its output connected to the output 52, i.e., its output connected to the AD conversion circuit 90. The third buffer 23C is indicated as buf3 in FIG. 11 and in circuit diagrams, plan views, etc. described later.

[0177] Here, it is assumed that the characteristics of the first buffer 21A, the second buffer 22A, and the third buffer 23C are equal to each other.

[0178] The fourth input switch 34C is a switch connected to the input 51 and the fourth capacitor 14C, and switches the input 51 and the fourth capacitor 14C between a conductive state and a non-conductive state. That is, the fourth input switch 34C is a switch disposed on the electrical path between the vertical signal line 80 and the fourth capacitor 14C, and switches the vertical signal line 80 and the fourth capacitor 14C between a conductive state and a non-conductive state. The fourth input switch 34C is indicated as SW41 in FIG. 11 and in circuit diagrams, plan views, etc. described below.

[0179] The fifth input switch 35C is a switch connected to the input 51 and the fifth capacitor 15C, and switches the input 51 and the fifth capacitor 15C between a conductive state and a non-conductive state. That is, the fifth input switch 35C is a switch disposed on the electrical path between the vertical signal line 80 and the fifth capacitor 15C, and switches the vertical signal line 80 and the fifth capacitor 15C between a conductive state and a non-conductive state. The fifth input switch 35C is indicated as SW51 in FIG. 11 and in circuit diagrams, plan views, etc. described below.

[0180] The fifth output switch 45C is connected to the fourth capacitor 14C and the input of the third buffer 23C, and switches between a conductive state and a non-conductive state between the fourth capacitor 14C and the input of the third buffer 23C. That is, the fifth output switch 45C is disposed on the electrical path between the fourth capacitor 14C and the input of the third buffer 23C, and switches between a conductive state and a non-conductive state between the fourth capacitor 14C and the input of the third buffer 23C. The fifth output switch 45C is indicated as SW52 in FIG. 11 and in the circuit diagrams, plan views, etc. described below.

[0181] The sixth output switch 46C is connected to the fifth capacitor 15C and the input of the third buffer 23C, and switches between a conductive state and a non-conductive state between the fifth capacitor 15C and the input of the third buffer 23C. That is, the fifth output switch 45C is disposed on the electrical path between the fifth capacitor 15C and the input of the third buffer 23C, and switches between a conductive state and a non-conductive state between the fifth capacitor 15C and the input of the third buffer 23C. The sixth output switch 46C is indicated as SW62 in FIG. 11 and in the circuit diagrams, plan views, etc. described below.

[0182] FIG. 12 is a schematic plan view showing an example of the physical configuration of the sample-and-hold circuit 10 shown in FIG.

[0183] 12, the X-axis direction is the column direction of the pixel array 70, and the Y-axis direction is the row direction of the pixel array 70. Therefore, FIG. 12 is a schematic plan view of the sample and hold circuit 10 in the plan view of the pixel array 70.

[0184] As shown in FIG. 12 , in a planar view of the sample and hold circuit 10, that is, in a planar view of the pixel array 70, the first output switch 41A and the first buffer 21A are adjacent to each other in the column direction of the pixel array 70 (the X-axis direction in FIG. 12 ), the second output switch 42A and the first buffer 21A are adjacent to each other in the column direction of the pixel array 70, the third output switch 43A and the second buffer 22A are adjacent to each other in the column direction of the pixel array 70, the fourth output switch 44A and the second buffer 22A are adjacent to each other in the column direction of the pixel array 70, the fifth output switch 45C and the third buffer 23C are adjacent to each other in the column direction of the pixel array 70, and the sixth output switch 46C and the third buffer 23C are adjacent to each other in the column direction of the pixel array 70.

[0185] According to the solid-state imaging device 1 including the sample-and-hold circuit 10 having the above-described configuration, it is possible to minimize the parasitic capacitance present on the electrical path between the first output switch 41A and the input of the first buffer 21A, the parasitic capacitance present on the electrical path between the second output switch 42A and the input of the first buffer 21A, the parasitic capacitance present on the electrical path between the third output switch 43A and the input of the second buffer 22A, the parasitic capacitance present on the electrical path between the fourth output switch 44A and the input of the second buffer 22A, the parasitic capacitance present on the electrical path between the fifth output switch 45C and the input of the third buffer 23C, and the parasitic capacitance present on the electrical path between the sixth output switch 46C and the input of the third buffer 23C.

[0186] Furthermore, according to the solid-state imaging device 1 including the sample-and-hold circuit 10 of the above configuration, it is possible to suppress relative variations in the parasitic capacitance present on the electrical path between the first input switch 31A and the first output switch 41A, the parasitic capacitance present on the electrical path between the second input switch 32A and the second output switch 42A, the parasitic capacitance present on the electrical path between the second input switch 32A and the third output switch 43A, the parasitic capacitance present on the electrical path between the third input switch 33A and the input of the fourth output switch 44A, the parasitic capacitance present on the electrical path between the fourth input switch 34C and the fifth output switch 45C, and the parasitic capacitance present on the electrical path between the fifth input switch 35C and the sixth output switch 46C.

[0187] Furthermore, the solid-state imaging device 1 having the sample-and-hold circuit 10 of the above configuration has a sample-and-hold circuit 10 having a first capacitor 11A, a second capacitor 12A, a third capacitor 13A, a fourth capacitor 14C, and a fifth capacitor 15C arranged in parallel with each other.

[0188] Therefore, the solid-state imaging device 1 including the sample-and-hold circuit 10 having the above configuration can realize high-speed imaging operation and also realize high-quality images.

[0189] As mentioned above, the sample and hold circuit 10 may further include one or more buffer inputs and one or more reset switches for resetting the capacitors.

[0190] 13 is a circuit diagram showing an example of the circuit configuration of the sample and hold circuit 10 shown in FIG. 11 when the sample and hold circuit 10 further includes a first reset switch 61A for resetting the input of the first buffer 21A with the initialization voltage Vinit, a second reset switch 62A for resetting the input of the second buffer 22A with the initialization voltage Vinit, and a third reset switch 63C for resetting the input of the third buffer 23C with the initialization voltage Vinit.

[0191] The third reset switch 63C is connected to the output of an initialization power supply that supplies the initialization voltage Vinit and to the input of the third buffer 23C, and switches between a conductive state and a non-conductive state between the output of the initialization power supply and the input of the third buffer 23C. That is, the third reset switch 63C is disposed on the electrical path between the output of the initialization power supply and the input of the third buffer 23C, and switches between a conductive state and a non-conductive state between the output of the initialization power supply and the input of the third buffer 23C. The third reset switch 63C is indicated as SW63 in FIG. 13 .

[0192] The solid-state imaging device 1 including the sample-and-hold circuit 10 configured as described above can reset the input of the first buffer 21A to the initialization voltage Vinit by turning on the first reset switch 61A.

[0193] Furthermore, the solid-state imaging device 1 including the sample-and-hold circuit 10 configured as described above can reset the input of the second buffer 22A to the initialization voltage Vinit by turning on the second reset switch 62A.

[0194] Furthermore, the solid-state imaging device 1 including the sample-and-hold circuit 10 configured as described above can reset the input of the third buffer 23C to the initialization voltage Vinit by turning on the third reset switch 63C.

[0195] [1.2. E. Configuration of Sample and Hold Circuit Having 4+2k (k is an integer equal to or greater than 1) Capacitors] Sample and hold circuit 10 having 4+2k capacitors can be realized, for example, by adding k circuit groups in parallel to sample and hold circuit 10 shown in FIG. 8 , each circuit group including a third capacitor 13B, a fourth capacitor 14B, a second buffer 22B, a third input switch 33B, a fourth input switch 34B, a third output switch 43B, and a fourth output switch 44B.

[0196] In this case, in each of the k additional circuit groups, the relative positional relationship between the third capacitor 13B, the fourth capacitor 14B, the second buffer 22B, the third input switch 33B, the fourth input switch 34B, the third output switch 43B, and the fourth output switch 44B that constitute the circuit group is maintained as shown in FIG.

[0197] Furthermore, a sample-and-hold circuit 10 having 4+2k capacitors can be realized by, for example, adding to the sample-and-hold circuit 10 shown in FIG. 10 k circuit groups each consisting of a third capacitor 13B, a fourth capacitor 14B, a second buffer 22B, a third input switch 33B, a fourth input switch 34B, a third output switch 43B, a fourth output switch 44B, and a second reset switch 62B in parallel.

[0198] In this case, in each of the k additional circuit groups, the relative positional relationship between the third capacitor 13B, the fourth capacitor 14B, the second buffer 22B, the third input switch 33B, the fourth input switch 34B, the third output switch 43B, and the fourth output switch 44B that constitute the circuit group is maintained as shown in FIG.

[0199] [1.2. F. Configuration of Sample and Hold Circuit Having 5+2k (k is an integer equal to or greater than 1) Capacitors] Sample and hold circuit 10 having 5+2k capacitors can be realized, for example, by adding k circuit groups in parallel to sample and hold circuit 10 shown in FIG. 11 , each circuit group including a fourth capacitor 14C, a fifth capacitor 15C, a third buffer 23C, a fourth input switch 34C, a fifth input switch 35C, a fifth output switch 45C, and a sixth output switch 46C.

[0200] In this case, in each of the k additional circuit groups, the relative positional relationship between the fourth capacitor 14C, the fifth capacitor 15C, the third buffer 23C, the fourth input switch 34C, the fifth input switch 35C, the fifth output switch 45C, and the sixth output switch 46C that constitute the circuit group is maintained as shown in FIG. 12.

[0201] Furthermore, a sample-and-hold circuit 10 having 5+2k capacitors can be realized by, for example, providing k parallel circuit groups each consisting of a fourth capacitor 14C, a fifth capacitor 15C, a third buffer 23C, a fourth input switch 34C, a fifth input switch 35C, a fifth output switch 45C, a sixth output switch 46C, and a third reset switch 63C in addition to the sample-and-hold circuit 10 shown in FIG. 13 .

[0202] In this case, in each of the k additional circuit groups, the relative positional relationship between the fourth capacitor 14C, the fifth capacitor 15C, the third buffer 23C, the fourth input switch 34C, the fifth input switch 35C, the fifth output switch 45C, and the sixth output switch 46C that constitute the circuit group is maintained as shown in FIG. 12.

[0203] [1.3. Operation of Solid-State Imaging Device] Hereinafter, the operation of the solid-state imaging device 1 having the above configuration will be described.

[0204] Here, the solid-state imaging device 1 will be described as an example in which the sample-and-hold circuit 10 included in the solid-state imaging device 1 has three capacitors and two reset switches as shown in FIG.

[0205] FIG. 14 is a timing chart of the first readout pipeline control process performed by the solid-state imaging device 1.

[0206] This first readout pipeline control process is a process of reading out pixel signals from pixels 3 in the reset state and pixel signals from pixels 3 in the exposed state by pipeline control in order to perform digital correlated double sampling.

[0207] Hereinafter, the pixel signal of the pixel 3 in the reset state will also be referred to as the reset level or the dark level, and the pixel signal of the pixel 3 in the exposed state will also be referred to as the signal level.

[0208] In FIG. 14, SW11 is a control signal for the first input switch 31A, which, at a logic high level, brings the vertical signal line 80 and the first capacitor 11A into a conductive state, and, at a logic low level, brings the vertical signal line 80 and the first capacitor 11A into a non-conductive state.

[0209] SW21 is a control signal for the second input switch 32A, which, at a logic high level, brings the vertical signal line 80 and the second capacitor 12A into a conductive state, and, at a logic low level, brings the vertical signal line 80 and the second capacitor 12A into a non-conductive state.

[0210] SW31 is a control signal for the third input switch 33A, which, at a logic high level, brings the vertical signal line 80 and the third capacitor 13A into a conductive state, and, at a logic low level, brings the vertical signal line 80 and the third capacitor 13A into a non-conductive state.

[0211] SW61 is a control signal for the first reset switch 61A, which, at a logic high level, brings the output of the initialization power supply and the input of the first buffer 21A into a conductive state, and, at a logic low level, brings the output of the initialization power supply and the input of the first buffer 21A into a non-conductive state.

[0212] SW62 is a control signal for the second reset switch 62A, which, at a logic high level, brings the output of the initialization power supply and the input of the second buffer 22A into a conductive state, and, at a logic low level, brings the output of the initialization power supply and the input of the second buffer 22A into a non-conductive state.

[0213] SW12 is a control signal for the first output switch 41A, which, at a logic high level, brings the first capacitor 11A and the input of the first buffer 21A into a conductive state, and, at a logic low level, brings the first capacitor 11A and the input of the first buffer 21A into a non-conductive state.

[0214] SW22 is a control signal for the second output switch 42A, which, at a logic high level, brings the second capacitor 12A and the input of the first buffer 21A into a conductive state, and, at a logic low level, brings the second capacitor 12A and the input of the first buffer 21A into a non-conductive state.

[0215] SW32 is a control signal for the third output switch 43A, which, at a logic high level, brings the second capacitor 12A and the input of the second buffer 22A into a conductive state, and, at a logic low level, brings the second capacitor 12A and the input of the second buffer 22A into a non-conductive state.

[0216] SW42 is a control signal for the fourth output switch 44A, which, at a logic high level, brings the third capacitor 13A and the input of the second buffer 22A into a conductive state, and, at a logic low level, brings the third capacitor 13A and the input of the second buffer 22A into a non-conductive state.

[0217] ADC indicates the operation performed by the AD conversion circuit 90, D.C. (DownCount) indicates the operation of reading out the dark level, and U.C. (UpCount) indicates the operation of reading out the signal level.

[0218] 14 , at time t1, the solid-state imaging device 1 sets the control signal SW21 to a high logic level, causing the second capacitor 12A to capture (for the first time) the dark level of the pixel 3. The period during which the control signal SW21 is at a high logic level continues until time t2.

[0219] After that, at time t3, the solid-state imaging device 1 sets the control signal SW11 to a high logic level, causing the first capacitor 11A to capture (for the first time) the signal level of the pixel 3. The period during which the control signal SW11 is at a high logic level continues until time t7.

[0220] After that, at time t4, the solid-state imaging device 1 sets the control signal SW61 to a logic high level, thereby resetting the input of the first buffer 21A to the initialization voltage Vinit. The logic high period of the control signal SW61 continues until time t5.

[0221] Then, at time t5, the solid-state imaging device 1 sets the control signal SW22 to a logic high level, thereby outputting the dark level of pixel 3 captured and held by the second capacitor 12A to the input of the first buffer 21A. The first buffer 21A then outputs a signal corresponding to the dark level captured and held by the second capacitor 12A to the AD conversion circuit 90. The AD conversion circuit 90 then AD converts the signal output from the first buffer 21A, i.e., the AD conversion circuit 90 reads out the dark level of pixel 3 (first time). The logic high level of the control signal SW22 continues until time t6.

[0222] After that, at time t6, the solid-state imaging device 1 sets the control signal SW61 to a logic high level, thereby resetting the input of the first buffer 21A to the initialization voltage Vinit. The logic high period of the control signal SW61 continues until time t8.

[0223] Then, at time t8, the solid-state imaging device 1 sets the control signal SW12 to a logic high level, thereby outputting the signal level of pixel 3 captured and held by the first capacitor 11A to the input of the first buffer 21A. The first buffer 21A then outputs a signal corresponding to the signal level captured and held by the first capacitor 11A to the AD conversion circuit 90. The AD conversion circuit 90 then AD converts the signal output from the first buffer 21A, i.e., reads out the signal level of pixel 3 (first time). The logic high level of the control signal SW12 continues until time t10.

[0224] After that, at time t9, the solid-state imaging device 1 sets the control signal SW21 to a logic high level, causing the second capacitor 12A to capture (for the second time) the dark level of the pixel 3. The period in which the control signal SW21 is at a logic high level continues until time t11.

[0225] Thereafter, at time t10, the solid-state imaging device 1 sets the control signal SW62 to a logic high level, thereby resetting the input of the second buffer 22A to the initialization voltage Vinit. The logic high period of the control signal SW62 continues until time t13.

[0226] After that, at time t12, the solid-state imaging device 1 sets the control signal SW31 to a high logic level, causing the third capacitor 13A to capture (for the second time) the signal level of the pixel 3. The period in which the control signal SW31 is at a high logic level continues until time t16.

[0227] Then, at time t13, the solid-state imaging device 1 sets the control signal SW32 to a logic high level, thereby outputting the dark level of pixel 3 captured and held by the second capacitor 12A to the input of the second buffer 22A. The second buffer 22A then outputs a signal corresponding to the dark level captured and held by the second capacitor 12A to the AD conversion circuit 90. The AD conversion circuit 90 then AD converts the signal output from the second buffer 22A, i.e., reads out the dark level of pixel 3 (for the second time). The logic high level of the control signal SW32 continues until time t14.

[0228] Thereafter, at time t14, the solid-state imaging device 1 sets the control signal SW62 to a logic high level, thereby resetting the input of the second buffer 22A to the initialization voltage Vinit. The logic high period of the control signal SW62 continues until time t15.

[0229] Then, at time t15, the solid-state imaging device 1 sets the control signal SW42 to a logic high level, thereby outputting the signal level of pixel 3 captured and held by the third capacitor 13A to the input of the second buffer 22A. The second buffer 22A then outputs a signal corresponding to the signal level captured and held by the third capacitor 13A to the AD conversion circuit 90. The AD conversion circuit 90 then AD converts the signal output from the second buffer 22A, i.e., reads out the signal level of pixel 3 (for the second time). The logic high level of the control signal SW32 continues until time t18.

[0230] As shown in FIG. 14, the control signals SW11, SW21, and SW31 are never at a logic high level at the same time.

[0231] Moreover, the input of the first buffer 21A is reset to the initialization voltage Vinit immediately before the control signal SW12 becomes logic high and immediately before the control signal SW22 becomes logic high.

[0232] Furthermore, while the input of the first buffer 21A is being reset with the initialization voltage Vinit, the control signals SW12 and SW22 do not become logic high.

[0233] Moreover, the input of the second buffer 22A is reset to the initialization voltage Vinit immediately before the control signal SW32 becomes logic high and immediately before the control signal SW42 becomes logic high.

[0234] Furthermore, while the input of the second buffer 22A is being reset with the initialization voltage Vinit, the control signals SW32 and SW42 do not become logic high.

[0235] Furthermore, the reading of the dark level of pixel 3 and the reading of the signal level of pixel 3 are performed alternately and repeatedly by (1) reading the dark level via the second capacitor 12A and the first buffer 21A and reading the signal level via the first capacitor 11A and the first buffer 21A, and (2) reading the dark level via the second capacitor 12A and the second buffer 22A and reading the signal level via the third capacitor 13A and the second buffer 22A.

[0236] (Modification 1) A solid-state imaging device according to Modification 1 will be described below, which is configured by changing the sample-and-hold circuit 10 of the solid-state imaging device 1 according to Embodiment 1 to a sample-and-hold circuit according to Modification 1.

[0237] Here, the sample and hold circuit of the first modification is configured by adding to the sample and hold circuit 10 of the first embodiment a fixed voltage output circuit that outputs a fixed potential operating voltage to one or more buffers (corresponding to the first buffer 21, the first buffer 21A, the second buffer 22A, the second buffer 22B, and the third buffer 23C in the first embodiment) to operate these one or more buffers, and one or more reset switches that are arranged on the electrical path between the output of the fixed voltage output circuit and each of the inputs of these one or more buffers.

[0238] Here, a solid-state imaging device according to Modification 1 will be described as an example in which the sample-and-hold circuit according to Modification 1 has two capacitors and one reset switch.

[0239] FIG. 15 is a circuit diagram showing an example of a circuit configuration of a sample-and-hold circuit 10D according to the first modification included in the solid-state imaging device according to the first modification.

[0240] As shown in FIG. 15, a sample-and-hold circuit 10D is configured by adding a fixed voltage output circuit 65D and a first reset switch 61D to the sample-and-hold circuit 10 shown in FIG.

[0241] In addition, here, as an example of a specific circuit configuration of the first buffer 21, the first buffer 21 is illustrated as being composed of a constant current source 212 and a source follower transistor 211.

[0242] The fixed voltage output circuit 65D outputs a fixed potential operating voltage to one or more buffers (here, the first buffer 21) that the sample and hold circuit 10D has, to operate these one or more buffers (here, the first buffer 21).

[0243] As an example, the fixed voltage output circuit 65D includes a transistor 651, a potential holding capacitor 652, and a potential holding switch 653, as shown in FIG.

[0244] Here, the transistor 651 is described as an n-channel transistor, but the transistor 651 is not necessarily limited to an n-channel transistor, and the transistor 651 may be a p-channel transistor.

[0245] The transistor 651 has a drain connected to the power supply wiring of the solid-state imaging device according to the first modification, and a source connected to the output of the fixed voltage output circuit 65D.

[0246] Here, the threshold voltage of the transistor 651 is assumed to be Vth.

[0247] The potential holding capacitor 652 is connected to the gate of the transistor 651 .

[0248] The potential holding switch 653 is a switch connected to the power supply wiring of the solid-state imaging device according to Modification 1 and the potential holding capacitor 652, and switches between a conductive state and a non-conductive state between the power supply wiring of the solid-state imaging device according to Modification 1 and the potential holding capacitor 652. In other words, the potential holding switch 653 is a switch arranged on the electrical path between the power supply wiring of the solid-state imaging device according to Modification 1 and the potential holding capacitor 652, and switches between a conductive state and a non-conductive state between the power supply wiring of the solid-state imaging device according to Modification 1 and the potential holding capacitor 652.

[0249] The first reset switch 61D is a switch connected to the output of the fixed voltage output circuit 65D and the input of the first buffer 21, and switches between a conductive state and a non-conductive state between the output of the fixed voltage output circuit 65D and the input of the first buffer 21. That is, the first reset switch 61D is a switch disposed on the electrical path between the output of the fixed voltage output circuit 65D and the input of the first buffer 21, and switches between a conductive state and a non-conductive state between the output of the fixed voltage output circuit 65D and the input of the first buffer 21. The first reset switch 61D is indicated as SW61 in FIG. 15 and in circuit diagrams, plan views, etc. described below.

[0250] The solid-state imaging device of variant 1 having the above configuration keeps the potential holding switch 653 in a conductive state during a period when the potential of the power supply wiring of the solid-state imaging device of variant 1 is stable at VDD, for example, a period excluding a period when the solid-state imaging device of variant 1 is reading out a pixel signal from pixel 3, and keeps the potential holding switch 653 in a non-conductive state during a period when the potential of the power supply wiring of the solid-state imaging device of variant 1 is not stable at VDD, for example, a period when the solid-state imaging device of variant 1 is reading out a pixel signal from pixel 3, thereby steadily stabilizing the potential of the gate of transistor 651 at VDD.

[0251] As a result, the fixed voltage output circuit 65D outputs an operating voltage of VDD-Vth, which is a fixed potential, to one or more buffers (here, the first buffer 21).

[0252] In the solid-state imaging device of variant 1 having the sample-and-hold circuit 10D of the above configuration, the operating voltage of one or more buffers (here, the first buffer 21) of the sample-and-hold circuit 10D is VDD-Vth, which is a fixed potential that is not affected by fluctuations in the power supply voltage, and therefore the operation of these one or more buffers (here, the first buffer 21) can be made more stable.

[0253] This also makes it possible to reset the input of one or more of these buffers (here, the first buffer 21) to a stable fixed voltage of VDD-Vth.

[0254] Therefore, the solid-state imaging device according to the first modification that includes the sample-and-hold circuit 10D having the above configuration can achieve even higher quality of the captured image.

[0255] (Modification 2) A solid-state imaging device according to Modification 2, which is configured by changing the sample-and-hold circuit 10D of the solid-state imaging device according to Modification 1 to a sample-and-hold circuit according to Modification 2, will be described below.

[0256] The sample-and-hold circuit according to the second modification is configured by adding a pull-up switch that pulls up the output of a fixed voltage output circuit 65D to the sample-and-hold circuit 10D according to the first modification.

[0257] Here, a solid-state imaging device according to Modification 2 will be described as an example in which the sample-and-hold circuit according to Modification 2 has two capacitors and one reset switch.

[0258] FIG. 16 is a circuit diagram showing an example of a circuit configuration of a sample-and-hold circuit 10E according to the second modification included in the solid-state imaging device according to the second modification.

[0259] As shown in FIG. 16, a sample-and-hold circuit 10E is configured by adding a pull-up switch 64E to the sample-and-hold circuit 10D shown in FIG.

[0260] The pull-up switch 64E is a switch that pulls up the output of the fixed voltage output circuit 65D, and is connected to the power supply wiring of the solid-state imaging device according to Modification 2 and the output of the fixed voltage output circuit 65D, and switches between a conductive state and a non-conductive state between the power supply wiring of the solid-state imaging device according to Modification 2 and the output of the fixed voltage output circuit 65D. In other words, the pull-up switch 64E is arranged on the electrical path between the power supply wiring of the solid-state imaging device according to Modification 2 and the output of the fixed voltage output circuit 65D, and switches between a conductive state and a non-conductive state between the power supply wiring of the solid-state imaging device according to Modification 2 and the output of the fixed voltage output circuit 65D. The pull-up switch 64E is indicated as SW64 in FIG. 16 and in circuit diagrams, plan views, etc. described below.

[0261] In the solid-state imaging device according to variant example 2 of the above configuration, by turning on the pull-up switch 64E during the period when one or more buffers (here, the first buffer 21) of the sample-and-hold circuit 10E are operating, the one or more buffers (here, the first buffer 21) can be operated at a potential pulled up from VDD-Vth to VDD, thereby widening the dynamic range of each buffer (here, the first buffer 21).

[0262] This makes it possible to improve the linearity of each buffer (here, the first buffer 21).

[0263] Therefore, the solid-state imaging device according to the second modification that includes the sample-and-hold circuit 10E having the above configuration can achieve even higher image quality for the captured image.

[0264] Here, the pull-up switch 64E has been described as a switch that pulls up the output of the fixed voltage output circuit 65D, but the pull-up switch 64 is not necessarily limited to a switch that pulls up the output of the fixed voltage output circuit 65D, and may also be a switch that pulls down the output of the fixed voltage output circuit 65D.

[0265] FIG. 17 is a timing chart showing an example of the operation performed by the solid-state imaging device according to the second modification.

[0266] 17, SW12 indicates the state of the first output switch 41. That is, when SW12 is "ON", the first output switch 41 is in a conductive state, and when SW12 is "OFF", the first output switch 41 is in a non-conductive state.

[0267] SW64 indicates the state of the pull-up switch 64E. That is, when SW64 is "ON", the pull-up switch 64E is in a conductive state, and when SW64 is "OFF", the pull-up switch 64E is in a non-conductive state.

[0268] SW61 indicates the state of the first reset switch 61D. That is, when SW61 is "ON", the first reset switch 61D is in a conductive state, and when SW61 is "OFF", the first reset switch 61D is in a non-conductive state.

[0269] As shown in FIG. 17 , the solid-state imaging device according to variant 2 having the sample-and-hold circuit 10E configured as described above may, for example, set the pull-up switch 64E and the first output switch 41 to a non-conductive state during the reset period when the first reset switch 61D is in a conductive state, and set the pull-up switch 64E to a conductive state during the readout period when the first output switch 41 is in a conductive state, thereby widening the dynamic range of the first buffer 21.

[0270] Second Embodiment Hereinafter, a solid-state imaging device according to a second embodiment will be described, which is configured by partially modifying the configuration of the solid-state imaging device 1 according to the first embodiment.

[0271] Regarding the solid-state imaging device of embodiment 2, components that are similar to those of solid-state imaging device 1 have already been explained, so they will be assigned the same symbols and their detailed explanations will be omitted, and the explanation will focus on the differences from solid-state imaging device 1.

[0272] [2.1. Configuration of Solid-State Imaging Device] FIG. 18 is a block diagram showing the configuration of a solid-state imaging device 1F according to the second embodiment.

[0273] As shown in FIG. 18, the solid-state imaging device 1F is configured by changing the pixel array 70 of the solid-state imaging device 1 according to embodiment 1 to a pixel array 70F, changing the vertical scanning circuit 71 to a vertical scanning circuit 71F, changing the multiple vertical signal lines 80 to multiple first vertical signal lines 81F and multiple second vertical signal lines 82F, and changing the multiple sample-and-hold circuits 10 to multiple sample-and-hold circuits 10F.

[0274] The pixel array 70F is configured by replacing the plurality of pixels 3 in the pixel array 70 with a plurality of pixels 3F.

[0275] Pixel 3F has a photoelectric conversion unit that converts exposed light into a signal charge, and a signal charge holding unit that holds the signal charge converted by the photoelectric conversion unit, and outputs multiple pixel signals with different gains according to the signal charge held in the signal charge holding unit.

[0276] Here, the pixel 3F will be described as outputting two pixel signals: a first pixel signal and a second pixel signal having a higher gain than the first pixel signal.

[0277] Hereinafter, the first pixel signal may be referred to as an LCG (Low Conversion Gain) signal or simply as LCG, and the second pixel signal may be referred to as an HCG (High Conversion Gain) signal or simply as HCG.

[0278] Each of the multiple first vertical signal lines 81F extends in the column direction of the pixel array 70F (the X-axis direction in Figure 18), is connected to m pixels 3F arranged in the column direction of the pixel array 70F, and transmits a first pixel signal output from at least one of the connected pixels 3F.

[0279] That is, the number of the plurality of first vertical signal lines 81F included in the solid-state imaging device 1F is n, which is the same as the number of columns of the pixel array 70F, or an integer multiple of n. Here, the description will be given assuming that the number of the plurality of first vertical signal lines 81F is n, which is the same as the number of columns of the pixel array 70F.

[0280] Each of the multiple second vertical signal lines 82F extends in the column direction of the pixel array 70F, is connected to m pixels 3F arranged in the column direction of the pixel array 70F, and transmits a second pixel signal output from at least one of the connected pixels 3F.

[0281] That is, the number of the second vertical signal lines 82F included in the solid-state imaging device 1F is n, which is the same as the number of columns in the pixel array 70F, or an integer multiple of n. Here, the description will be given assuming that the number of the second vertical signal lines 82F is n, which is the same as the number of columns in the pixel array 70F.

[0282] The vertical scanning circuit 71F sequentially selects and scans the multiple pixels 3F that make up the pixel array 70F row by row, thereby causing each of the n pixels 3F belonging to the row to be scanned to simultaneously output a first pixel signal to each of the n first vertical signal lines 81F, and simultaneously output a second pixel signal to each of the n second vertical signal lines 82F.

[0283] Each of the plurality of sample-and-hold circuits 10F corresponds one-to-one to each of the plurality of first vertical signal lines 81F and each of the plurality of second vertical signal lines 82F, and holds the first pixel signal transmitted by the corresponding first vertical signal line 81F and the second pixel signal transmitted by the corresponding second vertical signal line 82F.

[0284] That is, the number of the plurality of sample and hold circuits 10F included in the solid-state imaging device 1F is n, which is the same as the number of columns of the pixel array 70F, or an integer multiple of n. Here, the description will be given assuming that the number of the plurality of sample and hold circuits 10F is n, which is the same as the number of columns of the pixel array 70F.

[0285] The sample and hold circuit 10F has one or more capacitors arranged in parallel to hold the first pixel signals and one or more capacitors arranged in parallel to hold the second pixel signals. That is, the sample and hold circuit 10F can hold one or more first pixel signals and one or more second pixel signals. The sample and hold circuit 10F also has one or more buffers for buffering the one or more first pixel signals and the one or more second pixel signals. The sample and hold circuit 10F outputs a signal corresponding to either the one or more first pixel signals or the one or more second pixel signals.

[0286] [2.2. Configuration of Sample-and-Hold Circuit] A specific configuration of the sample-and-hold circuit 10F will now be described.

[0287] As described above, the sample and hold circuit 10F has one or more capacitors arranged in parallel to each other for holding the first pixel signal, and one or more capacitors arranged in parallel to each other for holding the second pixel signal.

[0288] In the following description, the capacitor for holding the first pixel signal is also referred to as an LCG capacitor, and the capacitor for holding the second pixel signal is also referred to as an HCG capacitor.

[0289] First, the configuration of the sample-and-hold circuit 10F having one LCG capacitor and one HCG capacitor will be described.

[0290] [2.2. A. Configuration of Sample-and-Hold Circuit Having One LCG Capacitor and One HCG Capacitor] FIG. 19 is a circuit diagram showing an example of the circuit configuration of a sample-and-hold circuit 10F having one LCG capacitor and one HCG capacitor.

[0291] As shown in FIG. 19, the sample and hold circuit 10F has a first capacitor 11F, a second capacitor 12F, a first buffer 21F, a first input switch 31F, a second input switch 32F, a first output switch 41F, a second output switch 42F, an input 511F, an input 512F, and an output 52F.

[0292] The input 511F is connected to the first vertical signal line 81F.

[0293] The input 512F is connected to the second vertical signal line 82F.

[0294] The output 52F is connected to an AD conversion circuit 90.

[0295] The first capacitor 11F is a capacitor for holding a first pixel signal. That is, the first capacitor 11F is a capacitor for LCG. The first capacitor 11F is indicated as C1 in FIG. 19 and in circuit diagrams, plan views, and the like described below.

[0296] The second capacitor 12F is a capacitor for holding the second pixel signal. That is, the second capacitor 12F is an HCG capacitor. The capacitance of the first capacitor 11F is smaller than the capacitance of the second capacitor 12F. The second capacitor 12F is indicated as C2 in FIG. 19 and in circuit diagrams, plan views, etc. described below.

[0297] The first buffer 21F is a buffer that buffers the pixel signal held in the first capacitor 11F or the pixel signal held in the second capacitor 12F, the output of which is connected to the output 52F, i.e., the output of which is connected to the AD conversion circuit 90. The first buffer 21F is indicated as buf1 in FIG. 19 and in circuit diagrams, plan views, etc. described below.

[0298] The first input switch 31F is a switch connected to the input 511F and the first capacitor 11F, and switches the input 511F and the first capacitor 11F between a conductive state and a non-conductive state. That is, the first input switch 31F is a switch disposed on the electrical path between the first vertical signal line 81F and the first capacitor 11F, and switches the first vertical signal line 81F and the first capacitor 11F between a conductive state and a non-conductive state. The first input switch 31F is indicated as SW11 in FIG. 19 and in circuit diagrams, plan views, etc. described later.

[0299] The second input switch 32F is a switch connected to the input 512F and the second capacitor 12F, and switches the input 512F and the second capacitor 12F between a conductive state and a non-conductive state. That is, the second input switch 32F is a switch disposed on the electrical path between the second vertical signal line 82F and the second capacitor 12F, and switches the second vertical signal line 82F and the second capacitor 12F between a conductive state and a non-conductive state. The second input switch 32F is indicated as SW21 in FIG. 19 and in circuit diagrams, plan views, etc. described below.

[0300] The first output switch 41F is a switch connected to the first capacitor 11F and the input of the first buffer 21F, and switches between a conductive state and a non-conductive state between the first capacitor 11F and the input of the first buffer 21F. That is, the first output switch 41F is a switch disposed on the electrical path between the first capacitor 11F and the input of the first buffer 21F, and switches between a conductive state and a non-conductive state between the first capacitor 11F and the input of the first buffer 21F. The first output switch 41F is indicated as SW12 in FIG. 19 and in circuit diagrams, plan views, etc. described below.

[0301] The second output switch 42F is a switch connected to the second capacitor 12F and the input of the first buffer 21F, and switches between a conductive state and a non-conductive state between the second capacitor 12F and the input of the first buffer 21F. That is, the second output switch 42F is a switch disposed on the electrical path between the second capacitor 12F and the input of the first buffer 21F, and switches between a conductive state and a non-conductive state between the second capacitor 12F and the input of the first buffer 21F. The second output switch 42F is indicated as SW22 in FIG. 19 and in circuit diagrams, plan views, etc. described below.

[0302] FIG. 20 is a schematic plan view showing an example of the physical configuration of the sample-and-hold circuit 10F shown in FIG.

[0303] 20, the X-axis direction is the column direction of the pixel array 70F, and the Y-axis direction is the row direction of the pixel array 70F. Therefore, Fig. 20 is a schematic plan view of the sample and hold circuit 10F in the plan view of the pixel array 70F.

[0304] As shown in Figure 20, in a planar view of the sample and hold circuit 10F, that is, in a planar view of the pixel array 70F, the distance between the first output switch 41F and the first buffer 21F in the column direction of the pixel array 70F (the X-axis direction in Figure 20) is shorter than the distance between the second output switch 42F and the first buffer 21F in the column direction of the pixel array 70F.

[0305] In the solid-state imaging device 1F including the sample-and-hold circuit 10F configured as described above, the parasitic capacitance between the first output switch 41F and the input of the first buffer 21F, which exists on the electrical path between the first capacitor 11F having a smaller capacitance and the input of the first buffer 21F, can be made smaller than the parasitic capacitance between the second output switch 42F and the input of the first buffer 21F, which exists on the electrical path between the second capacitor 12F having a larger capacitance and the input of the first buffer 21F. This makes it possible to suppress the influence of charge redistribution accompanying the operation of the first output switch 41F and / or the second output switch 42F.

[0306] Furthermore, the solid-state imaging device 1F including the sample-and-hold circuit 10F configured as described above includes the sample-and-hold circuit 10F having a first capacitor 11F and a second capacitor 12F arranged in parallel with each other.

[0307] Therefore, the solid-state imaging device 1F including the sample-and-hold circuit 10F having the above configuration can realize high-speed imaging operation and also realize high-quality images.

[0308] The sample-and-hold circuit 10F may further include one or more buffer inputs, one or more LCG capacitors, and one or more reset switches for resetting one or more HCG capacitors.

[0309] FIG. 21 is a circuit diagram showing an example of the circuit configuration of the sample-and-hold circuit 10F shown in FIG. 19 when the sample-and-hold circuit 10F further includes a first reset switch 61F for resetting the input of the first buffer 21F, the first capacitor 11F, and the second capacitor 12F with an initialization voltage Vinit.

[0310] The first reset switch 61F is connected to the output of an initialization power supply that supplies the initialization voltage Vinit and to the input of the first buffer 21F, and switches between a conductive state and a non-conductive state between the output of the initialization power supply and the input of the first buffer 21F. That is, the first reset switch 61F is disposed on the electrical path between the output of the initialization power supply and the input of the first buffer 21F, and switches between a conductive state and a non-conductive state between the output of the initialization power supply and the input of the first buffer 21F. The first reset switch 61F is denoted as SW61 in FIG. 21 .

[0311] The solid-state imaging device 1F including the sample-and-hold circuit 10F having the above configuration can reset the input of the first buffer 21F to the initialization voltage Vinit by turning on the first reset switch 61F.

[0312] Next, a configuration of the sample-and-hold circuit 10F having two LCG capacitors arranged in parallel with each other and two HCG capacitors arranged in parallel with each other will be described.

[0313] [2.2. B. Configuration of Sample-and-Hold Circuit Having Two LCG Capacitors and Two HCG Capacitors] FIG. 22 is a circuit diagram showing an example of the circuit configuration of a sample-and-hold circuit 10F having two LCG capacitors and two HCG capacitors.

[0314] As shown in FIG. 22, the sample and hold circuit 10F is configured by adding a third capacitor 13G, a fourth capacitor 14G, a third input switch 33G, a fourth input switch 34G, a third output switch 43G, a fourth output switch 44G, an input 513G, and an input 514G to the sample and hold circuit 10F shown in FIG. 19 which has one LCG capacitor and one HCG capacitor.

[0315] The input 513G is connected to the first vertical signal line 81F.

[0316] The input 514G is connected to the second vertical signal line 82F.

[0317] The third capacitor 13G is a capacitor for holding the first pixel signal. That is, the third capacitor 13G is an LCG capacitor. The capacitance of the third capacitor 13G is equal to the capacitance of the first capacitor 11F. The third capacitor 13G is indicated as C3 in FIG. 22 and in circuit diagrams, plan views, and the like described below.

[0318] The fourth capacitor 14G is a capacitor for holding the second pixel signal. That is, the fourth capacitor 14G is an HCG capacitor. The capacitance of the fourth capacitor 14G is equal to the capacitance of the second capacitor 12F. The fourth capacitor 14G is indicated as C4 in FIG. 22 and in circuit diagrams, plan views, and the like described below.

[0319] The third input switch 33G is a switch connected to the input 513G and the third capacitor 13G, and switches the input 513G and the third capacitor 13G between a conductive state and a non-conductive state. That is, the third input switch 33G is a switch disposed on the electrical path between the first vertical signal line 81F and the third capacitor 13G, and switches the first vertical signal line 81F and the third capacitor 13G between a conductive state and a non-conductive state. The third input switch 33G is indicated as SW31 in FIG. 22 and in circuit diagrams, plan views, etc. described below.

[0320] The fourth input switch 34G is a switch connected to the input 514G and the fourth capacitor 14G, and switches the input 514G and the fourth capacitor 14G between a conductive state and a non-conductive state. That is, the fourth input switch 34G is a switch disposed on the electrical path between the second vertical signal line 82F and the fourth capacitor 14G, and switches the second vertical signal line 82F and the fourth capacitor 14G between a conductive state and a non-conductive state. The fourth input switch 34G is indicated as SW41 in FIG. 22 and in circuit diagrams, plan views, etc. described below.

[0321] The third output switch 43G is a switch connected to the third capacitor 13G and the input of the first buffer 21F, and switches between a conductive state and a non-conductive state between the third capacitor 13G and the input of the first buffer 21F. That is, the third output switch 43G is disposed on the electrical path between the third capacitor 13G and the input of the first buffer 21F, and switches between a conductive state and a non-conductive state between the third capacitor 13G and the input of the first buffer 21F. The third output switch 43G is indicated as SW32 in FIG. 22 and in circuit diagrams, plan views, etc. described below.

[0322] The fourth output switch 44G is a switch connected to the fourth capacitor 14G and the input of the first buffer 21F, and switches between a conductive state and a non-conductive state between the fourth capacitor 14G and the input of the first buffer 21F. That is, the fourth output switch 44G is disposed on the electrical path between the fourth capacitor 14G and the input of the first buffer 21F, and switches between a conductive state and a non-conductive state between the fourth capacitor 14G and the input of the first buffer 21F. The fourth output switch 44G is indicated as SW42 in FIG. 22 and in circuit diagrams, plan views, etc. described below.

[0323] FIG. 23 is a schematic plan view showing an example of the physical configuration of the sample-and-hold circuit 10F shown in FIG.

[0324] 23, the X-axis direction is the column direction of the pixel array 70F, and the Y-axis direction is the row direction of the pixel array 70F. Therefore, Fig. 23 is a schematic plan view of the sample and hold circuit 10F in the plan view of the pixel array 70F.

[0325] As shown in FIG. 23 , in a planar view of the sample and hold circuit 10F, that is, in a planar view of the pixel array 70F, the distance between the first output switch 41F and the first buffer 21F in the column direction of the pixel array 70F (the X-axis direction in FIG. 20 ) is shorter than the distance between the second output switch 42F and the first buffer 21F in the column direction of the pixel array 70F, and the distance between the third output switch 43G and the first buffer 21F in the column direction of the pixel array 70F is shorter than the distance between the fourth output switch 44G and the first buffer 21F in the column direction of the pixel array 70F.

[0326] With the solid-state imaging device 1F including the sample-and-hold circuit 10F configured as described above, the parasitic capacitance between the first output switch 41F and the input of the first buffer 21F, which exists on the electrical path between the first capacitor 11F having a smaller capacitance and the input of the first buffer 21F, can be made smaller than the parasitic capacitance between the second output switch 42F and the input of the first buffer 21F, which exists on the electrical path between the second capacitor 12F having a larger capacitance and the input of the first buffer 21F, and the parasitic capacitance between the third output switch 43G and the first buffer 21F, which exists on the electrical path between the third capacitor 13G having a smaller capacitance and the input of the first buffer 21F, can be made smaller than the parasitic capacitance between the fourth output switch 44G and the first buffer 21F, which exists on the electrical path between the fourth capacitor 14G having a larger capacitance and the input of the first buffer 21F. This makes it possible to suppress the influence of charge redistribution caused by the operation of the first output switch 41F, the second output switch 42F, the third output switch 43G, and / or the fourth output switch 44G.

[0327] Furthermore, the solid-state imaging device 1F equipped with the sample-and-hold circuit 10F having the above-described configuration includes a sample-and-hold circuit 10F having a first capacitor 11F, a second capacitor 12F, a third capacitor 13G, and a fourth capacitor 14G arranged in parallel with each other.

[0328] Therefore, the solid-state imaging device 1F including the sample-and-hold circuit 10F having the above configuration can realize high-speed imaging operation and also realize high-quality images.

[0329] FIG. 24 is a timing chart showing an example of the operation performed by the solid-state imaging device 1F including the sample-and-hold circuit 10F having the above configuration.

[0330] 24, SW11 indicates the state of the first input switch 31F. That is, when SW11 is "ON", the first input switch 31F is in a conductive state, and when SW11 is "OFF", the first input switch 31F is in a non-conductive state.

[0331] SW21 indicates the state of the second input switch 32F. That is, when SW21 is “ON”, the second input switch 32F is in a conductive state, and when SW21 is “OFF”, the second input switch 32F is in a non-conductive state.

[0332] SW31 indicates the state of the third input switch 33G. That is, when SW31 is "ON", the third input switch 33G is in a conductive state, and when SW31 is "OFF", the third input switch 33G is in a non-conductive state.

[0333] SW41 indicates the state of the fourth input switch 34G. That is, when SW41 is "ON", the fourth input switch 34G is in a conductive state, and when SW41 is "OFF", the fourth input switch 34G is in a non-conductive state.

[0334] SW12 indicates the state of the first output switch 41F. That is, when SW12 is "ON", the first output switch 41F is in a conductive state, and when SW12 is "OFF", the first output switch 41F is in a non-conductive state.

[0335] SW22 indicates the state of the second output switch 42F. That is, when SW22 is “ON”, the second output switch 42F is in a conductive state, and when SW22 is “OFF”, the second output switch 42F is in a non-conductive state.

[0336] SW32 indicates the state of the third output switch 43G. That is, when SW32 is "ON", the third output switch 43G is in a conductive state, and when SW32 is "OFF", the third output switch 43G is in a non-conductive state.

[0337] SW42 indicates the state of the fourth output switch 44G. That is, when SW42 is "ON", it indicates that the fourth output switch 44G is in a conductive state, and when SW42 is "OFF", it indicates that the fourth output switch 44G is in a non-conductive state.

[0338] As shown in FIG. 24 , a solid-state imaging device 1F including a sample and hold circuit 10F having the above configuration can read out the first pixel signal and the second pixel signal from pixel 3F by pipeline control, for example, by controlling the sampling periods of the sample and hold circuit 10F, i.e., the period when SW11 is “ON”, the period when SW21 is “ON”, the period when SW31 is “ON”, and the period when SW41 is “ON”, so that they do not overlap with the output selection periods of the sample and hold circuit 10, i.e., the period when SW12 is “ON”, the period when SW22 is “ON”, the period when SW32 is “ON”, and the period when SW42 is “ON”.

[0339] As a result, the solid-state imaging device 1F including the sample-and-hold circuit 10F having the above configuration can achieve high-speed imaging operations.

[0340] The sample-and-hold circuit 10F may further include one or more buffer inputs, one or more LCG capacitors, and one or more reset switches for resetting one or more HCG capacitors.

[0341] FIG. 25 is a circuit diagram showing an example of the circuit configuration of the sample-and-hold circuit 10F shown in FIG. 23 when the sample-and-hold circuit 10F further has an input of a first buffer 21F, a first capacitor 11F, a second capacitor 12F, a third capacitor 13G, a fourth capacitor 14G, and a first reset switch 61H for resetting with an initialization voltage Vinit.

[0342] The first reset switch 61H is connected to the output of an initialization power supply that supplies the initialization voltage Vinit and to the input of the first buffer 21F, and switches between a conductive state and a non-conductive state between the output of the initialization power supply and the input of the first buffer 21F. That is, the first reset switch 61H is disposed on the electrical path between the output of the initialization power supply and the input of the first buffer 21F, and switches between a conductive state and a non-conductive state between the output of the initialization power supply and the input of the first buffer 21F. The first reset switch 61H is denoted as SW61 in FIG. 25 .

[0343] The solid-state imaging device 1F including the sample-and-hold circuit 10F configured as described above can reset the input of the first buffer 21F to the initialization voltage Vinit by turning on the first reset switch 61H.

[0344] 26 is a circuit diagram showing an example of the circuit configuration of the sample and hold circuit 10F shown in FIG. 23 when the sample and hold circuit 10F further includes a first selection switch 66I arranged on the electrical path between the first output switch 41F and the second output switch 42F and the first buffer 21F, and a second selection switch 67I arranged on the electrical path between the third output switch 43G and the fourth output switch 44G and the first buffer 21F.

[0345] The first selection switch 66I is a switch connected to the first output switch 41F, the second output switch 42F, and the first buffer 21F, and switches between a conductive state and a non-conductive state among the first output switch 41F, the second output switch 42F, and the first buffer 21F. That is, the first selection switch 66I is a switch arranged on the electrical path between the first output switch 41F, the second output switch 42F, and the first buffer 21F, and switches between a conductive state and a non-conductive state among the first output switch 41F, the second output switch 42F, and the first buffer 21F. The first selection switch 66I is denoted as SW66 in FIG. 26 .

[0346] The second selection switch 67I is a switch connected to the third output switch 43G and the fourth output switch 44G and the first buffer 21F, and switches between a conductive state and a non-conductive state between the third output switch 43G and the fourth output switch 44G and the first buffer 21F. That is, the second selection switch 67I is a switch arranged on the electrical path between the third output switch 43G and the fourth output switch 44G and the first buffer 21F, and switches between a conductive state and a non-conductive state between the third output switch 43G and the fourth output switch 44G and the first buffer 21F. The second selection switch 67I is denoted as SW67 in FIG. 26 .

[0347] 27 is a schematic plan view showing an example of the physical configuration of the sample and hold circuit 10F shown in FIG. 26, and FIG. 28 is a schematic plan view showing another example of the physical configuration of the sample and hold circuit 10F shown in FIG. 26.

[0348] 27 and 28, the X-axis direction is the column direction of the pixel array 70F, and the Y-axis direction is the row direction of the pixel array 70F. Therefore, FIGS. 27 and 28 are schematic plan views of the sample and hold circuit 10F in the plan view of the pixel array 70F.

[0349] As shown in Figures 27 and 28, in a planar view of the sample and hold circuit 10F, that is, in a planar view of the pixel array 70F, the first selection switch 66I and the first buffer 21F are adjacent to each other in the column direction of the pixel array 70F (the X-axis direction in Figures 26 and 27), and the second selection switch 67I and the first buffer 21F are adjacent to each other in the column direction of the pixel array 70F.

[0350] A solid-state imaging device 1F having a sample and hold circuit 10F of the above configuration can suppress the parasitic capacitance present on the electrical path between the third output switch 43G and the fourth output switch 44G and the input of the first buffer 21F, as well as the parasitic capacitance present on the electrical path between the first output switch 41F and the second output switch 42F and the input of the first buffer 21F, compared to a configuration that does not have the first selection switch 66I and the second selection switch 67I (for example, a solid-state imaging device 1F having a sample and hold circuit 10F of the configuration shown in Figure 26).

[0351] Therefore, the solid-state imaging device 1F including the sample-and-hold circuit 10F having the above configuration can realize high-speed imaging operation and also realize high-quality images.

[0352] [2.2.C. Configuration of Sample and Hold Circuit Having 2+k (k is an integer of 1 or more) LCG Capacitors and 2+k HCG Capacitors] A sample and hold circuit 10F having 2+k LCG capacitors and 2+k HCG capacitors can be realized by, for example, adding to the sample and hold circuit 10F shown in FIG. 22 k k circuit groups each including a third capacitor 13G, a fourth capacitor 14G, a third input switch 33G, a fourth input switch 34G, a third output switch 43G, a fourth output switch 44G, an input 513G, and an input 514G in parallel.

[0353] In this case, in each of the k further circuit groups, the relative positional relationship between the first buffer 21F, the third output switch 43G, and the fourth output switch 44G that constitute the circuit group is maintained such that, in a planar view of the sample and hold circuit 10F, that is, in a planar view of the pixel array 70F, the distance between the third output switch 43G and the first buffer 21F in the column direction of the pixel array 70F is shorter than the distance between the fourth output switch 44G and the first buffer 21F in the column direction of the pixel array 70F.

[0354] Furthermore, a sample and hold circuit 10F having 2+k capacitors for LCG and 2+k capacitors for HCG can be realized by, for example, providing k parallel circuit groups each consisting of a third capacitor 13G, a fourth capacitor 14G, a third input switch 33G, a fourth input switch 34G, a third output switch 43G, a fourth output switch 44G, an input 513G, and an input 514G in addition to the sample and hold circuit 10F shown in FIG.

[0355] In this case, in each of the k further circuit groups, the relative positional relationship between the first buffer 21F, the third output switch 43G, and the fourth output switch 44G that constitute the circuit group is maintained such that, in a planar view of the sample and hold circuit 10F, that is, in a planar view of the pixel array 70F, the distance between the third output switch 43G and the first buffer 21F in the column direction of the pixel array 70F is shorter than the distance between the fourth output switch 44G and the first buffer 21F in the column direction of the pixel array 70F.

[0356] [2.3. Operation of Solid-State Imaging Device] Hereinafter, the operation of the solid-state imaging device 1F having the above configuration will be described.

[0357] Here, we will explain an example of a solid-state imaging device 1F in which the sample-and-hold circuit 10F provided in the solid-state imaging device 1F has two LCG capacitors, two HCG capacitors, and one reset switch, as shown in Figure 25.

[0358] FIG. 29 is a timing chart of the second readout pipeline control process performed by the solid-state imaging device 1F.

[0359] This second readout pipeline control process is a process of reading out, by pipeline control, the first pixel signal (LCG signal) and the second pixel signal (HCG signal) from the pixel 3F in the reset state, and the first pixel signal (LCG signal) and the second pixel signal (HCG signal) from the pixel 3F in the exposed state, in order to perform digital correlated double sampling.

[0360] Hereinafter, the first pixel signal of pixel 3F in the reset state will also be referred to as the LCG reset level or the LCG dark level, the first pixel signal of pixel 3F in the exposed state will also be referred to as the LCG signal level, the second pixel signal of pixel 3F in the reset state will also be referred to as the HCG reset level or the HCG dark level, and the second pixel signal of pixel 3F in the exposed state will also be referred to as the HCG signal level.

[0361] In FIG. 29, SW11 is a control signal for the first input switch 31F, which, at a logic high level, brings the first vertical signal line 81F and the first capacitor 11F into a conductive state, and, at a logic low level, brings the first vertical signal line 81F and the first capacitor 11F into a non-conductive state.

[0362] SW21 is a control signal for the second input switch 32F, which, at a logic high level, brings the second vertical signal line 82F and the second capacitor 12F into a conductive state, and, at a logic low level, brings the second vertical signal line 82F and the second capacitor 12F into a non-conductive state.

[0363] SW41 is a control signal for the fourth input switch 34G, which, at a logic high level, brings the second vertical signal line 82F and the fourth capacitor 14G into a conductive state, and, at a logic low level, brings the second vertical signal line 82F and the fourth capacitor 14G into a non-conductive state.

[0364] SW31 is a control signal for the third input switch 33G, which, at a logic high level, brings the first vertical signal line 81F and the third capacitor 13G into a conductive state, and, at a logic low level, brings the first vertical signal line 81F and the third capacitor 13G into a non-conductive state.

[0365] SW12 is a control signal for the first output switch 41F, which, at a logic high level, brings the first capacitor 11F and the input of the first buffer 21F into a conductive state, and, at a logic low level, brings the first capacitor 11F and the input of the first buffer 21F into a non-conductive state.

[0366] SW22 is a control signal for the second output switch 42F, which, at a logic high level, brings the second capacitor 12F and the input of the first buffer 21F into a conductive state, and, at a logic low level, brings the second capacitor 12F and the input of the first buffer 21F into a non-conductive state.

[0367] SW42 is a control signal for the fourth output switch 44G, which, at a logic high level, brings the fourth capacitor 14G and the input of the first buffer 21F into a conductive state, and, at a logic low level, brings the fourth capacitor 14G and the input of the first buffer 21F into a non-conductive state.

[0368] SW32 is a control signal for the third output switch 43G, which, at a logic high level, brings the third capacitor 13G and the input of the first buffer 21F into a conductive state, and, at a logic low level, brings the third capacitor 13G and the input of the first buffer 21F into a non-conductive state.

[0369] SW61 is a control signal for the first reset switch 61H, which, at a logic high level, brings the output of the initialization power supply and the input of the first buffer 21F into a conductive state, and, at a logic low level, brings the output of the initialization power supply and the input of the first buffer 21F into a non-conductive state.

[0370] ADC indicates the operation performed by the AD conversion circuit 90, D.C. (DownCount) indicates the operation of reading out the dark level, and U.C. (UpCount) indicates the operation of reading out the signal level.

[0371] 29, at time t1, the solid-state imaging device 1F sets the control signal SW11 to a high logic level, causing the first capacitor 11F to capture the LCG dark level of the pixel 3F. The period during which the control signal SW11 is at a high logic level continues until time t2.

[0372] Thereafter, at time t3, the solid-state imaging device 1F sets the control signal SW21 to a logic high level, causing the second capacitor 12F to capture the HCG dark level of the pixel 3F. The period during which the control signal SW21 is at a logic high level continues until time t4.

[0373] Thereafter, at time t5, the solid-state imaging device 1F sets the control signal SW41 to a logic high level, causing the fourth capacitor 14G to capture the HCG signal level of the pixel 3F. The period during which the control signal SW41 is at a logic high level continues until time t10.

[0374] After that, at time t6, the solid-state imaging device 1F sets the control signal SW61 to a logic high level, thereby resetting the input of the first buffer 21F to the initialization voltage Vinit. The logic high period of the control signal SW61 continues until time t7.

[0375] Thereafter, at time t7, the solid-state imaging device 1F sets the control signal SW22 to a logic high level, thereby outputting the HCG dark level of pixel 3F captured and held by the second capacitor 12F to the input of the first buffer 21F. The first buffer 21F then outputs a signal corresponding to the HCG dark level captured and held by the second capacitor 12F to the AD conversion circuit 90. The AD conversion circuit 90 then AD-converts the signal output from the first buffer 21F, i.e., reads out the HCG dark level of pixel 3. The logic high level of the control signal SW22 continues until time t8.

[0376] After that, at time t9, the solid-state imaging device 1F sets the control signal SW61 to a logic high level, thereby resetting the input of the first buffer 21F to the initialization voltage Vinit. The logic high period of the control signal SW61 continues until time t11.

[0377] Thereafter, at time t11, the solid-state imaging device 1 sets the control signal SW42 to a logic high level, thereby outputting the HCG signal level of pixel 3F captured and held by the fourth capacitor 14G to the input of the first buffer 21F. The first buffer 21F then outputs a signal corresponding to the HCG signal level captured and held by the fourth capacitor 14G to the AD conversion circuit 90. The AD conversion circuit 90 then AD-converts the signal output from the first buffer 21F, i.e., reads out the HCG signal level of pixel 3F. The logic high level of the control signal SW42 continues until time t13.

[0378] Thereafter, at time t12, the solid-state imaging device 1F sets the control signal SW31 to a logic high level, causing the third capacitor 13G to capture the LCG signal level of the pixel 3F. The period during which the control signal SW31 is at a logic high level continues until time t15.

[0379] Thereafter, at time t14, the solid-state imaging device 1F sets the control signal SW61 to a logic high level, thereby resetting the input of the first buffer 21F to the initialization voltage Vinit. The logic high period of the control signal SW61 continues until time t16.

[0380] Thereafter, at time t16, the solid-state imaging device 1F sets the control signal SW12 to a logic high level, thereby outputting the LCG dark level of pixel 3F captured and held by the first capacitor 11F to the input of the first buffer 21F. The first buffer 21F then outputs a signal corresponding to the LCG dark level captured and held by the first capacitor 11F to the AD conversion circuit 90. The AD conversion circuit 90 then AD-converts the signal output from the first buffer 21F, i.e., the AD conversion circuit 90 reads out the LCG dark level of pixel 3. The logic high level of the control signal SW12 continues until time t17.

[0381] Thereafter, at time t18, the solid-state imaging device 1F sets the control signal SW61 to a logic high level, thereby resetting the input of the first buffer 21F to the initialization voltage Vinit. The logic high level period of the control signal SW61 continues until time t19.

[0382] Thereafter, at time t19, the solid-state imaging device 1F sets the control signal SW32 to a logical high level, thereby outputting the LCG signal level of pixel 3F captured and held by the third capacitor 13G to the input of the first buffer 21F. The first buffer 21F then outputs a signal corresponding to the LCG signal level captured and held by the third capacitor 13G to the AD conversion circuit 90. The AD conversion circuit 90 then AD-converts the signal output from the first buffer 21F, i.e., reads out the LCG signal level of pixel 3F. The logical high level of the control signal SW32 continues until time t20.

[0383] As shown in FIG. 29, the control signals SW11, SW21, SW31, and SW41 are never at a logic high level at the same time.

[0384] In addition, the input of the first buffer 21F is reset to the initialization voltage Vinit immediately before the control signal SW12 becomes logic high, immediately before SW22 becomes logic high, immediately before SW32 becomes logic high, and immediately before the control signal SW42 becomes logic high.

[0385] Furthermore, while the input of the first buffer 21F is being reset by the initialization voltage Vinit, the control signals SW12, SW22, SW23, and SW24 do not become logic high.

[0386] (Supplementary Note) As described above, examples of the technology disclosed in this application have been described based on Embodiment 1, Embodiment 2, and Modifications 1 and 2. However, the present disclosure is not limited to these embodiments and modifications. As long as they do not deviate from the spirit of the present disclosure, various modifications that would occur to a person skilled in the art may be made to the embodiments or modifications, or forms constructed by combining components of different embodiments or modifications may also be included within the scope of one or more aspects of the present disclosure.

[0387] (1) In the second embodiment, pixel 3F was described as outputting two pixel signals, a first pixel signal (LCG pixel signal) and a second pixel signal (HCG pixel signal), among a plurality of pixel signals having different gains.

[0388] However, the pixel 3F is not necessarily limited to a configuration that outputs two pixel signals with mutually different gains, and may be a configuration that outputs three or more pixel signals with mutually different gains.

[0389] For example, pixel 3F may be configured to output three pixel signals: a first pixel signal (LCG pixel signal), a second pixel signal (HCG pixel signal), and a third pixel signal (hereinafter also referred to as MCG pixel signal) that has a higher gain than the first pixel signal (LCG pixel signal) and a lower gain than the second pixel signal.

[0390] In this case, the solid-state imaging device 1F further includes a plurality of third vertical signal lines extending in the column direction of the pixel array 70F (the X-axis direction in FIG. 18), connected to m pixels 3F arranged in the column direction of the pixel array 70F, and transmitting a third pixel signal output from at least one of the connected pixels 3F.

[0391] In this case, each of the plurality of sample and hold circuits 10F further includes one or more capacitors (MCG capacitors) arranged in parallel with each other, in one-to-one correspondence with each of the plurality of third vertical signal lines, for holding the third pixel signals transmitted by the corresponding third vertical signal lines, the one or more capacitors (MCG capacitors) having a capacitance greater than the capacitance of the one or more LCG capacitors for holding the first pixel signals and smaller than the capacitance of the one or more HCG capacitors for holding the second pixel signals.

[0392] (2) In the first modification, a sample-and-hold circuit 10D configured by adding a fixed voltage output circuit 65D and a first reset switch 61D to the sample-and-hold circuit 10 according to the first embodiment has been described with reference to FIG.

[0393] Similarly, as illustrated in FIG. 30, a sample and hold circuit 10J may be considered, which is configured by adding a fixed voltage output circuit 65D and a first reset switch 61D to the sample and hold circuit 10F according to the second embodiment.

[0394] (3) In the second modification, a sample-and-hold circuit 10E configured by adding a pull-up switch 64E to the sample-and-hold circuit 10D according to the first modification has been described with reference to FIG.

[0395] Similarly, as illustrated in FIG. 31, a sample-and-hold circuit 10K may be considered, which is configured by adding a pull-up switch 64E to the sample-and-hold circuit 10J illustrated in FIG.

[0396] The present disclosure is widely applicable to solid-state imaging devices that capture images, etc.

[0397] 1, 1F Solid-state imaging device 3, 3F Pixel 10, 10D, 10E, 10F, 10J, 10K Sample and hold circuit 11, 11A, 11F First capacitor 12, 12A, 12F Second capacitor 13A, 13B, 13G Third capacitor 14B, 14C, 14G Fourth capacitor 15C Fifth capacitor 21, 21A, 21F First buffer 22A, 22B Second buffer 31, 31A, 31F First input switch 32, 32A, 32F Second input switch 33A, 33B, 33G Third input switch 34B, 34C, 34G Fourth input switch 35C Fifth input switch 41, 41A, 41F First output switch 42, 42A, 42F Second output switch 43A, 43B, 43G Third output switch 44A, 44B, 44G Fourth output switch 45C Fifth output switch 46C Sixth output switch 51, 511F, 512F, 513G, 514G Input 52, 52F Output 61, 61A, 61D, 61F, 61H First reset switch 62A, 62B Second reset switch 63C Third reset switch 64E Pull-up switch 65D Fixed voltage output circuit 66I First selection switch 67I Second selection switch 70, 70F Pixel array 71, 71F Vertical scanning circuit 72 Reference signal generation unit 73 Control unit 74 Horizontal scanning circuit 75 Signal processing unit 80 Vertical signal line 81F First vertical signal line 82F Second vertical signal line 90 AD conversion circuit 91 Voltage comparator 92 Counter circuit 93 Memory 211 Source follower transistor 212 Constant current source 651 Transistor 652 Potential holding capacitor 653 Potential holding switch

Claims

1. A solid-state imaging device comprising: a pixel array in which a plurality of pixels are arranged in a matrix; a vertical signal line extending in a column direction of the pixel array and transmitting a pixel signal output from at least one of the plurality of pixels; a sample and hold circuit that holds the pixel signal transmitted by the vertical signal line; and an AD conversion circuit that performs AD conversion of the pixel signal held in the sample and hold circuit, wherein the sample and hold circuit has: a first capacitor; a second capacitor having a capacitance equal to that of the first capacitor; a first buffer having an output connected to the AD conversion circuit; a first input switch arranged on an electrical path between the vertical signal line and the first capacitor; a second input switch arranged on an electrical path between the vertical signal line and the second capacitor; a first output switch arranged on an electrical path between the first capacitor and an input of the first buffer; and a second output switch arranged on an electrical path between the second capacitor and an input of the first buffer, wherein in a plan view of the pixel array, the first output switch and the first buffer are adjacent to each other in the column direction, the second output switch and the first buffer are adjacent to each other in the column direction.

2. The solid-state imaging device of claim 1, wherein the sample-and-hold circuit further comprises: a third capacitor having a capacitance equal to that of the first capacitor; a fourth capacitor having a capacitance equal to that of the first capacitor; a second buffer having an output connected to the AD conversion circuit; a third input switch arranged on an electrical path between the vertical signal line and the third capacitor; a fourth input switch arranged on an electrical path between the vertical signal line and the fourth capacitor; a third output switch arranged on an electrical path between the third capacitor and an input of the second buffer; and a fourth output switch arranged on an electrical path between the fourth capacitor and an input of the second buffer, wherein in a planar view of the pixel array, the third output switch and the second buffer are adjacent to each other in the column direction, and the fourth output switch and the second buffer are adjacent to each other in the column direction.

3. A solid-state imaging device comprising: a pixel array in which a plurality of pixels are arranged in a matrix; a vertical signal line extending in a column direction of the pixel array and transmitting a pixel signal output from at least one of the plurality of pixels; a sample and hold circuit holding the pixel signal transmitted by the vertical signal line; and an AD conversion circuit performing AD conversion of the pixel signal held in the sample and hold circuit, wherein the sample and hold circuit comprises: a first capacitor; a second capacitor having a capacitance equal to that of the first capacitor; a third capacitor having a capacitance equal to that of the first capacitor; a first buffer having an output connected to the AD conversion circuit; a second buffer having an output connected to the AD conversion circuit; a first input switch arranged on an electrical path between the vertical signal line and the first capacitor; a second input switch arranged on an electrical path between the vertical signal line and the second capacitor; a third input switch arranged on an electrical path between the vertical signal line and the third capacitor; and a first output switch arranged on an electrical path between the first capacitor and an input of the first buffer. a second output switch arranged on an electrical path between the second capacitor and an input of the first buffer; a third output switch arranged on an electrical path between the second capacitor and the input of the second buffer; and a fourth output switch arranged on an electrical path between the third capacitor and the input of the second buffer, wherein, in a planar view of the pixel array, the first output switch and the first buffer are adjacent to each other in the column direction, the second output switch and the first buffer are adjacent to each other in the column direction, the third output switch and the second buffer are adjacent to each other in the column direction, and the fourth output switch and the second buffer are adjacent to each other in the column direction.

4. The solid-state imaging device of claim 3, wherein the sample-and-hold circuit further comprises: a fourth capacitor having a capacitance equal to that of the first capacitor; a fifth capacitor having a capacitance equal to that of the first capacitor; a third buffer having an output connected to the AD conversion circuit; a fourth input switch arranged on an electrical path between the vertical signal line and the fourth capacitor; a fifth input switch arranged on an electrical path between the vertical signal line and the fifth capacitor; a fifth output switch arranged on an electrical path between the fourth capacitor and an input of the third buffer; and a sixth output switch arranged on an electrical path between the fifth capacitor and an input of the third buffer, wherein in a planar view of the pixel array, the fifth output switch and the third buffer are adjacent to each other in the column direction, and the sixth output switch and the third buffer are adjacent to each other in the column direction.

5. A solid-state imaging device comprising: a pixel array in which a plurality of pixels are arranged in a matrix; a first vertical signal line extending in a column direction of the pixel array for transmitting a first pixel signal output from at least one of the plurality of pixels; a second vertical signal line extending in the column direction for transmitting a second pixel signal output from at least one of the plurality of pixels and having a higher gain than the first pixel signal; a sample and hold circuit for holding the first pixel signal transmitted by the first vertical signal line and the second pixel signal transmitted by the second vertical signal line; and an AD conversion circuit for AD converting the first pixel signal and the second pixel signal held in the sample and hold circuit, wherein the sample and hold circuit comprises: a first capacitor; a second capacitor; a buffer having an output connected to the AD conversion circuit; a first input switch disposed on an electrical path between the first vertical signal line and the first capacitor; and a second input switch disposed on an electrical path between the second vertical signal line and the second capacitor. A solid-state imaging device comprising: a first output switch arranged on an electrical path between the first capacitor and an input of the buffer; and a second output switch arranged on an electrical path between the second capacitor and the input of the buffer, wherein in a planar view of the pixel array, a distance between the first output switch and the buffer in the column direction is shorter than a distance between the second output switch and the buffer in the column direction, and a capacitance of the first capacitor is smaller than a capacitance of the second capacitor.

6. The solid-state imaging device of claim 5, wherein the sample-and-hold circuit further comprises: a third capacitor having a capacitance equal to that of the first capacitor; a fourth capacitor having a capacitance equal to that of the second capacitor; a third input switch arranged on an electrical path between the first vertical signal line and the third capacitor; a fourth input switch arranged on an electrical path between the second vertical signal line and the fourth capacitor; a third output switch arranged on an electrical path between the third capacitor and an input of the buffer; and a fourth output switch arranged on an electrical path between the fourth capacitor and an input of the buffer, and wherein, in a planar view of the pixel array, a distance in the column direction between the third output switch and the buffer is shorter than a distance in the column direction between the fourth output switch and the buffer.

7. The solid-state imaging device of claim 6, wherein the sample-and-hold circuit further comprises: a first selection switch arranged on an electrical path between the first and second output switches and the input of the buffer; and a second selection switch arranged on an electrical path between the third and fourth output switches and the input of the buffer, and wherein, in a planar view of the pixel array, the first selection switch and the buffer are adjacent to each other in the column direction, and the second selection switch and the buffer are adjacent to each other in the column direction.

8. The solid-state imaging device according to claim 1, wherein the sample-and-hold circuit further comprises: a fixed voltage output circuit that outputs an operating voltage of a fixed potential to the first buffer to operate the first buffer; and a reset switch that is arranged on an electrical path between the output of the fixed voltage output circuit and the input of the first buffer.

9. The solid-state imaging device of claim 3, wherein the sample-and-hold circuit further comprises: a fixed voltage output circuit that outputs an operating voltage of a fixed potential to the first buffer and the second buffer to operate the first buffer and the second buffer; a first reset switch arranged on an electrical path between the output of the fixed voltage output circuit and the input of the first buffer; and a second reset switch arranged on an electrical path between the output of the fixed voltage output circuit and the input of the second buffer.

10. The solid-state imaging device according to claim 5, wherein the sample-and-hold circuit further includes: a fixed voltage output circuit that outputs an operating voltage of a fixed potential to the buffer to operate the buffer; and a reset switch that is arranged on an electrical path between the output of the fixed voltage output circuit and the input of the buffer.

11. A solid-state imaging device as described in any one of claims 8 to 10, wherein the constant voltage output circuit comprises: a transistor having a drain connected to a power supply wiring and a source connected to the output of the constant voltage output circuit; a potential holding capacitor connected to the gate of the transistor; and a potential holding switch arranged on an electrical path between the power supply wiring and the potential holding capacitor.

12. The solid-state imaging device according to any one of claims 8 to 11, wherein the sample-and-hold circuit further includes a pull-up switch that pulls up or pulls down the output of the fixed voltage output circuit.

Images