Electronic device and method for fast fourier transform

Abstract

According to an embodiment, an electronic device may comprise: a memory; and at least one processing circuit for orthogonal frequency division multiplexing (OFDM) demodulation for changing the domain of a symbol sequence from a first domain to a second domain. The at least one processing circuit may be configured to acquire a first symbol sequence for the first domain on the basis of a reception signal acquired from an external electronic device. The at least one processing circuit may be configured to acquire a second symbol sequence for the second domain by performing, on the first symbol sequence, a fast Fourier transform (FFT) operation using a cyclic shift operation. The FFT operation using the cyclic shift operation may include an operation of changing, for each FFT index among FFT indexes for the second domain according to an FFT size, a value of a most significant bit (MSB) of a bit sequence of the FFT index from 0 to 1 or from 1 to 0.

Description

Electronic devices and methods for fast Fourier transforms

[0001] The present disclosure relates to an electronic device and method for fast Fourier transform.

[0002] In wireless communication systems, when receiving a signal, the fast Fourier transform (FFT) operation is used to convert a time-domain sequence into a frequency-domain sequence. When transmitting a signal, the cyclic extension operation is used to insert a cyclic prefix (CP) into the signal to prevent inter-channel interference.

[0003] The above information may be provided as background art to aid in understanding the present disclosure. No claim or determination is made as to whether any of the above-described matters constitute prior art related to the present disclosure.

[0004] According to one embodiment, an electronic device may include a memory, and at least one processing circuit for orthogonal frequency division multiplexing (OFDM) demodulation that changes a domain of a symbol sequence from a first domain to a second domain. The at least one processing circuit may be configured to obtain a first symbol sequence for the first domain based on a received signal obtained from an external electronic device. The at least one processing circuit may be configured to obtain a second symbol sequence for the second domain by performing a fast Fourier transform (FFT) operation using a cyclic shift operation on the first symbol sequence. The FFT operation using the cyclic shift operation may include an operation for changing a value of a most significant bit (MSB) of a bit sequence of each FFT index among FFT indices for the second domain according to an FFT size from 0 to 1 or from 1 to 0.

[0005] According to one embodiment, a method performed by an electronic device may include an operation of obtaining a first symbol sequence for a first domain based on a received signal obtained from an external electronic device. The method may include an operation of obtaining a second symbol sequence for a second domain by performing a fast Fourier transform (FFT) operation using a cyclic shift operation on the first symbol sequence. The FFT operation using the cyclic shift operation may include an operation of changing a value of a most significant bit (MSB) of a bit sequence of each FFT index among FFT indices for the second domain according to an FFT size from 0 to 1 or from 1 to 0.

[0006] Figure 1 illustrates a wireless communication system.

[0007] Figure 2a illustrates a front-hole interface.

[0008] Figure 2b illustrates the fronthaul interface of an O(open)-RAN(radio access network).

[0009] Figure 3a illustrates the functional configuration of a distributed unit (DU).

[0010] Figure 3b illustrates the functional configuration of a RU (radio unit).

[0011] Figure 4 illustrates an example of function split between DU and RU.

[0012] Figure 5a illustrates an example of the operation of an orthogonal frequency division multiplexing (OFDM) modulation circuit.

[0013] Figure 5b shows an example of the operation of an OFDM demodulation circuit.

[0014] Figure 6a illustrates an example of a cyclic shift operation of an OFDM modulation circuit.

[0015] Figure 6b shows an example of a cyclic shift operation of an OFDM demodulation circuit.

[0016] Figure 7 illustrates a signal flow graph regarding the FFT operation of the DIF FFT (decimation in frequency fast Fourier transform) structure.

[0017] Figure 8 illustrates a signal flow graph regarding the FFT operation of the DIT FFT (decimation in time fast Fourier transform) structure.

[0018] Figure 9 illustrates a signal flow diagram for an FFT operation using a circular shift operation of a DIT FFT structure.

[0019] Figure 10 illustrates an OFDM demodulation circuit for performing FFT operations for circular shift operations and reordering operations.

[0020] Figure 11 illustrates a flowchart of the operation of an electronic device for performing an FFT operation using a circular shift operation.

[0021] Figure 12 shows an example of the configuration of a processing device.

[0022] The terms used in this disclosure are used only to describe specific embodiments and may not be intended to limit the scope of other embodiments. The singular expression may include plural expressions unless the context clearly indicates otherwise. Terms used herein, including technical or scientific terms, may have the same meaning as commonly understood by those of ordinary skill in the art described in this disclosure. Terms defined in general dictionaries among the terms used in this disclosure may be interpreted as having the same or similar meaning in the context of the relevant technology, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined in this disclosure. In some cases, even if a term is defined in this disclosure, it cannot be interpreted to exclude embodiments of the present disclosure.

[0023] The various embodiments of the present disclosure described below illustrate a hardware-based approach as an example. However, since the various embodiments of the present disclosure include techniques utilizing both hardware and software, the various embodiments of the present disclosure do not exclude a software-based approach.

[0024] In the following description, terms referring to signals (e.g., signal, information, message, signaling), terms referring to resources (e.g., symbol, slot, subframe, radio frame, subcarrier, resource element (RE), resource block (RB), bandwidth part (BWP), occasion), terms for operational states (e.g., step, operation, procedure), terms referring to data (e.g., packet, user stream, information, bit, symbol, codeword), terms referring to channels, terms referring to network entities, terms referring to components of devices, etc. are examples for convenience of description. Therefore, the present disclosure is not limited to the terms described below, and other terms having equivalent technical meanings may be used.

[0025] In addition, in the present disclosure, expressions such as "more than" or "less than" may be used to determine whether a specific condition is satisfied or fulfilled, but this is merely a description for expressing an example and does not exclude descriptions such as "more than" or "less than." A condition described as "more than" may be replaced with "more than," a condition described as "less than" may be replaced with "less than," and a condition described as "more than and less than" may be replaced with "more than and less than." In addition, hereinafter, "A" to "B" mean at least one of elements from A (including A) to B (including B). hereinafter, "C" and / or "D" mean at least one of "C" or "D," that is, including {"C", "D", "C" and "D"}.

[0026] Although the present disclosure describes various embodiments using terms used in some communication standards (e.g., 3rd Generation Partnership Project (3GPP), extensible radio access network (xRAN), open-radio access network (O-RAN), etc.), these are merely examples for explanation. The various embodiments of the present disclosure can be easily modified and applied to other communication systems.

[0027] Figure 1 illustrates a wireless communication system.

[0028] Referring to FIG. 1, FIG. 1 illustrates a base station (110) and a terminal (120) as some of the nodes utilizing a wireless channel in a wireless communication system. Although FIG. 1 illustrates only one base station, the wireless communication system may further include other base stations identical or similar to the base station (110).

[0029] The base station (110) is a network infrastructure that provides wireless access to the terminal (120). The base station (110) has coverage defined based on the distance at which a signal can be transmitted. In addition to the base station, the base station (110) may be referred to as an 'access point (AP)', 'eNodeB (eNB)', '5th generation node', 'next generation nodeB (gNB)', 'wireless point', 'transmission / reception point (TRP)', or other terms having equivalent technical meanings.

[0030] The terminal (120) is a device used by a user and communicates with the base station (110) via a wireless channel. The link from the base station (110) to the terminal (120) is referred to as a downlink (DL), and the link from the terminal (120) to the base station (110) is referred to as an uplink (UL). In addition, although not shown in FIG. 1, the terminal (120) and another terminal may communicate with each other via a wireless channel. In this case, the link between the terminal (120) and another terminal (device-to-device link, D2D) is referred to as a sidelink, and the sidelink may be used interchangeably with the PC5 interface. In some other embodiments, the terminal (120) may be operated without the involvement of a user. According to one embodiment, the terminal (120) is a device that performs machine type communication (MTC) and may not be carried by the user. Additionally, according to one embodiment, the terminal (120) may be an NB (narrowband)-IoT (internet of things) device.

[0031] The terminal (120) may be referred to as a terminal, or other terms such as 'user equipment (UE),' 'customer premises equipment (CPE),' 'mobile station,' 'subscriber station,' 'remote terminal,' 'wireless terminal,' 'electronic device,' or 'user device,' or other terms having equivalent technical meanings.

[0032] The base station (110) and the terminal (120) can perform beamforming. The base station (110) and the terminal (120) can transmit and receive wireless signals in a relatively low frequency band (e.g., FR 1 (frequency range 1) of NR). In addition, the base station (110) and the terminal (120) can transmit and receive wireless signals in a relatively high frequency band (e.g., FR 2 (or, FR 2-1, FR 2-2, FR 2-3), FR 3 of NR), millimeter wave (mmWave) band (e.g., 28 GHz, 30 GHz, 38 GHz, 60 GHz)). To improve channel gain, the base station (110) and the terminal (120) can perform beamforming. Here, the beamforming can include transmission beamforming and reception beamforming. The base station (110) and the terminal (120) can impart directionality to the transmitted or received signal. To this end, the base station (110) and the terminal (120) can select serving beams through a beam search or beam management procedure. After the serving beams are selected, subsequent communication can be performed through resources that have a QCL relationship with the resource that transmitted the serving beams.

[0033] If large-scale characteristics of a channel carrying a symbol on a first antenna port can be inferred from a channel carrying a symbol on a second antenna port, the first antenna port and the second antenna port can be evaluated to have a QCL relationship. For example, the large-scale characteristics may include at least one of delay spread, Doppler spread, Doppler shift, average gain, average delay, and a spatial receiver parameter.

[0034] Although both the base station (110) and the terminal (120) are described as performing beamforming in FIG. 1, the embodiments of the present disclosure are not necessarily limited thereto. In some embodiments, the terminal may or may not perform beamforming. Furthermore, the base station may or may not perform beamforming. That is, either only one of the base station and the terminal may perform beamforming, or neither the base station nor the terminal may perform beamforming.

[0035] In the present disclosure, a beam refers to a spatial flow of a signal in a wireless channel, and is formed by one or more antennas (or antenna elements), and this forming process may be referred to as beamforming. Beamforming may include at least one of analog beamforming and digital beamforming (e.g., precoding). Reference signals transmitted based on beamforming may include, for example, a demodulation-reference signal (DM-RS), a channel state information-reference signal (CSI-RS), a synchronization signal / physical broadcast channel (SS / PBCH), and a sounding reference signal (SRS). In addition, as a configuration for each reference signal, an IE such as a CSI-RS resource or an SRS-resource may be used, and this configuration may include information associated with the beam. Information associated with a beam may mean whether the configuration (e.g., a CSI-RS resource) uses the same spatial domain filter as another configuration (e.g., another CSI-RS resource within the same CSI-RS resource set) or a different spatial domain filter, or whether it is quasi-co-located (QCL) with a reference signal, and if so, what type it is (e.g., QCL type A, B, C, D).

[0036] In the past, in communication systems with relatively large cell radius of base stations, each base station was installed to include the functions of a digital processing unit (or distributed unit (DU)) and a radio frequency (RF) processing unit (or radio unit (RU)). However, as higher frequency bands are used in 4G (4th generation) and / or subsequent communication systems (e.g., 5G) and the cell coverage of base stations decreases, the number of base stations to cover a specific area has increased. The installation costs for operators to install base stations have also increased. In order to minimize the installation costs of base stations, a structure has been proposed in which the DU and RU of a base station are separated, one or more RUs are connected to one DU via a wired network, and one or more RUs are geographically distributed to cover a specific area. Hereinafter, the deployment structure and expanded examples of base stations according to various embodiments of the present disclosure are described through FIGS. 2A and 2B.

[0037] FIG. 2A illustrates a fronthaul interface. Unlike the backhaul between a base station and a core network, fronthaul refers to the connection between entities between a wireless LAN and a base station. FIG. 2A illustrates an example of a fronthaul structure between a DU (210) and one RU (220), but this is merely for convenience of explanation and the present disclosure is not limited thereto. In other words, embodiments of the present disclosure can also be applied to a fronthaul structure between one DU and multiple RUs. For example, embodiments of the present disclosure can be applied to a fronthaul structure between one DU and two RUs. Furthermore, embodiments of the present disclosure can also be applied to a fronthaul structure between one DU and three RUs.

[0038] Referring to FIG. 2A, a base station (110) may include a DU (210) and an RU (220). A fronthaul (215) between the DU (210) and the RU (220) may be operated via an FX interface. For operation of the fronthaul (215), an interface such as an enhanced common public radio interface (eCPRI) or radio over ethernet (ROE) may be used, for example.

[0039] As communications technology advances, mobile data traffic increases, significantly increasing the bandwidth requirements for the fronthaul between the digital unit and the radio unit. In deployments such as C-RAN (centralized / cloud radio access network), the DU performs functions for the packet data convergence protocol (PDCP), radio link control (RLC), media access control (MAC), and physical layer (PHY), while the RU can be implemented to perform additional functions for the PHY layer in addition to its radio frequency (RF) functions.

[0040] DU (210) may be responsible for upper layer functions of a wireless network. For example, DU (210) may perform functions of the MAC layer and a part of the PHY layer. Here, a part of the PHY layer refers to functions performed at a higher level among the functions of the PHY layer, and may include, for example, channel encoding (or channel decoding), scrambling (or descrambling), modulation (or demodulation), and layer mapping (or layer demapping). According to an embodiment, if DU (210) complies with the O-RAN standard, it may be referred to as O-DU (O-RAN DU). DU (210) may be replaced with a first network entity for a base station (e.g., gNB) in embodiments of the present disclosure, if necessary.

[0041] The RU (220) may be responsible for lower layer functions of a wireless network. For example, the RU (220) may perform a part of the PHY layer, an RF function. Here, a part of the PHY layer refers to functions of the PHY layer that are performed at a relatively lower level than the DU (210), and may include, for example, iFFT transformation (or FFT transformation), CP (cyclic prefix) insertion (CP removal), and digital beamforming. An example of such specific functional separation is described in detail in FIG. 4. The RU (220) may be referred to as an 'access unit (AU)', an 'access point (AP)', a 'transmission / reception point (TRP)', a 'remote radio head (RRH)', a 'radio unit (RU)', or other terms having an equivalent technical meaning thereto. In one embodiment, if RU (220) complies with the O-RAN standard, it may be referred to as O-RU (O-RAN RU). RU (220) may be represented as a second network entity for a base station (e.g., gNB) in embodiments of the present disclosure, if necessary.

[0042] Although FIG. 2A illustrates that the base station (110) includes a DU (210) and a RU (220), the embodiments of the present disclosure are not limited thereto. The base station according to the embodiments may be implemented in a distributed deployment according to a centralized unit (CU) configured to perform functions of upper layers of an access network (e.g., packet data convergence protocol (PDCP), radio resource control (RRC)) and a distributed unit (DU) configured to perform functions of lower layers. In this case, the distributed unit (DU) may include the digital unit (DU) and radio unit (RU) of FIG. 1. Between a core (e.g., 5GC (5G core) or NGC (next generation core)) network and a radio network (RAN), the base station may be implemented in a structure in which CU, DU, and RU are arranged in that order. The interface between CU and DU (distributed unit) can be referred to as the F1 interface.

[0043] A centralized unit (CU) can be connected to one or more DUs and can be responsible for functions at a higher layer than the DU. For example, the CU can be responsible for functions at the RRC (radio resource control) and PDCP (packet data convergence protocol) layers, while the DU and RU can be responsible for functions at lower layers. The DU can perform some functions (high PHY) of the RLC (radio link control), MAC (media access control), and PHY (physical) layers, while the RU can be responsible for the remaining functions (low PHY) of the PHY layer. In addition, for example, a digital unit (DU) can be included in a distributed unit (DU) depending on the implementation of a distributed deployment of the base station. Hereinafter, unless otherwise defined, the operations of DU (digital unit) and RU are described, but various embodiments of the present disclosure can be applied to both a base station deployment including CU and a deployment in which DU is directly connected to the core network (i.e., a base station in which CU and DU are integrated as a single entity (e.g., NG-RAN node)).

[0044] Figure 2b illustrates the fronthaul interface of an open RAN (radio access network). A base station (110) according to a distributed deployment is exemplified as an eNB or gNB.

[0045] Referring to FIG. 2b, the base station (110) may include an O-DU (251) and O-RUs (253-1, 253-n). Hereinafter, for convenience of explanation, the operation and function of the O-RU (253-1) may be understood as a description of each of the other O-RUs (e.g., O-RU (253-n)).

[0046] The O-DU (251) is a logical node that includes functions, excluding functions exclusively assigned to the O-RU (253-1), among the functions of a base station (e.g., eNB, gNB) according to FIG. 4 described below. The O-DU (251) can control the operation of the O-RUs (253-1, 253-n). The O-DU (251) may be referred to as an LLS (lower layer split) CU (central unit). The O-RU (253-1) is a logical node that includes a subset of the functions of a base station (e.g., eNB, gNB) according to FIG. 4 described below. Real-time aspects of control plane (C-plane) communication and user plane (U-plane) communication with the O-RU (253-1) can be controlled by the O-DU (251).

[0047] The O-DU (251) can communicate with the O-RU (253-1) through an LLS interface. The LLS interface corresponds to a fronthaul interface. The LLS interface refers to a logical interface between the O-DU (251) and the O-RU (253-1) that utilizes lower layer functional split (i.e., intra-PHY based functional split). The LLS-C between the O-DU (251) and the O-RU (253-1) provides the C-plane through the LLS interface. The LLS-U between the O-DU (251) and the O-RU (253-1) provides the U-plane through the LLS interface.

[0048] In FIG. 2B, to explain the O-RAN, entities of the base station (110) are described as O-DU and O-RU. However, these names are not to be construed as limiting the embodiments of the present disclosure. In the embodiments described below, it is obvious that the operations of the DU (210) can be performed by the O-DU (251). The description of the DU (210) can be applied to the O-DU (251). Similarly, in the embodiments described below, it is obvious that the operations of the RU (220) can be performed by the O-RU (253-1). The description of the RU (220) can be applied to the O-DU (253-1).

[0049] Fig. 3a illustrates the functional configuration of a DU (distributed unit). The configuration illustrated in Fig. 3a can be understood as the configuration of the DU (210) of Fig. 2a (or the O-DU (250) of Fig. 2b) as part of a base station. Terms such as "...unit" and "...unit" used hereinafter mean a unit that processes at least one function or operation, and this can be implemented by hardware, software, or a combination of hardware and software.

[0050] Referring to FIG. 3a, DU (210) includes a transceiver (310), memory (320), and processor (330).

[0051] The transceiver (310) can perform functions for transmitting and receiving signals in a wired communication environment. The transceiver (310) can include a wired interface for controlling direct connections between devices via a transmission medium (e.g., copper wire, optical fiber). For example, the transceiver (310) can transmit electrical signals to other devices via copper wire, or perform conversion between electrical signals and optical signals. The DU (210) can communicate with a radio unit (RU) via the transceiver (310). The DU (210) can be connected to a core network or a CU in a distributed arrangement via the transceiver (310).

[0052] The transceiver (310) may perform functions for transmitting and receiving signals in a wireless communication environment. For example, the transceiver (310) may perform a conversion function between a baseband signal and a bit stream according to the physical layer specifications of the system. For example, when transmitting data, the transceiver (310) generates complex symbols by encoding and modulating the transmitted bit stream. In addition, when receiving data, the transceiver (310) restores the received bit stream by demodulating and decoding the baseband signal. In addition, the transceiver (310) may include multiple transmission and reception paths. Furthermore, according to one embodiment, the transceiver (310) may be connected to the core network or other nodes (e.g., an integrated access backhaul (IAB).

[0053] The transceiver (310) can transmit and receive signals. For example, the transceiver (310) can transmit a management plane (M-plane) message. For example, the transceiver (310) can transmit a management plane (S-plane) message. For example, the transceiver (310) can transmit a control plane (C-plane) message. For example, the transceiver (310) can transmit a user plane (U-plane) message. For example, the transceiver (310) can receive a user plane message. Although only the transceiver (310) is illustrated in FIG. 3A, in other implementations, the DU (210) may include two or more transceivers.

[0054] The transceiver (310) transmits and receives signals as described above. Accordingly, all or part of the transceiver (310) may be referred to as a "communication unit," a "transmitter," a "receiver," or a "transmitter-receiver unit." Furthermore, in the following description, transmission and reception performed via a wireless channel are used to mean that the transceiver (310) performs the processing described above.

[0055] Although not illustrated in FIG. 3A, the transceiver (310) may further include a backhaul transceiver for connection to the core network or other base stations. The backhaul transceiver provides an interface for communicating with other nodes within the network. That is, the backhaul transceiver converts a bit stream transmitted from the base station to other nodes, such as other access nodes, other base stations, upper nodes, the core network, etc., into a physical signal, and converts a physical signal received from other nodes into a bit stream.

[0056] The memory (320) stores data such as basic programs, application programs, and setting information for the operation of the DU (210). The memory (320) may be referred to as a storage unit. The memory (320) may be composed of volatile memory, nonvolatile memory, or a combination of volatile memory and nonvolatile memory. In addition, the memory (320) provides stored data upon request from the processor (330).

[0057] The processor (330) controls the overall operations of the DU (210). The processor (380) may be referred to as a control unit. For example, the processor (330) transmits and receives signals through the transceiver (310) (or through the backhaul communication unit). In addition, the processor (330) records and reads data from the memory (320). In addition, the processor (330) may perform the functions of the protocol stack required by the communication standard. Although only the processor (330) is illustrated in FIG. 3A, the DU (210) may include two or more processors according to other implementation examples.

[0058] The configuration of DU (210) illustrated in FIG. 3A is merely an example, and examples of DUs performing embodiments of the present disclosure are not limited to the configuration illustrated in FIG. 3A. In some embodiments, some configurations may be added, deleted, or changed.

[0059] Fig. 3b illustrates the functional configuration of a radio unit (RU). The configuration illustrated in Fig. 3b can be understood as a configuration of the RU (220) of Fig. 2b or the O-RU (253-1) of Fig. 2b as part of a base station. Terms such as "...unit" and "...unit" used hereinafter mean a unit that processes at least one function or operation, and this can be implemented by hardware, software, or a combination of hardware and software.

[0060] Referring to FIG. 3b, the RU (220) includes an RF transceiver (360), a fronthaul transceiver (365), a memory (370), and a processor (380).

[0061] The RF transceiver (360) performs functions for transmitting and receiving signals via a wireless channel. For example, the RF transceiver (360) upconverts a baseband signal into an RF band signal and transmits it via an antenna, and downconverts an RF band signal received via the antenna into a baseband signal. For example, the RF transceiver (360) may include a transmit filter, a receive filter, an amplifier, a mixer, an oscillator, a DAC, an ADC, and the like.

[0062] The RF transceiver (360) may include multiple transmission and reception paths. Furthermore, the RF transceiver (360) may include an antenna unit. The RF transceiver (360) may include at least one antenna array composed of multiple antenna elements. In terms of hardware, the RF transceiver (360) may be composed of digital circuits and analog circuits (e.g., a radio frequency integrated circuit (RFIC)). Here, the digital circuits and analog circuits may be implemented in a single package. In addition, the RF transceiver (360) may include multiple RF chains. The RF transceiver (360) may perform beamforming. The RF transceiver (360) may apply beamforming weights to a signal to be transmitted and received in order to impart directionality according to the settings of the processor (380). According to one embodiment, the RF transceiver (360) may include a radio frequency (RF) block (or RF section).

[0063] According to one embodiment, the RF transceiver (360) can transmit and receive signals on a radio access network. For example, the RF transceiver (360) can transmit a downlink signal. The downlink signal can include a synchronization signal (SS), a reference signal (RS) (e.g., a cell-specific reference signal (CRS), a demodulation (DM)-RS), system information (e.g., a MIB, a SIB, remaining system information (RMSI), other system information (OSI)), a configuration message, control information, or downlink data. In addition, for example, the RF transceiver (360) can receive an uplink signal. The uplink signal may include a random access related signal (e.g., a random access preamble (RAP) (or Msg1 (message 1)), Msg3 (message 3)), a reference signal (e.g., a sounding reference signal (SRS), DM-RS), or a power headroom report (PHR). Although only the RF transceiver (360) is illustrated in FIG. 3b, in other implementation examples, the RU (220) may include two or more RF transceivers.

[0064] According to embodiments, the RF transceiver (460) may transmit a RIM-RS. The RF transceiver (460) may transmit a first type of RIM-RS (e.g., RIM-RS type 1 of 3GPP) to indicate the detection of far-field interference. The RF transceiver (460) may transmit a second type of RIM-RS (e.g., RIM-RS type 2 of 3GPP) to indicate the presence or absence of far-field interference.

[0065] The fronthaul transceiver (365) can transmit and receive signals. According to one embodiment, the fronthaul transceiver (365) can transmit and receive signals on the fronthaul interface. For example, the fronthaul transceiver (365) can receive a management plane (M-plane) message. For example, the fronthaul transceiver (365) can receive a management plane (S-plane) message. For example, the fronthaul transceiver (365) can receive a control plane (C-plane) message. For example, the fronthaul transceiver (365) can transmit a user plane (U-plane) message. For example, the fronthaul transceiver (365) can receive a user plane message. Although only the fronthaul transceiver (365) is shown in FIG. 3b, according to other implementation examples, the RU (220) may include two or more fronthaul transceivers.

[0066] The RF transceiver (360) and the fronthaul transceiver (365) transmit and receive signals as described above. Accordingly, all or part of the RF transceiver (360) and the fronthaul transceiver (365) may be referred to as a 'communication unit', a 'transmitter unit', a 'receiver unit', or a 'transmitter-receiver unit'. In addition, in the following description, transmission and reception performed through a wireless channel are used to mean that the processing as described above is performed by the RF transceiver (360). In the following description, transmission and reception performed through a wireless channel are used to mean that the processing as described above is performed by the RF transceiver (360).

[0067] The memory (370) stores data such as basic programs, application programs, and setting information for the operation of the RU (220). The memory (370) may be referred to as a storage unit. The memory (370) may be configured as volatile memory, non-volatile memory, or a combination of volatile memory and non-volatile memory. In addition, the memory (370) provides the stored data according to a request from the processor (380). According to one embodiment, the memory (370) may include a memory for conditions, commands, or setting values ​​related to the SRS transmission method.

[0068] The processor (380) controls the overall operations of the RU (220). The processor (380) may be referred to as a control unit. For example, the processor (380) transmits and receives signals through the RF transceiver (360) or the fronthaul transceiver (365). In addition, the processor (380) records and reads data in the memory (370). In addition, the processor (380) may perform functions of a protocol stack required by a communication standard. Although only the processor (380) is illustrated in FIG. 3B, the RU (220) may include two or more processors according to other implementation examples. The processor (380) may be a set of instructions or codes stored in the memory (370), or may be a storage space that stores instructions / codes or instructions / codes that are at least temporarily residing in the processor (380), or may be a part of the circuitry that constitutes the processor (380). Additionally, the processor (380) may include various modules for performing communication. The processor (380) may control the RU (220) to perform operations according to the embodiments described below.

[0069] The configuration of RU (220) illustrated in FIG. 3b is merely an example, and examples of RUs performing embodiments of the present disclosure are not limited to the configuration illustrated in FIG. 3b. In some embodiments, some configurations may be added, deleted, or changed.

[0070] Figure 4 illustrates an example of function split between DUs and RUs. As wireless communication technologies advance (e.g., the introduction of 5G (5th generation) communication systems (or NR (new radio) communication systems), the frequency bands used have increased further. As the cell radius of a base station has become significantly smaller, the number of RUs required for installation has also increased further. Furthermore, in 5G communication systems, the amount of data transmitted has increased by a factor of up to ten, significantly increasing the transmission capacity of the wired network transmitted to the fronthaul. Due to the factors described above, the installation cost of the wired network in the 5G communication system may increase significantly. Therefore, in order to lower the transmission capacity of the wired network and reduce the installation cost of the wired network, 'function split' can be utilized, which transfers some of the functions of the modem of the DU to the RU to lower the transmission capacity of the fronthaul.

[0071] To reduce the burden on the DU, the role of the RU, which is traditionally solely responsible for RF functions, can be expanded to include some physical layer functions. As the RU performs higher-layer functions, its throughput increases, which can increase transmission bandwidth in the fronthaul while reducing latency requirements due to response processing. However, as the RU performs higher-layer functions, virtualization gains decrease, and the RU's size, weight, and cost increase. Considering the trade-offs between the advantages and disadvantages described above, implementing an optimal functional separation is required.

[0072] Referring to Figure 4, the functional separation in the physical layer below the MAC layer is illustrated. For the downlink (DL) that transmits a signal to a terminal through a wireless network, the base station can sequentially perform channel encoding / scrambling, modulation, layer mapping, antenna mapping, RE mapping, digital beamforming (e.g., precoding), iFFT transform / CP insertion, and RF transform. For the uplink (UL) that receives a signal from a terminal through a wireless network, the base station can sequentially perform RF transform, FFT transform / CP removal, digital beamforming (pre-combining), RE demapping, channel estimation, layer demapping, demodulation, and decoding / descrambling. The separation of uplink and downlink functions can be defined in various types depending on the needs of vendors, discussions in standards, etc., according to the above-mentioned trade-offs.

[0073] In the first functional separation (405), the RU performs the RF function, and the DU performs the PHY function. The first functional separation is one in which the PHY function is not substantially implemented in the RU, and may be referred to as Option 8, for example. In the second functional separation (410), the RU performs iFFT conversion / CP insertion in the DL and FFT conversion / CP removal in the UL of the PHY function, and the DU performs the remaining PHY functions. As an example, the second functional separation (410) may be referred to as Option 7-1. In the third functional separation (420a), the RU performs iFFT conversion / CP insertion in the DL and FFT conversion / CP removal and digital beamforming in the UL of the PHY function, and the DU performs the remaining PHY functions. As an example, the third functional separation (420a) may be referred to as Option 7-2x Category A. In the fourth functional separation (420b), the RU performs up to digital beamforming in both the DL and UL, and the DU performs upper PHY functions after the digital beamforming. For example, the fourth functional separation (420b) may be referred to as Option 7-2x Category B. In the fifth functional separation (425), the RU performs up to RE mapping (or RE demapping) in both the DL and UL, and the DU performs upper PHY functions after RE mapping (or RE demapping). For example, the fifth functional separation (425) may be referred to as Option 7-2. In the sixth functional separation (430), the RU performs up to modulation (or demodulation) in both the DL and UL, and the DU performs upper PHY functions after modulation (or demodulation). For example, the sixth functional separation (430) may be referred to as Option 7-3. In the seventh functional separation (440), the RU performs encoding / scrambling (or decoding / descrambling) in both the DL and UL, and the DU performs subsequent upper PHY functions up to modulation (or demodulation). For example, the seventh functional separation (440) may be referred to as Option 6.

[0074] In one embodiment, when a large amount of signal processing is expected, such as in the FR 1 MMU, functional separation at a relatively high layer (e.g., the fourth functional separation (420b)) may be required to reduce fronthaul capacity. In addition, functional separation at too high a layer (e.g., the sixth functional separation (430)) may complicate the control interface and cause a burden on the implementation of the RU due to the inclusion of a large number of PHY processing blocks within the RU. Therefore, appropriate functional separation may be required depending on the arrangement and implementation method of the DU and the RU.

[0075] In one embodiment, if the precoding of data received from the DU cannot be processed (i.e., if the precoding capability of the RU is limited), the third functional separation (420a) or a lower functional separation (e.g., the second functional separation (410)) may be applied. Conversely, if the DU has the capability to process the precoding of data received from the DU, the fourth functional separation (420b) or a higher functional separation (e.g., the sixth functional separation (430)) may be applied.

[0076] Hereinafter, embodiments in the present disclosure are described based on the third functional separation (420a) (which may be referred to as category A (CAT-A)) or the fourth functional separation (420b) (which may be referred to as category B (CAT-B)) for performing beamforming processing in an RU unless otherwise specified. The O-RAN standard distinguishes the types of O-RUs depending on whether the precoding function is located at the interface of the O-DU or the O-RU interface. An O-RU that does not perform precoding (i.e., has low complexity) may be referred to as a CAT-A O-RU. An O-RU that performs precoding may be referred to as a CAT-B O-RU.

[0077] Hereinafter, the term "upper-PHY" refers to physical layer processing handled in the DU of the fronthaul interface. For example, the upper-PHY may include FEC encoding / decoding, scrambling, and modulation / demodulation. Hereinafter, the term "lower-PHY" refers to physical layer processing handled in the RU of the fronthaul interface. For example, the lower-PHY may include FFT / iFFT, digital beamforming, PRACH (physical random access channel) extraction, and filtering. However, the above-described criteria do not exclude embodiments through other functional separations. The functional configuration, signaling, or operation of the embodiments described below may be applied not only to the third functional separation (420a) or the fourth functional separation (420b), but also to other functional separations.

[0078] Embodiments of the present disclosure exemplarily describe the standards of eCPRI and O-RAN as fronthaul interfaces when transmitting messages between a DU (e.g., DU (210) of FIG. 2a) and an RU (e.g., RU (220) of FIG. 2a). The Ethernet payload of the message may include an eCPRI header, an O-RAN header, and additional fields. Hereinafter, various embodiments of the present disclosure are described using standard terms of eCPRI or O-RAN, but other expressions having equivalent meanings to each term may be used instead in various embodiments of the present disclosure. Hereinafter, various embodiments of the present disclosure are described using standard terms of eCPRI or O-RAN, but are not limited thereto. For example, in various embodiments of the present disclosure, the CPRI standard may be used as the fronthaul interface.

[0079] The fronthaul transport protocol can use Ethernet and eCPRI, which are easy to share with networks. The Ethernet payload can include an eCPRI header and an O-RAN header. The eCPRI header can be located at the beginning of the Ethernet payload. The contents of the eCPRI header are as follows.

[0080] 1) ecpriVersion (4 bits): This parameter indicates the eCPRI protocol version.

[0081] 2) ecpriReserved (3 bits): This parameter is reserved for further use by eCPRI.

[0082] 3) ecpriConcatenation (1 bit): This parameter indicates when eCPRI concatenation is in use.

[0083] 4) ecpriMessage (1 byte): This parameter indicates the type of service carried by the message type. For example, the parameter indicates an IQ data message, a real-time control data message, or a transmission network delay measurement message.

[0084] 5) ecpriPayload (2 bytes): This parameter indicates the byte size of the payload portion of the eCPRI message.

[0085] 6) ecpriRtcid / ecpriPcid (2 bytes): This parameter is the eAxC (extended antenna-carrier) identifier (eAxC ID) and identifies a specific data flow associated with each C-plane (ecpriRtcid) or U-plane (ecpriPcid) message.

[0086] 7) ecpriSeqid (2 bytes): This parameter provides unique message identification and ordering at both levels. The first octet of this parameter is a sequence ID used to identify the order of messages within the eAxC message stream. The sequence ID is used to ensure that all messages are received and to reorder out-of-order messages. The second octet of this parameter is a subsequence ID. The subsequence ID is used to ensure ordering and implement reordering when radio-transport-level (eCPRI or IEEE-1914.3) fragmentation occurs.

[0087] The eAxC identifier (ID) includes a band and sector identifier ('BandSector_ID'), a component carrier identifier ('CC_ID'), a spatial stream identifier ('RU_Port_ID'), and a distributed unit identifier ('DU_Port_ID'). The bit allocation of the eAxC ID can be distinguished as follows.

[0088] 1) DU_port ID: The DU_port ID is used to distinguish processing units (e.g., different baseband cards) in the O-DU. The O-DU is expected to allocate bits for the DU_port ID, and the O-RU is expected to append the same value to the UL U-plane message carrying the same sectionId data.

[0089] 2) BandSector_ID: Aggregated cell identifier (band and sector distinction supported by O-RU).

[0090] 3) CC_ID: CC_ID identifies the carrier component supported by the O-RU.

[0091] 4) RU_port ID: The RU_port ID specifies logical flows such as data layer or spatial streams, and signaling channels that require separate numerologies (e.g. PRACH) or special antenna allocation such as SRS.

[0092] The application protocol of the fronthaul may include a control plane (C-plane), a user plane (U-plane), a synchronization plane (S-plane), and a management plane (M-plane).

[0093] The control plane may be configured to provide scheduling information and beamforming information via control messages. The control plane refers to real-time control between DUs and RUs. The user plane may include IQ sample data transmitted between DUs and RUs. The user plane may include user downlink data (IQ data or SSB / RS), uplink data (IQ data or SRS / RS), or PRACH data. A weight vector of the beamforming information described above may be multiplied by the user's data. The synchronization plane generally refers to traffic between DUs and RUs for a synchronization controller (e.g., IEEE grand master). The synchronization plane may be related to timing and synchronization. The management plane refers to non-real-time control between DUs and RUs. The management plane may be related to initial setup, non-realtime reset or reset, and non-realtime report.

[0094] Control plane messages, or C-plane messages, can be encapsulated based on a two-layer header approach. The first layer can consist of the eCPRI common header or the IEEE 1914.3 common header, which contains fields used to indicate the message type. The second layer is the application layer, which contains fields necessary for control and synchronization. Within the application layer, sections define the characteristics of U-plane data transmitted or received on a beam with a single pattern ID. The following section types are supported within the C-plane:

[0095] Section Type can indicate the purpose of control messages transmitted on the control plane. For example, the purposes of each Section Type are as follows.

[0096] 1) sectionType=0: Used to indicate resource blocks or symbols not used in DL or UL.

[0097] 2) sectionType=1: Used for most DL / UL wireless channels. Here, "most" refers to channels that do not require time or frequency offsets, such as those required for mixed numerology channels.

[0098] 3) sectionType=2: reserved for further use

[0099] 4) sectionType=3: PRACH and mixed-numerology channels. Channels that require a time or frequency offset or differ from the nominal SCS value(s).

[0100] 5) sectionType=4: reserved for further use

[0101] 6) sectionType=5: UE scheduling information. Transmits UE scheduling information so that the RU can perform real-time BF weight calculations (O-RAN optional BF method).

[0102] 7) sectionType=6: Transmits UE-specific channel information. Periodically transmits UE channel information to enable the RU to perform real-time BF weight calculations (O-RAN optional BF method).

[0103] 8) sectionType=7: Used for LAA support

[0104] In the following specification, an electronic device (e.g., a base station (110) or a terminal (120) of FIG. 1) may include at least one processing circuit for orthogonal frequency division multiplexing (OFDM) demodulation that changes a domain of a symbol sequence from a first domain to a second domain. The at least one processing circuit may include a memory (or buffer) for OFDM demodulation. For example, the at least one processing circuit may be referred to as an OFDM demodulation circuit. In the following, technical features for minimizing (or optimizing) the memory and delay time of the OFDM demodulation circuit will be described.

[0105] Figure 5a illustrates an example of the operation of an orthogonal frequency division multiplexing (OFDM) modulation circuit.

[0106] Figure 5b shows an example of the operation of an OFDM demodulation circuit.

[0107] Figure 6a illustrates an example of a cyclic shift operation of an OFDM modulation circuit.

[0108] Figure 6b shows an example of a cyclic shift operation of an OFDM demodulation circuit.

[0109] A system (e.g., a base station or user equipment (UE)) based on the NR (new radio) standard or the LTE (long term evolution) standard may include an OFDM modulation circuit and an OFDM demodulation circuit. An example of an OFDM modulation circuit will be described in FIG. 5a. An example of an OFDM demodulation circuit will be described in FIG. 5b.

[0110] Referring to FIG. 5A, the OFDM modulation circuit (510) can change the domain of a signal (or symbol sequence, symbol) from the frequency domain to the time domain based on performing an inverse fast Fourier transform (IFFT) operation. For example, the base station (110) (e.g., RU (220)) can change the domain of a downlink signal from the frequency domain to the time domain using the OFDM modulation circuit (510). The base station (110) can transmit the downlink signal in the time domain to the terminal (120). For example, the terminal (120) can change the domain of an uplink signal from the frequency domain to the time domain using the OFDM modulation circuit (510). The terminal (120) can transmit the uplink signal in the time domain to the base station (110).

[0111] According to one embodiment, the OFDM modulation circuit (510) may include a buffer (511), an inverse fast Fourier transform (IFFT) operation circuit (512), and / or a buffer (513).

[0112] For example, the buffer (511) may be used for a cyclic shift operation. For example, the OFDM modulation circuit (510) may perform a cyclic shift operation on a signal (or symbol sequence, symbol). The cyclic shift operation may be referred to as a pre-IFFT operation or an IFFT shift operation.

[0113] Referring to FIG. 6A, for a circular shift operation, a signal (or symbol sequence, symbol) can be divided into a signal (601) of a first band (e.g., high band) and a signal (602) of a second band (e.g., low band). For example, the number of tones for the signal can be n. The number of tones for the signal (601) can be n / 2. The number of tones for the signal (602) can be n / 2.

[0114] The OFDM modulation circuit (510) can change the order of the signal (601) and the signal (602). The OFDM modulation circuit (510) can configure the signal (601) as a front end of the input for the IFFT operation. The OFDM modulation circuit (510) can configure the signal (602) as a rear end of the input for the IFFT operation. The OFDM modulation circuit (510) can configure a guard band between the signal (601) and the signal (602). In order to configure the guard band, the OFDM modulation circuit (510) can set the input values ​​for the IFFT operation corresponding to the guard band to 0. Based on the above-described process, the OFDM modulation circuit (510) can perform a circular shift operation. N_FFT of FIG. 6A can represent the FFT size.

[0115] The OFDM modulation circuit (510) may utilize a buffer (511) to perform a circular shift operation. The size of the buffer (511) may be configured to be twice the maximum number of tones (or FFT size) of the signal. For example, a dual buffer having a depth twice the maximum number of tones (or FFT size) of the signal may be used for the buffer (511).

[0116] Referring back to FIG. 5A, the IFFT operation circuit (512) may be configured with a DIF (decimation in frequency) FFT structure of the Cooley-Tukey FFT algorithm for pipelined FFT. When the IFFT operation circuit (512) is configured with a DIF IFFT structure, a signal (or symbol sequence, symbol) in a bit-reversed order may be output based on a signal (or symbol sequence, symbol) in a natural bit order (or natural order) being input to the IFFT operation circuit (512).

[0117] As described above, when the IFFT operation circuit (512) is configured with a DIF IFFT structure, a signal (or symbol sequence, symbol) in a bit-reversed order is output, so the OFDM modulation circuit (510) can perform a reordering operation (or function) to change the signal (or symbol sequence, symbol) back to the natural bit order. The reordering operation (or function) can be set as in the following mathematical expression 1.

[0118]

[0119] Referring to Equation 1, x is the natural order index. y is the bit-reversed order index. N FFT is the size of the FFT.

[0120] The buffer (513) may be used for a cyclic extension operation. For example, the OFDM modulation circuit (510) may perform a cyclic extension operation on the output signal of the IFFT operation circuit (512). For example, the OFDM modulation circuit (510) may perform the cyclic extension operation based on inserting a cyclic prefix (CP) into the signal. The cyclic extension operation may be referred to as a CP insertion operation.

[0121] Referring to FIG. 5b, the OFDM demodulation circuit (520) can change the domain of a signal (or symbol sequence, symbol) from the time domain to the frequency domain based on performing a fast Fourier transform (FFT) operation. For example, the base station (110) (e.g., RU (220)) can receive an uplink signal in the time domain from the terminal (120). The base station (110) can change the domain of the uplink signal from the time domain to the frequency domain using the OFDM demodulation circuit (520). For example, the terminal (120) can receive a downlink signal in the time domain from the base station (110). The terminal (120) can change the domain of the downlink signal from the time domain to the frequency domain using the OFDM demodulation circuit (520).

[0122] According to one embodiment, the OFDM demodulation circuit (520) may include a buffer (521), a fast Fourier transform (FFT) operation circuit (522), and / or a buffer (523).

[0123] For example, the buffer (521) can be used for a digital AGC (digital auto gain control) operation. The base station (110) (or terminal (120)) can receive an RF signal using an antenna and obtain an amplified signal (531) through an RF (radio frequency) AGC (auto gain control) operation. Since the RF AGC operation cannot apply a gain to the RF signal in units of OFDM symbols, a digital AGC operation can be performed in the OFDM demodulation circuit (520). For example, the digital AGC operation can obtain (or measure, identify) the power of all OFDM symbols and obtain average data (e.g., upstream average data or downstream average data) about the power in units of digital bits. The OFDM demodulation circuit (520) can increase or decrease the power of all OFDM symbols based on the average data.

[0124] The OFDM demodulation circuit (520) may utilize the buffer (521) to perform a digital AGC operation. For example, the OFDM demodulation circuit (520) may acquire the power of all OFDM symbols of the signal (531) to perform the digital AGC operation. The buffer (521) may be used to acquire the power of all OFDM symbols of the signal (531). For a pipelined FFT, the size of the buffer (521) may be configured to be twice the maximum number of tones (or FFT size, FFT point size) of the signal (531). For example, a dual buffer having a depth twice the maximum number of tones (or FFT size) of the signal (531) may be used for the buffer (521).

[0125] The FFT operation circuit (522) may be configured with a DIF (decimation in frequency) FFT structure of the Cooley-Tukey FFT algorithm for pipelined FFT. When the FFT operation circuit (522) is configured with a DIF FFT structure, a signal (or symbol sequence, symbol) in bit-reversed order may be output based on a signal (e.g., signal (531)) (or symbol sequence, symbol) in natural bit order (or natural order) being input to the FFT operation circuit (522).

[0126] As described above, when the FFT operation circuit (522) is configured with a DIF FFT structure, a signal (or symbol sequence, symbol) in a bit-reversed order is output, so the OFDM demodulation circuit (520) can perform a reordering operation (or function) to change the signal (or symbol sequence, symbol) back to the natural bit order. The reordering operation (or function) can be set as in the above-described mathematical expression 1.

[0127] The buffer (523) may be used for reordering operations and cyclic shift operations. For example, the OFDM demodulation circuit (520) may perform reordering operations and cyclic shift operations on a signal (or symbol sequence, symbol). The cyclic shift operation may be referred to as a post-FFT operation or an FFT shift operation.

[0128] Referring to FIG. 6B, for a circular shift operation, a signal (or symbol sequence, symbol) can be divided into a signal (612) of a first band (e.g., high band) and a signal (611) of a second band (e.g., low band). The signal (611) can be related to the signal (601) of FIG. 6A. The signal (612) can be related to the signal (602) of FIG. 6A. For example, the number of tones for the signal can be n. The number of tones for the signal (611) can be n / 2. The number of tones for the signal (612) can be n / 2.

[0129] The OFDM demodulation circuit (520) can change the order of signals (611) and (612). For example, signal (611) can be the front end of the output of an FFT operation. Signal (612) can be the rear end of the output of the FFT operation. A guard band can be configured between signals (611) and (612). The OFDM demodulation circuit (520) can remove the guard band and change the order of signals (611) and (612). The OFDM demodulation circuit (520) can configure signal (612) as the front end of the output of the OFDM demodulation circuit (520). The OFDM demodulation circuit (520) can configure signal (611) as the rear end of the output of the OFDM demodulation circuit (520). N_FFT in FIG. 6b can represent the FFT size.

[0130] Referring again to FIG. 5b, the OFDM demodulation circuit (520) may utilize a buffer (523) to perform reordering operations and cyclic shift operations. The size of the buffer (523) may be configured to be twice the maximum number of tones (or FFT size) of the signal. For example, a dual buffer having a depth twice the maximum number of tones (or FFT size) of the signal may be used for the buffer (523).

[0131] As shown in FIGS. 5A and 5B, the IFFT operation circuit (512) and the FFT operation circuit (522) may be configured with a DIF FFT structure. For example, the size of the memory for an FFT operation circuit (or IFFT operation circuit) configured with a DIF FFT structure may be smaller than the size of the memory for an FFT operation circuit (or IFFT operation circuit) configured with a DIT FFT (decimation in time fast Fourier transform) structure. Therefore, the IFFT operation circuit and the FFT operation circuit may be configured with a DIF FFT structure.

[0132] In one embodiment, multiple antennas may be used in a wireless communication system for the purposes of spatial multiplexing, inter-signal interference reduction, diversity, and / or reliability enhancement. As the number of antennas increases, the FFT point size (or FFT size) may increase due to real-time multi-antenna signal processing and bandwidth expansion. As the FFT point size increases, hardware resource usage (e.g., memory usage) within the OFDM demodulation circuit may also increase.

[0133] The increase in hardware resource usage, as described above, can lead to increased system latency and decreased response speed. Increased power consumption can also lead to increased capital expenditures and operating expenditures. Furthermore, increased heat generation can lead to increased product size for heat dissipation. Therefore, technical features may be required to prevent this in OFDM demodulation circuits. Below, technical features for reducing hardware resource usage in OFDM demodulation circuits will be described. Specifically, technical features for optimizing the memory of OFDM demodulation circuits according to changes in the FFT algorithm will be described below.

[0134] First, the DFT (discrete Fourier transform) operation for the FFT operation can be configured as in mathematical expression 2.

[0135]

[0136] Referring to Equation 2, n is the time domain index and k is the frequency domain index. is the twiddle factor.

[0137] For example, the twiddle factor can be constructed as in mathematical formula 3.

[0138]

[0139] Based on the above-described DFT operation, an FFT operation can be constructed. For the FFT operation, N=2 p For a complex input x(n), a signal flow graph of p stages (or steps) is constructed, and N / 2 butterfly structure operations can be performed for each stage.

[0140] For convenience of explanation, a 16-point FFT operation will be described below. However, this is for convenience of explanation, and the FFT size may vary depending on the embodiment.

[0141] If the above mathematical expression 2 is decomposed into binary steps, it can be constructed as mathematical expression 4.

[0142]

[0143] Based on the FFT operation configured as in mathematical expression 4, an OFDM demodulation circuit of a DIF FFT structure or a DIT FFT structure can be configured. Hereinafter, the FFT operation of the DIF FFT structure or the DIT FFT structure and the signal flow diagram according to the FFT operation will be described.

[0144] Figure 7 illustrates a signal flow graph regarding the FFT operation of the DIF FFT (decimation in frequency fast Fourier transform) structure.

[0145] Referring to Fig. 7, mathematical expression 4 can be expanded as mathematical expression 5. In mathematical expression 4, According to the development, the FFT operation can be configured as in mathematical expression 5.

[0146]

[0147] In Equation 5, depending on the expansion for n2, n3, and n4, the FFT operation can be configured as in Equation 6.

[0148]

[0149] A signal flow diagram (700) may be constructed according to mathematical expression 6. The signal flow diagram (700) may illustrate an FFT operation. For example, referring to the signal flow diagram (700), as an FFT operation is performed on a symbol sequence (or symbol) constructed based on a natural bit order, a symbol sequence (or symbol) constructed based on a bit inversion order may be output (or acquired). Accordingly, in order to align the symbol sequence (or symbol) constructed based on the bit inversion order (or align the FFT index (time domain index)), all data related to the symbol sequence may be stored in a memory (e.g., a buffer (512) of FIG. 5A) and then output.

[0150] According to one embodiment, the signal flow diagram (700) may be composed of multiple stages. For example, the signal flow diagram (700) may include stages (701), (702), (703), and (704). The OFDM demodulation circuit may perform the operation of Equation 6 by sequentially performing operations on stages (701) to (704).

[0151] According to one embodiment, a buffer (e.g., buffer (521)) for input of an FFT operation circuit (e.g., FFT operation circuit (522)) in an OFDM demodulation circuit (e.g., OFDM demodulation circuit (520)) may be used for a digital AGC operation. If the digital AGC operation is not performed, the buffer for input of the FFT operation circuit may be omitted. However, if the digital AGC operation is not performed, since a wide fixed-bit structure of the FFT is required, it is more efficient to maintain a buffer for input of the FFT operation circuit in the OFDM demodulation circuit.

[0152] When the FFT operation circuit is configured with a DIT FFT structure, a signal can be output from the FFT operation circuit in a natural bit order. When the signal is output from the FFT operation circuit in a natural bit order, a buffer (e.g., buffer (523)) for the output of the OFDM demodulation circuit can be omitted. For example, the size of the memory for the FFT operation circuit configured with a DIT FFT structure can be larger than the size of the memory for the FFT operation circuit (or IFFT operation circuit) configured with a DIF FFT structure, but when the buffer (e.g., buffer (523)) for the output of the OFDM demodulation circuit is omitted, the memory of the OFDM demodulation circuit can be significantly reduced.

[0153] Therefore, below, the structure of an OFDM demodulation circuit that does not include a buffer (e.g., buffer (523)) for the output of the OFDM demodulation circuit will be described using an FFT operation circuit configured with a DIT FFT structure.

[0154] Figure 8 illustrates a signal flow graph regarding the FFT operation of the DIT FFT (decimation in time fast Fourier transform) structure.

[0155] Figure 9 illustrates a signal flow diagram for an FFT operation using a circular shift operation of a DIT FFT structure.

[0156] Referring to Fig. 8, the above mathematical expression 4 can be developed as the above mathematical expression 5. In mathematical expression 5, can be configured as in mathematical formula 7.

[0157]

[0158]

[0159]

[0160]

[0161]

[0162] Using Equations 8, 9, and 10, Equation 5 can be changed to Equation 11.

[0163]

[0164] According to the expansion for n2 in Equation 11, the FFT operation can be configured as in Equation 12.

[0165]

[0166] In mathematical expression 12, can be configured as in mathematical formula 13.

[0167]

[0168] In mathematical expression 12, According to the development, the FFT operation can be configured as in Equation 14.

[0169]

[0170] In mathematical expression 14, can be configured as in mathematical formula 15.

[0171]

[0172] According to mathematical formula 15, It can be configured as in mathematical formula 16.

[0173]

[0174] According to Equation 16, the FFT operation can be configured as in Equation 17.

[0175]

[0176] According to the expansion for n3 in Equation 17, the FFT operation can be configured as in Equation 18.

[0177]

[0178] In mathematical expression 18, can be configured as in mathematical formula 19.

[0179]

[0180] According to Equation 19, the FFT operation can be configured as in Equation 20.

[0181]

[0182] In mathematical expression 20, can be configured as in mathematical formula 21.

[0183]

[0184] According to the expansion for Equation 21 and n4, the FFT operation can be configured as in Equation 22.

[0185]

[0186] A signal flow diagram (800) can be constructed according to mathematical expression 22. The signal flow diagram (800) can illustrate an FFT operation.

[0187] According to one embodiment, the signal flow diagram (800) may be composed of multiple stages. For example, the signal flow diagram (800) may include stages (801), (802), (803), and (804). The OFDM modulation circuit may perform the operation of Equation 22 by sequentially performing operations on stages (801) to (804).

[0188] Referring to the signal flow diagram (800), as an FFT operation is performed on a symbol sequence (or symbol) constructed based on a bit-reversal order, a symbol sequence (or symbol) constructed based on a natural bit order may be output (or acquired). As the FFT operation is performed, since the symbol sequence (or symbol) is constructed based on the natural bit order, memory for aligning the symbol sequence (or symbol) (or aligning the FFT index (time domain index)) may not be required.

[0189] As described above, when the FFT operation circuit is configured with a DIT FFT structure, a sequence (or symbol) configured based on the natural bit order can be obtained as the output of the FFT operation circuit. Therefore, the OFDM demodulation circuit may not include a memory (or buffer) for the reordering operation. However, the OFDM demodulation circuit may require a memory (or buffer) for the cyclic shift operation.

[0190] According to one embodiment, when a cyclic shift operation is performed on the output of an FFT operation circuit and a sequence (or symbol) constructed based on the natural bit order is obtained, a memory (or buffer) for the cyclic shift operation may not be required. The structure of an FFT operation circuit for performing a cyclic shift operation and obtaining a sequence (or symbol) constructed based on the natural bit order will be described later in FIG. 9.

[0191] Referring to Fig. 9, in order to configure an FFT operation circuit utilizing a circular shift operation, k4 in the above-described mathematical expression 22 can be replaced with 'k4. For example, k4 can be the MSB of the bit sequence of the FFT index (frequency domain index). For example, 'k4 can be configured as in mathematical expression 23.

[0192]

[0193] Referring to mathematical expression 23, 'k1' is the value obtained by performing a modulo 2 operation on k1+1.

[0194] As k4 is replaced with 'k4' in the above mathematical expression 22, the output of the FFT operation circuit can be shifted by half. The above equation is 2 n It can be applied to the FFT operation of the size of . As k4 is replaced with 'k4' in the above mathematical expression 22, a signal flow diagram (900) can be constructed.

[0195] The signal flow diagram (900) of FIG. 9 may be composed of multiple stages. For example, the signal flow diagram (900) may include stages (901), (902), (903), and (904). The FFT operation circuit (or OFDM demodulation circuit) may sequentially perform operations on stages (901) to (904). For example, stage (904) may be configured such that the sign for the last operation of stage (804) is switched (or changed) as k4 is replaced with 'k4.

[0196] Referring to the signal flow diagram (900) for the FFT operation circuit, the input data of the FFT operation circuit may be composed of a symbol sequence (or symbols) configured based on a bit-reversal order. The output data of the FFT operation circuit may be composed of a symbol sequence (or symbols) to which a circular shift operation is applied to a symbol sequence (or symbols) configured based on a natural bit order.

[0197] Since the output data of the FFT operation circuit is composed of a symbol sequence (or symbols) to which a circular shift operation is applied based on a symbol sequence (or symbols) composed based on a natural bit order, a memory (or buffer) for aligning the symbol sequence (or symbols) (or aligning the FFT index (time domain index)) and a memory (or buffer) for performing the circular shift operation may not be required. The above-described formula conversion may not cause an increase in the complexity of the system.

[0198] Figure 10 illustrates an OFDM demodulation circuit for performing FFT operations for circular shift operations and reordering operations.

[0199] Referring to FIG. 10, the OFDM demodulation circuit (1000) may include a buffer (1010) and an FFT operation circuit (1020). The FFT operation circuit (1020) may be configured based on the signal flow diagram (900) of FIG. 9.

[0200] Based on the signal flow diagram (900) of FIG. 9, when an FFT operation circuit (1020) is configured, as an FFT operation for a symbol sequence (or symbol) configured based on a bit inversion order is performed in the FFT operation circuit (1020), a symbol sequence (or symbol) to which a circular shift operation is applied to a symbol sequence (or symbol) configured based on a natural bit order can be output (or obtained).

[0201] For example, the buffer (1010) may be used to perform a digital AGC operation and input a symbol sequence (or symbol) constructed based on a bit inversion order to the FFT operation circuit (1020). Since the symbol sequence (or symbol) is stored in a memory (e.g., buffer (1010)) before being input to the FFT operation circuit (1020), the OFDM demodulation circuit (1000) may output a symbol sequence (or symbol) constructed based on a natural bit order based on a bit inversion order. As an example, the OFDM demodulation circuit (1000) may set a read address for outputting a symbol sequence (or symbol) based on a bit inversion order. The symbol sequence (or symbol) constructed based on the bit inversion order may be input to the FFT operation circuit (1020).

[0202] The output data of the FFT operation circuit (1020) may be composed of a symbol sequence (or symbol) in which a cyclic shift operation is applied to a symbol sequence (or symbol) composed based on a natural bit order, by half the FFT size. Accordingly, the OFDM demodulation circuit (1000) may not include a memory (or buffer) for aligning the symbol sequence (or symbol) and a memory (or buffer) for performing the cyclic shift operation. For example, since the guard band is located in the central region of the symbol sequence as in FIG. 6b, the same output as the outputs of FIGS. 5a and 5b can be obtained through the OFDM demodulation circuit (1000) without a memory.

[0203] In the above-described embodiments, an example in which the size of the FFT is set to 16 has been described, but this is for convenience of explanation, and the size of the FFT may be set in various ways. In addition, although the above-described embodiments have been described based on the Radix 2 algorithm, this is for convenience of explanation. The technical features according to the above-described embodiments can be applied to various algorithms, including the Radix 4 algorithm and the Radix 2^2 algorithm.

[0204] Figure 11 illustrates a flowchart of the operation of an electronic device for performing an FFT operation using a circular shift operation.

[0205] In operations 1110 and 1120, the electronic device may include at least one processing circuit for OFDM demodulation that changes the domain of the symbol sequence from a first domain to a second domain. For example, an example of the electronic device according to operations 1110 and 1120 may be an example of the OFDM demodulation circuit (1000) of FIG. 10.

[0206] Referring to FIG. 11, in operation 1110, at least one processing circuit of an electronic device may obtain a first symbol sequence for a first domain based on a received signal. For example, the at least one processing circuit may obtain a first symbol sequence for a first domain based on a received signal obtained from an external electronic device. For example, the first domain may be a time domain. The first domain may include a time domain. The first symbol sequence may be configured based on the time domain.

[0207] For example, if an electronic device corresponds to a base station, an external electronic device may correspond to a terminal. For example, if an electronic device corresponds to a terminal, an external electronic device may correspond to a base station.

[0208] For example, at least one processing circuit can obtain a third symbol sequence for a first domain from the received signal. The at least one processing circuit can store the third symbol sequence for the first domain in a second buffer (e.g., buffer (1010) of FIG. 10). The at least one processing circuit can perform an automatic gain control operation based on the third symbol sequence. The at least one processing circuit can identify an average value of power for the third symbol sequence stored in the second buffer and perform an automatic gain control operation based on the average value.

[0209] For example, at least one processing circuit can obtain a first symbol sequence using a second buffer based on a third symbol sequence. The third symbol sequence can be constructed based on a natural bit order. The first symbol sequence can be constructed based on a bit-reversed order. The at least one processing circuit can obtain (or output) the first symbol sequence by changing an output order of the third symbol sequence stored in the second buffer.

[0210] The fact that the third symbol sequence is constructed based on the natural bit order may mean that the FFT index (or frequency domain index) is constructed sequentially. For example, the fact that the first symbol sequence is constructed based on the natural bit order may mean that the FFT index (or frequency domain index) is constructed similarly to the input of the signal flow diagram (700) of FIG. 7.

[0211] The fact that the first symbol sequence is constructed based on a bit-reversal order may mean that the FFT index (or time domain index) is constructed based on a bit-reversal order. For example, the fact that the first symbol sequence is constructed based on a bit-reversal order may mean that the FFT index (or time domain index) is constructed similarly to the input of the signal flow diagram (900) of FIG. 9.

[0212] According to one embodiment, the size of the second buffer may be set based on the FFT size for the FFT operation performed below. For example, the size of the second buffer may be set to twice the FFT size.

[0213] In operation 1120, at least one processing circuit can obtain a second symbol sequence for a second domain by performing an FFT operation using a circular shift operation on the first symbol sequence.

[0214] For example, at least one processing circuit can perform an FFT operation using a circular shift operation on the first symbol sequence. As an example, the at least one processing circuit can perform an FFT operation using a circular shift operation on the first symbol sequence without a first buffer for the circular shift operation (e.g., buffer (523) of FIG. 5B).

[0215] For example, an FFT operation using a circular shift operation may include an operation of changing, for each FFT index among FFT indices (or time domain indices) for the first domain according to the FFT size, the MSB (most significant bit) value of the bit sequence of the corresponding FFT index from 0 to 1 or from 1 to 0. For example, an FFT operation using a circular shift operation may be performed based on a . DIT (decimation in time) FFT structure.

[0216] For example, an FFT operation using a circular shift operation may be performed based on a plurality of twiddle factors. An FFT operation using a circular shift operation may be composed of a plurality of steps (or stages) based on a plurality of twiddle factors. The plurality of steps may include stages (901) to (904) of the signal flow diagram (900) of FIG. 9.

[0217] For example, at least one processing circuit can perform an FFT operation using a circular shift operation on a first symbol sequence without a first buffer for the circular shift operation. Since the first symbol sequence is configured based on a bit-reversal order, the first symbol sequence configured based on the bit-reversal order can be input to a circuit configured for the FFT operation (e.g., the FFT operation circuit (1020) of FIG. 10).

[0218] At least one processing circuit can obtain a second symbol sequence for a second domain. For example, the at least one processing circuit can obtain the second symbol sequence for the second domain based on a result of an FFT operation using a cyclic shift operation. For example, the second domain may be a frequency domain. The second domain may include a frequency domain. The second symbol sequence may be constructed based on the frequency domain. The second symbol sequence may be constructed based on a natural bit order in which the cyclic shift operation is performed (or a cyclic shifted natural bit order). The at least one processing circuit may not include a first buffer for the cyclic shift operation. A storage area for the first buffer may not be configured within the electronic device (or within the at least one processing circuit).

[0219] The fact that the second symbol sequence is constructed based on the natural bit order (or cyclic shifted natural bit order) on which the cyclic shift operation is performed may mean that the FFT index (or frequency domain index) is constructed similarly to the output of the signal flow diagram (900) of FIG. 9. For example, at least one processing circuit may obtain the second symbol sequence shifted by half the FFT size based on the FFT operation using the cyclic shift operation.

[0220] Figure 12 shows an example of the configuration of a processing device.

[0221] Referring to FIG. 12, the processing device (1200) may be composed of one or more chips. For example, the processing device (1200) may be composed of a field programmable gate array (FPGA). For example, the processing device (1200) may be composed based on an application specific integrated circuit (ASIC). For example, an example of the processing device (1200) may be the electronic device (or OFDM demodulation circuit) described above. For example, the processing device (1200) may perform at least some or all of the functions of the RU. However, the present invention is not limited thereto. The processing device (1200) may also perform at least some or all of the functions of the DU.

[0222] For example, the processing unit (1200) may be controlled by a processor (or at least a portion of a processor). As an example, the processing unit (1200) may be controlled by the processor (380) of FIG. 3B. For example, the processing unit (1200) may also be configured as at least a portion of a processor.

[0223] According to one embodiment, the processing device (1200) may include a processing circuit (1210) and a memory (1220).

[0224] For example, the processing circuit (1210) may be an example of at least one processing circuit of FIG. 11. The processing circuit (1210) may include at least one component for OFDM demodulation. The processing circuit (1210) may perform an FFT operation of a DIT FFT structure (or a DIF FFT structure) depending on the configuration of the at least one component.

[0225] The memory (1220) may include a plurality of storage spaces. The memory (1220) may be divided into the plurality of storage spaces. For example, the memory (1220) may include a first storage space (1221), a second storage space (1222), and / or a third storage space (1223). For example, the first storage space (1221) may be allocated for the first buffer described above (e.g., buffer (1010) of FIG. 10). According to an embodiment, the memory (1220) may be configured with one memory (or one storage circuit). For example, storage spaces may be divided within one memory, and multiple storage spaces (e.g., the first storage space (1221), the second storage space (1222), and the third storage space (1223)) may be configured. According to an embodiment, the memory (1220) may be configured with a plurality of memories (or a plurality of storage circuits). A first number of memories among the plurality of memories may be used for a first storage space (1221). A second number of memories among the plurality of memories may be used for a second storage space (1222). A third number of memories among the plurality of memories may be used for a third storage space (1223).

[0226] According to one embodiment, an electronic device (e.g., an OFDM demodulation circuit (1000)) may include a memory and at least one processing circuit for orthogonal frequency division multiplexing (OFDM) demodulation that changes a domain of a symbol sequence from a first domain to a second domain. The at least one processing circuit may be configured to obtain a first symbol sequence for the first domain based on a received signal obtained from an external electronic device. The at least one processing circuit may be configured to obtain a second symbol sequence for the second domain by performing a fast Fourier transform (FFT) operation using a cyclic shift operation on the first symbol sequence. The FFT operation using the above circular shift operation may include an operation of changing the value of the most significant bit (MSB) of the bit sequence of each FFT index from 0 to 1 or from 1 to 0 among the FFT indices for the second domain according to the FFT (fast Fourier transform) size.

[0227] According to one embodiment, the first symbol sequence may be constructed based on a bit-reversed order. The second symbol sequence may be constructed based on a natural bit order in which the circular shift operation is performed.

[0228] According to one embodiment, the at least one processing circuit may be configured to perform the FFT operation using the circular shift operation on the first symbol sequence without a first buffer for the circular shift operation.

[0229] According to one embodiment, the at least one processing circuit may be configured to store a third symbol sequence regarding the first domain obtained from the received signal in a second buffer. The at least one processing circuit may be configured to perform an automatic gain control operation based on the third symbol sequence.

[0230] According to one embodiment, the third symbol sequence may be constructed based on a natural bit order.

[0231] According to one embodiment, the at least one processing circuit may be configured to obtain the first symbol sequence using the second buffer based on the third symbol sequence.

[0232] According to one embodiment, the size of the second buffer may be set to twice the size of the FFT.

[0233] According to one embodiment, the FFT operation using the circular shift operation may be performed based on a plurality of twiddle factors.

[0234] According to one embodiment, the at least one processing circuit may be configured to obtain the second symbol sequence shifted by half of the FFT size based on the FFT operation using the circular shift operation.

[0235] According to one embodiment, the FFT operation using the circular shift operation may be performed based on a DIT (decimation in time) FFT structure.

[0236] According to one embodiment, a method performed by an electronic device may include an operation of obtaining a first symbol sequence for a first domain based on a received signal obtained from an external electronic device. The method may include an operation of obtaining a second symbol sequence for a second domain by performing a fast Fourier transform (FFT) operation using a cyclic shift operation on the first symbol sequence. The FFT operation using the cyclic shift operation may include an operation of changing a value of a most significant bit (MSB) of a bit sequence of each FFT index among FFT indices for the second domain according to an FFT size from 0 to 1 or from 1 to 0.

[0237] According to one embodiment, the first symbol sequence may be constructed based on a bit-reversed order. The second symbol sequence may be constructed based on a natural bit order in which the circular shift operation is performed.

[0238] According to one embodiment, the method may include performing the FFT operation using the circular shift operation on the first symbol sequence without a first buffer for the circular shift operation.

[0239] According to one embodiment, the method may include an operation of storing a third symbol sequence regarding the first domain obtained from the received signal in a second buffer. The method may include an operation of performing an automatic gain control operation based on the third symbol sequence.

[0240] According to one embodiment, the third symbol sequence may be constructed based on a natural bit order.

[0241] According to one embodiment, the method may include an operation of obtaining the first symbol sequence using the second buffer based on the third symbol sequence.

[0242] According to one embodiment, the size of the second buffer may be set to twice the size of the FFT.

[0243] According to one embodiment, the FFT operation using the circular shift operation may be performed based on a plurality of twiddle factors.

[0244] According to one embodiment, the method may include an operation of obtaining the second symbol sequence shifted by half of the FFT size based on the FFT operation using the circular shift operation.

[0245] According to one embodiment, the FFT operation using the circular shift operation may be performed based on a DIT (decimation in time) FFT structure.

[0246] According to one embodiment, an electronic device (e.g., an OFDM demodulation circuit (1000)) may include a memory that stores instructions for OFDM (orthogonal frequency division multiplexing) demodulation that changes a domain of a symbol sequence from a first domain to a second domain, and includes one or more storage media, and at least one processing circuit. The instructions, when individually or collectively executed by the at least one processing circuit, may cause the electronic device to obtain a first symbol sequence for the first domain based on a received signal obtained from an external electronic device. The instructions, when individually or collectively executed by the at least one processing circuit, may cause the electronic device to obtain a second symbol sequence for the second domain by performing a fast Fourier transform (FFT) operation using a cyclic shift operation on the first symbol sequence. The FFT operation using the above circular shift operation may include an operation of changing the value of the most significant bit (MSB) of the bit sequence of each FFT index from 0 to 1 or from 1 to 0 among the FFT indices for the second domain according to the FFT (fast Fourier transform) size.

[0247] According to one embodiment, the first symbol sequence may be constructed based on a bit-reversed order. The second symbol sequence may be constructed based on a natural bit order in which the circular shift operation is performed.

[0248] According to one embodiment, the instructions, when individually or collectively executed by the at least one processing circuit, may cause the electronic device to perform the FFT operation using the circular shift operation on the first symbol sequence without a first buffer for the circular shift operation.

[0249] In one embodiment, the instructions, when individually or collectively executed by the at least one processing circuit, may cause the electronic device to store a third symbol sequence relating to the first domain obtained from the received signal in a second buffer. The instructions, when individually or collectively executed by the at least one processing circuit, may cause the electronic device to perform an automatic gain control operation based on the third symbol sequence.

[0250] According to one embodiment, the third symbol sequence may be constructed based on a natural bit order.

[0251] According to one embodiment, the instructions, when individually or collectively executed by the at least one processing circuit, may cause the electronic device to obtain the first symbol sequence using the second buffer based on the third symbol sequence.

[0252] According to one embodiment, the size of the second buffer may be set to twice the size of the FFT.

[0253] According to one embodiment, the FFT operation using the circular shift operation may be performed based on a plurality of twiddle factors.

[0254] According to one embodiment, the instructions, when individually or collectively executed by the at least one processing circuit, may cause the electronic device to obtain the second symbol sequence shifted by half the FFT size based on the FFT operation using the circular shift operation.

[0255] According to one embodiment, the FFT operation using the circular shift operation may be performed based on a DIT (decimation in time) FFT structure.

[0256] According to the above-described embodiment, an OFDM demodulation circuit can be configured that does not include a memory (or buffer) for performing a reordering operation and a circular shift operation at the output terminal of the FFT operation circuit. The size of the memory for the FFT operation circuit (or IFFT operation circuit) configured with a DIF FFT structure is smaller than the size of the memory for the FFT operation circuit (or IFFT operation circuit) configured with a DIT FFT (decimation in time fast Fourier transform) structure, but the FFT operation circuit (e.g., FFT operation circuit (1020)) of the OFDM demodulation circuit (e.g., OFDM demodulation circuit (1000)) according to the above-described embodiment can be configured with a DIT FFT structure. Even when the FFT operation circuit (e.g., FFT operation circuit (1020)) of the OFDM demodulation circuit (e.g., OFDM demodulation circuit (1000)) according to the above-described embodiment is configured with a DIT FFT structure, memory usage can be reduced because memory for performing reordering operation and circular shift operation is not configured at the output terminal of the FFT operation circuit. Since the storage operation for the output data of the FFT operation circuit is omitted, the latency of an OFDM symbol or more can be reduced, and additional heat generation and power consumption can be reduced.

[0257] According to the above-described embodiment, input buffers can be omitted or the size of output buffers can be reduced without performance degradation through simple formula changes. According to the above-described embodiment, since the storage procedure is simplified, latency beyond OFDM symbols can be reduced. According to the above-described embodiment, heat generation and power consumption can be reduced as hardware resource usage is reduced. Since the OFDM modulation circuit must perform an IFFT operation per antenna, heat generation and power consumption can be significantly reduced in systems with large bandwidths and many antennas.

[0258] The methods according to the embodiments described in the claims or specification of the present disclosure may be implemented in the form of hardware, software, or a combination of hardware and software.

[0259] When implemented in software, a computer-readable storage medium storing one or more programs (software modules) may be provided. The one or more programs stored in the computer-readable storage medium are configured to be executed by one or more processors in an electronic device. The one or more programs include instructions that cause the electronic device to execute methods according to embodiments described in the claims or specification of the present disclosure. The one or more programs may be provided as a computer program product. The computer program product may be traded between a seller and a buyer as a commodity. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., compact disc read only memory (CD-ROM)), or may be distributed online (e.g., downloaded or uploaded) through an application store (e.g., Play Store) or directly between two user devices (e.g., smart phones). In the case of online distribution, at least a portion of the computer program product may be temporarily stored or temporarily created in a device-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or an intermediary server.

[0260] These programs (software modules, software) may be stored in random access memory, non-volatile memory including flash memory, read only memory (ROM), electrically erasable programmable read only memory (EEPROM), magnetic disc storage devices, compact disc-ROM (CD-ROM), digital versatile discs (DVDs) or other forms of optical storage devices, magnetic cassettes, or may be stored in memories formed by a combination of some or all of these. In addition, each configuration memory may include multiple copies.

[0261] Additionally, the program may be stored on an attachable storage device that is accessible via a communication network, such as the Internet, an intranet, a local area network (LAN), a wide area network (WAN), a storage area network (SAN), or a combination thereof. Such a storage device may be connected to a device performing an embodiment of the present disclosure via an external port. Additionally, a separate storage device on the communication network may be connected to a device performing an embodiment of the present disclosure.

[0262] In the specific embodiments of the present disclosure described above, components included in the disclosure are expressed in the singular or plural form, depending on the specific embodiment presented. However, the singular or plural expressions are selected to suit the presented situation for convenience of explanation, and the present disclosure is not limited to singular or plural components. Components expressed in the plural form may be composed of singular elements, or components expressed in the singular form may be composed of plural elements.

[0263] According to embodiments, one or more of the components or operations of the aforementioned components may be omitted, or one or more other components or operations may be added. Alternatively or additionally, a plurality of components (e.g., modules or programs) may be integrated into a single component. In such a case, the integrated component may perform one or more functions of each of the plurality of components identically or similarly to those performed by the corresponding component among the plurality of components prior to the integration. According to embodiments, the operations performed by a module, program, or other component may be executed sequentially, in parallel, iteratively, or heuristically, or one or more of the operations may be executed in a different order, omitted, or one or more other operations may be added.

[0264] Meanwhile, although the detailed description of the present disclosure has described specific embodiments, it is obvious that various modifications are possible within the scope of the present disclosure.

Claims

1. In electronic devices, A memory storing instructions for OFDM (orthogonal frequency division multiplexing) demodulation that changes the domain of a symbol sequence from a first domain to a second domain, and including one or more storage media; and comprising at least one processing circuit, The above instructions, when individually or collectively executed by the at least one processing circuit, cause the electronic device to: Based on a received signal obtained from an external electronic device, a first symbol sequence for the first domain is obtained, By performing a fast Fourier transform (FFT) operation using a cyclic shift operation on the first symbol sequence, a second symbol sequence for the second domain is obtained, The FFT operation using the above circular shift operation is, for each FFT index among the FFT indices for the second domain according to the FFT (fast Fourier transform) size: An operation that includes changing the value of the most significant bit (MSB) of the bit sequence of the corresponding FFT index from 0 to 1 or from 1 to 0. Electronic devices.

2. In the first paragraph, the first symbol sequence is, It is constructed based on bit-reversed order, The second symbol sequence above is, It is constructed based on the natural bit order in which the above circular shift operation is performed. Electronic devices.

3. In the second paragraph, the instructions, when individually or collectively executed by the at least one processing circuit, cause the electronic device to: Further causing the FFT operation using the circular shift operation to be performed on the first symbol sequence without the first buffer for the circular shift operation. Electronic devices.

4. In the third paragraph, the instructions, when individually or collectively executed by the at least one processing circuit, cause the electronic device to: Store the third symbol sequence for the first domain obtained from the received signal in the second buffer, Further causing an automatic gain control operation to be performed based on the third symbol sequence. Electronic devices.

5. In the fourth paragraph, the third symbol sequence is, It is constructed based on the natural bit order, Electronic devices.

6. In the fifth paragraph, the instructions, when individually or collectively executed by the at least one processing circuit, cause the electronic device to: Based on the third symbol sequence, further causing the first symbol sequence to be obtained using the second buffer. Electronic devices.

7. In the fourth paragraph, the size of the second buffer is Set to twice the above FFT size, Electronic devices.

8. In the first paragraph, the FFT operation using the circular shift operation is is performed based on a plurality of twiddle factors, Electronic devices.

9. In the first paragraph, the instructions, when individually or collectively executed by the at least one processing circuit, cause the electronic device to: Based on the FFT operation using the above circular shift operation, further causing the second symbol sequence to be obtained by shifting half of the FFT size. Electronic devices.

10. In the first paragraph, the FFT operation using the circular shift operation is It is performed based on the DIT(decimation in time) FFT structure. Electronic devices.

11. In a method performed by an electronic device, An operation of obtaining a first symbol sequence for a first domain based on a received signal obtained from an external electronic device; and An operation of obtaining a second symbol sequence for a second domain by performing a fast Fourier transform (FFT) operation using a cyclic shift operation on the first symbol sequence, The FFT operation using the above circular shift operation is, for each FFT index among the FFT indices for the second domain according to the FFT (fast Fourier transform) size: An operation that includes changing the value of the most significant bit (MSB) of the bit sequence of the corresponding FFT index from 0 to 1 or from 1 to 0. method.

12. In the 11th paragraph, the first symbol sequence is, It is constructed based on bit-reversed order, The second symbol sequence above is, It is constructed based on the natural bit order in which the above circular shift operation is performed. method.

13. In the 12th paragraph, the method, Further comprising an operation of performing the FFT operation using the circular shift operation on the first symbol sequence without a first buffer for the circular shift operation. method.

14. In the 13th paragraph, the method, An operation of storing a third symbol sequence regarding the first domain obtained from the received signal in a second buffer; and Further comprising an operation of performing an automatic gain control operation based on the third symbol sequence. method.

15. In the 14th paragraph, the third symbol sequence is, It is constructed based on the natural bit order, method.

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