Electronic device and memory operation control method using same

Abstract

An electronic device according to one embodiment of the present disclosure comprises: a memory module; and a processor electrically connected to the memory module, wherein the processor is capable of: obtaining first error improvement data regarding the memory module; identifying an error for at least a partial area of the memory module; on the basis of the identification of the error, identifying an error area of the memory module and a manufacturing time of the memory module; and controlling an operation of the memory module on the basis of memory module operation control data corresponding to the error area of the memory module and the manufacturing time of the memory module from the first error improvement data.

Description

Electronic device and method for controlling memory operation using the same

[0001] The present disclosure relates to an electronic device and a method for controlling memory operation using the same.

[0002] As semiconductor memory ages, at least one memory cell in the memory cell array may deteriorate, resulting in deteriorated performance. To protect against memory cell failure due to deterioration, the semiconductor memory module may include a redundancy circuit and / or redundant memory cells. Furthermore, the semiconductor memory module may include a fuse circuit for changing internal setting values ​​or programming repair addresses, etc.

[0003] Users are unable to recognize performance degradation due to deterioration that occurs during the process of using an electronic device equipped with semiconductor memory, and after the semiconductor memory is packaged into an electronic device, the electronic device must be disassembled to evaluate the memory itself and conduct a failure analysis.

[0004] The above information may be provided as background art to aid in understanding the present disclosure. No claim or determination is made as to whether any of the above is applicable as prior art in connection with the present disclosure.

[0005] An electronic device according to one embodiment includes a memory, and a processor electrically connected to the memory, wherein the processor obtains first error improvement data regarding the memory, identifies an error for at least a portion of the memory, identifies an error area of ​​the memory and a manufacturing time of the memory based on the identification of the error, and controls an operation of the memory based on memory operation control data identified from the first error improvement data, wherein the memory operation control data may correspond to the error area of ​​the memory and the manufacturing time of the memory.

[0006] A method of an electronic device according to one embodiment includes the steps of: obtaining first error improvement data regarding a memory; identifying an error in at least a portion of the memory; identifying an error area of ​​the memory and a manufacturing time of the memory based on the identification of the error; and controlling an operation of the memory based on memory operation control data identified from the first error improvement data, wherein the memory operation control data may correspond to the error area of ​​the memory and the manufacturing time of the memory.

[0007] A non-transitory computer-readable recording medium storing instructions according to one embodiment of the present invention is configured such that when the instructions are executed by a processor, the processor can obtain first error improvement data regarding a memory, identify an error for at least a portion of the memory, identify an error area of ​​the memory and a manufacturing date of the memory based on the identification of the error, and control an operation of the memory based on memory operation control data identified from the first error improvement data, wherein the memory operation control data can correspond to the error area of ​​the memory and the manufacturing date of the memory.

[0008] Figure 1 is a block diagram showing the configuration of an electronic device according to one embodiment.

[0009] FIG. 2 is a block diagram showing the configuration of an application processor (AP) and a memory module according to one embodiment.

[0010] Figures 3a, 3b, and 3c are flowcharts illustrating the operation of an electronic device according to one embodiment.

[0011] FIG. 4 illustrates a memory module failure improvement table according to one embodiment.

[0012] FIG. 5 illustrates a UI displayed on a display according to one embodiment.

[0013] FIG. 6 is a block diagram of an electronic device within a network environment according to one embodiment.

[0014] In connection with the description of the drawings, the same or similar reference numerals may be used for identical or similar components.

[0015] Hereinafter, various embodiments of the present invention will be described with reference to the attached drawings. However, this is not intended to limit the present invention to specific embodiments, and it should be understood that the present invention encompasses various modifications, equivalents, and / or alternatives of the embodiments.

[0016] Figure 1 is a block diagram showing the configuration of an electronic device according to one embodiment.

[0017] Referring to FIG. 1, an electronic device (10) according to one embodiment may include a processor (100), a display (110), an internal memory (120), a communication module (130), a memory module (140), and a memory controller (105). The electronic device (10) of FIG. 1 may correspond, for example, to the electronic device (601) of FIG. 6. The configurations of the electronic device (10) described below with reference to FIG. 1 are merely examples, and the embodiments of the present disclosure are not limited thereto. For example, the electronic device (10) may not include at least some of the configurations illustrated in FIG. 1 (e.g., the communication module (130) of FIG. 1). For example, the electronic device (10) may further include other configurations (e.g., the configuration of the electronic device (601) of FIG. 6) in addition to the configurations illustrated in FIG. 1.

[0018] According to one embodiment, the processor (100) may be electrically or operatively connected to a display (110), internal memory (120), a communication module (130), a memory module (140), and a memory controller (105). The term "operatively connected" between components may mean that the components are functionally connected or communicatively connected. For example, operatively connected components may exchange data with each other.

[0019] According to one embodiment, the processor (100) can control various components constituting the electronic device (10). The processor (100) can execute instructions stored in the internal memory (120). For example, the processor (100) can update the software of the electronic device (10) and update the defect improvement table of the memory module (140) based on the software update of the electronic device (10). In addition, the processor (100) can perform a defect detection test on the memory module (140) when an error occurs in the operation of the memory module (140). In one example, the processor (100) can correspond to the processor (620) of FIG. 6. In one example, the defect improvement table can include error improvement data for the memory module (140).

[0020] According to one embodiment, the display (110) can display images and / or videos. The display (110) can include a plurality of pixels and wiring for driving each pixel. In one example, the processor (100) can display a UI on the display (110) based on the operation of the memory module (140). For example, if an error occurs in the operation of the memory module (140), the processor (100) can perform a defect detection test on the memory module (140), and based on the defect detection test result, the processor (100) can display a UI corresponding to improvement of defects in the memory module (140), a repair notification for the memory module (140), or a notification to induce a visit to a service center on the display (110). In one example, the UI can display information on service centers that can repair the memory module (140). For example, the URL and address information of a nearby service center that can repair the memory module (140) displayed on the display (110) can be included.

[0021] According to one embodiment, the internal memory (120) may store instructions executed by the processor (100). For example, the memory (120) may at least temporarily store data corresponding to a failure improvement table for the memory module (140) received from an external electronic device or a network. At this time, the data corresponding to the failure improvement table for the memory module (140) may be stored together with data including at least one of the manufacturing date of the memory module (140), a failure type, an error area, a certain log record, or an improvement plan. In one example, the log record of the memory module (140) may include information that can identify an error area of ​​the memory module (140).

[0022] According to one embodiment, the communication module (130) may receive data corresponding to a defect improvement table for the memory module (140) from an external server device. In one example, the processor (100) may use the communication module (130) to transmit and receive data with an external electronic device or an external server device, and may transmit data corresponding to a defect detection test result to the external electronic device or the external server device. For example, the processor (100) may use the communication module (130) to receive data for a software update from an external device or an external server device, and may update the defect improvement table for the memory module (140) based on the received data.

[0023] According to one embodiment, when an error occurs in the operation of the memory module (140), the processor (100) may perform a defect detection test on the memory module (140) and transmit the defect detection test result to an external device or an external server device. In one example, the error improvement data that may be included in the defect improvement table may be divided into first error improvement data received by the processor (100) and second error improvement data transmitted by the processor (100).

[0024] According to one embodiment, the memory module (140) may be operatively connected to the processor (100) and / or the memory controller (105) to transmit and receive data. The memory module (140) may receive a control signal from the processor (100) and / or the memory controller (105) and perform an operation (e.g., a defect detection test operation and / or a defect improvement operation) based on the received control signal. For example, the control signal may refer to a signal generated by the processor (100) of the electronic device (10) loading at least a portion of data of a boot loader area using the internal memory (120). In one example, the control signal may refer to a signal generated by the processor (100) loading and executing a boot loader program stored in the internal memory (120).

[0025] According to one embodiment, the memory module (140) may be a DRAM module including at least one DRAM chip or including at least one DRAM package. In one example, the memory module (140) may include at least one memory selected from the group consisting of Static RAM (SRAM), Synchronous DRAM (SDRAM), Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable and Programmable ROM (EEPROM), flash memory, Phase-change RAM (PRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), and Ferroelectric RAM (FRAM). In one example, the memory module (140) may include a memory cell array, an address register, a plurality of anti-fuses, a repair address latch unit, and / or a repair control circuit. A detailed description of components included in the memory module (140) will be described below with reference to FIG. 2.

[0026] According to one embodiment, the memory controller (105) may be connected to and operate with at least one memory. For example, the processor (100) may transmit a test signal (e.g., a test command) to the memory module (140) to detect whether the memory module (140) is defective using the memory controller (105). In one example, the memory controller (105) may store one or more instructions to generate a defective improvement signal corresponding to data associated with at least one defective memory cell based on a command of the processor (100) and transmit the generated defective improvement signal to the memory module (140).

[0027] FIG. 2 is a block diagram showing the configuration of an application processor (AP) and a memory module according to one embodiment.

[0028] Referring to FIG. 2, an electronic device (10) according to one embodiment may include an AP and a memory module (221). The AP (201) may include a memory controller (203), and the memory module (221) may include a column decoder (223), a data buffer (224), a sense amplifier (225), a row decoder (227), and a memory array (229). In one example, the AP (201), the memory controller (203), and the memory module (221) may correspond to the processor (100), the memory controller (105), and the memory module (140) of FIG. 1.

[0029] According to one embodiment, the AP (201) and the memory module (221) may be electrically or operatively connected. The AP (201) may transmit commands and address information of memory cells to the memory module (221) using a command line (CMD), and may exchange read and write data using a data bus (DATA). In one example, the memory cell may correspond to a basic unit configuration of the memory array (229). The memory cell may include one or more transistors (235) and one or more capacitors (237), and a gate of the transistor (235) may be controlled through a word line (233), and a source of the transistor (235) may be controlled through a bit line (231). For example, the memory cell may control the transistor (235) based on power corresponding to each of the bit line (231) and the word line (233).

[0030] According to one embodiment, the AP (201) may transmit a command to the memory module (221) to disable at least a portion of the memory module (221). For example, the AP (201) may identify an error for at least a portion of the memory module (221) and transmit bit data corresponding to address information of a memory cell in which an error has occurred to the memory module (221) using the memory controller (203). In one example, the AP (201) and the memory module (221) may be configured in a three-dimensional POP (package of package) structure in which the package of the memory module (221) is placed on top of the AP (201) package to improve signal integrity and increase integration.

[0031] According to one embodiment, the memory controller (203) may transmit commands received from an external source (e.g., AP (201)) to the memory module (221). For example, the memory controller (203) may generate a command to deactivate at least a portion of an identified memory cell based on address information of the identified memory cell in the AP (201), and transmit the generated command to the memory module (221). In one example, the memory controller (203) may transmit a command to change at least one data path setting of the memory module (221) to the memory module (221). In one example, the data path setting may determine the order of data transmission and processing within the memory module (221) and the processing of commands received from the AP (201).

[0032] According to one embodiment, the memory controller (203) can change the signal timing of at least one data path of the memory module (221). For example, the memory controller (203) can be configured to push or pull the timing of generation, transmission, or transmission / reception of a signal corresponding to at least one data path of the memory module (221). For example, the memory controller (203) can modify the signal timing to improve the delay of a signal corresponding to at least one data path of the memory module (221).

[0033] According to one embodiment, the memory module (221) may be divided into a peripheral region and a core. For example, the peripheral region may be referred to as a region other than the core, which includes a circuit region for controlling memory cell addresses, command signals, and data input / output.

[0034] According to one embodiment, the memory module (221) may be configured to perform a remedial operation under the control of the memory controller (203) on a defective memory cell derived as a result of a test operation performed by the AP (201). For example, if a first memory cell is determined to be defective, when an access request is made to the first memory cell, the semiconductor memory module (221) may block access to the defective memory cell by avoiding an address corresponding to the first memory cell to an address corresponding to a second memory cell.

[0035] According to one embodiment, the address information of the memory cell may be distinguished based on the die, the chip selection (CS), the channel, the bank group (BG), the bank (BA), and the row / column of the memory array (229). In one example, one or more dies may be included within the memory module (221). For example, for a memory module (221) corresponding to 8 GB (gigabyte), when a die corresponding to 16 Gb (gigabit) is used, four dies may be included based on the calculation formula of 8 GB * 8 Gb / GB = 64 Gb = 16 Gb / 1 die * 4 die.

[0036] According to one embodiment, the dies may be distinguished by channel, and when the number of dies is large, the dies may be grouped by CS. In one example, when the number of dies is four, the dies may be distinguished by channel, and may be identified as Ch A, Ch B, Ch C, and Ch D, respectively. In one example, when the number of dies is eight, the four channels may be grouped into CS0 and CS1, respectively, and may be identified as ch A, ch B, ch C, ch D of CS0 and ch A, ch B, ch C, ch D of CS1. In one example, the memory cell address information of the memory module (221) may include information indicating at least one of CS, Ch, BG, BA, and row / column of the memory array (229). In one example, the cell location information of the memory module (221) is classified according to the CS, BG, BA, and row / column of the memory array (229), and the information of the classified CS, BG, BA, and row / column of the memory array (229) can be usefully used as information for identifying the location of a defective memory cell of the memory module (221).

[0037] According to one embodiment, the column decoder (223), data buffer (224), sense amplifier (225), row decoder (227), and memory array (229) are components belonging to the core area of ​​the memory module (221), and perform reading and writing of data, amplification and restoration of data signals, and interpretation of row and column addresses of memory cells. For example, the column decoder (223) can be used to select and read or write data according to the column address of the memory array (229), the data buffer (224) can temporarily store data transmitted and received between the AP (201) and the memory module (221), the sense amplifier (225) can amplify data transmitted and received in response to the data buffer (224) or data read from a memory cell, restore it to the data path, and perform a read operation, and the row decoder (227) can be used to interpret the row address of the memory array (229) and access a selected row based on a request from the AP (201). The memory array (229) is a collection of memory cells, and the AP (201) can access a memory cell of a desired address through the column decoder (223) and the row decoder (227).

[0038] According to one embodiment, the memory cell of the memory module (221) may include a kernel panic, a system hang, a system power off, a random defect failure (RDF), a signal timing failure, or memory cell damage as a type of defect. In one example, an RDF may include a defect of a defect nature that occurs during the process, a defect that is not detected during the manufacturing stage of the memory module (140) but is detected during the user's use stage, a memory cell failure, a sense amplifier (225) failure, or a data input / output failure. In one example, a signal timing failure may include a defect in which a transmitted or received signal is transmitted or generated faster or slower than a set time. In one example, a memory cell damage may include a defect that occurs when a rank indicating at least one of a part of a memory module (221) or a data group is destroyed when a physical shock is applied to the memory module (221). For example, the memory cell damage may include a Ch A failure of CS0 or a Ch D failure of the first rank (rank1).

[0039] Figures 3a to 3c are flowcharts illustrating the operation of an electronic device according to one embodiment.

[0040] Referring to FIG. 3A, the processor (100) of the electronic device (10) according to one embodiment receives a defect improvement table of the memory module (140), and when an abnormality occurs during the operation of the memory module (140), performs a defect detection test of the memory module (140), and then performs a defect improvement operation of the memory module (140) or displays a UI based on the result of comparing the defect improvement table with the defect detection test.

[0041] According to one embodiment, in operation 301, when performing a software update from an external device or an external server device, the processor (100) may receive a failure improvement table of the memory module (140) and update a previously received failure improvement table of the memory module (140). In one example, the processor may receive data on the failure improvement table of the memory module (140) from the external device or the external server device, and the processor (100) may record the received data on the failure improvement table of the memory module (140) in a memory module quantity improvement table that the processor (100) currently stores. In one example, the operation of receiving data on the failure improvement table of the memory module (140) from the external device or the external server device may be performed together with a software update operation of the memory module (140). For example, the processor (100) may be configured to receive update data for updating the first error improvement data from the external device or the external server device using the communication module (130). In one example, the processor (100) may receive an updated defect improvement table from an external device or an external server device in operation 301.

[0042] According to one embodiment, the processor (100) may determine whether an error has occurred during the operation of the memory module (140) in operation 303. In one example, if an error has occurred during the operation of the memory module (140) (e.g., yes in operation 303), the processor (100) may perform a defect detection test on the memory module (140). In addition, if no error has occurred during the operation of the memory module (140) (e.g., no in operation 303), the processor (100) may determine that there is no abnormality in the memory module (140) and terminate the defect improvement process for the memory module (140). For example, an error occurring during the operation of the memory module (140) may include a kernel panic phenomenon in which the system of the electronic device (10) is abnormally terminated or rebooted, a system hang phenomenon in which the system of the electronic device (10) does not respond or stops operating, and a power-off phenomenon of the electronic device (10).

[0043] According to one embodiment, in operation 303, if no error occurs during the operation of the memory module (140) (e.g., NO in operation 303), the processor (100) may not perform a failure improvement process for the memory module (140) until it receives update data for updating the error improvement data from an external device or an external server device. In one example, the processor (100) may not perform a failure improvement process for the memory module (140) until an error occurs during the operation of the memory module (140).

[0044] According to one embodiment, in operation 305, when an error occurs during the operation of the memory module (140) (e.g., the example of operation 303), the processor (100) may perform a failure detection test of the memory module (140), and, based on the result of the failure detection test, identify a log record corresponding to the failure of the memory module (140). For example, the log record corresponding to the failure of the memory module (140) may include information about an address of a memory cell, a data usage record, or data changes. In one example, the processor (100) may reboot the electronic device (10) for the failure detection test of the memory module (140).

[0045] According to one embodiment, the processor (100) may, at operation 307, compare the memory module (140) with the failure improvement table to determine whether a failure type corresponding to the memory module (140) exists in the failure improvement table. In one example, if the failure type corresponding to the memory module (140) exists in the failure improvement table (e.g., YES in operation 307), the processor may perform a failure improvement operation on the memory module (140) based on the failure improvement table. In addition, if the failure type corresponding to the memory module (140) does not exist in the failure improvement table (e.g., NO in operation 307), the processor may display a UI regarding the current status and processing method of the memory module (140). In one example, the failure improvement table may correspond to error improvement data for improving a failure of the memory module (140) and may be received from an external electronic device or an external server device. For example, the error improvement data may include a log record of the memory module (140) and memory module operation control data corresponding to the manufacturing time of the memory module (140).

[0046] According to one embodiment, the processor (100) may perform a fault improvement operation of the memory module (140) based on a result of the fault improvement table in operation 309 if a fault type corresponding to the memory module (140) exists in the fault improvement table (e.g., the example of operation 307). In one example, the fault improvement table may include information about the production week of the memory module, target log records, and improvement measures, and the processor (100) may identify a fault improvement measure in the fault improvement table based on the manufacturing time and log records of the memory module (140) where an error occurred. For example, if the manufacturing date of the memory module (140) in which an error occurred is the first week of January 23rd and the log record of 100101 is identified as a result of a defect detection test for the memory module (140), the processor (100) can identify a defect improvement plan corresponding to the first week of January 23rd and the log record of 100101 in the defect improvement table and control the operation of the memory module (140) according to the identified defect improvement plan.

[0047] According to one embodiment, the failure improvement method may include a method of designating at least a portion of the memory module (140) as an inactive area and not using it. In addition, the failure improvement method may include a method of changing a data path of the memory module (140) and a method of changing a signal generation time to improve signal delay. In one example, when the processor (100) controls the memory module (140) based on the failure improvement method, the processor (100) may display a UI based on the capacity of the available memory module (140). For example, when the size of an inactive area among some areas of the memory module (140) based on the failure improvement method is greater than a reference size, the processor (100) may display a UI notifying that the capacity of the memory module (140) may be reduced.

[0048] According to one embodiment, the processor (100) may designate a defective memory cell as a prohibited area for a defect in the memory cell and may set the designated defective memory cell not to be used. For example, if the number of defective memory cell areas is less than or equal to a certain number, the processor (100) may set the defective memory cell not to be used, and if the number of defective memory cell areas exceeds a certain number, the processor (100) may set the defective memory cell not to be used, and then generate data notifying the user that the capacity of the memory module (140) may be reduced. In one example, the processor (100) may control the timing setting of a signal corresponding to a defect corresponding to a signal logic. For example, the processor (100) may slow down or speed up the generation or transmission timing of a signal corresponding to a defect.

[0049] According to one embodiment, if the type of defect corresponding to the memory module (140) does not exist in the defect improvement table in operation 311 (e.g., NO in operation 307), the processor (100) may determine that there is no defect improvement method for the memory module (140) through the processor (100) and display a UI regarding the current status and processing method of the memory module (140). For example, the processor (100) may output a UI on the display (110) that prompts a repair notification for the memory module (140) or a visit to a service center.

[0050] According to one embodiment, a processor (100) of an electronic device (10) may obtain first error improvement data regarding a memory module (140), identify an error for at least a portion of an area of ​​the memory module (140), identify an error area of ​​the memory module (140) and a manufacturing time of the memory module (140) based on the identification of the error, and control the operation of the memory module (140) based on memory module operation control data identified from the first error improvement data, and the memory module operation control data may correspond to the error area of ​​the memory module (140) and the manufacturing time of the memory module (140).

[0051] A method of an electronic device (10) according to one embodiment may include an operation of obtaining first error improvement data regarding a memory module (140), an operation of identifying an error for at least a portion of an area of ​​the memory module (140), an operation of identifying an error area of ​​the memory module (140) and a manufacturing time of the memory module (140) based on the identification of the error, and an operation of controlling an operation of the memory module (140) based on memory module operation control data identified from the first error improvement data, wherein the memory module operation control data may correspond to an error area of ​​the memory module (140) and a manufacturing time of the memory module (140).

[0052] A non-transitory computer-readable recording medium storing instructions according to one embodiment of the present invention is configured such that when the instructions are executed by a processor (100), the processor (100) obtains first error improvement data regarding a memory module (140), identifies an error for at least a portion of an area of ​​the memory module (140), and based on the identification of the error, identifies an error area of ​​the memory module (140) and a manufacturing time of the memory module (140), and controls the operation of the memory module (140) based on memory module operation control data identified from the first error improvement data, and the memory module operation control data may correspond to the error area of ​​the memory module (140) and the manufacturing time of the memory module (140).

[0053] Referring to FIG. 3B, the processor (100) of the electronic device (10) according to one embodiment may, in addition to the operation of FIG. 3A, determine whether a partial area of ​​the memory module (140) can be temporarily used by disabling the area when a failure type corresponding to the memory module (140) does not exist in the failure improvement table, and may be set to perform a failure improvement operation or display a UI based on the temporary usability of the memory module (140). In one example, operations 301 to 311 of FIG. 3A may correspond to operations 321 to 327, operations 333, and 335 of FIG. 3B. Hereinafter, operations 329, 331, and 333, which are characteristic operations of FIG. 3B, will be described.

[0054] According to one embodiment, the processor (100) may determine whether the memory module (140) can be temporarily used by disabling a portion of the memory module (140) if the failure type corresponding to the memory module (140) does not exist in the failure improvement table (e.g., No in operation 327) at operation 329. In one example, if temporary use is possible by disabling a portion of the memory module (140) (e.g., Yes in operation 329), the processor (100) may disable a portion of the memory module (140) and output a UI indicating that temporary use is possible. In addition, if temporary use is not possible even if a portion of the memory module (140) is disabled (e.g., No in operation 329), the processor (100) may output a UI that notifies the user of a repair request for the memory module (140) or prompts a visit to a service center.

[0055] According to one embodiment, in operation 329, if the failure type corresponding to the memory module (140) does not exist in the failure improvement table (e.g., NO in operation 327), the processor (100) may determine whether the failure of the memory module (140) can be improved by disabling some areas of the memory module (140). For example, even if the failure improvement plan corresponding to the memory module (140) where a failure has occurred does not exist in the failure improvement table, the processor (100) may independently disable some areas of the memory module (140) and then determine whether the failure of the memory module (140) can be improved by disabling some areas. In one example, the failure improvement plan independently determined by the processor (100) may include a method of changing a data path of the memory module (140) and a method of changing a signal generation time.

[0056] According to one embodiment, in operation 331, if a partial area of ​​the memory module (140) is disabled to allow temporary use (e.g., an example of operation 329), the processor (100) may determine that there is a memory module (140) improvement plan that is not present in the defect improvement table but can be used by the processor (100), and may disable a partial area of ​​the memory module (140) and output a UI that notifies the user of the possibility of temporary use. For example, if the processor (100) determines that the temporary use of the memory module (140) is possible by disabling a memory cell corresponding to a first row of a memory array (e.g., 229 of FIG. 2) of the memory module (140), the processor (100) may, after disabling the memory cell corresponding to the first row, display a UI that guides the possibility of temporary use of the memory module (140) on the display (110).

[0057] According to one embodiment, the processor (100) may output a UI that guides the user to visit a repair or service center for the memory module (140) at operation 333. In one example, after disabling some areas of some memory modules (140) at operation 331, the processor (100) may display a UI regarding the current status and processing method of the memory module (140) in addition to a UI that guides the temporary availability of the memory module (140) on the display (110). In one example, if the temporary availability of the memory module (140) is not possible even after disabling some areas of the memory module (140) (e.g., No in operation 329), the processor (100) may determine that there is no method to improve the defect of the memory module (140) through the processor (100), and may display a UI regarding the current status and processing method of the memory module (140). For example, the processor (100) may output a UI that induces a visit to a repair or service center for the memory module (140) so that the entire capacity of the memory module (140) can be used, or if temporary use is impossible, a part of the memory module (140) may be disabled so that temporary use is possible.

[0058] According to one embodiment, if a failure type corresponding to a memory module (140) does not exist in the failure improvement table, the processor (100) may determine whether temporary use is possible by disabling a portion of the memory module (140). In one example, if a failure type of die damage is not included in the failure improvement table, the processor (100) may set the defective die as a prohibited area. At this time, the processor (100) may determine whether temporary use of the memory module (140) is possible by setting the defective die as a prohibited area. In one example, if the failure improvement table does not include information on a failure type of a bank, rank, or portion of an area of ​​the memory module (140), the processor (100) may set a defective bank, rank, or portion of an area of ​​the memory module (140) as a prohibited area. At this time, the processor (100) can determine whether temporary use of the memory module (140) is possible by setting a defective bank, rank, or some area unit of the memory module (140) as a prohibited area. In one example, the processor (100) can set a defective area as a prohibited area in response to a defect in some area unit of the memory module (140), such as a defective die, bank, or rank, and perform a defect detection test on the memory module (140) after setting the prohibited area.

[0059] According to one embodiment, the processor (100) of the electronic device (10) may be set to disable at least a portion of the memory module (140) based on the error area of ​​the memory module (140), if the memory module operation control data corresponding to the error area of ​​the memory module (140) and the manufacturing time of the memory module (140) are not identified from the first error improvement data.

[0060] A method of an electronic device (10) according to one embodiment may include an operation of disabling at least a portion of a memory module (140) based on an error area of ​​the memory module (140), if memory module operation control data corresponding to an error area of ​​the memory module (140) and a manufacturing time of the memory module (140) are not identified from the first error improvement data.

[0061] A non-transitory computer-readable recording medium storing instructions according to one embodiment may be configured to, when the instructions are executed by the processor (100), cause the processor (100) to disable at least a portion of the memory module (140) based on the error area of ​​the memory module (140), if memory module operation control data corresponding to the error area of ​​the memory module (140) and the manufacturing time of the memory module (140) are not identified from the first error improvement data.

[0062] Referring to FIG. 3C, the processor (100) of the electronic device (10) according to one embodiment may be configured to report, in addition to the operation of FIG. 3B, information related to the defect improvement operation of the memory module (140) performed by the processor (100) to an external device or an external server device. In one example, operations 321 to 335 of FIG. 3B may correspond to operations 341 to 355 of FIG. 3C. Hereinafter, operation 357, which is a characteristic operation of FIG. 3C, will be described.

[0063] According to one embodiment, if there is a failure improvement plan corresponding to a memory module (140) in which a failure has occurred in the received failure improvement table (e.g., example 347), the processor (100) may perform a failure improvement operation on the memory module (140) based on the failure improvement table and transmit data related to the failure improvement (e.g., log records of the memory module (140) and the manufacturing date of the memory module (140)) to an external device and an external server device. For example, after the processor (100) performs the failure improvement operation on the memory module (140) based on the failure improvement table, the processor (100) may transmit data including the log records used to identify memory operation data in the failure improvement table and the manufacturing date of the memory module (140) to the external device and the external server device in order to update the failure improvement table. In one example, the failure improvement table received by the processor (100) may correspond to first error improvement data, and the failure improvement-related data that the processor (100) transmits to the external device and the external server device may correspond to second error improvement data.

[0064] According to one embodiment, if there is no failure improvement plan corresponding to the memory module (140) in which a failure has occurred in the received failure improvement table (e.g., No of 347), the processor (100) may determine whether the memory module (140) is temporarily usable based on an operation of deactivating a portion of the memory module (140), and may transmit data related to the determination result of the temporary usability (e.g., whether temporary usability is possible, a log record of the memory module (140), and the manufacturing date of the memory module (140)) to the external device and the external server device. For example, even if the processor (100) cannot identify memory control data corresponding to the memory module (140) in which a failure has occurred in the previously received failure improvement table, the processor (100) may transmit data including the memory module (140) control operation performed by the processor (100) itself and the memory cell deactivation area that enables at least temporary use of the memory module (140) to the external device and the external server device in order to update the failure improvement table.

[0065] According to one embodiment, the processor (100) may provide a UI for the user to select whether to transmit failure improvement data to an external device and an external server device. In one example, even if a failure improvement plan corresponding to a memory module (140) in which a failure has occurred does not exist in the failure improvement table, the processor (100) may independently deactivate some areas of the memory module (140) and then improve the failure of the memory module (140) by deactivating some areas, and may display a UI that prompts the user to decide whether to report the results of the failure improvement plan performed by the processor (100) to an external electronic device or an external server device. For example, the processor (100) may display a UI on the display (110) that prompts the user to decide whether to report data on a log record used in a failure improvement operation of the memory module (140), the manufacturing date of the memory module (140), whether it is temporarily available, or a memory cell deactivation area that enables at least temporary use of the memory module (140) to an external electronic device or an external server device.

[0066] An electronic device (10) according to one embodiment further includes a communication module (130), and the processor (100) may be configured to receive update data for updating first error improvement data using the communication module (130).

[0067] A method of an electronic device (10) according to one embodiment may include an operation of receiving update data for updating first error improvement data.

[0068] A non-transitory computer-readable recording medium storing instructions according to one embodiment may be configured such that when the instructions are executed by the processor (100), the processor (100) receives update data for updating the first error improvement data.

[0069] An electronic device (10) according to one embodiment may further include a communication module (130), and the processor (100) may be configured to generate second error improvement data including information on a deactivated area of ​​a memory module (140) and manufacturing date information of the memory module (140), and transmit the second error improvement data to an external server device using the communication module (130).

[0070] A method of an electronic device (10) according to one embodiment may include an operation of generating second error improvement data including information about a deactivated area of ​​a memory module (140) and manufacturing date information of the memory module (140), and an operation of transmitting the second error improvement data to an external server device.

[0071] FIG. 4 illustrates a memory module failure improvement table according to one embodiment.

[0072] Referring to FIG. 4, the processor (100) of the electronic device (10) according to one embodiment may identify an improvement plan for a memory module (140) in which a defect has occurred by referring to the production week, defect type, and log record data included in the defect improvement table (40) in order to perform a defect improvement operation for the memory module (140). The data included in the defect improvement table (40) may correspond to first error improvement data.

[0073] In one embodiment, the manufacturing date may correspond to a production week code, and if two different memory modules have the same production week code, the two memory modules may correspond to memory modules produced in the same production week code. In one example, the manufacturing date included in the defect improvement table (40) may be replaced with data on the production region, production plant, or production facility of the memory module, as information for determining whether the memory modules correspond to the same manufacturing process.

[0074] In one embodiment, the failure type may correspond to identification information regarding a failure type occurring in the memory module (140). In one example, the internal failure type of the memory module (140) may include a kernel panic, a system hang, a system power-off, a random defect failure (RDF), a signal delay, or memory cell damage. For example, the failure improvement table (40) may record a failure type of a signal delay for a memory module (140) produced in the second week of January 23.

[0075] According to one embodiment, the log record may include information about the address of the memory cell where reading or writing was performed, the data usage record of the memory module (140), or the data change, and the processor (100) may identify the type of defect of the memory module (140) by comparing the log record of the memory module (140) alone with the log record of the memory module (140) in which a defect has occurred, but may identify the type of defect of the memory module (140) by comparing the log record recorded in the defect improvement table (40). For example, when a defect occurs during the operation of the memory module (140), the processor (100) may identify the manufacturing date and log record of the memory module (140), and compare the manufacturing date and log record identified with the defect improvement table (40) to find out the type of defect and improvement plan of the memory module (140). In one example, the log record of the memory module (140) may include information that can identify an error area of ​​the memory module (140).

[0076] According to one embodiment, the improvement method may include data on a method of controlling the memory module (140) corresponding to a failure type of the memory module (140). In one example, the improvement method recorded in the failure improvement table (40) may include at least one of address information of a memory cell, data path allocation information, or signal generation timing information. In one example, the data path allocation information may include information for changing a line through which data is transmitted in the memory module (140) or for changing a command processing order, and the signal generation timing information may include information for adjusting the generation timing of a signal used for data processing in the memory module (140) or for adjusting the timing at which data is stored in a register or a buffer. For example, the address information of the memory cell in the failure improvement table (40) may include information indicating at least one of a CS (chip selection), a Ch (channel), a BG (bank group), a BA (bank), a row, and a column. In one example, the address information of the memory cell may include information on a rank indicating at least one of the data groups. For example, the improvement plan of the defect improvement table (40) may include information indicating the deactivation of a memory area where CS=00, Ch=01, BG=11, BA=01, row=0110, column=all. In this case, the improvement plan may correspond to a method of indicating the deactivation of a memory area where CS=00, Ch=01, BG=11, BA=01, row=0110, column=all. In one example, multiple defect types, log records, or improvement plans may be recorded in the defect improvement table (40) corresponding to one manufacturing period.

[0077] According to one embodiment, the processor (100) may perform a defect improvement operation of the memory module (140) by comparing the manufacturing date and log record of the memory module (140) with the defect improvement table (40). For example, the processor (100) may perform a defect detection test on the memory module (140), identify the manufacturing date of the memory module (140) as the 3rd week of January 23, identify that 011010 is included as the log record of the memory module (140), and then confirm the defect type of the memory module (140) as memory cell damage based on the defect improvement table (40), and improve the defect of the memory module (140) by disabling the memory area in which CS=01, Ch=00, BG=10, BA=10, row=0100, and column=1000~1010 are among the memory areas of the memory module (140). In one example, the operation of the processor (100) to improve a defect of the memory module (140) may be performed by transmitting memory module control data to the memory module (140). In one example, the memory module control data may include a memory module defect processing method. For example, the memory module operation control data may include a command to deactivate a memory area of ​​the memory module (140) in which CS=01, Ch=00, BG=10, BA=10, row=0100, and column=1000~1010. In one example, memory cell damage may correspond to damage to a defective area corresponding to the addresses of CS and Ch in response to a die crack. The memory module operation control data may include a command to deactivate a memory area of ​​the memory module (140) in which CS=01, Ch=00.

[0078] According to one embodiment, the processor (100) may compare the manufacturing date and log record of the memory module (140) with the defect improvement table (40), and if there is no improvement plan corresponding to the defective memory module (140) in the defect improvement table (40), the processor (100) may transmit the manufacturing date and log record of the memory module (140) to an external device and an external electronic device. For example, the processor (100) may transmit the manufacturing date and log record of the memory module (140) to an external device and an external electronic device together with information that there is no improvement plan corresponding to the defective memory module (140) in order to supplement the data included in the defect improvement table (40).

[0079] According to one embodiment, when the processor (100) determines that at least temporary use of the defective memory module (140) is possible by controlling a portion of the memory module (140), the processor may transmit the portion of the memory module (140) controlled by the processor, information indicating that temporary use is possible, the manufacturing date of the memory module (140), and a log record to an external device and an external electronic device. For example, when the processor (100) determines that at least temporary use of the defective memory module (140) is possible by changing the data path order of the memory module (140), the processor may transmit the log record and manufacturing date information of the memory module (140) corresponding to the self-failure improvement of the memory module (140) to the external device and an external electronic device. In one example, the data that the processor (100) transmits to supplement the fault improvement table (40) may correspond to the second error improvement data.

[0080] The first error improvement data included in the defect improvement table (40) according to one embodiment may include memory module operation control data corresponding to the error area of ​​the memory module (140) and the manufacturing time of the memory module (140).

[0081] The memory module operation control data included in the failure improvement table (40) according to one embodiment may include a memory module failure handling method corresponding to at least one of RDF, signal delay failure, or hardware damage regarding the memory module (140).

[0082] According to one embodiment, the processor (100) of the electronic device (10) can disable at least one area of ​​the memory module (140) or change at least one data path setting of the memory module (140) based on memory module operation control data.

[0083] A method of an electronic device (10) according to one embodiment may include an operation of disabling at least one area of ​​a memory module (140) or changing at least one data path setting of the memory module (140) based on memory module operation control data.

[0084] A non-transitory computer-readable recording medium storing instructions according to one embodiment of the present invention may, when the instructions are executed by the processor (100), cause the processor (100) to disable at least one area of ​​the memory module (140) or change at least one data path setting of the memory module (140) based on memory module operation control data.

[0085] FIG. 5 illustrates a UI displayed on a display according to one embodiment when operation 351 or operation 353 of FIG. 2 is performed.

[0086] Referring to FIG. 5, the processor (100) of the electronic device (10) according to one embodiment may output a UI regarding improvement of a defect in a memory module (140). In one example, the processor (100) may identify an improvement plan for a defective memory module (140) based on a defect improvement table (e.g., 40 of FIG. 4), and if the capacity of the memory module (140) may be reduced when the improvement plan is applied, the processor (100) may output a UI informing the user that the capacity may be reduced. In one example, if the processor (100) cannot identify an improvement plan for a defective memory module (140) from the defect improvement table (e.g., 40 of FIG. 4), the processor (100) may output a UI on the display (110) that notifies the user of a repair request for the memory module (140) or a visit to a service center. In one example, the processor (100) may, through an operation of disabling a portion of the memory module (140), output a UI on the display (110) that notifies the memory module (140) that it is temporarily usable, along with information that temporary use is possible, and that repairs are required for the memory module (140) or that a visit to a service center is recommended. In one example, the UI may also display information on service centers capable of repairing the memory module (140). For example, the information displayed on the display (110) may include at least one of location information, a URL of the service center, or address information of a nearby service center capable of repairing the memory module (140).

[0087] According to one embodiment, when the processor (100) controls the operation of the memory module (140), it may output a UI that prompts the user to select whether to transmit the operation control log record of the memory module (140) to an external device or an external server device. In one example, the operation control log record of the memory module (140) that the processor (100) transmits to the external device or the external server device may correspond to second error improvement data that may be recorded in a defect improvement table (e.g., 40 of FIG. 4).

[0088] An electronic device (10) according to one embodiment further includes a display (110), and the processor (100) is set to display a UI on the display (110) based on a result of comparing the first error improvement data with an error area of ​​the memory module (140) and the manufacturing date of the memory module (140), and the UI may include at least one of an available time, an available area, an available capacity, a repair requirement notification, or a service center visit inducing message of the memory module (140). In one example, the available time, the available area, or the available capacity of the memory module (140) may be calculated based on an available memory cell of the memory module (140) that has changed after the operation of the memory module (140) is controlled by the processor (100). For example, when the processor (100) deactivates at least a portion of the memory module (140) to improve a defect in the memory module (140), the processor (100) may calculate the activated area of ​​the memory module (140) and display information about the available time, available area, or available capacity of the memory module (140) on the display (110).

[0089] A method of an electronic device (10) according to one embodiment includes an operation of displaying a UI on a display (110) based on a result of comparing first error improvement data with an error area of ​​a memory module (140) and a manufacturing date of the memory module (140), and the UI may include at least one of an available time of the memory module (140), an available area, a repair requirement notification, or a message inducing a visit to a service center.

[0090] FIG. 6 is a block diagram of an electronic device within a network environment according to one embodiment.

[0091] Referring to FIG. 6, FIG. 6 is a block diagram of an electronic device (601) within a network environment (600) according to various embodiments. Referring to FIG. 6, in the network environment (600), the electronic device (601) may communicate with the electronic device (602) via a first network (698) (e.g., a short-range wireless communication network), or may communicate with at least one of the electronic device (604) or the server (608) via a second network (699) (e.g., a long-range wireless communication network). In one embodiment, the electronic device (601) may communicate with the electronic device (604) via the server (608). According to one embodiment, the electronic device (601) may include a processor (620), a memory (630), an input module (650), an audio output module (655), a display module (660), an audio module (670), a sensor module (676), an interface (677), a connection terminal (678), a haptic module (679), a camera module (680), a power management module (688), a battery (689), a communication module (690), a subscriber identification module (696), or an antenna module (697). In some embodiments, the electronic device (601) may omit at least one of these components (e.g., the connection terminal (678)), or may have one or more other components added. In some embodiments, some of these components (e.g., the sensor module (676), the camera module (680), or the antenna module (697)) may be integrated into one component (e.g., the display module (660)).

[0092] The processor (620) may, for example, execute software (e.g., a program (640)) to control at least one other component (e.g., a hardware or software component) of the electronic device (601) connected to the processor (620) and perform various data processing or operations. According to one embodiment, as at least a part of the data processing or operations, the processor (620) may store commands or data received from other components (e.g., a sensor module (676) or a communication module (690)) in a volatile memory (632), process the commands or data stored in the volatile memory (632), and store result data in a non-volatile memory (634). According to one embodiment, the processor (620) may include a main processor (621) (e.g., a central processing unit or an application processor) or an auxiliary processor (623) (e.g., a graphics processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor) that can operate independently or together with the main processor (621). For example, when the electronic device (601) includes the main processor (621) and the auxiliary processor (623), the auxiliary processor (623) may be configured to use less power than the main processor (621) or to be specialized for a given function. The auxiliary processor (623) may be implemented separately from the main processor (621) or as a part thereof.

[0093] The auxiliary processor (623) may control at least a portion of functions or states associated with at least one component (e.g., a display module (660), a sensor module (676), or a communication module (690)) of the electronic device (601), for example, on behalf of the main processor (621) while the main processor (621) is in an inactive (e.g., sleep) state, or together with the main processor (621) while the main processor (621) is in an active (e.g., application execution) state. In one embodiment, the auxiliary processor (623) (e.g., an image signal processor or a communication processor) may be implemented as a part of another functionally related component (e.g., a camera module (680) or a communication module (690)). In one embodiment, the auxiliary processor (623) (e.g., a neural network processing unit) may include a hardware structure specialized for processing artificial intelligence models. The artificial intelligence models may be generated through machine learning. This learning can be performed, for example, on the electronic device (601) itself where the artificial intelligence model is executed, or can be performed through a separate server (e.g., server (608)). The learning algorithm can include, for example, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning, but is not limited to the examples described above. The artificial intelligence model can include multiple artificial neural network layers.The artificial neural network may be one of a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but is not limited to the examples described above. In addition to, or alternatively to, a hardware structure, an artificial intelligence model may include a software structure.

[0094] The memory (630) can store various data used by at least one component (e.g., the processor (620) or the sensor module (676)) of the electronic device (601). The data can include, for example, software (e.g., the program (640)) and input data or output data for commands related thereto. The memory (630) can include a volatile memory (632) or a non-volatile memory (634).

[0095] The program (640) may be stored as software in the memory (630) and may include, for example, an operating system (642), middleware (644), or an application (646).

[0096] The input module (650) can receive commands or data to be used in a component of the electronic device (601) (e.g., a processor (620)) from an external source (e.g., a user) of the electronic device (601). The input module (650) can include, for example, a microphone, a mouse, a keyboard, a key (e.g., a button), or a digital pen (e.g., a stylus pen).

[0097] The audio output module (655) can output audio signals to the outside of the electronic device (601). The audio output module (655) can include, for example, a speaker or a receiver. The speaker can be used for general purposes, such as multimedia playback or recording playback. The receiver can be used to receive incoming calls. In one embodiment, the receiver can be implemented separately from the speaker or as part of the speaker.

[0098] The display module (660) can visually provide information to an external party (e.g., a user) of the electronic device (601). The display module (660) may include, for example, a display, a holographic device, or a projector and a control circuit for controlling the device. In one embodiment, the display module (660) may include a touch sensor configured to detect a touch, or a pressure sensor configured to measure the intensity of a force generated by the touch.

[0099] The audio module (670) can convert sound into an electrical signal, or vice versa, convert an electrical signal into sound. According to one embodiment, the audio module (670) can acquire sound through the input module (650), output sound through the sound output module (655), or an external electronic device (e.g., electronic device (602)) (e.g., speaker or headphone) directly or wirelessly connected to the electronic device (601).

[0100] The sensor module (676) can detect the operating status (e.g., power or temperature) of the electronic device (601) or the external environmental status (e.g., user status) and generate an electrical signal or data value corresponding to the detected status. According to one embodiment, the sensor module (676) can include, for example, a gesture sensor, a gyro sensor, a barometric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0101] The interface (677) may support one or more designated protocols that may be used to directly or wirelessly connect the electronic device (601) with an external electronic device (e.g., the electronic device (602)). In one embodiment, the interface (677) may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface.

[0102] The connection terminal (678) may include a connector through which the electronic device (601) may be physically connected to an external electronic device (e.g., the electronic device (602)). In one embodiment, the connection terminal (678) may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0103] The haptic module (679) can convert electrical signals into mechanical stimuli (e.g., vibration or movement) or electrical stimuli that a user can perceive through tactile or kinesthetic sensations. According to one embodiment, the haptic module (679) can include, for example, a motor, a piezoelectric element, or an electrical stimulation device.

[0104] The camera module (680) can capture still images and videos. According to one embodiment, the camera module (680) may include one or more lenses, image sensors, image signal processors, or flashes.

[0105] The power management module (688) can manage the power supplied to the electronic device (601). According to one embodiment, the power management module (688) can be implemented as, for example, at least a part of a power management integrated circuit (PMIC).

[0106] A battery (689) may power at least one component of the electronic device (601). In one embodiment, the battery (689) may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0107] The communication module (690) may support the establishment of a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device (601) and an external electronic device (e.g., electronic device (602), electronic device (604), or server (608)), and the performance of communication through the established communication channel. The communication module (690) may operate independently from the processor (620) (e.g., application processor) and may include one or more communication processors that support direct (e.g., wired) communication or wireless communication. According to one embodiment, the communication module (690) may include a wireless communication module (692) (e.g., a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module (694) (e.g., a local area network (LAN) communication module, or a power line communication module). Any of these communication modules may communicate with an external electronic device (604) via a first network (698) (e.g., a short-range communication network such as Bluetooth, wireless fidelity (WiFi) direct, or infrared data association (IrDA)) or a second network (699) (e.g., a long-range communication network such as a legacy cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (e.g., a LAN or WAN)). These various types of communication modules may be integrated into a single component (e.g., a single chip) or implemented as multiple separate components (e.g., multiple chips). The wireless communication module (692) may use subscriber information (e.g., an international mobile subscriber identity (IMSI)) stored in the subscriber identification module (696) to verify or authenticate the electronic device (601) within a communication network such as the first network (698) or the second network (699).

[0108] The wireless communication module (692) can support 5G networks and next-generation communication technologies following the 4G network, such as NR access technology (new radio access technology). The NR access technology can support high-speed transmission of high-capacity data (eMBB (enhanced mobile broadband)), minimization of terminal power and connection of multiple terminals (mMTC (massive machine type communications)), or high reliability and low latency (URLLC (ultra-reliable and low-latency communications)). The wireless communication module (692) can support, for example, a high-frequency band (e.g., mmWave band) to achieve a high data transmission rate. The wireless communication module (692) may support various technologies for securing performance in a high-frequency band, such as beamforming, massive multiple-input and multiple-output (MIMO), full dimensional MIMO (FD-MIMO), array antenna, analog beam-forming, or large scale antenna. The wireless communication module (692) may support various requirements specified in the electronic device (601), an external electronic device (e.g., the electronic device (604)), or a network system (e.g., the second network (699)). According to one embodiment, the wireless communication module (692) may support a peak data rate (e.g., 20 Gbps or more) for eMBB realization, a loss coverage (e.g., 164 dB or less) for mMTC realization, or a U-plane latency (e.g., 0.5 ms or less for downlink (DL) and uplink (UL), or 1 ms or less for round trip) for URLLC realization.

[0109] The antenna module (697) can transmit or receive signals or power to or from an external device (e.g., an external electronic device). In one embodiment, the antenna module (697) may include an antenna including a radiator formed of a conductor or a conductive pattern formed on a substrate (e.g., a PCB). In one embodiment, the antenna module (697) may include a plurality of antennas (e.g., an array antenna). In this case, at least one antenna suitable for a communication method used in a communication network, such as the first network (698) or the second network (699), may be selected from the plurality of antennas, for example, by the communication module (690). A signal or power may be transmitted or received between the communication module (690) and the external electronic device via the at least one selected antenna. In some embodiments, in addition to the radiator, another component (e.g., a radio frequency integrated circuit (RFIC)) may be additionally formed as a part of the antenna module (697).

[0110] According to various embodiments, the antenna module (697) may form a mmWave antenna module. In one embodiment, the mmWave antenna module may include a printed circuit board, an RFIC disposed on or adjacent a first side (e.g., a bottom side) of the printed circuit board and capable of supporting a designated high-frequency band (e.g., a mmWave band), and a plurality of antennas (e.g., an array antenna) disposed on or adjacent a second side (e.g., a top side or a side side) of the printed circuit board and capable of transmitting or receiving signals in the designated high-frequency band.

[0111] At least some of the above components can be interconnected and exchange signals (e.g., commands or data) with each other via a communication method between peripheral devices (e.g., a bus, GPIO (general purpose input and output), SPI (serial peripheral interface), or MIPI (mobile industry processor interface)).

[0112] According to one embodiment, commands or data may be transmitted or received between the electronic device (601) and an external electronic device (604) via a server (608) connected to a second network (699). Each of the external electronic devices (602 or 604) may be the same or a different type of device as the electronic device (601). According to one embodiment, all or part of the operations executed in the electronic device (601) may be executed in one or more of the external electronic devices (602, 604, or 608). For example, when the electronic device (601) is to perform a certain function or service automatically or in response to a request from a user or another device, the electronic device (601) may, instead of or in addition to executing the function or service itself, request one or more external electronic devices to perform the function or at least part of the service. One or more external electronic devices that receive the request may execute at least a portion of the requested function or service, or an additional function or service related to the request, and transmit the result of the execution to the electronic device (601). The electronic device (601) may process the result as is or additionally and provide it as at least a portion of a response to the request. For this purpose, cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technology may be used, for example. The electronic device (601) may provide an ultra-low latency service by using distributed computing or mobile edge computing, for example. In another embodiment, the external electronic device (604) may include an Internet of Things (IoT) device. The server (608) may be an intelligent server utilizing machine learning and / or a neural network. According to one embodiment, the external electronic device (604) or the server (608) may be included in the second network (699).The electronic device (601) can be applied to intelligent services (e.g., smart home, smart city, smart car, or healthcare) based on 5G communication technology and IoT-related technology.

[0113] Electronic devices according to the various embodiments disclosed in this document may take various forms. Electronic devices may include, for example, portable communication devices (e.g., smartphones), computer devices, portable multimedia devices, portable medical devices, cameras, wearable devices, or home appliances. Electronic devices according to the embodiments of this document are not limited to the aforementioned devices.

[0114] The various embodiments of this document and the terminology used therein are not intended to limit the technical features described in this document to specific embodiments, but should be understood to include various modifications, equivalents, or substitutes of the embodiments. In connection with the description of the drawings, similar reference numerals may be used for similar or related components. The singular form of a noun corresponding to an item may include one or more of the items, unless the context clearly indicates otherwise. In this document, each of the phrases "A or B", "at least one of A and B", "at least one of A or B", "A, B, or C", "at least one of A, B, and C", and "at least one of A, B, or C" can include any one of the items listed together in the corresponding phrase among those phrases, or all possible combinations thereof. Terms such as "first," "second," or "first" or "second" may be used merely to distinguish one component from another, and do not limit the components in any other respect (e.g., importance or order). When a component (e.g., a first component) is referred to as "coupled" or "connected" to another component (e.g., a second component), with or without the terms "functionally" or "communicatively," it means that the component can be connected to the other component directly (e.g., wired), wirelessly, or through a third component.

[0115] The term "module" used in various embodiments of this document may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with terms such as logic, logic block, component, or circuit. A module may be an integral component, or a minimum unit or part of such a component that performs one or more functions. For example, according to one embodiment, a module may be implemented in the form of an application-specific integrated circuit (ASIC).

[0116] Various embodiments of the present document may be implemented as software (e.g., a program (640)) including one or more instructions stored in a storage medium (e.g., an internal memory (636) or an external memory (638)) readable by a machine (e.g., an electronic device (601)). For example, a processor (e.g., a processor (620)) of the machine (e.g., an electronic device (601)) may call at least one instruction among the one or more instructions stored from the storage medium and execute it. This enables the machine to operate to perform at least one function according to the at least one called instruction. The one or more instructions may include code generated by a compiler or code executable by an interpreter. The machine-readable storage medium may be provided in the form of a non-transitory storage medium. Here, 'non-transitory' simply means that the storage medium is a tangible device and does not contain signals (e.g., electromagnetic waves), and the term does not distinguish between cases where data is stored semi-permanently or temporarily on the storage medium.

[0117] According to one embodiment, the method according to various embodiments disclosed in this document may be provided as included in a computer program product. The computer program product may be traded as a commodity between a seller and a buyer. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., compact disc read-only memory (CD-ROM)), or may be distributed online (e.g., downloaded or uploaded) via an application store (e.g., Play Store™) or directly between two user devices (e.g., smart phones). In the case of online distribution, at least a portion of the computer program product may be temporarily stored or temporarily generated in a machine-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or an intermediary server.

[0118] According to various embodiments, each component (e.g., a module or a program) of the above-described components may include one or more entities, and some of the entities may be separated and placed in other components. According to various embodiments, one or more components or operations of the aforementioned components may be omitted, or one or more other components or operations may be added. Alternatively or additionally, a plurality of components (e.g., a module or a program) may be integrated into a single component. In such a case, the integrated component may perform one or more functions of each of the plurality of components identically or similarly to those performed by the corresponding component among the plurality of components prior to the integration. According to various embodiments, the operations performed by a module, program, or other component may be executed sequentially, in parallel, iteratively, or heuristically, or one or more of the operations may be executed in a different order, omitted, or one or more other operations may be added.

Claims

1. In electronic devices, memory modules; and A processor electrically connected to the memory module, the processor comprising: Obtaining first error improvement data regarding the above memory module, Identifying errors in at least some areas of said memory module, Based on the identification of the above error, the error area of ​​the memory module and the manufacturing time of the memory module are identified, Controlling the operation of the memory module based on the memory module operation control data identified from the first error improvement data, The above memory module operation control data is an electronic device corresponding to an error area of ​​the memory module and the manufacturing date of the memory module.

2. In paragraph 1, Further comprising a communication circuit, An electronic device, wherein the processor is configured to receive update data for updating the first error improvement data using the communication circuit.

3. In paragraph 1, An electronic device, wherein the first error improvement data includes memory module operation control data corresponding to an error area of ​​the memory module and a manufacturing time of the memory module.

4. In paragraph 3, An electronic device, wherein the memory module operation control data includes a memory module failure handling method corresponding to at least one of a random defect failure (RDF), a signal delay failure, or hardware damage regarding the memory module.

5. In paragraph 1, An electronic device wherein the processor disables at least one area of ​​the memory module or changes at least one data path setting of the memory module based on the memory module operation control data.

6. In paragraph 1, An electronic device wherein the processor is set to disable at least a portion of the memory module based on an error area of ​​the memory module, based on a failure to identify an error area of ​​the memory module and memory module operation control data corresponding to a manufacturing time of the memory module from the first error improvement data.

7. In paragraph 6, Further comprising a communication circuit, The above processor: Generate second error improvement data including information about the disabled area and manufacturing date information of the memory module, An electronic device set to transmit the second error improvement data to an external server device using the communication circuit.

8. In paragraph 1, Including more displays, The processor is set to display a UI on the display based on a result of comparing the first error improvement data with the error area of ​​the memory module and the manufacturing date of the memory module. An electronic device, wherein the UI includes at least one of an available time of the memory module, an available area of ​​the memory module, or a repair notification.

9. In the method of an electronic device, An operation for obtaining first error improvement data regarding a memory module; An operation for identifying errors in at least a portion of said memory module; Based on the identification of the above error, an operation of identifying an error area of ​​the memory module and a manufacturing date of the memory module; and An operation for controlling the operation of the memory module based on the memory module operation control data identified from the first error improvement data, A method wherein the above memory module operation control data corresponds to an error area of ​​the memory module and a manufacturing time of the memory module.

10. In paragraph 9, A method further comprising the action of receiving update data for updating the first error improvement data.

11. In paragraph 9, A method wherein the first error improvement data includes memory module operation control data corresponding to an error area of ​​the memory module and a manufacturing time of the memory module.

12. In paragraph 11, The above memory module operation control data includes a memory module failure handling method corresponding to at least one of RDF, signal delay failure, or hardware damage regarding the memory module.

13. In paragraph 9, A method further comprising an operation of disabling at least one area of ​​the memory module or changing at least one data path setting of the memory module based on the memory module operation control data.

14. In paragraph 9, A method further comprising an operation of disabling at least a portion of the memory module based on the error area of ​​the memory module, if the memory module operation control data corresponding to the error area of ​​the memory module and the manufacturing time of the memory module are not identified from the first error improvement data.

15. In a non-transitory computer-readable recording medium storing instructions, When instructions are executed by a processor, the processor, Obtain the first error improvement data regarding the memory module, Identifying errors in at least some areas of said memory module, Based on the identification of the above error, the error area of ​​the memory module and the manufacturing date of the memory module are identified, Controlling the operation of the memory module based on the memory module operation control data identified from the first error improvement data, A non-transitory computer-readable recording medium, wherein the above memory module operation control data corresponds to an error area of ​​the memory module and a manufacturing date of the memory module.

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