Tiled architecture for display assembly

Abstract

Tiled architectures for display assemblies with transferred pixel emitters are described herein. One such display assembly includes a set of pixel emitters transferred to a carrier substrate after fabrication of the set of pixel emitters. A first driver circuit is disposed on the carrier substrate and configured to drive a first subset of pixel emitters included in the set, and a second driver circuit is disposed on the carrier substrate and configured to drive a second subset of pixel emitters included in the set. A controller circuit is configured to display a first content frame on the set of pixel emitters by transmitting frame data both to the first driver circuit and the second driver circuit, and to display a second content frame by transmitting frame data to the first driver circuit without transmitting frame data to the second driver circuit.

Description

TILED ARCHITECTURE FOR DISPLAY ASSEMBLYCROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to, and the benefit of, U.S. Provisional Application No. 63 / 595,950. filed on November 3, 2023, the disclosure of which is hereby incorporated by reference in its entirety.BACKGROUND

[0002] Semiconductor fabrication processes allow for the creation of extremely small electronic components such as transistors, resistors, capacitors, light emitting diodes (LEDs), and so forth. Fabrication of these semiconductor products may involve a series of precise steps, including depositing thin films of materials, patterning circuits using photolithography and etching techniques, and finally connecting every thing through metallization.

[0003] For many electronic components, it may be advantageous to miniaturize the components to a nearly unlimited extent. For instance, the more that transistor logic can be miniaturized, the more functionality (e.g., processing and storage capability) may fit on a single chip to result in electronic devices that are portable, light, low power, and so forth. For other electronic components, however, their usefulness may be limited as the components become smaller in size. As one example, micro light emitting diodes (microLEDs) and other small light emission components used as pixels in electronic displays may, when miniaturized beyond a certain extent, become so small that magnification is required for a user to see and appreciate the high resolution being provided. While such magnification may be acceptable or desirable for certain applications, the high resolution possible with these types of pixel emitters may be wasteful and undesirable for direct-view applications in which display screens are not magnified.SUMMARY

[0004] Extremely small pixel emitters such as microLEDs can be sparsely distributed on a display assembly to make the display suitable for direct viewing while still being efficient in various respects. One challenge with such a configuration, however, is that fanout to possibly many thousands of individual pixel emitters (or more) may be virtually impossible to accomplish using a single integrated circuit configured to perform all the tasks (e g., data processing, buffering, pixel driving, etc.) typically handled by backplane circuitryin conventional display assemblies. Accordingly, tiled architectures for such display assemblies (e.g., display assemblies that use pixel emitters transferred to a carrier substrate after being fabricated elsewhere) are described herein. Tiled architectures described herein divide tasks such as data processing, image buffering, and pulse-width-modulation (PWM) sequencing between one or more centralized integrated circuits (e.g., a central controller circuit) and a plurality of distributed integrated circuits (e.g., a plurality of driver circuits or tile drivers) in a variety of ways. Since each driver circuit can connect to a respective subset of the pixel emitters, the fanout problem may be alleviated even as various other benefits are provided. For example, efficiencies are provided by distributed driver circuits as they selfrefresh when their portion of a content frame remains unchanged from a previous frame and / or when the driver circuits power down when their portion of a frame has no content.

[0005] To this end, one implementation described herein involves a display assembly that includes: 1) a set of pixel emitters disposed on a carrier substrate (e.g., having been transferred to the carrier substrate after fabrication of the set of pixel emitters), the set of pixel emitters including a first subset of pixel emitters and a second subset of pixel emitters; 2) a first driver circuit disposed on the earner substrate and configured to drive the first subset of pixel emitters; 3) a second driver circuit disposed on the carrier substrate and configured to drive the second subset of pixel emitters; and 4) a controller circuit. The controller circuit may be configured to display a first content frame on the set of pixel emitters by transmitting frame data both to the first driver circuit and the second driver circuit. The controller circuit may also be configured to display a second content frame on the set of pixel emitters by transmitting frame data to the first driver circuit without transmitting frame data to the second driver circuit (since the second driver circuit may perform a selfrefresh of unchanged image content).

[0006] Other implementations described herein involve methods that may be performed by display assemblies described herein. For instance, one example method performed by a controller circuit within a display assembly may include: 1) displaying a first content frame on a set of pixel emitters, the set of pixel emitters being transferred to a carrier substrate after fabrication of the set of pixel emitters and including a first subset of pixel emitters and a second subset of pixel emitters; and 2) displaying a second content frame on the set of pixel emitters. The displaying of the first content frame may include both: (a) transmitting frame data to a first driver circuit disposed on the carrier substrate and configured to drive the first subset of pixel emitters, and (b) transmitting frame data to a second driver circuit disposed on the carrier substrate and configured to drive the secondsubset of pixel emitters. Conversely, the displaying of the second content frame may include transmitting frame data to the first driver circuit without transmitting frame data to the second driver circuit (again, since the second driver circuit may perform a self-refresh of unchanged image content).

[0007] Still other implementations described herein may involve a non-transitory computer-readable medium storing instructions that, when executed, cause a controller circuit of a display assembly to perform a process. For example, the process may include: 1) displaying a first content frame on a set of pixel emitters, the set of pixel emitters being disposed on a carrier substrate (e.g., having been transferred to the carrier substrate after fabrication of the set of pixel emitters) and including a first subset of pixel emitters and a second subset of pixel emitters; and 2) displaying a second content frame on the set of pixel emitters. The displaying of the first content frame may include both (a) transmitting frame data to a first driver circuit disposed on the carrier substrate and configured to drive the first subset of pixel emitters, and (b) transmitting frame data to a second driver circuit disposed on the earner substrate and configured to drive the second subset of pixel emitters. Conversely, the displaying of the second content frame may include transmitting frame data to the first driver circuit without transmitting frame data to the second driver circuit (again, since the second driver circuit may perform a self-refresh of unchanged image content).

[0008] Various additional implementations are explicitly described herein or may- follow from principles described below. It will be understood that each of the examples mentioned above and described below may be implemented in different types of implementations. For example, the various display systems described herein could each be implemented in a variety of different types of devices, methods described herein could be implemented by instructions stored in a non-transitory computer-readable medium, a non- transitory computer-readable medium storing such instructions could be implemented in a display system, or the like.

[0009] The details of these and other implementations are set forth in the accompanying drawings and the description below. Other features will also be made apparent from the following description, drawings, and claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 shows illustrative aspects of a display assembly implementing a tiled architecture in accordance with principles described herein.

[0011] FIG. 2 shows illustrative scenarios in which a display assembly implementinga tiled architecture may be used to display different content frames in accordance with principles described herein.

[0012] FIG. 3 shows illustrative aspects of transferring a set of pixel emitters to a carrier substrate after fabrication of the set of pixel emitters in accordance with principles described herein.

[0013] FIG. 4 shows illustrative portions of a display assembly and certain aspects relating to a driver circuit that corresponds to one of the portions in accordance with principles described herein.

[0014] FIG. 5 shows illustrative electrical connections between an example controller circuit and a plurality of driver circuits in accordance with principles described herein.

[0015] FIG. 6 shows illustrative content frames that may be displayed using a tiled architecture for a display assembly with transferred pixel emitters in accordance with principles described herein.

[0016] FIG. 7 shows an illustrative method that a display assembly implementing a tiled architecture may perform in accordance with principles described herein.

[0017] FIGS. 8A-8E show a variety of example implementations of tiled architectures for display assemblies with transferred pixel emitters in accordance with principles described herein.

[0018] FIG. 9 shows an illustrative computing system that may be used to implement various devices and / or systems in accordance with principles described herein.DETAILED DESCRIPTION

[0019] Tiled architectures for display assemblies with transferred pixel emitters are described herein. While various advantages can be gained by distributing small pixel emitters (e.g., microLEDs) to a direct-view' display, various technical problems described herein may also be addressed. As one example, there may be far too many individual pixel emitters on a given display (e.g., many thousands or more) for a singular integrated circuit to connect to and drive. Accordingly, tiled architectures described herein provide a hierarchy of integrated circuits that ease fanout requirements while also supporting efficient performance of all the tasks (e.g., data processing, buffering, pixel driving, pulse-width-modulation (PWM) sequencing, etc.) ty pically handled by backplane circuitry' in conventional display assemblies. As described herein, these and other tasks may be divided between one or more centralized integrated circuits (e.g., a central controller circuit) and a plurality of distributed integrated circuits (e.g., a plurality of driver circuits) in a variety' of ways to allow for differentefficiency tradeoffs while providing significant benefits of direct-view microLED displays.

[0020] Display assemblies featuring pixel emitters such as microLEDs offer significant advantages compared to other display technologies (e.g., OLED, LCD). For example, each pixel emitter (e.g., each individual microLED or each cluster of red, green, and blue microLEDs) may be controllable to emit light (ON) or not emit light (OFF), leading to extremely high (e.g., infinite) contrast ratios. Moreover, response times of microLED pixels may be very short, leading to crisp and responsive displays with bright colors, high frame rates, and high power efficiency. To gain these and other significant benefits of microLEDs on a direct- view display, however, a variety of technical problems may need to be addressed.

[0021] One technical problem relates to the size and angular pitch of microLED pixel emitter technologies. MicroLED fabrication processes may produce pixel panels with a pixel pitch in the range of a few microns, allowing for the fabrication of panels with hundreds of thousands or millions of pixels per square centimeter. Such pixel resolution goes well beyond the resolving capacity7of the human visual system, such that panels with pixel density in this range are typically magnified significantly before being viewed by the user. As one example of where these technologies have been useful, extended reality headsets (e.g., augmented reality glasses, etc.) are a good fit for extremely dense pixel panels, since the form factor provides very limited space for the pixel panel and since there is ty pically a complex optical stack (including magnification and other optical manipulation) between the pixel panel and the heads-up display viewed by the user.

[0022] While high-density microLED pixel panels may be a natural fit for magnified displays such as may be integrated into head-mounted display devices (e.g., extended reality glasses, etc.), the brightness, power efficiency, and other attributes of microLED devices maymake these devices desirable for other types of applications as well, including for direct-view display applications. As used herein, a direct-view display refers to a display that is configured for viewers to look at directly, without significant manipulation of the light (e.g., beyond natural distortion that may be introduced by a cover glass or other such optical device integrated with the display for protection or aesthetic purposes). For example, direct-view displays may stand in contrast to displays, such as may be included in head-mounted extended reality devices, that manipulate light in more significant ways (e g., significantly magnifying the light, moving the light through a waveguide, projecting the light to form an image on a display separate from the pixel panel or directly on the user’s retina, etc.). While it may be common for head-mounted display devices to magnify and otherwise process the light for their displays, a few example applications that typically use direct- view displays aresmartwatch devices, mobile devices (e.g., smartphones, tablets, etc.), and television screens.

[0023] This first technical problem that may arise relates to extremely small pixel emitters (such as microLEDs) being employed for direct-view displays and the pixel pitch being so small as to be wasteful and inefficient. For example, even though a smartwatch display may only be a few square centimeters in size, the number of microLEDs that could fit on a direct-view display of that size could be in the tens of millions. Along with adding significant cost to the device's bill of materials, a display with this type of resolution would place significant strain on power and heat requirements of the device, along with creating other complications and resource requirements associated with driving the display and processing / storing the high-resolution images it would produce. Even if all of these issues were addressed by a certain design, the design would still be wasteful and inefficient as the human visual system is unable to resolve such high resolution.

[0024] In response to this technical problem, at least one technical solution described herein involves producing direct-view display assemblies that use sparse distributions of pixel emitters. For example, after fabrication of a set of pixel emitters on a donor wafer at a first pixel pitch (e.g., a very small pixel pitch that the human visual system would be unable to resolve), the set of pixel emitters may be transferred to a carrier substrate in a manner that distributes the pixel emitters more sparsely to increase the pixel pitch to a greater pitch that is more reasonably resolvable by the human visual system (though an arbitrarily high display resolution can still be provided). In this way, the waste and inefficiency of overly high display resolution may be avoided for the direct-view display, while the desired brightness, power-efficiency, dynamic range, and other benefits of microLED technology7can be provided. While smartwatch displays provide one good example of an application where direct-view display assembly with sparse distribution of pixel emitters could be used, it will be understood that principles described herein could similarly be used with a variety of other direct-view display applications such as mobile devices, computer screens, television screens, appliance panels, automotive interfaces, and so forth.

[0025] Along with distributing pixel emitters more sparsely on a display assembly (so as to increase the pixel pitch to a level that can be more reasonably resolved by users), another technical problem addressed by display assemblies described herein relates to how power and signaling can be distributed to the pixel emitters in their sparsely-distributed positions. While conventional microLED displays may include pixel emitters disposed on a backplane circuit, spreading the pixel emitters out over a larger area (to thereby increase the pixel pitch in the ways that have been described) may involve communicating with all of thepixel emitters from a centralized circuit (e.g., a controller circuit) configured to perform various roles of the conventional backplane circuit such as image processing, data buffering, pixel emitter driving, pulse-width-modulation (PWM) sequencing, and so forth. For display assemblies described herein with transferred pixel emitters (i.e., display assemblies in which pixel emitters are transferred from a donor substrate on which they were fabricated, to a display assembly where the pixel emitters can operate with more space between them), signal routing from a centralized display controller to pixel emitters that are sparsely fanned out across a relatively large display area becomes a significant technical problem for the display assembly to address.

[0026] Accordingly, for this technical problem of signal distribution to large numbers of sparsely placed pixel emitters, at least one technical solution provided herein involves a tiled architecture in which a centralized controller circuit communicates indirectly to a set of pixel emitters through a plurality of driver circuits (or tile drivers) that is each responsible for its own portion (or tile) of the display. For example, a first driver circuit disposed on a carrier substrate with the set of transferred pixel emitters may be in communication with the controller circuit and configured to drive a first subset of the pixel emitters, a second dnver circuit disposed on the carrier substrate with the set of transferred pixel emitters may also be in communication with the controller circuit and configured to drive a second subset of the pixel emitters, and so forth. In certain implementations, a plurality of controller circuits each communicating to their own plurality of driver circuits (which, in turn, are each responsible for their own subset of pixel emitters) may even be controlled by a higher-level controller circuit, such that arrays of pixel emitters of arbitrary size can be efficiently and effectively controlled using the architecture at different scales.

[0027] Various technical effects and benefits may be provided by use of tiled architectures such as those described herein. For example, direct-view display assemblies with sparse distributions of pixel emitters may allow for the benefits of microLEDs to apply to direct-view display applications, even as wasteful inefficiency is avoided that could otherwise accompany displays with extremely high density. These benefits include bright, sharp-looking displays that are also power efficient as non-emissive power consumption (e.g.. from leakage power, memory access, interface signal transitions, etc.) is minimized. Additionally, emitter density may be reduced (i.e., pixel pitch may be increased) to more efficiently account for the capacity' of the human visual system and without sacrificing display performance.

[0028] As will be described in more detail below, another significant technical effectarising from technical solutions described herein relates to the ability of individual tiles (e.g., individual driver circuits and their respective subsets of pixel emitters) to manage themselves at least somewhat independently (e.g., with signaling from the controller circuit only when changed content is to be presented). For example, if a portion of the display that a first driver circuit is responsible for includes no content for one or more content frames, the driver circuit responsible for that portion may be powered down and no refresh time or power may be wasted on that portion of the display (as opposed to a conventional display refresh scheme in which an entire display may be updated for each frame regardless of the image content of the frame). Similarly, if the subset of pixel emitters includes content that is unchanged from previous content already being displayed on the tile (in association with a previous content frame), similar efficiencies may be gained by the driver circuit being able to self-refresh without storing new data, receiving additional frame data from the controller circuit, or the like. As a result, tiled architectures described herein may be highly efficient and responsive to content frames involving only partial updates of the display. Technical effects of this responsiveness may include reduced flicker and frame update times with increased brightness and power efficiency.

[0029] Additional technical effects of display assemblies described herein include significant flexibility' and a variety' of options for how the displays may be constructed so as to potentially provide unique features for the device in which the display assembly is used. For example, the flexibility with how pixel emitters are placed in implementations described herein impose no requirement that arrays of pixel emitters have any particular shape or layout (e.g., a rectangular shape or rectilinear layout). As a result, display assemblies of a variety7of shapes and sizes may be conveniently produced as may serve a particular implementation. Other example benefits may include that display assemblies in accordance with principles described herein may tend to be very thin (which may be a critical design constraint for certain applications), may allow for flexible controller circuit placement, may be fully integrated (e.g., with all the driver circuits and even the controller embedded in the assembly with the carrier sheet), and so forth.

[0030] Various implementations will now be described in more detail with reference to the figures. It will be understood that particular implementations described below are provided as non-limiting examples and may be applied in various situations. Additionally, it will be understood that other implementations not explicitly described herein may also fall within the scope of the claims set forth below. Systems and methods described herein for tiled architectures for display assemblies with transferred pixel emitters may result in any orall of the technical effects mentioned above, as well as various additional effects and benefits that will be described and / or made apparent below.

[0031] FIG. 1 shows illustrative aspects of a display assembly 100 implementing a tiled architecture in accordance with principles described herein. As shown, display assembly 100 includes a set of pixel emitters (pixel emitter set 102) that will be understood to have been transferred to a carrier substrate (not shown in FIG. 1) after fabrication of the set of pixel emitters. Pixel emitter set 102 is shown to include a first subset of pixel emitters (pixel emitter subset 104-1), a second subset of pixel emitters (pixel emitter subset 104-2), and any suitable number of additional subsets of pixel emitters (“Other Pixel Emitter Subsets”) as may serve a particular implementation (represented by dotted lines). Display assembly 100 is further shown to include a first driver circuit 106-1, which may be disposed on the earner substrate with pixel emitter set 102 and may be configured to drive pixel emitter subset 104-1, as well as a second driver circuit 106-2, which may also be disposed on the carrier substrate with pixel emitter set 102 and may be configured to drive pixel emitter subset 104-2. Any suitable number of additional driver circuits (along with driver circuits 106-1 and 106- 2) may also be understood to be included within display assembly 100. as represented by a dotted box (“Other Driver Circuits”).

[0032] Display assembly 100 further shows a controller circuit 108 in communication with each of the driver circuits (i.e., driver circuits 106-1 and 106-2, as well as any other driver circuits as may be included in a given implementation). Controller circuit 108 may be configured to receive and display various content frames such as illustrated in FIG. 1 by content frames 110-A, 110-B, and 110-C. Each of these content frames may include various portions corresponding to the tiles being managed by the various driver circuits controlled by controller circuit 108. For example, a portion 112-1 of content in each content frame may correspond to the content that is to be displayed on pixel emitter subset 104-1 by driver circuit 106-1, while a portion 112-2 of content in each content frame may correspond to the content that is to be displayed on pixel emitter subset 104-2 by driver circuit 106-2.

[0033] As indicated by the Key in FIG. 1, the different portions 112-1 and 112-2 of each content frame 1 10-A through 1 10-C may include different types of content that may be handled by the driver circuits in different ways. For example, portions of a content frame that include new and different content from the previous frame (“Changed Content”) are shown to be illustrated by a dotted fill pattern, portions of the content frame that include the same content as the previous frame (“Unchanged Content”) are shown to be illustrated by a grid fill pattern, and portions of the content frame that do not include any content (“No Content”) areshown to be illustrated by a solid black fill pattern (suggestive of pixel emitters being powered off). Using this notation, FIG. 1 thus shows: 1) a first content frame 110-A in which portion 1 12-1 and portion 112-2 both include changed content (such that driver circuits 106-1 and 106-2 will each need to receive updated frame data from controller circuit 108); 2) a second content frame 110-B in which portion 112-1 includes changed content while portion 112-2 includes unchanged content (such that driver circuit 106-1 will need updated frame data from controller circuit 108 but driver circuit 106-2 will be able to self-refresh with no new frame data); and 3) a third content frame 110-C in which portion 112-1 again includes changed content while portion 112-2 includes no content (such that driver circuit 106-1 will again need updated frame data from controller circuit 108 but driver circuit 106-2 will be able to power down and not drive its subset of pixel emitters).

[0034] In other words, given the examples provided by these particular content frames, controller circuit 108 may be configured to: 1) display the first content frame 110-A on pixel emitter set 102 by transmitting frame data both to driver circuit 106-1 and driver circuit 106-2; 2) display the second content frame 110-B on pixel emitter set 102 by transmitting frame data to driver circuit 106-1 without also transmitting frame data to driver circuit 106-2; and 3) display the third content frame 1 10-C on pixel emitter set 102 by transmitting frame data to driver circuit 106-1 while directing driver circuit 106-2 to be powered down. It will be understood that controller circuit 108 may transmit some data to driver circuits that are not actively displaying changed content, though that data would not, in these examples, include updated frame data (i.e., data indicative of image content, etc ). For instance, non-frame data transmitted in such cases could be used to communicate timing signals, an instruction for the driver circuit to self-refresh until further notice, an instruction for the driver circuit to power down, or the like.

[0035] To further illustrate examples of how tiled architectures may function in accordance with principles described herein, FIG. 2 shows several illustrative scenarios in which a display assembly implementing a tiled architecture may be used to display different content frames. More particularly, a scenario 200-A may correspond to content frame 110-A, a scenario 200-B may correspond to content frame 110-B, and a scenario 200-C may correspond to content frame 110-C.

[0036] In each of scenarios 200-A through 200-C, FIG. 2 shows pixel emitter set 102, which will be understood to include the entire array of pixel emitters of a display assembly such as display assembly 100. The pixel emitters in pixel emitter set 102 are shown to be represented, in this figure, by small squares that could represent individual pixel emitters(e.g., red emitters, green emitters, blue emitters, etc.) or could represent pixel emitter clusters (e.g., clusters including at least one red, one green, and one blue emitter so as to be able to display many different colors as a combination of these three primary colors). The pixel emitters of pixel emitter set 102 are shown to then be subdivided into various subsets of pixel emitters, including pixel emitter subset 104-1 (corresponding to driver circuit 106-1), pixel emitter subset 104-2 (corresponding to driver circuit 106-2), and other subsets (“Other Pixel Emitter Subsets”) that correspond to other driver circuits (“Other Driver Circuits”) and are not explicitly broken out in FIG. 2 (represented by dotted lines). Controller circuit 108 is shown above the various driver circuits to display content frames by indirectly controlling pixel emitter set 102 by way of the driver circuits in the w ays described herein.

[0037] For each of the scenarios 200-A through 200-C, frame data communication (or a lack thereof) between controller circuit 108 and the respective driver circuits are indicated by a callout 202- lx (for frame data transmission to driver circuit 106-1) and a callout 202-2x (for frame data transmission to driver circuit 106-2), where ‘x’ is a lerter ‘A’, ‘B‘, or ‘C’ corresponding to the particular scenario 200-A, 200-B, or 200-C. Similarly, voltages or currents (or a lack thereof) produced by the driver circuits to drive their respective pixel emitter subsets are indicated by a callout 204-lx (for pixel emitter subset 104-1 driven by driver circuit 106-1) and a callout 204-2x (for pixel emitter subset 104-2 driven by driver circuit 106-2), where ‘x‘ again represents ‘A’. ‘B‘, or ‘C’ corresponding to the particular scenario.

[0038] Using this notation, FIG. 2 shows that for each of scenarios 200-A, 200-B, and 200-C, controller circuit 108 may display respective content frames on pixel emitter set 102 by transmitting frame data to driver circuit 106-1 (callout 202-1A in scenario 200-A, callout 202- IB in scenario 200-B, and callout 202- 1C in scenario 200-C). This is because, as described and illustrated in FIG. 1, each of content frames 110-A, 110-B, and 110-C includes changed content for the portion 112-1 of the content frames to which pixel emitter subset 104-1 corresponds. This is not true, however, for the portion 112-2 of the content frames to which pixel emitter subset 104-2 corresponds. As described above, while content frame 110- A includes changed content for portion 112-2. content frame 110-B includes unchanged content for this portion while content frame 110-C includes no content for this portion. Accordingly, as shown, while controller circuit 108 may transmit frame data to driver circuit 106-2 in scenario 200-A (callout 202-2A). controller circuit 108 does not transmit frame data to driver circuit 106-2 in either of scenario 200-B (callout 202-2B) or scenario 200-C (callout 202-2C).

[0039] In accordance with the direction given to the driver circuits by controller circuit 108. FIG. 2 further shows that, for each of scenarios 200- A, 200-B, and 200-C, driver circuit 106-1 drives pixel emitter subset 104-1 to present the changed content (callout 204-1 A in scenario 200-A, callout 204-1B in scenario 200-B, and callout 204-1C in scenario 200-C). Again, however, driver circuit 106-2 will be understood to behave differently as a result of the differences in the types of content it is tasked with displaying in the various scenarios. Like driver circuit 106-1, driver circuit 106-2 drives pixel emitter subset 104-2 to present changed content (callout 204-2A) for scenario 200-A. But given that the content in portion 112-2 remains unchanged for the content frame of scenario 200-B (as indicated by callout 202-2B, described above), driver circuit 106-2 will be understood to perform a self-refresh of pixel emitter subset 104-2 for this content frame (callout 204-2B). In other words, driver circuit 106-2 may continue to provide the voltage and current needed to properly drive pixel emitter subset 104-2 for the second content frame of scenario 200-B, but driver circuit 106-2 performs this refresh independently without receiving additional frame data from controller circuit 108 (callout 202 -2B). It is noted, as mentioned above, that driver circuit 106-2 may receive certain timing or instructional signaling from controller circuit 108 (e.g., synchronization or clocking signals, data representing instructions to self-refresh, etc.), even though no new frame data is received.

[0040] For scenario 200-C, where there is no content in portion 112-2, controller circuit 108 again transmits no frame data to driver circuit 106-2 (callout 202 -2C) even though frame data is transmitted to driver circuit 106-1 (callout 202-1 C). Unlike in scenario 200-B, however, where driver circuit 106-2 still drove pixel emitter subset 104-2 to perform the selfrefresh of pixel emitter subset 104-2, scenario 200-C shows that driver circuit 106-2 may be powered down (indicated by dark shading in driver circuit 106-2) and no voltage or current may be driven for pixel emitter subset 104-2 (callout 204-2C). As pixel emitter subset 104-2 is not driven by the powered-down driver circuit 106-2 in this scenario, the pixel emitters of pixel emitter subset 104-2 are each shown to be filled in with solid black to illustrate that the pixel emitters may also be powered off in this scenario.

[0041] In these various scenarios, power may be used to drive pixel emitters when needed, but power (e.g., in the form of leakage current, switching current, etc.) may be efficiently conserved w henever a portion of the display is static (i.e., having unchanging content from frame to frame) or when a portion of the display is not showing content. In implementations using pulse-width modulation (PWM) of various bitplanes (or subframes) for each content frame, these same principles may apply not only for a given content frame,but also for the bitplanes (or subframes) presented in the course of presenting the content frame. For example, if a portion of the display is relatively dim and therefore off for a large portion of the total frame time of a content frame (i. e. , off for many subframes of the various subframes comprising the content frame), power may be saved by powering down the driver circuit during these subframes. In some examples, driver circuits could include their own clock generators so that they can operate without a controller sequence signal, while in other examples, clocking and / or sequence signaling may be received from the controller circuit to assist with self-refresh even though additional frame data is not received.

[0042] Additionally, in implementations where each driver circuit drives a subset of monochrome pixel emitters (e.g., where one driver circuit is configured to drive red pixel emitters for a portion of the display, a separate driver circuit is configured to drive green pixel emitters for that portion of the display, etc.), corresponding efficiencies may be gained by self-refreshing and / or powering down when the relevant color is not needed to display the content (e.g., w hen red content in a portion of the display means that no green pixel emitters are to be driven for that portion, etc.).

[0043] FIG. 3 shows illustrative aspects of transferring a set of pixel emitters to a carrier substrate after fabrication of the set of pixel emitters in accordance with principles described herein. More particularly, FIG. 3 illustrates aspects of an implementation 300 of the display assembly 100 described above. In this example, a direct- view display 302 is illustrated and described as being configured for use as a smartwatch display (e.g., based on its shape, size, etc.). However, as mentioned above, it will be understood that the same principles described in relation to direct-view display 302 may be applied to other types of direct-view display assemblies configured for us in other applications such as mobile device displays, laptop screens, televisions, appliance panels, and so forth.

[0044] As shown in FIG. 3, a small segment 304 of direct-view display 302 is broken out and zoomed in to illustrate certain aspects of the display that will be described. Additionally, FIG. 1 shows a donor wafer 306 (not drawn to scale in relation to direct-view' display 302) that may undergo lithographic and / or other processing to fabricate a large number of pixel emitters (e.g.. microLED devices or the like). More particularly, as shown by a small segment 308 of donor wafer 306 that is similarly shown to be broken out and zoomed into, a set of pixel emitters 310 (represented by small squares within segment 308) is fabricated on donor wafer 306 before undergoing a transfer 312 to direct-view display 302.

[0045] Transfer 312 may be performed in any suitable way. For example, after the pixel emitters 310 have been fabricated with high density on donor w afer 306, the donorwafer may be aligned with a carrier substrate of the display assembly and the pixel emitters 310 may be released or detached from the donor wafer to be coupled (e.g., electrically connected, adhesively connected, etc.) at the desired location on the carrier substrate (i.e. , the location to which the pixel emitter has been aligned). This detachment may be facilitated by a laser that is focused (e.g., from a first side of the donor wafer) in a manner that creates a defect (e.g., a crack) at a specified depth within the wafer under the emitter or emitters that are to be released. With the donor wafer and carrier aligned, another laser (e.g., introduced from the opposite side of the donor wafer) may then cause the defect to expand (e g., the crack to spread) within boundaries that have been set around a particular pixel emitter (or group of pixel emitters) that is to be released by the action of the laser. As such, the pixel emitter or group may detach from the donor wafer where it or they were fabricated and may attach to the carrier substrate. As mentioned above and as will be described in more detail below, the pixel pitch of the pixel emitters may be increased by transfer 312 so that the pixel emitters are not so densely packed. In some cases, for instance, the donor wafer may be aligned and then only one in every N pixel emitters may be released to the carrier sheet (where N could equal 2, 10, 25, 50, or any other suitable number) prior to the donor wafer being realigned to the same or another carrier sheet to repeat the process for other, not-yet- released pixel emitters.

[0046] The set of pixel emitters 310 will be understood to correspond to pixel emitter set 102 described herein. However, while pixel emitter set 102 refers to the pixel emitters included on given direct-view display 302, it will be understood that the set of pixel emitters 310 produced on donor wafer 306 may be transferred not only to direct-view display 302 but also to one or more other display assemblies. For example, pixel emitters fabricated on one large donor wafer may be transferred to dozens or hundreds of relatively small display assemblies (such as for smartwatch displays).

[0047] Segment 304 shows that the set of pixel emitters 310 is disposed in direct- view display 302 subsequent to being transferred (transfer 312) to the carrier substrate of direct-view display 302 from the donor wafer 306 on which the set of pixel emitters 310 was fabricated. As further illustrated in FIG. 3. the set of pixel emitters 310 may be fabricated at a first pixel pitch 314-1 and may be distributed on the carrier substrate of direct-view display 302 at a second pixel pitch 314-2 that is greater than pixel pitch 314-1. In some examples, the pixel pitch 314-1 at which the set of pixel emitters 310 are fabricated may be a very small pixel pitch, such as in the range of about 2-4 microns. In contrast, the pixel pitch 314-2 at which the set of pixel emitters 310 is distributed within the direct- view display 302 may besignificantly larger than pixel pitch 314-1. While not necessarily draw n to scale in relation to pixel pitch 314-1 in FIG. 3, pixel pitch 314-2 could be, in various examples, at least double pixel pitch 314-1, at least four times greater than pixel pitch 314-1, at least ten times greater than pixel pitch 314-1, at least twenty times greater than pixel pitch 314-1, at least forty times greater than pixel pitch 314-1, or another suitable increase as may serve a particular implementation. As a specific example, for instance, pixel pitch 314-1 could represent a high- density pitch in the range of 2-4 microns while pixel pitch 314-2 could represent a low- density (sparse) pitch in the range of 50-120 microns (e.g., 80 microns).

[0048] One advantage of having pixel emitters distributed relatively sparsely (i.e., with a pitch such as shown by pixel pitch 314-2) is that the space between sparsely- distributed pixel emitters may be used by other components (e.g.. antennas, alternate wavelength emitters, imaging sensors, ambient light sensors, etc.). For example, these spaces may provide placement locations for the other components (e.g., when integrated directly into the display assembly) or may at least facilitate surface access and visibility for such components (e.g., in the event they are placed beneath the display assembly, deeper into the device).

[0049] To illustrate how such usage could be advantageous, a conventional display assembly w ill be considered. If an antenna or set of sensors (e.g., light detectors for a fingerprint reader, etc.) were to be integrated into a device such as a smartwatch, these components would typically need to be placed beneath the conventional display assembly. Such placement would not be ideal, since the antenna or sensors would be farther from the surface of the display, forcing attenuation of signals that are transmitted and / or received through the display itself. In contrast, the ample space between sparsely distributed pixel emitters 310 (as illustrated in FIG. 3) leaves room for such components to be integrated directly into the display assembly so that they are located right at the surface and have direct access and visibility. For example, an antenna could be made to weave between the pixel emitters (e.g., on a redistribution layer without traces or with fewer traces connecting the emitters to their respective driver circuit) so that it could be right at the surface and not buried deeper in the device under the display assembly. As another example, many small sensors such as might be used to capture an image (e.g., sensors forming a camera, a fingerprint or facial identic detector, an ambient light detector, etc.) could be interspersed with the pixel emitters and routed to a controller in a similar way as described herein for the pixel emitters.

[0050] Even if antennas and sensors (such as have been described) are not integrated into the display assembly itself in these ways, the sparseness of the pixel emitters andpotential thinness of display assemblies described herein may mitigate the antenna / sensor issues described above (i.e. , issues faced by conventional display assemblies). For example, even for antennas and sensors that happen to be incorporated outside of the display assembly (e.g., deeper within a device, beneath the display assembly), the relatively sparse distribution of pixel emitters and the flexibility with which they may be placed may facilitate surface access for antennas and sensors anywhere within the device.

[0051] FIG. 4 shows illustrative portions of direct-view display 302 and certain aspects relating to a driver circuit that corresponds to one of the portions in accordance with principles described herein. More particularly, in this example, the direct-view display 302 is shown to be divided into a 4x4 grid of 16 different portions 402-1 through 402-16 (i.e., portions 402-1. 402-2, 402-3, 402-4. 402-5, 402-6, 402-7. 402-8, 402-9, 402-10, 402-11. 402- 12, 402-13, 402-14, 402-15, and 402-16) that will each be understood to be associated with a respective driver circuit and subset of pixel emitters (from a total set of pixel emitters of the display assembly). For example, portion 402-8 (selected arbitrarily) is shown, in a zoomed-in segment outlined by a dotted line in FIG. 4, to include one driver circuit 106 that is connected, by vanous electrical connections 404 (e.g., traces on the carrier substrate), to a subset of the pixel emitters 310 that happen to be disposed in this portion of the display.

[0052] Pixel emitters 310 may be implemented by any suitable light emission devices that may serve as a pixel for a display. A principal example used throughout this disclosure is that of a microLED device. For instance, each pixel emitter 310 could represent a microLED cluster with a red element, a green element, and a blue element that combine to create a white pixel or any desired color (based on the influence given to each of the primary colors). As another example, each pixel emitter 310 could represent a single microLED of one individual color (e.g., a red microLED, a green microLED. etc.). While microLEDs are used as the principal example in the disclosure, it will be understood that principles described herein could be applied to other types of pixel emitters, particularly those that, like microLEDs, may be extremely small such that sparser distribution is desirable before they can be used for an efficient direct- view display.

[0053] The driver circuits for each of the portions 402-1 through 402-16 (including driver circuit 106 for portion 402-8) may each be implemented by semiconductor chips or integrated circuits, whether those chips be unpackaged semiconductor dies, fully packaged chips, or something in between. The controller circuit (mentioned above but not explicitly shown in FIG. 4) may be implemented in a similar way. For example, these circuits may each represent different complementary-metal-oxide-semiconductor (CMOS) integrated circuitsthat are fabricated separately (e.g., on a wafer similar to donor wafer 306) and then integrated into the direct-view display 302 to serve the functions described herein. In some examples, these chips may be configured to be relatively thin and low profile (e.g., with a thickness less than 300 microns, less than 50 microns, less than 20 microns, etc.).

[0054] The various electrical connections 404 may be implemented as emitter traces implemented on a single plane (as shown), or. in cases where more complex fanout is necessary (e.g., to a subset of pixel emitters with several dozens or hundreds of pixel emitter devices) may be implemented on two or more planes separated by layers of insulative dielectric material. A set of controller traces (not explicitly show n) between a controller circuit and each of the driver circuits may similarly be implemented on the same plane of insulating material as the controller circuit and / or the driver circuits themselves, or on a separate layer.

[0055] FIG. 4 shows direct- view- display 302 to be divided into 16 square (or nearly square) portions and shows the example portion 402-8 to include a subset of pixel emitters in an 8x8 square grid including 64 pixel emitters. These numbers, shapes, and layout are provided only for the sake of illustration, and it will be understood that a given implementation of direct-view display 302 could include any suitable number of portions or tiles (more or less than the 16 shown in the example of FIG. 4), each with any suitable number of pixel emitters (more or less than the 64 shown in FIG. 4). Indeed, different implementations may handle a tradeoff between routing complexity and display thickness on the one hand (which may be optimized by having fewer portions and driver circuits for the controller circuit to be routed to) and power and chip complexity / cosl on the other hand (which may be optimized by having more portions and driver circuits that are each responsible for fewer pixel emitters and thus use less power and buffering resources, etc.) in different ways according to their unique design goals.

[0056] Additionally, just as the comer portions of direct-view- display 302 (i.e., portions 402-1, 402-4, 402-13, and 402-16) are shown to be non-square shapes (i.e., due to the rounded comers), it will be understood that the shape and lattice type of the pixel emitters in any given portion need not be square or rectilinear. For instance, pixel emitters could be disposed on a triangular lattice in a portion that has a circular, rectangular, or irregular shape. In certain implementations, this flexibility in pixel emitter placement and shaping, as w ell as the sparseness of the pixel emitters, may facilitate the placement and function of certain components under the direct-view display 302. For example, one or more antennas beneath direct-view- display 302 may have significant visibility for wireless communication throughthe gaps between the pixel emitters, sensors (e.g., cameras, fingerprint readers, facial recognition modules, etc.) could be placed under the display, and so forth.

[0057] While not explicitly shown in FIG. 4, it will be understood that each of portions 402-1 through 402-16 may be associated with similar driver circuits (like driver circuit 106 of portion 402-8) and subsets of pixel emitters (like the 64-emitter subset of pixel emitters 310 shown in portion 402-8). It will also be understood that a controller circuit (e.g., controller circuit 108) may be disposed on the carrier substrate of direct- view display 302 (not explicitly shown) together with the driver circuits and may be communicatively coupled (e.g., by way of similar electrical connections or traces) with each of the driver circuits (16 driver circuits in this example) to display content frames on the pixel emitters by controlling the driver circuits in ways described herein.

[0058] To illustrate in more detail, FIG. 5 shows illustrative electrical connections between an example implementation of controller circuit 108 and a plurality of driver circuits 106 associated with various portions of a display assembly (e.g., portions 402-1 through 402- 16 of direct- view display 302, for example). More particularly, FIG. 5 shows a block diagram showing logical connections between different outputs of the controller circuit 108 and each of the driver circuits 106 in a given implementation.

[0059] While the physical connections and routing (e.g., electrical traces on the carrier substrate, etc.) are not explicitly shown in FIG. 5, it will be understood that the routing of the signals represented in the diagram of FIG. 5 may be performed based on similar principles as described and illustrated above in relation to routing electrical connections from each driver circuit 106 to its subset of pixel emitters 310. More particularly, as show n by respective electrical connections 404 in FIG. 4, traces connecting controller circuit 108 to driver circuits 106 and connecting driver circuits 106 to pixel emitters 310 may be routed on a single layer of the carrier substrate if possible, or may, in other implementations, be implemented on two or more layers. It will be understood that it may be desirable to have as few' layers as possible for a given implementation (e.g., so that the direct-view7display 302 may have a low profile, may possibly be flexible, may avoid certain thermal issues, and so forth). As such, to the extent that it is possible to including the routing of emitter traces (between driver circuits 106 and pixel emitters) and controller traces (between controller circuit 108 and driver circuits 106) on a single layer or on a relatively small number of layers, this may be desirable for certain implementations.

[0060] As shown in FIG. 5, the controller circuit 108 may be communicatively coupled to the various driver circuits 106 by way of an architecture in which the drivercircuits are organized into row groups and string groups. In the example of FIG. 5, for instance, row groups 502-1 through 502-3 are drawn using solid lines and explicit labels, while dotted lines indicate that “Additional Row Groups” (of any suitable number as may serve a particular implementation) may also be included. Similarly, string groups 504-1 through 504-3 (also referred to as column groups) are drawn using solid lines and explicit labeling, while dotted lines indicate that “Additional String Groups” (of any suitable number that may be the same or different from the number of additional row groups) may also be included.

[0061] While the row groups and string groups in FIG. 5 are shown to be organized in a grid-like pattern of row s and columns, it will be understood that this logical organization need not have any particular relation to how the driver circuits 106 and their respective subsets of pixel emitters are physically arranged on the display assembly. For example, while it is possible that the driver circuits 106 and subsets of pixel emitters are arranged in row-s and columns such as shown by portions 402-1 through 402-16 in FIG. 4, non-rectangular, serpentine, circular, or other (e.g., fully irregular) placements of both driver circuits 106 and their respective subsets of pixel emitters may also be possible using the logical architecture illustrated in FIG. 5. In other words, driver circuits 106 in the same row group or same string group need not necessarily have any physical or geometric relationship with one another (being on the same row or column of a grid, etc.), and, indeed, no grid of row s and / or columns may be used in certain implementations. Additionally, as mentioned above, while there may be the same number of row groups as column groups in certain implementations, this need not necessarily be the case, since there may be certain advantages of organizing the driver circuits 106 into larger row groups with fewer driver circuits per string group or vice versa. Similarly, there may not be the same number of driver circuits in each row group as in every other row group, and there may not be the same number of driver circuits in each string group as in every other string group.

[0062] While no placement limitation is to be implied by the architecture of FIG. 5, however, the connections illustrated in FIG. 5 show that, for a given driver circuit 106 associated with a given row group and a given string group, there may be certain connection commonalities and differences with other driver circuits in the same groups. For instance, taking a first driver circuit in the top-left comer as an example, this first driver circuit is shown to be included in a first row7group 502-1 that has an address line (“Addr”) that is shared by each of the driver circuits 106 in first row group 502-1 and is not shared by driver circuits 106 outside of first row group 502-1 (i.e., since driver circuits 106 in row7groups 502-2, 502-3, and the additional row groups are shown to be connected to different address lines from controller circuit 108). Similarly to the address lines, this implementation also shows advance lines ('‘Adv”) that are shared by driver circuits 106 in the same row groups and not shared by driver circuits in other row groups. The function of these signals will be described in more detail below.

[0063] Other signals provided by controller circuit 108 are shown to be orthogonal to the address and advance lines, or in other words, to be shared by string groups rather than row groups. Using the same first driver circuit again as an example (in the top-left comer), this driver circuit 106 is shown to be included in a first string group 504-1 that has a data line (“Data"’) that is shared by each of the driver circuits 106 in string group 504-1 and is not shared by driver circuits 106 outside of string group 504-1 (i.e.. since driver circuits 106 in string groups 504-2, 504-3, and the additional string groups are shown to be connected to different data lines from controller circuit 108). Similarly to the data lines, this implementation also shows clock lines (“CLK”) that are shared by driver circuits 106 in the same string groups and not shared by driver circuits in other string groups. The function of these signals will also be described in more detail below.

[0064] This architecture provides controller circuit 108 significant flexibility in communicating with the various driver circuits 106. For example, taking any two driver circuits 106 that controller circuit 108 is to communicate with, the driver circuits could be: 1) in the same row group, such that they share a same address line (and advance line) while having different data lines (and clock lines); 2) in the same string group, such that they share a same data line (and clock line) while having different address lines (and advance lines); or 3) in different row and string groups, such that they have no signaling in common with one another. This flexibility of this actively-controlled matrix is distinguishable from the constraints typical to a passive matrix of rows and columns that is only controllable by scanning or writing to the entire matrix, one row or column at a time. Rather than driving an array of emitters row-by-row or column-by-column, each driver circuit 106 may be configured to independently drive all of their subset of pixel emitters in parallel, while the controller circuit 108 may provide direction to individual driver circuits 106 on an as needed basis (e.g., based on image content of incoming content frames).

[0065] To illustrate, FIG. 6 shows illustrative content frames that may be displayed using a tiled architecture such as shown in FIG. 5 in accordance with principles described herein. If each content frame 600 is divided into a grid of 16 portions 602-1 through 602-16 (i.e., portions 602-1, 602-2, 602-3, 602-4, 602-5, 602-6, 602-7, 602-8, 602-9, 602-10, 602-11,602-12, 602-13, 602-14, 602-15. and 602-16, corresponding to portions 402-1 through 402- 16 of direct-view display 302), FIG. 6 shows how image content included in each of these portions (i.e., image content associated with subsets of pixel emitters for each of the portions of the display) may change or remain unchanged from content frame to content frame, if there is image content at all.

[0066] For example, in accordance with the Key in the comer of FIG. 6 (described above in relation to FIG. 1), a first example content frame 600-A is shown to include no image content in any of its comer portions (i.e., portions 602-1, 602-4, 602-13, and 602-16), while having changed (i.e., new, updated) image content in the remainder of the display (i.e., portions 602-2. 602-3, 602-5 through 602-12, 602-14. and 602-15). A second example content frame 600-B is shown in FIG. 6 to include unchanged (i.e., static, already displayed) image content in all of the portions of the display (i.e., portions 602-1, 602-2, 602-5, 602-6, and 602-9 through 602-16) other than the four in the top-right comer (i.e., portions 602-3, 602-4, 602-7, and 602-8), which include changed image content. Yet another example content frame 600-C is also shown in FIG. 6 to include unchanged image content along the top portions of the display (i.e., portions 602-1 through 602-4) while including no content in the remainder of the display (i.e., portions 602-5 through 602-16).

[0067] These content frames 600-A through 600-C will be understood to be provided as examples of the types of content frames that might be typically displayed in a device such as a smartwatch, though they are provided strictly for illustrative purposes and are not limiting with respect to the many possible content frames that could be received by a controller circuit in a given implementation. For example, content frame 600-A could represent a watch face that is animated and fairly active in the middle while not having any content near the edges and comers. Content frame 600-B could represent a watch face that is dynamic in the top-right comer (e.g., to present the time) while presenting more static information (e.g., date and weather, etc.) on other portions of the display. Content frame 600- C could represent a low-power state (e.g., presented when it is detected that the user is unlikely to be viewing the display) in which basic information such as the time and date are presented at the top of the display (e.g., only changing once per second or once per minute depending on the time format) while the rest of the display shows no content to save power.

[0068] Given these and other similar configurations of content frames, each portion of the display (corresponding to a singular driver circuit and a subset of pixel emitters from the overall set of pixel emitters of the display) may be directed by a controller circuit to respond appropriately and efficiently to present the image content assigned to them to therebyproduce the images. As a first example, given a content frame such as content frame 600-B, a first subset of pixel emitters such as a subset associated with portion 602-8, and a second subset of pixels emitters such as a subset associated with portion 602-12, FIG. 6 shows that image content associated with the first subset of pixel emitters may change (from a previous content frame to content frame 600-B) while image content associated with the second subset of pixel emitters is unchanged (from the previous content frame to content frame 600-B). As another example, given a first content frame such as content frame 600-B, a second content frame such as content frame 600-C, a first subset of pixel emitters such as a subset associated with portion 602-1, and a second subset of pixels emitters such as a subset associated with portion 602-5, FIG. 6 shows that the first content frame includes image content (unchanged image content in this example) associated with both the first subset of pixel emitters and the second subset of pixel emitters, while the second content frame includes image content associated with the first subset of pixel emitters and is devoid of image content associated with the second subset of pixel emitters. As has been mentioned, based on the second content frame being devoid of image content associated with the second subset of pixel emitters, the controller circuit may be configured not only to have the driver circuit not drive the pixel emitters of the second subset for this second content frame, but may be further configured to cause the second driver circuit to power down while the second content frame is displayed.

[0069] Returning to FIG. 5, each of the address, advance, data, and clock lines provided by controller circuit 108 to the various driver circuits 106 in the tiled architecture will now be described in more detail to show how content frames such as content frames 600- A through 600-C may be displayed by the controller circuit transmitting signaling and frame data to the various driver circuits.

[0070] The address lines and data lines are orthogonal to one another to allow controller circuit 108 to provide frame data (e.g., for changed image content) to driver circuits 106 as appropriate. For example, the address lines may sen e to enable data transmission to row groups that include driver circuits 106 for which changed (updated) frame data is available, while the frame data itself may then be provided (e g., serially with an optional clock signal or with a self-clocking signal) to the driver circuit. For example, if updated frame data is available for the top-left driver circuit 106 in FIG. 5, controller circuit 108 may drive the address line associated with row group 502-1 while sending the data on the data line associated with string group 504-1. The content represented by the frame data may be presented by each driver circuit 106 using a pulse-width modulation (PWM) technique to advance through a plurality of bitplanes (i.e., subframes). Accordingly, the advance lines maybe used to direct each row group to update to the next bitplane in this type of implementation. In other examples, each tile driver could have its own timing circuitry such that the clock lines and / or advance lines from controller circuit 108 would not be needed. Various examples of different architectures in both of these categories will be described and illustrated in more detail below.

[0071] FIG. 7 shows an illustrative method 700 that a display assembly implementing a tiled architecture may perform in accordance with pnnciples described herein. For example, method 700 may be embodied within instructions stored in the display assembly. While FIG. 7 shows illustrative operations according to a specific implementation, it will be understood that other implementations of these methods may omit, add to, reorder, and / or modify any of operations 702-704 (or sub-operations 706-1 through 706-3) that are explicitly represented in FIG. 7. Each of the operations of method 700 will now be described in more detail as the operations may be performed by a controller circuit of a display assembly (e.g., such as an implementation of controller circuit 108 of display assembly 100).

[0072] At operation 702. the controller circuit may display a first content frame (i.e., cause the first content frame to be displayed) on a set of pixel emitters. For example, as has been described and illustrated, the set of pixel emitters may be transferred to a carrier substrate after fabrication of the set of pixel emitters. The set of pixel emitters may include a first subset of pixel emitters, a second subset of pixel emitters, and any suitable number of other subsets of pixel emitters as may serve a particular implementation.

[0073] As used herein, a controller circuit may display a content frame by directing, controlling, triggering, and / or otherwise causing the content frame to be displayed in any of the ways described herein. It will be understood that, in this sense, the controller circuit may display content frames without itself driving the pixel emitters or otherwise directly communicating with the display elements. Rather, as described herein, the displaying performed by the controller circuit may involve transmitting certain data to driver circuits so that these components (and, more particularly, modulation and pixel driver circuitry included therein) may drive the pixel emitters to cause the content frame to be presented. To accomplish operation 702. method 700 shows that the displaying of the first content frame may be performed by way of two sub-operations 706-1 and 706-2. In sub-operation 706-1, the controller circuit may transmit frame data to a first driver circuit disposed on the carrier substrate. For example, the first driver circuit may be configured to drive the first subset of pixel emitters to present image content associated with this frame data. In sub-operation 706- 2, the controller circuit may transmit frame data to a second driver circuit disposed on thecarrier substrate. The second driver circuit may be configured to drive the second subset of pixel emitters to present image content associated with this latter frame data.

[0074] At operation 704, the controller circuit may display a second content frame on the set of pixel emitters. However, whereas transmissions associated with both sub-operations 706-1 and 706-2 were performed to accomplish operation 702, operation 704 shows that the displaying of the second content frame (i.e., the causing of the second content frame to be displayed) may include a sub-operation 706-3 wherein frame data is transmitted to the first driver circuit while a note 708 indicates that this is done without also transmitting frame data to the second driver circuit (“(No transmission of frame data to second driver circuit)”). In other words, the displaying (or causing to be displayed) of the second content frame on the set of pixel emitters may be performed by transmitting frame data exclusively to the first driver circuit of the first driver circuit and the second driver circuit. As has been described, the second driver circuit may not require frame data for the second content frame since it may self-refresh to continue to display unchanged content, or it may not be assigned, for this second content frame, to display any content (in which case the second driver circuit could be powered down, as has been described).

[0075] While not explicitly shown in method 700, it will be understood that the controller circuit may make various determinations in the process of performing operations 702 and 704 and the various sub-operations (sub-operations 706-1 through 706-3) or lack thereof (note 708) associated therewith. For example, the controller circuit may: 1) determine, as a first determination, that image content associated with the first subset of pixel emitters changes from the first content frame to the second content frame; and 2) determine, as a second determination, that image content associated with the second subset of pixel emitters is unchanged from the first content frame to the second content frame. The transmitting of the frame data to the first driver circuit (at sub-operation 706-3) without transmitting frame data to the second driver circuit (at note 708) may therefore be performed based on these first and second determinations. As another example, the controller circuit may: 1) determine, as a first determination, that the first content frame includes image content associated with both the first subset of pixel emitters and the second subset of pixel emitters; and 2) determine, as a second determination, that the second content frame includes image content associated with the first subset of pixel emitters and is devoid of image content associated with the second subset of pixel emitters. The transmitting of the frame data to the first driver circuit (at sub-operation 706-1) and the transmitting of the frame data to the second driver circuit (at sub-operation 706-2) may then be performed based on this firstdetermination, while the transmitting of the frame data to the first driver circuit (at suboperation 706-3) without transmitting frame data to the second driver circuit (at note 708) may be performed based on this second determination.

[0076] In some implementations, a method such as method 700 may be embodied as a process within a memory. For example, a non-transitory computer-readable medium may store instructions that, when executed, cause a controller circuit of a display assembly (e g., an implementation of controller circuit 108 of display assembly 100) to perform a process embodying method 700. Specifically, when executing the instructions on the non-transitory computer-readable medium, the controller circuit may: 1) display a first content frame on a set of pixel emitters, the set of pixel emitters being transferred to a carrier substrate after fabrication of the set of pixel emitters and including a first subset of pixel emitters and a second subset of pixel emitters, the displaying of the first content frame including: (a) transmitting frame data to a first driver circuit disposed on the carrier substrate and configured to drive the first subset of pixel emitters, and (b) transmitting frame data to a second driver circuit disposed on the carrier substrate and configured to drive the second subset of pixel emitters; and 2) displaying a second content frame on the set of pixel emitters, the displaying of the second content frame including transmitting frame data to the first driver circuit without transmitting frame data to the second driver circuit.

[0077] The process embodied in these instructions may further include steps for making determinations such as described above. For example, the process may further include: 1) determining, as a first determination, that image content associated with the first subset of pixel emitters changes from the first content frame to the second content frame; and 2) determining, as a second detennination, that image content associated with the second subset of pixel emitters is unchanged from the first content frame to the second content frame. In this example, the transmitting of the frame data to the first driver circuit without transmitting frame data to the second driver circuit may be performed based on the first determination and the second determination. As another example, the process may further include: 1) determining, as a first determination, that the first content frame includes image content associated with both the first subset of pixel emitters and the second subset of pixel emitters; and 2) determining, as a second determination, that the second content frame includes image content associated with the first subset of pixel emitters and is devoid of image content associated with the second subset of pixel emitters. In this example, the transmitting of the frame data to the first driver circuit and the transmitting of the frame data to the second driver circuit may be performed based on the first determination, and thetransmitting of the frame data to the first driver circuit without transmitting frame data to the second driver circuit may be performed based on the second determination.

[0078] As has been described, the division of operations between a controller circuit within a display assembly (e.g., an implementation of controller circuit 108 in display assembly 100) and a plurality of driver circuits with which the controller circuit is communicatively coupled (e g., implementations of driver circuits 106) may be configured in various ways to achieve different tradeoffs for different design goals and / or circumstances. For example, one division of operation between the controller circuit and the display circuits may be selected to optimize power efficiency, another to optimize yield or cost efficiency, another to optimize display quality, and / or others to optimize other such design objectives. Additionally, certain divisions of operation could support fewer routing layers to help produce a thinner display, which may be more conducive to using a flexible carrier substrate and fabricating a display assembly configured to take on curved profiles. Other considerations may include fitting into a form factor of a particular size, distributing pixel emitters and driver circuits in a manner that allows for a transparent (or substantially transparent) display under which sensors or antennas could be implemented, and so forth.

[0079] To illustrate a few examples of how functional operations could be divided between the controller circuit and the driver circuits, FIGS. 8A-8E show a variety7of example implementations of tiled architectures for display assemblies with transferred pixel emitters in accordance with principles described herein. In each of FIGS. 8A-8E, a particular architecture (i.e., architecture 800-A in FIG. 8A, architecture 800-B in FIG. 8B, architecture 800-C in FIG. 8C, architecture 800-D in FIG. 8D, and architecture 800-E in FIG. 8E) is shown to include an implementation of controller circuit 108 communicatively coupled to an implementation of driver circuit 106. While only one driver circuit 106 is shown in each architecture, it will be understood that a plurality of similar driver circuits 106 may be communicatively coupled to each controller circuit 108 in the ways that have been described and illustrated.

[0080] A variety of functional blocks are represented in each of architectures 800-A through 800-E. most of which are implemented by either the controller circuit 108 or the driver circuits 106, though the distribution of the blocks to these integrated circuits is different from architecture to architecture. More particularly, a video source 801 is shown to be external to both the controller circuit 108 and the driver circuit 106 in each of the architectures, and then the blocks distributed between the integrated circuits include a video interface 805, a previous frame buffer 810, a display controller 815, a tile selector 820, apreprocessor 825, an incoming frame buffer 830, a postprocessor 840, a display frame buffer 850, a modulator 855, a sequencer 860, a driver 870, and a tile driver controller 875. An emitter 880 is also shown in each of FIG. 8A to represent a pixel emitter of the subset of pixel emitters being driven by the particular driver circuit 106 shown in the architecture. Each of these functional blocks will now be described individually, and a description will be provided of how the functional blocks may be distributed in different ways to create the various architectures 800-A through 800-E.

[0081] Video interface 805 represents the interface by which the display system (e.g., display assembly 100) receives video data from video source 801 (e.g., a display driver within a smartwatch device that sends video data to the display assembly to be presented). Video content may take the form of a sequence of content frames and video data may therefore describe the content in these frames using any suitable image or video format. As used herein, however, video data (of any format) is distinguished from bitplane data that may be derived therefrom. Both video data and bitplane data are types of frame data, as that term is used herein. However, whereas video data describes a content frame in one manner (e.g., as an array of pixels each assigned a particular chromaticity and luminosity, etc.), bitplane data describes individual subframes, typically using binary data for each subpixel, that may be presented in rapid succession within a frame period to thereby display the content frame. For example, video data received by video interface 805 may describe a pixel using several bits indicative of how red the pixel is, several bits indicative of how green the pixel is, and several bits indicative of how blue the pixel is (e g., 8 bits each for a 24-bit value describing the color of the pixel for the particular content frame, in one example). Bitplane data derived from this video data may then describe a number of subframes composed of binary values for each subpixel. For example, three bits (one for red, one for green, and one for blue) in each subframe may represent whether the red, green, and blue subpixels associated with the pixel described above are to be driven on or off during that subframe, and at least 8 subframes may be represented by the bitplane data to allow pulse-width modulation to be used to recreate the illustrative 24-bit video data described above.

[0082] Previous frame buffer 810 may be configured to buffer video data received at video interface 805 before providing frame data (e.g., either video data or bitplane data, depending on the architecture) from controller circuit 108 to the driver circuits 106. For example, previous frame buffer 810 may store one entire content frame so that respective portions of the content frame can be divided up and transmitted down to the various driver circuits 106. One advantage of maintaining the video data in this way may be to minimizedata traffic. For example, by comparing an incoming video frame to a previous video frame, a determination may be made as to what portions of the frame have changed and only these may be transmitted to their respective driver circuits (leaving the others to self-refresh in the ways that have been described).

[0083] Display controller 815 may be configured to manage the timing of the display. The updating of the display and the PWM modulation may be carefully orchestrated at both a frame level (where a global signal to control the overall timing may be provided) and at a more granular like level (where row-specific advance signaling may be implemented, such as described above). In implementations featuring clocking circuitry' (e.g., a phase-locked loop (PLL) circuit, etc.) in each driver circuit, the tasks of the display controller could essentially be handled by each driver circuit on its own. In other examples where the driver circuit does not have its own clocking circuitry’, the timing would be managed by the controller circuit and timing signals (e.g., clock signals, advance signals, etc.) would be provided to the driver circuits in the ways that have been described.

[0084] Tile selector 820 may be configured to compare a new (incoming) frame (i.e., video data received for the new frame at video interface 805) with a previous (currently- displayed) frame to determine which portions may have image content to display (as opposed to having no image content to display, as described above), and, of those portions that have image content, which portions include changed (new) content rather than maintaining unchanged (previous) content. As has been described, only those driver circuits associated with portions having changed content to display may need frame data to be transmitted. Those driver circuits associated with portions that either have unchanged content from the previous frame or no content may be allowed to self-refresh or may, in the no-content case, be powered down based on these determinations by tile selector 820. Along with determining w hich types of content are associated with each portion of new content frames, tile selector 820 may be further configured to determine where the frame data is to be routed (sometimes using information from previous frame buffer 810).

[0085] Preprocessor 825 may receive data from tile selector 820 once tile selector 820 determines what frame data is to be transmitted to which driver circuit 106. Together with postprocessor 840, preprocessor 825 may be responsible for a variety' of video processing functions that may be desirable for content before it is displayed. As will be described in more detail below, preprocessor 825 and postprocessor 840 may collectively perform various functions and may divide these functions between them in various suitable ways (e.g., depending on where the preprocessor 825 and the postprocessor 840 are implemented in agiven architecture, etc.). For example, these functions may include, without limitation, gamma decoding, color space conversion, coarse uniformity correction, pixel-by -pixel uniformity correction (i.e., demura), spatial and / or temporal dither, bitplane generation (including specific bitplanes for temporal dither), resampling, pixel shifting, color translation, and / or any other image processing as may serve a particular implementation. Upon the performance of zero or more of these functions at preprocessor 825, processed frame data (e.g.. either processed video data or. if it has been converted to bitplane data, processed bitplane data) may be prepared for storage at incoming frame buffer 830.

[0086] Incoming frame buffer 830 may be present along with previous frame buffer 810 to store data or, in some examples, only one or the other may be used. For instance, previous frame buffer 810 could be used to store a video data version of a content frame while incoming frame buffer 830 could be used to store bitplane data derived therefrom (e.g., as part of the operations performed by preprocessor 825). As another example, both previous frame buffer 810 and incoming frame buffer 830 could store video data of a given content frame, though one may do so within controller circuit 108 while the other is implemented, within the architecture, on the driver circuits 106.

[0087] Display frame buffer 850 may be specifically configured to store bitplane data once it has been generated. In this way, driver circuits 106 may be able to perform the selfrefresh functionality that has been described, in which a portion of content that the driver circuit 106 is responsible for may be displayed for any number of content frame periods until changed data for that portion is provided. In some architectures, both incoming frame buffer 830 and display frame buffer 850 may be implemented within driver circuit 106. For instance, incoming frame buffer 830 could store video data while display frame buffer 850 could store bitplane data after it is generated by postprocessor 840. In other architectures, only one of incoming frame buffer 830 and display frame buffer 850 may be implemented as their role could be rendered redundant depending on how much of the image processing is performed at preprocessor 825 versus at postprocessor 840. In architectures in which both frame buffers reside in the driver circuits 106 and postprocessor 840 does not change the data, a ping-pong buffer construction may be performed whereby no data is exchanged between incoming frame buffer 830 and display frame buffer 850 (thereby saving power).

[0088] Modulator 855 may be configured to receive timing data from sequencer 860 and bitplane data from display frame buffer 850 and to perform pulse-width modulation to drive the pixel emitters (by way of driver 870) to display the relevant portion of the content frame as a series of bitplanes or subframes (such as described above). For example, uponreceiving an advance signal from sequencer 860 that it is time for the next bitplane to be displayed, modulator 855 may direct each driver 870 for each pixel emitter that the driver circuits 106 is responsible for to either drive or cease driving its pixel emitter in accordance with the binary bitplane data for the next subframe in the sequence. Sequencer 860 receives timing data from display controller 815 and provides the advance signaling to modulator 855, as described above. Using display controller 815 and sequencer 860, both frame sequencing and subframe advancement may be accomplished as content frames are displayed.

[0089] Driver 870 may represent a single emitter driver of a set of emitter drivers that corresponds to each of the pixel emitters in the subset of pixel emitters the given driver circuit 106 is responsible for. As such, driver 870 may include a current source (or a voltage source) operating based on particular analog settings to drive the associated pixel emitter at a particular current or voltage that has been determined (e.g., as part of a calibration process) to be appropriate for the relative brightness and efficiency of the pixel emitter.

[0090] Tile driver controller 875 may manage various states for the driver circuits 106. As such, tile driver controller 875 may be involved when controller circuit 108 directs the driver circuit 106 to power down (e.g., when no content needs to be presented for a particular frame) or to otherwise put the driver circuit 106 into a low-power state that helps to conserve energy when appropriate.

[0091] As mentioned above, each of the architectures 800-A through 800-E may distribute and implement these various building blocks that have been described in different ways to accomplish different goals. Each of these architectures will now be described in more detail.

[0092] FIG. 8A shows architecture 800-A, in which video interface 805, previous frame buffer 810, display controller 815, tile selector 820, and preprocessor 825 are all implemented within controller circuit 108, while incoming frame buffer 830, postprocessor 840, display frame buffer 850, modulator 855, sequencer 860, driver 870, and tile driver controller 875 are all implemented w ithin the driver circuits 106.

[0093] In this example, the frame data associated with the content frame may be processed by a plurality of data processing operations (e.g.. the operations described above in relation to preprocessor 825 and postprocessor 840), which may be divided up between the controller circuit 108 and the driver circuits 106. More particularly, a first data processing operation (of this plurality of data processing operations) may be performed by the controller circuit (i.e., at preprocessor 825) prior to frame data associated with the content frame being transmitted to the driver circuits 106, while a second data processing operation (of thisplurality of data processing operations) may be performed by the driver circuits 106 (at postprocessor 840) after the frame data associated with the content frame is transmitted from the controller circuit.

[0094] Another aspect illustrated by architecture 800-A is that two frame buffers, incoming frame buffer 830 and display frame buffer 850, may both be implemented within the driver circuits 106 with certain data processing performed (at postprocessor 840) between the buffers. In particular, a first frame buffer (incoming frame buffer 830) and a second frame buffer (display frame buffer 850) may each be implemented within the driver circuits 106, the first frame buffer being configured to store video data for the content frames and the second frame buffer being configured to store bitplane data for the content frames. Accordingly, in this example, the frame data transmitted to the driver circuits may include video data for the content frames and the driver circuits (e.g., at postprocessor 840) may be configured to convert this video data into the bitplane data.

[0095] Y et another aspect illustrated by architecture 800-A is that both the sequencer and the modulator may be implemented on the driver circuits 106. More particularly, a given content frame may be associated with a set of content subframes (e.g., bitplanes represented by bitplane data) and may be displayed using pulse width modulation of the set of content subframes. To this end, the display assembly includes both sequencer 860 and modulator 855 on each driver circuit 106, and, based on a synchronization signal received from the controller circuit (e.g., from display controller 815). the sequencer 860 produces a timing signal (e.g., an advance signal) configured to facilitate displaying the set of content subframes in a timed sequence. Based on the timing signal, the modulator 855 causes the corresponding subset of pixel emitters to present image content associated with the subset of pixel emitters for each of the set of content subframes, as has been described.

[0096] FIG. 8B shows architecture 800-B, in which video interface 805, previous frame buffer 810, display controller 815, tile selector 820, preprocessor 825, and sequencer 860 are all implemented within controller circuit 108, while incoming frame buffer 830, postprocessor 840, display frame buffer 850, modulator 855, driver 870, and tile driver controller 875 are all implemented within the driver circuits 106. In other words, architecture 800-B may be similar to architecture 800-A except that sequencer 860 is implemented within the controller circuit 108 rather than duplicated in each of the driver circuits 106.

[0097] As with architecture 800-A, the frame data associated with the content frame in architecture 800-B may be processed by a plurality of data processing operations (e.g., the operations described above in relation to preprocessor 825 and postprocessor 840), whichmay be divided up between the controller circuit 108 and the driver circuits 106. Again, a first data processing operation may be performed by the controller circuit (i.e., at preprocessor 825) prior to frame data associated with the content frame being transmitted to the driver circuits 106, while a second data processing operation (of this plurality of data processing operations) may be performed by the driver circuits 106 (at postprocessor 840) after the frame data associated with the content frame is transmitted from the controller circuit. Additionally, architecture 800-B shows that both incoming frame buffer 830 and display frame buffer 850 may be implemented together within the driver circuits 106 with certain data processing performed (at postprocessor 840) between the buffers. Again, incoming frame buffer 830 and display frame buffer 850 may both be implemented within the driver circuits 106. but may be configured to store different forms of frame data (incoming frame buffer 830 storing video data for the content frames and display frame buffer 850 storing bitplane data for the content frames). As such, the frame data transmitted to driver circuits 106 may again include video data for the content frames and the driver circuits may (e.g., at postprocessor 840) convert this video data into the bitplane data.

[0098] In contrast to architecture 800- A, however, architecture 800-B illustrates that a sequencer implemented on the controller circuit may drive a modulator implemented on the driver circuit. More particularly, a given content frame may be associated with a set of content subframes and may be displayed using pulse width modulation of the set of content subframes. As such, architecture 800-B shows that the display assembly may include both: 1) a sequencer implemented on the controller circuit (i.e., sequencer 860), the sequencer transmitting a timing signal configured to facilitate displaying the set of content subframes in a timed sequence, and 2) a modulator implemented on the driver circuit (i.e., modulator 855), the modulator causing the respective subset of pixel emitters to present, based on the timing signal, image content associated with the subset of pixel emitters for each of the set of content subframes.

[0099] FIG. 8C shows architecture 800-C, in which video interface 805, previous frame buffer 810, display controller 815, tile selector 820, preprocessor 825, sequencer 860, incoming frame buffer 830, and postprocessor 840 are all implemented within controller circuit 108, while display frame buffer 850, modulator 855, driver 870, and tile driver controller 875 are all implemented within the driver circuits 106. In other words, architecture 800-C may be similar to architecture 800-B except that incoming frame buffer 830 and postprocessor 840 are both now implemented within the controller circuit 108 rather than being duplicated in each of the driver circuits 106.

[0100] In this example, the frame data associated with the content frame may again be processed by a plurality of data processing operations (e.g., the operations described above in relation to preprocessor 825 and postprocessor 840). However, rather than being divided up between the controller circuit 108 and the driver circuits 106 (as described above in relation to architectures 800-A and 800-B), architecture 800-C shows an implementation in which each data processing operation (of this plurality of data processing operations) may be performed by the controller circuit 108 prior to the frame data associated with the content frame being transmitted to the driver circuits 106. That is, whether performed by preprocessor 825 or postprocessor 840, all of the plurality of data process operations performed by this type of implementation may be performed by the controller circuit 108.

[0101] Another aspect illustrated by architecture 800-C (and distinct from architectures 800-A and 800-B) is that the incoming frame buffer 830 (which may store video data for the content frames) and the display frame buffer 850 (which may store bitplane data for the content frames) may be distributed on different integrated circuits such that bitplane data (rather than video data) is communicated between them. More particularly, a first frame buffer (incoming frame buffer 830) is shown to be implemented within the controller circuit 108, while a second frame buffer (display frame buffer 850) is shown to be implemented within the driver circuits 106. The first frame buffer may be configured to store video data for the content frames, while the second frame buffer may be configured to store bitplane data for the content frames. As such, the controller circuit 108 (at postprocessor 840) may be configured to convert the video data for the content frames into the bitplane data for the content frames and the frame data transmitted to the driver circuits 106 may include the bitplane data for the content frames.

[0102] Similar to architecture 800-B (though in contrast to architecture 800-A), architecture 800-C illustrates that a sequencer implemented on the controller circuit may drive a modulator implemented on the driver circuit. More particularly, a given content frame may be associated with a set of content subframes and may be displayed using pulse width modulation of the set of content subframes. As such, architecture 800-C shows that the display assembly may include both: 1) a sequencer implemented on the controller circuit (i.e., sequencer 860), the sequencer transmitting a timing signal configured to facilitate displaying the set of content subframes in a timed sequence, and 2) a modulator implemented on the driver circuit (i.e., modulator 855), the modulator causing the respective subset of pixel emitters to present, based on the timing signal, image content associated with the subset of pixel emitters for each of the set of content subframes.

[0103] FIG. 8D shows architecture 800-D, in which video interface 805, previous frame buffer 810, display controller 815, tile selector 820, preprocessor 825, incoming frame buffer 830, and postprocessor 840 are all implemented within controller circuit 108, while display frame buffer 850, modulator 855, sequencer 860, driver 870, and tile driver controller 875 are all implemented within the driver circuits 106. In other words, architecture 800-D may be similar to architecture 800-C except that, like architecture 800- A. sequencer 860 is implemented within each of the driver circuits 106 rather than within the controller circuit 108.

[0104] In this configuration, architecture 800-D may, like architecture 800-C, perform all of the data processing operations on the controller circuit 108 prior to the frame data associated with the content frame being transmitted to the driver circuits 106. Additionally, also like architecture 800-C, architecture 800-D may distribute the different frame buffers (i.e., incoming frame buffer 830 and display frame buffer 850) to different integrated circuits such that bitplane data (rather than video data) is communicated between them. However, like architecture 800-A (and in contrast to architecture 800-C), architecture 800-D shows that both the sequencer and the modulator may be implemented on the driver circuits 106, such that, based on a synchronization signal received from the controller circuit (e.g., from display controller 815), the sequencer 860 produces a timing signal (e.g., an advance signal) configured to facilitate displaying the set of content subframes in a timed sequence. Then, based on the timing signal, the modulator 855 causes the corresponding subset of pixel emitters to present image content associated with the subset of pixel emitters for each of the set of content subframes.

[0105] FIG. 8E shows architecture 800-E, which is notably distinct from architectures 800-A through 800-D since it shows an example in which a hierarchy of multiple controller circuits 108-1 and 108-2 may perform the role that has previously been described as being performed by a single integrated circuit. More particularly, as shown, both controller circuits 108-1 and 108-2 may include a respective video interface 805, a respective previous frame buffer 810, a respective display controller 815, a respective tile selector 820, and a respective preprocessor 825, while the driver circuits 106 (only one of which is shown and all of which would be connected to controller circuit 108-2 or other controller circuits downstream from controller circuit 108-1) include the incoming frame buffer 830, the postprocessor 840, the display frame buffer 850, the modulator 855, the sequencer 860, the driver 870, and the tile driver controller 875. In other words, architecture 800-E may be similar to architecture 800-A except that multiple controller circuits are cascaded to facilitate higher performance displayassemblies (e.g., display assemblies with higher resolutions, higher frame rates, etc.). It will be understood that one higher-level controller circuit (e.g., controller circuit 108-1) may be configured to control a plurality of lower-level controller circuits (e.g., controller circuit 108- 2), each of which may, in turn, be responsible for its own plurality of driver circuits (e.g., driver circuits 106) that correspond to their ow n subsets of pixel emitters. In this way, a hierarchy with an arbitrary number of levels may be implemented to allow display assemblies to scale to arbitrary sizes, display resolutions, and other such parameters.

[0106] As has been mentioned, various methods and processes described herein may be implemented at least in part as instructions embodied in a non-transitory computer- readable medium and executable by one or more computing devices. In general, a processor (e.g., a microprocessor) receives instructions, from a non-transitory computer-readable medium (e.g., a memory, etc.), and executes those instructions, thereby performing one or more operations such as the operations described herein. Such instructions may be stored and / or transmitted using any of a variety of known computer-readable media.

[0107] A computer-readable medium (also referred to as a processor-readable medium) includes any non-transitory medium that participates in providing data (e.g., instructions) that may be read by a computer (e.g., by a processor of a computer). Such a medium may take many forms, including, but not limited to, non-volatile media, and / or volatile media. Non-volatile media may include, for example, optical or magnetic disks and other persistent memory. Volatile media may include, for example, dynamic random-access memory (DRAM), which typically constitutes a main memory. Common forms of computer- readable media include, for example, a disk, hard disk, magnetic tape, any other magnetic medium, a compact disc read-only memory (CD-ROM), a digital video disc (DVD), any other optical medium, random access memory (RAM), programmable read-only memory (PROM), electrically erasable programmable read-only memory (EPROM), FLASH- EEPROM, any7other memory chip or cartridge, or any other tangible medium from which a computer can read.

[0108] FIG. 9 shows an illustrative computing system 900 that may be used to implement various devices and / or systems described herein. For example, computing system 900 may include or implement (or partially implement) display assemblies (e.g., display assembly 100) described herein, devices featuring such as display assemblies, any implementations thereof, any components thereof, and / or other devices used therewith.

[0109] As shown in FIG. 9, computing system 900 may include a communication interface 902, a processor 904, a storage device 906, and an input / output (I / O) module 908communicatively connected via a communication infrastructure 910. While an illustrative computing system 900 is shown in FIG. 9, the components illustrated in FIG. 9 are not intended to be limiting. Additional or alternative components may be used in other embodiments. Components of computing system 900 show n in FIG. 9 will now be described in additional detail.

[0110] Communication interface 902 may be configured to communicate with one or more computing devices. Examples of communication interface 902 include, without limitation, a wired network interface (such as a network interface card), a wireless network interface (such as a wireless network interface card), a modem, an audio / video connection, and any other suitable interface.

[0111] Processor 904 generally represents any type or form of processing unit capable of processing data or interpreting, executing, and / or directing execution of one or more of the instructions, processes, and / or operations described herein. Processor 904 may direct execution of operations in accordance with one or more applications 912 or other computerexecutable instructions such as may be stored in storage device 906 or another computer- readable medium.

[0112] Storage device 906 may include one or more data storage media, devices, or configurations and may employ any ty pe, form, and combination of data storage media and / or device. For example, storage device 906 may include, but is not limited to, a hard drive, network drive, flash drive, magnetic disc, optical disc, RAM. dynamic RAM, other non-volatile and / or volatile data storage units, or a combination or sub-combination thereof. Electronic data, including data described herein, may be temporarily and / or permanently stored in storage device 906. For example, data representative of one or more executable applications 912 configured to direct processor 904 to perform any of the operations described herein may be stored within storage device 906. In some examples, data may be arranged in one or more databases residing within storage device 906.

[0113] I / O module 908 may include one or more I / O modules configured to receive user input and provide user output. One or more I / O modules may be used to receive input for a single virtual experience. I / O module 908 may include any hardware, firmware, software, or combination thereof supportive of input and output capabilities. For example, I / O module 908 may include hardware and / or software for capturing user input, including, but not limited to, a keyboard or key pad, a touchscreen component (e.g., touchscreen display), a receiver (e.g.. an RF or infrared receiver), motion sensors, and / or one or more input buttons.

[0114] I / O module 908 may include one or more devices for presenting output to auser, including, but not limited to, a graphics engine, a display (e.g., a display screen), one or more output drivers (e.g., display drivers), one or more audio speakers, and one or more audio drivers. In certain embodiments, I / O module 908 is configured to provide graphical data to a display for presentation to a user. The graphical data may be representative of one or more graphical user interfaces and / or any other graphical content as may sen e a particular implementation.

[0115] The following examples describe implementations of tiled architectures for display assemblies with transferred pixel emitters in accordance with principles described herein.

[0116] Example 1. 1 : A display assembly comprising: a set of pixel emitters disposed on a carrier substrate, the set of pixel emitters including a first subset of pixel emitters and a second subset of pixel emitters; a first driver circuit disposed on the carrier substrate and configured to drive the first subset of pixel emitters; a second driver circuit disposed on the carrier substrate and configured to drive the second subset of pixel emitters; and a controller circuit configured to: display a first content frame on the set of pixel emitters by transmitting frame data both to the first driver circuit and the second driver circuit, and display a second content frame on the set of pixel emitters by transmitting frame data to the first driver circuit without transmitting frame data to the second driver circuit.

[0117] Example 1.2: A display assembly comprising: a set of pixel emitters disposed on a carrier substrate, the set of pixel emitters including a first subset of pixel emitters and a second subset of pixel emitters; a first driver circuit disposed on the carrier substrate and configured to drive the first subset of pixel emitters; a second driver circuit disposed on the carrier substrate and configured to drive the second subset of pixel emitters; and a controller circuit configured to: cause a displaying of a first content frame on the set of pixel emitters by transmitting frame data both to the first driver circuit and the second driver circuit, and cause a displaying of a second content frame on the set of pixel emitters by transmitting frame data to the first driver circuit without transmitting frame data to the second driver circuit.

[0118] Example 1.3: A display assembly comprising: a set of pixel emitters disposed on a carrier substrate, the set of pixel emitters including a first subset of pixel emitters and a second subset of pixel emitters; a first driver circuit disposed on the carrier substrate and configured to drive the first subset of pixel emitters; a second driver circuit disposed on the carrier substrate and configured to drive the second subset of pixel emitters; and a controller circuit configured to: cause a displaying of a first content frame on the set of pixel emitters by transmitting frame data both to the first driver circuit and the second driver circuit, and causea displaying of a second content frame on the set of pixel emitters by transmitting frame data exclusively to the first driver circuit of the first driver circuit and the second driver circuit.

[0119] Example 2: The display assembly of any of Examples 1. 1 to 1.3, wherein: image content associated with the first subset of pixel emitters changes from the first content frame to the second content frame; and image content associated with the second subset of pixel emitters is unchanged from the first content frame to the second content frame.

[0120] Example 3: The display assembly of any of Examples 1.1 to 1.3, wherein: the first content frame includes image content associated with both the first subset of pixel emitters and the second subset of pixel emitters; and the second content frame includes image content associated with the first subset of pixel emitters and is devoid of image content associated with the second subset of pixel emitters.

[0121] Example 4: The display assembly of Example 3, wherein, based on the second content frame being devoid of image content associated with the second subset of pixel emitters, the controller circuit is further configured to cause the second driver circuit to power down while the second content frame is displayed.

[0122] Example 5: The display assembly of any of the preceding examples, wherein: the set of pixel emitters is transferred to the carrier substrate from a donor wafer on which the set of pixel emitters is fabricated; and the set of pixel emitters is fabricated at a first pixel pitch on the donor wafer and is distributed on the carrier substrate at a second pixel pitch greater than the first pixel pitch.

[0123] Example 6. 1 : The display assembly of any of the preceding examples, wherein: the controller circuit is communicatively coupled to the first driver circuit and the second driver circuit by way of an architecture in which driver circuits are organized into row groups and string groups; the first driver circuit is included in a first row group, the first row group having an address line that is shared by each of the driver circuits in the first row group and is not shared by driver circuits outside of the first row group; and the first driver circuit is included in a first string group, the first string group having a data line that is shared by each of the driver circuits in the first string group and is not shared by driver circuits outside of the first string group.

[0124] Example 6.2: The display assembly of any of the preceding examples, wherein: the controller circuit is communicatively coupled to the first driver circuit and the second driver circuit by way of an architecture in which driver circuits are organized into row groups and string groups; the first driver circuit is included in a first row group, the first row group having an address line that is shared exclusively by each of the driver circuits in thefirst row group; and the first driver circuit is included in a first string group, the first string group having a data line that is shared exclusively by each of the driver circuits in the first string group.

[0125] Example 7: The display assembly of any of the preceding examples, wherein: frame data associated with the first content frame is processed by a plurality of data processing operations; a first data processing operation of the plurality of data processing operations is performed by the controller circuit prior to the frame data associated with the first content frame being transmitted to the first driver circuit and the second driver circuit; and a second data processing operation of the plurality' of data processing operations is performed by the first driver circuit and the second driver circuit after the frame data associated with the first content frame is transmitted from the controller circuit.

[0126] Example 8: The display assembly of any of Examples 1.1 to 6.2, wherein: frame data associated with the first content frame is processed by a plurality of data processing operations; and each data processing operation of the plurality of data processing operations is performed by the controller circuit prior to the frame data associated with the first content frame being transmitted to the first driver circuit and the second driver circuit.

[0127] Example 9: The display assembly of any of the preceding examples, further including a first frame buffer and a second frame buffer each implemented within the first driver circuit, the first frame buffer being configured to store video data for the first content frame and the second frame buffer being configured to store bitplane data for the first content frame; the frame data transmitted to the first driver circuit includes the video data for the first content frame; and the first driver circuit is configured to convert the video data for the first content frame into the bitplane data for the first content frame.

[0128] Example 10: The display assembly of any of Examples 1.1 to 8. further including a first frame buffer implemented within the controller circuit and a second frame buffer implemented within the first driver circuit, the first frame buffer being configured to store video data for the first content frame and the second frame buffer being configured to store bitplane data for the first content frame; the controller circuit is configured to convert the video data for the first content frame into the bitplane data for the first content frame; and the frame data transmitted to the first driver circuit includes the bitplane data for the first content frame.

[0129] Example 11 : The display assembly of any of the preceding examples, wherein: the first content frame is associated with a set of content subframes and is displayed using pulse width modulation of the set of content subframes; and the display assembly furthercomprises: a sequencer implemented on the controller circuit, the sequencer transmitting a timing signal configured to facilitate displaying the set of content subframes in a timed sequence, and a modulator implemented on the first driver circuit, the modulator causing the first subset of pixel emitters to present, based on the timing signal, image content associated with the first subset of pixel emitters for each of the set of content subframes.

[0130] Example 12: The display assembly of any of Examples 1.1 to 10, wherein: the first content frame is associated with a set of content subframes and is displayed using pulse width modulation of the set of content subframes; the display assembly further comprises a sequencer and a modulator both implemented on the first driver circuit; based on a synchronization signal received from the controller circuit, the sequencer produces a timing signal configured to facilitate displaying the set of content subframes in a timed sequence; and based on the timing signal, the modulator causes the first subset of pixel emitters to present image content associated with the first subset of pixel emitters for each of the set of content subframes.

[0131] Example 13: The display assembly of any of the preceding examples, wherein: the set of pixel emitters is implemented by a set of micro light emitting diodes (microLEDs); and the first driver circuit and the second driver circuit are implemented by complementary - metal-oxide-semiconductor (CMOS) integrated circuits.

[0132] Example 14: The display assembly of any of the preceding examples, wherein the display assembly is configured for use as a smartwatch display.

[0133] Example 15.1 : A method comprising: displaying, by a controller circuit, a first content frame on a set of pixel emitters, the set of pixel emitters being transferred to a carrier substrate after fabrication of the set of pixel emitters and including a first subset of pixel emitters and a second subset of pixel emitters, the displaying of the first content frame including: transmitting frame data to a first driver circuit disposed on the earner substrate and configured to drive the first subset of pixel emitters, and transmitting frame data to a second driver circuit disposed on the carrier substrate and configured to drive the second subset of pixel emitters; and displaying, by the controller circuit, a second content frame on the set of pixel emitters, the displaying of the second content frame including transmitting frame data to the first driver circuit without transmitting frame data to the second driver circuit.

[0134] Example 15.2: A method comprising: causing, by a controller circuit, a displaying of a first content frame on a set of pixel emitters, the set of pixel emitters being disposed on a carrier substrate and including a first subset of pixel emitters and a second subset of pixel emitters, the displaying of the first content frame including: transmitting framedata to a first driver circuit disposed on the carrier substrate and configured to drive the first subset of pixel emitters, and transmitting frame data to a second driver circuit disposed on the carrier substrate and configured to drive the second subset of pixel emitters; and causing, by the controller circuit, a displaying of a second content frame on the set of pixel emitters, the displaying of the second content frame including transmitting frame data exclusively to the first driver circuit of the first driver circuit and the second driver circuit.

[0135] Example 16: The method of any of Examples 15.1 to 15.2, further comprising: determining, as a first determination, that image content associated with the first subset of pixel emitters changes from the first content frame to the second content frame; and determining, as a second determination, that image content associated with the second subset of pixel emitters is unchanged from the first content frame to the second content frame; wherein the transmitting of the frame data to the first driver circuit (exclusively, or without transmitting frame data to the second driver circuit) is performed based on the first determination and the second determination.

[0136] Example 17: The method of any of Examples 15.1 to 15.2, further comprising: determining, as a first determination, that the first content frame includes image content associated with both the first subset of pixel emitters and the second subset of pixel emitters; and determining, as a second determination, that the second content frame includes image content associated with the first subset of pixel emitters and is devoid of image content associated with the second subset of pixel emitters; wherein: the transmitting of the frame data to the first driver circuit and the transmitting of the frame data to the second driver circuit are performed based on the first determination, and the transmitting of the frame data to the first driver circuit (exclusively, or without transmitting frame data to the second driver circuit) is performed based on the second determination.

[0137] Example 18.1 : A non-transitory computer-readable medium storing instructions that, when executed, cause a controller circuit of a display assembly to perform a process comprising: displaying a first content frame on a set of pixel emitters, the set of pixel emitters being disposed on a carrier substrate and including a first subset of pixel emitters and a second subset of pixel emitters, the displaying of the first content frame including: transmitting frame data to a first driver circuit disposed on the carrier substrate and configured to drive the first subset of pixel emitters, and transmitting frame data to a second driver circuit disposed on the carrier substrate and configured to drive the second subset of pixel emitters; and displaying a second content frame on the set of pixel emitters, the displaying of the second content frame including transmitting frame data to the first drivercircuit without transmitting frame data to the second driver circuit.

[0138] Example 18.2: A non-transitory computer-readable medium storing instructions that, when executed, cause a controller circuit of a display assembly to perform a process comprising: causing a displaying of a first content frame on a set of pixel emitters, the set of pixel emitters being disposed on a carrier substrate emitters and including a first subset of pixel emitters and a second subset of pixel emitters, the displaying of the first content frame including: transmitting frame data to a first driver circuit disposed on the carrier substrate and configured to drive the first subset of pixel emitters, and transmitting frame data to a second driver circuit disposed on the carrier substrate and configured to drive the second subset of pixel emitters; and displaying a second content frame on the set of pixel emitters, the displaying of the second content frame including transmitting frame data exclusively to the first driver circuit of the first driver circuit and the second driver circuit.

[0139] Example 19: The non-transitory computer-readable medium of any of Examples 18.1 to 18.2, wherein: the process further comprises: determining, as a first determination, that image content associated with the first subset of pixel emitters changes from the first content frame to the second content frame; and determining, as a second determination, that image content associated with the second subset of pixel emitters is unchanged from the first content frame to the second content frame; and the transmitting of the frame data to the first driver circuit (exclusively, or without transmitting frame data to the second driver circuit) is performed based on the first determination and the second determination.

[0140] Example 20: The non-transitory computer-readable medium of any of Examples 18.1 to 18.2, wherein: the process further comprises: determining, as a first determination, that the first content frame includes image content associated with both the first subset of pixel emitters and the second subset of pixel emitters; and determining, as a second determination, that the second content frame includes image content associated with the first subset of pixel emitters and is devoid of image content associated with the second subset of pixel emitters; the transmitting of the frame data to the first driver circuit and the transmitting of the frame data to the second driver circuit are performed based on the first determination, and the transmitting of the frame data to the first driver circuit (exclusively, or without transmitting frame data to the second driver circuit) is performed based on the second determination.

[0141] Various implementations of the systems and techniques described herein can be realized in digital electronic circuitry, integrated circuitry, specially designed ASICs(application specific integrated circuits), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0142] A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the description and claims. In addition, the logic flows depicted in the figures do not require the particular order shown, or sequential order, to achieve desirable results. In addition, other steps may be provided, or steps may be eliminated, from the described flows, and other components may be added to, or removed from, the described systems. Accordingly, other implementations are within the scope of the following claims.

[0143] Specific structural and functional details disclosed herein are merely representative for purposes of describing example implementations. Example implementations, however, may be embodied in many alternate forms and should not be construed as limited to only the implementations set forth herein.

[0144] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. A first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the implementations of the disclosure. As used herein, the term and / or includes any and all combinations of one or more of the associated listed items.

[0145] The terminology used herein is for the purpose of describing particular implementations only and is not intended to be limiting of the implementations. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and / or “including,” when used in this specification, specify the presence of the stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0146] It will be understood that when an element is referred to as being “coupled,” “connected,” or “responsive” to, or “on,” another element, it can be directly coupled,connected, or responsive to, or on, the other element, or interv ening elements may also be present. In contrast, when an element is referred to as being ‘"directly coupled,’7“directly connected,” or “directly responsive” to, or “directly on,” another element, there are no intervening elements present. As used herein the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0147] Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper.” and the like, may be used herein for ease of description to describe one element or feature in relationship to another element(s) or feature(s) as illustrated in the figures. It wi 11 be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 130 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0148] Unless otherwise defined, the terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which these concepts belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0149] Further to the descriptions above, a user may be provided with controls allowing the user to make an election as to both if and when systems, programs, or features described herein may enable collection of user information (e.g., information about a user's social network, social actions, or activities, profession, a user's preferences, or a user's current location), and if the user is sent content or communications from a server. In addition, certain data may be treated in one or more ways before it is stored or used, so that personally identifiable information is removed. For example, a user's identity may be treated so that no personally identifiable information can be determined for the user, or a user's geographic location may be generalized, or location information may be obtained (such as to a city, zip code, or state level), so that a particular location of a user cannot be determined. Thus, the user may have control over what information is collected about the user, how that information is used, and what information is provided to the user.

[0150] While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes, and equivalents may occur to those skilled in the art. It is therefore to be understood that the appended claims are intended to cover such modifications and changes as fall within the scope of the implementations. It will be understood that they have been presented by way of example only, not limitation, and various changes in form and details may be made. Any portion of the apparatus and / or methods described herein may be combined in any combination, except mutually exclusive combinations. The implementations described herein can include various combinations and / or sub-combinations of the functions, components, and / or features of the different implementations described. As such, the scope of the present disclosure is not limited to the particular combinations hereafter claimed, but instead extends to encompass any combination of features or example implementations described herein irrespective of whether or not that particular combination has been specifically enumerated in the accompanying claims at this time.

Claims

WHAT IS CLAIMED IS:

1. A display assembly comprising: a set of pixel emitters disposed on a carrier substrate, the set of pixel emitters including a first subset of pixel emitters and a second subset of pixel emitters; a first driver circuit disposed on the carrier substrate and configured to drive the first subset of pixel emitters; a second driver circuit disposed on the carrier substrate and configured to drive the second subset of pixel emitters; and a controller circuit configured to: display a first content frame on the set of pixel emitters by transmitting frame data both to the first driver circuit and the second driver circuit, and display a second content frame on the set of pixel emitters by transmitting frame data to the first driver circuit without transmitting frame data to the second driver circuit.

2. The display assembly of claim 1, wherein: image content associated with the first subset of pixel emitters changes from the first content frame to the second content frame; and image content associated with the second subset of pixel emitters is unchanged from the first content frame to the second content frame.

3. The display assembly of claim 1, wherein: the first content frame includes image content associated with both the first subset of pixel emitters and the second subset of pixel emitters; and the second content frame includes image content associated with the first subset of pixel emitters and is devoid of image content associated with the second subset of pixel emitters.

4. The display assembly of claim 3, wherein, based on the second content frame being devoid of image content associated with the second subset of pixel emitters, the controller circuit is further configured to cause the second driver circuit to power down while the second content frame is displayed.

5. The display assembly of any of claims 1 to 4, wherein: the set of pixel emitters is transferred to the carrier substrate from a donor wafer on which the set of pixel emitters is fabricated; and the set of pixel emitters is fabricated at a first pixel pitch on the donor wafer and is distributed on the carrier substrate at a second pixel pitch greater than the first pixel pitch.

6. The display assembly of any of claims 1 to 5, wherein: the controller circuit is communicatively coupled to the first driver circuit and the second driver circuit by way of an architecture in which driver circuits are organized into row groups and string groups; the first driver circuit is included in a first row group, the first row group having an address line that is shared by each of the driver circuits in the first row group and is not shared by driver circuits outside of the first row group; and the first driver circuit is included in a first string group, the first string group having a data line that is shared by each of the driver circuits in the first string group and is not shared by driver circuits outside of the first string group.

7. The display assembly of any of claims 1 to 6, wherein: frame data associated with the first content frame is processed by a plurality of data processing operations; a first data processing operation of the plurality of data processing operations is performed by the controller circuit prior to the frame data associated with the first content frame being transmitted to the first driver circuit and the second driver circuit; and a second data processing operation of the plurality of data processing operations is performed by the first driver circuit and the second driver circuit after the frame data associated with the first content frame is transmitted from the controller circuit.

8. The display assembly of any of claims 1 to 6, wherein: frame data associated with the first content frame is processed by a plurality of data processing operations; and each data processing operation of the plurality of data processing operations is performed by the controller circuit prior to the frame data associated with the first content frame being transmitted to the first driver circuit and the second driver circuit.

9. The display assembly of any of claims 1 to 8, further including a first frame buffer and a second frame buffer each implemented within the first driver circuit, the first frame buffer being configured to store video data for the first content frame and the second frame buffer being configured to store bitplane data for the first content frame; the frame data transmitted to the first driver circuit includes the video data for the first content frame; and the first driver circuit is configured to convert the video data for the first content frame into the bitplane data for the first content frame.

10. The display assembly of any of claims 1 to 8, further including a first frame buffer implemented within the controller circuit and a second frame buffer implemented within the first driver circuit, the first frame buffer being configured to store video data for the first content frame and the second frame buffer being configured to store bitplane data for the first content frame; the controller circuit is configured to convert the video data for the first content frame into the bitplane data for the first content frame; and the frame data transmitted to the first driver circuit includes the bitplane data for the first content frame.

11. The display assembly of any of claims 1 to 10. wherein: the first content frame is associated with a set of content subframes and is displayed using pulse width modulation of the set of content subframes; and the display assembly further comprises: a sequencer implemented on the controller circuit, the sequencer transmitting a timing signal configured to facilitate displaying the set of content subframes in a timed sequence, and a modulator implemented on the first driver circuit, the modulator causing the first subset of pixel emitters to present, based on the timing signal, image content associated with the first subset of pixel emitters for each of the set of content subframes.

12. The display assembly of any of claims 1 to 10, wherein: the first content frame is associated with a set of content subframes and is display ed using pulse width modulation of the set of content subframes:the display assembly further comprises a sequencer and a modulator both implemented on the first driver circuit; based on a synchronization signal received from the controller circuit, the sequencer produces a timing signal configured to facilitate displaying the set of content subframes in a timed sequence; and based on the timing signal, the modulator causes the first subset of pixel emitters to present image content associated with the first subset of pixel emitters for each of the set of content subframes.

13. The display assembly of any of claims 1 to 12. wherein: the set of pixel emitters is implemented by a set of micro light emitting diodes (microLEDs); and the first driver circuit and the second driver circuit are implemented by complementary-metal-oxide-semiconductor (CMOS) integrated circuits.

14. The display assembly of any of claims 1 to 13. wherein the display assembly is configured for use as a smartwatch display.

15. A method comprising: displaying, by a controller circuit, a first content frame on a set of pixel emitters, the set of pixel emitters being transferred to a carrier substrate after fabrication of the set of pixel emitters and including a first subset of pixel emitters and a second subset of pixel emitters, the displaying of the first content frame including: transmitting frame data to a first driver circuit disposed on the carrier substrate and configured to drive the first subset of pixel emitters, and transmitting frame data to a second driver circuit disposed on the carrier substrate and configured to drive the second subset of pixel emitters; and displaying, by the controller circuit, a second content frame on the set of pixel emitters, the displaying of the second content frame including transmitting frame data to the first driver circuit without transmitting frame data to the second driver circuit.

16. The method of claim 15, further comprising: determining, as a first determination, that image content associated with the first subset of pixel emitters changes from the first content frame to the second content frame; anddetermining, as a second determination, that image content associated with the second subset of pixel emitters is unchanged from the first content frame to the second content frame; wherein the transmitting of the frame data to the first driver circuit without transmitting frame data to the second driver circuit is performed based on the first determination and the second determination.

17. The method of claim 15, further comprising: determining, as a first determination, that the first content frame includes image content associated with both the first subset of pixel emitters and the second subset of pixel emitters; and determining, as a second determination, that the second content frame includes image content associated with the first subset of pixel emitters and is devoid of image content associated with the second subset of pixel emitters; wherein: the transmitting of the frame data to the first driver circuit and the transmitting of the frame data to the second driver circuit are performed based on the first determination, and the transmitting of the frame data to the first driver circuit without transmitting frame data to the second driver circuit is performed based on the second determination.

18. A non-transitory computer-readable medium storing instructions that, when executed, cause a controller circuit of a display assembly to perform a process comprising: displaying a first content frame on a set of pixel emitters, the set of pixel emitters being disposed on a carrier substrate and including a first subset of pixel emitters and a second subset of pixel emitters, the displaying of the first content frame including: transmitting frame data to a first driver circuit disposed on the carrier substrate and configured to drive the first subset of pixel emitters, and transmitting frame data to a second driver circuit disposed on the carrier substrate and configured to drive the second subset of pixel emitters; and displaying a second content frame on the set of pixel emitters, the displaying of the second content frame including transmitting frame data to the first driver circuit without transmitting frame data to the second driver circuit.

19. The non-transitory computer-readable medium of claim 18, wherein: the process further comprises: determining, as a first determination, that image content associated with the first subset of pixel emitters changes from the first content frame to the second content frame; and determining, as a second determination, that image content associated with the second subset of pixel emitters is unchanged from the first content frame to the second content frame; and the transmitting of the frame data to the first driver circuit without transmitting frame data to the second driver circuit is performed based on the first determination and the second determination.

20. The non-transitory computer-readable medium of claim 18, wherein: the process further comprises: determining, as a first determination, that the first content frame includes image content associated with both the first subset of pixel emitters and the second subset of pixel emitters; and determining, as a second determination, that the second content frame includes image content associated with the first subset of pixel emitters and is devoid of image content associated with the second subset of pixel emitters; the transmitting of the frame data to the first driver circuit and the transmitting of the frame data to the second driver circuit are performed based on the first determination, and the transmitting of the frame data to the first driver circuit without transmitting frame data to the second driver circuit is performed based on the second determination.

Images