Direct-view display assembly with sparse distribution of pixel emitters

Abstract

Direct-view display assemblies with sparse distributions of pixel emitters are described herein, along with methods for their construction. One example display assembly includes a set of pixel emitters that are transferred to the display assembly from a donor wafer on which the pixel emitters were fabricated. While fabricated at a first pixel pitch, these pixel emitters are distributed within the display assembly at a second pixel pitch greater than the first pixel pitch. The display assembly further includes a first driver circuit electrically coupled to a first subset of the set of pixel emitters via a first set of emitter traces, a second driver circuit electrically coupled to a second subset of the set of pixel emitters via a second set of emitter traces, and a controller circuit electrically coupled to the first driver circuit and the second driver circuit via a set of controller traces.

Description

DIRECT-VIEW DISPLAY ASSEMBLY WITHSPARSE DISTRIBUTION OF PIXEL EMITTERSCROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority- to, and the benefit of, U.S. Provisional Application No. 63 / 595,950, filed on November 3, 2023, the disclosure of which is hereby incorporated by reference in its entirety.BACKGROUND

[0002] Semiconductor fabrication processes allow for the creation of extremely small electronic components such as transistors, resistors, capacitors, light emitting diodes (LEDs), and so forth. Fabrication of these semiconductor products may involve a series of precise steps, including depositing thin films of materials, patterning circuits using photolithography and etching techniques, and connecting everything through metallization.

[0003] For many electronic components, it may be advantageous to miniaturize the components to a nearly unlimited extent. For instance, the more that transistor logic can be miniaturized, the more functionality (e.g., processing and storage capability) may fit on a single chip to result in electronic devices that are portable, light, low power, and so forth. For other electronic components, however, their usefulness may be limited as the components become smaller in size. As one example, micro light emitting diodes (microLEDs) and other small light emission components used as pixels in electronic displays may, when miniaturized beyond a certain extent, become so small that magnification is required for a user to see and appreciate the high resolution being provided. While such magnification may be acceptable or desirable for certain applications, the high resolution possible with these ty pes of pixel emitters may be wasteful and undesirable for direct-view applications in which display screens are not magnified.SUMMARY

[0004] Certain pixel emitters, such as microLEDs, may be fabricated at such a small size and pixel pitch that they become inefficient and suboptimal (e.g., in terms of power usage, cost, etc.) for use in direct-view displays in which users' limited eyesight fails to appreciate the full resolution that the microscopic emitters provide. Since microLEDs havemany other advantages (despite this direct-view limitation), however, this disclosure relates to direct-view display assemblies with sparse distributions of pixel emitters. More particularly, processes and methods for producing direct-view display assemblies are described in which microLEDs or other small pixel emitters are distributed across the display in a relatively sparse way so as to have a greater pixel pitch than the pixel emitters have when fabricated. In this way. display assemblies described herein may benefit from all the advantages of microLED technology while still being suitable for direct viewing (without magnification) and without needlessly wasting power, cost, and other resources on a higher pixel resolution than a user can reasonably appreciate or perceive. Additionally, other benefits enabled by direct-view display assemblies with sparse distributions of pixel emitters described herein include the possibility of using flexible substrates, the opportunity’ for other components (e.g., antennas, cameras, sensors, etc.) to be placed below the pixel emitters and still have largely unimpeded paths to clear air, and so forth.

[0005] To this end, one implementation described herein involves a display assembly constructed in accordance with principles described herein. The display assembly may include a set of pixel emitters, a plurality of driver circuits, and a controller circuit. The set of pixel emitters may be transferred to the display assembly from a donor wafer on which the set of pixel emitters were fabricated. The set of pixel emitters may be fabricated at a first pixel pitch and distributed within the display assembly at a second pixel pitch greater than the first pixel pitch. The plurality of driver circuits may include a first driver circuit electrically coupled to a first subset of the set of pixel emitters via a first set of emitter traces, as well as a second driver circuit electrically coupled to a second subset of the set of pixel emitters via a second set of emitter traces. The controller circuit may be electrically coupled to the first driver circuit and the second driver circuit (as well as other driver circuits of the plurality of driver circuits) via a set of controller traces. These traces may be enclosed within one or more layers of dielectric material.

[0006] Other implementations described herein involve methods for constructing display assemblies like the example display assembly described above. For instance, one example method comprises steps including, but not necessarily limited to: 1) transferring a set of pixel emitters from a donor wafer to a superstrate carrier, the set of pixel emitters being fabricated on the donor wafer at a first pixel pitch and distributed onto the superstrate carrier at a second pixel pitch greater than the first pixel pitch; 2) subsequent to the transferring of the set of pixel emitters, depositing: (a) a first set of emitter traces configured to electrically couple a first driver circuit to a first subset of the set of pixel emitters, and (b) a second set ofemitter traces configured to electrically couple a second driver circuit to a second subset of the set of pixel emitters; 3) subsequent to the depositing of the first set of emitter traces and the second set of emitter traces, attaching the first driver circuit to the first set of emitter traces and the second driver circuit to the second set of emitter traces; and 4) depositing a set of controller traces configured to electrically couple a controller circuit to the first driver circuit and the second driver circuit.

[0007] Other example methods descnbed herein use a substrate and builds from the bottom of the display assembly, rather than building down from a superstate as described above. For instance, another example method comprises steps including, but not necessarily limited to: 1) attaching a first driver circuit and a second driver circuit to a substrate carrier; 2) subsequent to the attaching of the first driver circuit and the second driver circuit, depositing: (a) a set of controller traces configured to electrically couple a controller circuit to the first driver circuit and the second driver circuit, (b) a first set of emitter traces configured to electrically couple the first driver circuit to a first subset of a set of pixel emitters, and (c) a second set of emitter traces configured to electrically couple the second driver circuit to a second subset of the set of pixel emitters; and 3) subsequent to the depositing of the set of controller traces, the first set of emitter traces, and the second set of emitter traces, transferring the first subset and the second subset of the set of pixel emitters from a donor wafer to couple, respectively, with the first set of emitter traces and the second set of emitter traces on the substrate carrier, the pixel emitters being fabricated on the donor wafer at a first pixel pitch and distributed onto the substrate carrier at a second pixel pitch greater than the first pixel pitch.

[0008] Various additional operations may be added to these processes and methods as may serve a particular implementation, examples of which will be described in more detail below. Additionally, it will be understood that each of the processes and operations described as being performed by different types of implementations in the examples above may additionally or alternatively be performed by other types of implementations as well.

[0009] The details of these and other implementations are set forth in the accompanying drawings and the description below. Other features will also be made apparent from the following description, drawings, and claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 shows illustrative aspects of an example implementation of a direct- view display assembly with a sparse distribution of pixel emitters in accordance withprinciples described herein.

[0011] FIG. 2 shows views of illustrative aspects of a portion of a display assembly constructed from a superstate carrier using a top-down approach in accordance with principles described herein.

[0012] FIG. 3 show s an illustrative method for constructing a display assembly from a superstrate carrier using a top-down approach in accordance with principles described herein.

[0013] FIGS. 4A-4K show- illustrative aspects of various intermediate steps in the construction of a display assembly from a superstrate using a top-down approach in accordance with principles described herein.

[0014] FIG. 5 shows views of illustrative aspects of a portion of a display assembly- constructed from a substrate earner using a bottom-up approach in accordance with principles described herein.

[0015] FIG. 6 shows an illustrative method for constructing a display assembly from a substrate carrier using a bottom-up approach in accordance with principles described herein.

[0016] FIGS. 7A-7G show- illustrative aspects of various intermediate steps in the construction of a display assembly from a substrate using a bottom-up approach in accordance with principles described herein.DETAILED DESCRIPTION

[0017] Emerging light emission technologies provide a number of advantages over conventional technologies. As one example, extremely bright and power-efficient displaypanels may be made from extremely small pixel emitters using micro light emitting diodes (microLEDs) or other similar technologies. These technologies may produce pixel panels with a pixel pitch in the range of a few- microns allowing for the fabrication of panels with hundreds of thousands or millions of pixels per square centimeter. Such pixel resolution goes well beyond the resolving limit of the human visual system, such that panels with pixel density in this range are typically magnified significantly before being viewed by the user. As one example of where these technologies have been useful, extended reality headsets (e.g., augmented reality- glasses, etc.) are a good fit for extremely- dense pixel panels, since the form factor provides very limited space for the display and since there is typically a complex optical stack (including magnification and other optical manipulation) between the pixel panel and the heads-up display viewed by the user.

[0018] While high-density microLED pixel panels may serve as a particularly good option for magnified displays such as may be integrated into head-mounted display devices, desirable attributes of microLED components (e.g., brightness, power efficiency, etc.) may also make these components desirable for other types of applications as well, including for direct-view display applications. As used herein, a direct-view display refers to a display that is configured for viewers to look at directly, without significant manipulation of the light (e.g.. beyond natural distortion that may be introduced by a cover glass or other such optical device integrated with the display for protection or aesthetic purposes). For example, direct- view displays may stand in contrast to displays, such as may be included in head-mounted extended reality devices, that manipulate light in more significant ways (e.g., significantly magnifying the light, moving the light through a waveguide, projecting the light to form an image on a display separate from the pixel panel or directly on the user’s retina, etc.). In certain direct-view- examples, including examples described herein, individual pixel emitters (e.g., individual microLEDs of a single color; individual white pixels that include a grouping of red, green, and blue microLEDs; etc.) may be viewed through optics configured to protect the pixel emitters or to collect and direct light in a particular way. For instance, a pixel panel featuring individual micro-lenses in front of each pixel emitter would still be a direct-view display if the optics are not magnify ing the image (i.e., increasing the apparent pixel pitch) or moving or reprojecting the image to be viewed apart from the panel itself. A few example applications that typically use direct-view displays include smartwatch devices, mobile devices (e g., smartphones, tablets, etc.), and television screens.

[0019] A technical problem that can arise when extremely small pixel emitters such as microLEDs are employed for direct-view displays is that the pixel pitch can be so small as to be wasteful and inefficient. For example, even though a smartwatch display may only be a few' square centimeters in size, the number of microLEDs that could fit on a direct-view display of that size could be in the tens of millions. Along with adding significant cost to the device’s bill of materials, a display with this type of resolution would place significant strain on power and heat requirements of the device, along with creating other complications and resource requirements associated with driving the display and processing / storing the high- resolution images it would produce. Even if all of these issues were addressed by a certain design, the design would still be wasteful and inefficient as the human visual system is unable to resolve such high resolution.

[0020] In response to these technical problems, technical solutions described herein relate to direct-view display assemblies that use sparse distributions of pixel emitters. Forexample, methods and processes described herein allow a direct-view display assembly to be constructed that makes use of microLEDs or other small pixel emitter technologies (thereby enjoying the associated brightness, power-efficiency, and other benefits of these technologies) while increasing the pixel pitch of the pixel emitters to avoid the waste and inefficiency described above. While smartwatch display s provide one good example of an application where a direct-view display assembly with a sparse distribution of pixel emitters could be used, it will be understood that principles descnbed herein could similarly be used with a variety of other direct-view display applications such as mobile devices, computer screens, television screens, appliance panels, automotive interfaces, and so forth.

[0021] Along with distributing pixel emitters more sparsely on a display assembly (so as to increase the pixel pitch to a level that can be more reasonably resolved by users), another technical problem addressed by display assemblies described herein relates to how' power and signaling can be distributed to the pixel emitters in their sparsely-distributed positions. To spread the pixel emitters out over a relatively larger area to thereby increase the pixel pitch in the ways that have been described, the pixel emitters are transferred from a donor substrate on which they were fabricated, to a display assembly where the pixel emitters can operate with more space between them. This transfer, however, precludes the pixel emitters from being fabricated directly on a chip in which routing and other backplane functions are already integrated. Instead, routing from a central display controller to pixel emitters that are sparsely fanned out across a relatively large display area becomes the responsibility of the display assembly itself.

[0022] To address this technical challenge, implementations described herein include methods and processes for laying down layers of metal routing traces enclosed by dielectric material to route from a controller circuit to a plurality of driver circuits (also referred to as tile drivers), and from the driver circuits to the pixel emitters themselves (e.g., the sparsely distributed microLED devices). In some implementations, the resulting display assembly may include sparsely-distributed pixel emitters and all the infrastructure to drive them (e.g., the driver circuits, controller circuit, and necessary routing) on a discrete display assembly that can be installed in a device (e.g.. a smartwatch or the like) as a ready-made direct-view7display. In other implementations, certain elements of the display assembly (e g., the controller circuit, certain routing, etc.) may be implemented separately from the pixel emitters and driver circuits, but may be configured to interoperate when connected. For example, a display assembly could be partially implemented on a superstrate to which the pixel emitters and driver circuits are coupled, and partially implemented within a printedcircuit board (PCB) or other preformed element that includes other elements of the display assembly (e.g.. the controller circuit some of the power and / or signal routing, etc.).

[0023] Additionally, the construction of direct-view display assemblies with sparse distributions of pixel emitters may be performed using either a top-down approach (building from a superstrate to which the pixel emitters are coupled down to the controller circuit and its routing) or a bottom-up approach (building from a substrate to which the driver circuits are coupled up to the fan-out routing where the pixel emitters are connected). Each of these examples and other optional aspects of how direct-view' display assemblies with sparse distributions of pixel emitters may be constructed will be described in more detail below.

[0024] Various beneficial technical effects arise from these solutions. For example, as has already been mentioned, direct-view display assemblies with sparse distributions of pixel emitters may allow' for the benefits of microLEDs to apply to a direct-view display application, even as wasteful inefficiency is avoided that could otherwise accompany displays with extremely high density. These benefits include bright, vivid displays with accurate color, dark blacks, and that also have high power efficiency and other advantages. Additional technical effects of display assemblies described herein include a variety of options for how the displays may be constructed so as to potentially provide unique features for the device in which the display assembly is used.

[0025] As one example, if a flexible superstrate or substrate is used for the construction, the resulting display assembly may be thin and flexible so as to form fit devices that may not be rigid and / or flat. As another example, the flexibility' with how pixel emitters are placed in implementations described herein impose no preference for arrays of pixel emitters that are rectilinear or any particular shape. As a result, display assemblies of a variety of shapes and sizes may be conveniently produced as may serve a particular implementation. As yet another example, the use of very small pixel emitters (e.g., microLEDs) in direct view' displays may allow the opportunity to place other components and / or sensors betw een the emitters. For instances, antennas that require an unimpeded path to clear air may be conveniently positioned beneath direct-view displays, photosensitive detectors (e.g.. camera pixel arrays) may be interleaved between emitters to allow the display to act as an image capture device, and so forth. Other example benefits may include that display assemblies described herein may tend to be very thin (which may be a critical design constraint for certain applications), may allow for flexible controller circuit placement, maybe fully integrated (e.g., with all the driver circuits and even the controller embedded in the assembly with the carrier sheet), and so forth.

[0026] Various implementations will now be described in more detail with reference to the figures. It will be understood that particular implementations described below are provided as non-limiting examples and may be applied in various situations. Additionally, it will be understood that other implementations not explicitly described herein may also fall within the scope of the claims set forth below. Systems and methods described herein for direct-view display assemblies with sparse distributions of pixel emitters may result in any or all of the technical effects mentioned above, as well as vanous additional effects and benefits that will be described and / or made apparent below.

[0027] FIG. 1 show s illustrative aspects of an example implementation 100 of a direct-view display assembly 102 with sparse distribution of pixel emitters in accordance with principles described herein. The example of display assembly 102 is depicted in FIG. 1 as being configured for use as a smartwatch display (e.g., based on its shape, size, etc.). However, as mentioned above, it will be understood that the same principles described in relation to display assembly 102 may be applied to other types of direct-view display assemblies configured for us in other applications such as mobile device displays, laptop screens, televisions, appliance panels, and so forth.

[0028] As shown in FIG. 1, a small segment 104 of direct- view display assembly 102 is broken out and zoomed in to illustrate certain aspects of the display that will be described. Additionally. FIG. 1 shows a donor wafer 106 (not drawn to scale in relation to direct-view display assembly 102) that may undergo lithographic and / or other processing to fabricate a large number of pixel emitters (e.g., microLED devices or the like). More particularly, as shown by a small segment 108 of donor wafer 106 that is similarly show n to be broken out from the wafer and zoomed into in the figure, a set of pixel emitters 110 (represented by small squares within segment 108) may be fabricated on donor wafer 106 before undergoing a transfer 1 12 to display assembly 102.

[0029] Transfer 112 may be performed in any suitable way. For example, after the pixel emitters 110 have been fabricated with high density on donor wafer 106, the donor wafer may be aligned with a earner substrate of the display assembly and the pixel emitters 110 may be released or detached from the donor wafer to be coupled (e.g., electrically connected, adhesively connected, etc.) at the desired location on the carrier substrate (i.e., the location to which the pixel emitter has been aligned). This detachment may be facilitated by a laser that is focused (e.g., from a first side of the donor wafer) in a manner that creates a defect (e.g., a crack) at a specified depth within the wafer under the emitter or emitters that are to be released. With the donor wafer and carrier aligned, another laser (e.g., introducedfrom the opposite side of the donor wafer) may then cause the defect to expand (e.g., the crack to spread) within boundaries that have been set around a particular pixel emitter (or group of pixel emitters) that is to be released by the action of the laser. As such, the pixel emitter or group may detach from the donor wafer where it or they were fabricated and may attach to the carrier substrate. As mentioned above and as will be described in more detail below, the pixel pitch of the pixel emitters may be increased by transfer 112 so that the pixel emitters are not so densely packed. In some cases, for instance, the donor wafer may be aligned and then only one in every N pixel emitters may be released to the carrier sheet (where N could equal 2, 10, 25, 50, or any other suitable number) prior to the donor wafer being realigned to the same or another carrier sheet to repeat the process for other, not-yet- released pixel emitters.

[0030] Accordingly, segment 104 shows that the set of pixel emitters 110 (only a few of which are explicitly labeled in FIG. 1 , but which will be understood to incorporate all the small squares shown) is disposed in the display assembly 102 subsequent to being transferred (transfer 112) to display assembly 102 from the donor wafer 106 on which they were fabricated. As further illustrated in FIG. 1. the set of pixel emitters 110 may be fabricated at a first pixel pitch 114-1 and distributed within the display assembly 102 at a second pixel pitch 114-2 that is greater than pixel pitch 114-1. In some examples, the pixel pitch 114-1 at which the set of pixel emitters 110 are fabricated may be a very small pixel pitch, such as in the range of about 2-4 microns. In contrast, the pixel pitch 114-2 at which the set of pixel emitters 110 are distributed within the display assembly 102 may be far larger than pixel pitch 114-1. While not necessarily draw n to scale in relation to pixel pitch 114-1, pixel pitch 114-2 could be, in various examples, at least double the pixel pitch 114-1, at least four times greater than pixel pitch 114-1, at least ten times greater than pixel pitch 114-1, at least twenty times greater than pixel pitch 114-1, at least forty times greater than pixel pitch 114-1, or another suitable increase as may serve a particular implementation. For instance, while pixel pitch 114-1 may represent a high-density pitch in the range of 2-4 microns, pixel pitch 114-2 may represent a low-density or sparse pitch in the range of 50-120 microns (e.g., 80 microns).

[0031] Along with the sparse distribution of the set of pixel emitters 110. display assembly 102 is also shown, in segment 104, to include a first driver circuit 116-1 electrically coupled to a first subset 118-1 of the set of pixel emitters 110 via a first set of emitter traces 120-1. Subset 118-1 will be understood to include each of the pixel emitters 110 (i.e., each of the small squares) in the dotted box labeled as subset 118-1. As shown, each of these pixel emitters 110 is routed to driver circuit 116-1 by an emitter trace that is drawn as a bold lineextending between the pixel emitter 110 and driver circuit 116-1 and that will be understood to represent one or more traces that electrically connect the emitter trace to the driver circuit. For example, in some implementations, both an active line and a return line from the driver circuit to each individual pixel emitter may be represented by the black pixel traces, whereas in other implementations, the return lines may be implemented on another layer that is not shown in FIG. 1. The emitter traces are collectively referred to as the set of emitter traces 120-1.

[0032] Similar to the driver circuit 116-1, the subset 118-1 of the set of pixel emitters 110, and the set of emitter traces 120-1, display assembly 102 is also show n in segment 104 to include a second driver circuit 116-2 electrically coupled to a second subset 118-2 of the set of pixel emitters 110 via a second set of emitter traces 120-2. While only these driver circuits and their corresponding subsets of pixel emitters and traces are explicitly labeled in FIG. 1, it will be understood that any suitable number of driver circuits, each likew ise corresponding to their own subsets of pixel emitters and traces, may be used to implement a display assembly of a desired size. Additionally, while driver circuit 116-1 and driver circuit 116-2 are shown to correspond to subsets of 16 pixel emitters for the example of implementation 100, it will be understood that different sized subsets may be used as may serve a particular implementation. For instance, each circuit driver could be electrically coupled to (and responsible for driving) 64 pixel emitters (e.g., an 8x8 grid), 256 pixel emitters (e.g., a 16x16 grid), or another suitable number (not necessarily a power of two and not necessarily in a square or rectilinear grid). If, for example, a display assembly included 160,000 pixel emitters in a 400x400 grid and each driver circuit corresponded to a 100x100 subset of the pixel emitters (100,000 pixel emitters), the display assembly may use 16 individual driver circuits to drive all the emitter elements of the display.

[0033] Along with this plurality of driver circuits (e.g., driver circuits 116-1, 116-2, and other driver circuits of the display assembly 102 that are not explicitly shown in segment 104), display assembly 102 may further include a controller circuit 122 electrically coupled to driver circuit 116-1, driver circuit 116-2, and the other driver circuits (not shown) via a set of controller traces 124. These traces are drawn in a similar manner as emitter traces 120-1 and 120-2, but are shown to extend from controller circuit 122 to the driver circuits 116-1 and 116-2. As with the other traces described above, controller traces 124 may represent one or more connections betw een the controller circuit and the driver circuits (e.g., to transfer data signaling, power, a return, etc.). While shown on the same layer in the illustration of implementation 100, it will be understood that the set of controller traces 124 may, in certainimplementations, be implemented on one or more layers distinct from one or more layers on which the sets of emitter traces 120-1 and 120-2 are implemented. That being said, it may be desirable to have as few layers as possible for a given implementation (e.g., so that the display assembly 102 may have a low profile, may possibly be flexible, may avoid certain thermal issues, and so forth). As such, to the extent that it is possible to include the routing of emitter traces and controller traces on a single layer (as shown) or on a relatively small number of layers, this may help achieve certain design objectives.

[0034] The set of controller traces 124 shown in FIG. 1 suggests point-to-point connections between the controller circuit 122 and each of the driver circuits 116-1 and 116- 2, and this indeed may be a suitable way for controller circuit 122 to communicate with the driver circuits in certain implementations. It will be understood, however, that point-to-point communication is not required and may not be the most efficient mode of communication in certain implementations. Rather, in some examples, a single controller circuit 122 may communicate with a large number of driver circuits using, for example, an architecture logically configured in a row / column grid. For example, row signals and column signals generated by the controller circuit may each be connected to many tile drivers in parallel, the connections being arranged such that activation of any given pair of row and column signals selects a single tile driver. Though this type of architecture may use row s and columns in a logical manner, it will be understood that the driver circuits need not necessarily be physically arranged in geometric rows and column. To the contrary, the physical placement of each driver circuit may be arranged in any suitable geometry while the connections to the controller circuit may be configured to create a row7column architecture.

[0035] The implementation 100 illustrated in FIG. 1 represents one example of a direct-view display assembly with sparse distribution of pixel emitters in accordance with principles described herein. It will be understood, however, that additional details and variations on what is explicitly shown in FIG. 1 may be implemented for other display assemblies. As one example variation, the first subset 118-1 of the set of pixel emitters 110 to which the first driver circuit 116-1 is electrically coupled may include pixel emitters in anon- rectilinear arrangement, rather than the square, 4x4 rectilinear arrangement shown. The same is true of the second subset 118-2 and any other subsets of the set of pixel emitters 110 as may be included on display assembly 102. As has been mentioned, displays of different shapes may be conveniently and efficiently constructed by the flexibility provided by this non-rectilinear possibility. In a relatively simple case, the rounded comers of display assembly 102 shown in FIG. 1 may be implemented by subsets of pixel emitters that do notshare the square, rectilinear layout of those pixel emitters of subsets 118-1 and 118-2. In more advanced examples, arbitrarily-shaped display screens may be efficiently produced for a variety of applications, sections of the display could be efficiently carved out (e.g., to make room for a camera or fingerprint reader in the display), and so forth.

[0036] Each of the elements illustrated in segment 104 of display assembly 102 will now be described in more detail, including with possible variations and details that may be used in certain implementations.

[0037] The set of pixel emitters 110 may be implemented by any suitable light emission device that may serve as a pixel for a display. A principal example used throughout this disclosure is that of a microLED device. For instance, each pixel emitter 110 could represent a white microLED that has a red element, a green element, and a blue element that combine to create a white pixel or any desired color (based on the influence given to each of the primary colors). As another example, each pixel emitter 110 could represent a single microLED component of one individual color (e.g., a red microLED, a green microLED. etc.). While microLEDs are used as the principal example in the disclosure, it will be understood that principles described herein could be applied to other types of pixel emitters, particularly those that, like microLEDs, may be extremely small such that sparser distribution is desirable before they can be used for an efficient direct-view display.

[0038] The driver circuits 116-1 and 116-2, as well as the controller circuit 122, may each be implemented by semiconductor chips or integrated circuits, whether those chips are unpackaged semiconductor dies, fully packaged chips, or something in between. For example, these circuits may each represent different complementary-metal-oxide- semiconductor (CMOS) chips that are fabricated separately (e.g., on a wafer similar to donor wafer 106) and then integrated into the display assembly 102 to serve the functions described herein. In some examples, these chips may be configured to be relatively thin and low profile (e.g., with a thickness less than 100 microns, less than 50 microns, less than 20 microns, etc.).

[0039] The sets of emitter traces 120-1 and 120-2 may be implemented on a single plane (as shown), or. in cases where more complex fanout is necessary (e.g., to a subset of pixel emitters with several dozens or hundreds of pixel emitter devices), may be implemented on two or more planes separated by layers of insulative dielectric material (as will be described and illustrated in more detail below). The set of controller traces 124 similarly may be implemented on the same plane of insulating substrate as controller circuit 122 and / or driver circuits 116-1 and 116-2 themselves, or on a separate layer. Power traces may have a thickness in a range 5-50 microns and may be separate from traces configured to carrysignaling information (e.g., image data).

[0040] Details of display assemblies such as display assembly 102, as well as processes and techniques for constructing the same, will now be described in relation to the remainder of the figures. More particularly, FIGS. 2, 3, and 4A-4K relate to construction techniques that use what is referred to herein as a top-down approach to produce a direct- view display assembly with a sparse distribution of pixel emitters. As will be illustrated and described, this approach involves starting with a superstrate carrier (e.g., an insulative and transparent carrier sheet that will eventually be the front part of the display that the user looks at) and building downward from the pixel emitters themselves to the layers of traces, the plurality of driver circuits, and the controller circuit.

[0041] FIGS. 5, 6, and 7A-7G then relate to construction techniques that use what is referred to herein as a bottom-up approach for producing a similar or identical direct-view display assembly with a sparse distribution of pixel emitters. As will be illustrated and described, this approach involves starting with a substrate carrier (e.g., a carrier sheet that will form the back or bottom of the display, rather than the part that the user looks at) and building u w ard from the driver circuits and layers of traces up to the sparsely distributed pixel emitters.

[0042] As made clear in the follow ing description, either of these approaches, or a combination of approaches that builds certain layers top-down and others bottom-up before combining them, may be suitable ways to create the types of direct-view display assemblies described and illustrated above. Certain advantages may attend one approach or the other to help achieve certain goals and objectives that may be associated with a particular implementation.

[0043] FIG. 2 shows a top view 200-1 and a corresponding side view 200-2 depicting certain aspects of a portion of a display assembly constructed from a superstrate using a top- down approach in accordance with principles described herein. As shown, top view 200-1 depicts similar elements as shown within one of the subsets 118-1 or 118-2 of the set of pixel emitters 110 of FIG. 1 described above. While the elements may not be identical as described above for FIG. 1, the reference numbers for these elements (and other elements in other figures below) are similar. Specifically, as shown, a subset 218 of an overall set of pixel emitters 210 (similar to either of subsets 118-1 or 118-2 or the set of pixel emitters 110) is shown in the illustrated portion of the display assembly to be electrically coupled to a driver circuit 216 (similar to either of driver circuits 116-1 or 116-2) by a set of emitter traces 220 (similar to emitter traces 120-1 or 120-2). Additionally, a controller trace 224 (similar to oneof the controller traces 124) is shown that will be understood to electrically couple driver circuit 216 to a controller circuit (“To Controller”), though that controller circuit is not explicitly show n in FIG. 2 (and will be understood to be serving a plurality of other driver circuits along with serving driver circuit 216). At the bottom of top view 200-1, an indicator shows the perspective of side view' 200-2, which is then depicted below' top view 200-1 with a similar indicator showing the perspective of top view 200-1.

[0044] In side view 200-2. certain elements are depicted, from the perspective of the side view; that have already been illustrated and described from the perspective of the top view. For example, 4 pixel emitters 210 are shown from the side view' along with several layers in which emitter traces 220 electrically couple the pixel emitters 210 to a driver circuit 216. Controller trace 224 is also shown to be routed on these layers and to go out of view to the (non-depicted) controller circuit (“To Controller”). While these traces appear to overlap and intersect with one another from the perspective of side view 200-2 (since, in this example, the set of emitter traces 220 and controller trace 224 are all routed on a same layer), it will be understood that each trace may be electrically independent from the others as can clearly be seen from top view 200-1.

[0045] Along with these elements that are visible in both views 200-1 and 200-2, side view7200-2 also illustrates certain additional elements that are not explicitly drawn or labeled from the top view 200-1. Specifically, as shown, a superstrate carrier 230 is shown above the pixel emitters 210. Additionally, optical devices 232 (e.g., microlenses, light collection or dispersion devices, etc.) are shown to be integrated in superstrate carrier 230 above each of the pixel emitters 210. Various dielectric layers 234 of dielectric material encapsulating various other elements (e.g., the pixel emitters 210, the set of emitter traces 220, the driver circuit 216. etc.) are also shown. In side view 200-2 and other side views depicted herein, various layers of material such as superstrate carrier 230, dielectric layers 234, and other such layers are shown with jagged edges illustrating that only a portion of a cutaw ay side view is shown, and that these layers extend in other directions (e.g., to incorporate other pixel emitter, other traces, other driver circuits, and so forth).

[0046] To illustrate how the display assembly of FIG. 2 may be constructed (i.e.. assembled, fabricated, manufactured, etc ), a method 300 illustrated in FIG. 3 for constructing a direct-view display assembly w ith sparse distribution of pixel emitters w ill now' be described with reference to individual process steps illustrated by FIGS. 4A-4K.

[0047] FIG. 3 shows method 300 for constructing the display assembly of FIG. 2 from a superstrate carrier using a top-down approach in accordance with principles describedherein. It will be understood that method 300, as well as other similar methods described herein (and / or variants of method 300 in accordance with principles described herein) may, in certain examples, be encoded in instructions that may be stored by a non-transitory computer- readable medium, and that, when executed, may cause a processor of a computing device (e.g., a display fabrication system) to perform one or more of the operations of method 300.

[0048] While FIG. 3 shows illustrative operations 302-308 according to a specific implementation, it will be understood that other implementations of this method may omit, add to, reorder, and / or modify any of operations 302-308 that are explicitly represented in FIG. 3. Additionally, while operations shown in FIG. 3 are illustrated with arrows suggestive of a sequential order of operation, it will be understood that some or all of the operations of method 300 may be performed concurrently (e.g.. in parallel) with one another. Each of the operations of these methods will now be described in more detail as the operations may be performed by a system such as a display fabrication system. Additionally, as mentioned above, further detail related to certain of the operations will be given with reference to FIGS. 4A-4K.

[0049] At operation 302, a display fabrication system may transfer a set of pixel emitters from a donor wafer to a superstate carrier. For example, as was illustrated and described in relation to FIG. 1, the set of pixel emitters (e.g., the set of pixel emitters 110) may have been fabricated on the donor wafer (e.g., donor wafer 106) and then transferred to a carrier sheet (i.e., a superstrate carrier in this example) so that the pixel emitters can be spread out for better direct viewing and for various other reasons (e.g., to allow for a flexible display, etc.). To further illustrate operation 302, FIGS. 4A-4C show illustrative aspects of various intermediate steps that may be performed in furtherance of operation 302.

[0050] In FIG. 4A. a step 400-A illustrates a superstrate carrier 230 that is produced, constructed, or otherwise obtained. Superstrate carrier 230 may be constructed of a transparent material such as a glass or plastic such that, when attached, the pixel emitters will be enabled to emit light through the transparent material of the superstrate carrier. In this way, superstrate carrier 230 may serve as a protective mechanism (e.g.. to shield the delicate set of pixel emitters from dust and debris, electrostatic discharge, and / or other potential damage). Additionally, as will be made apparent in the follow figures, superstrate carrier 230 may serve as a carrier sheet that helps to mechanically hold the display assembly together as sets of emitter traces and controller traces, circuitry (e.g., driver circuits and controller circuit), and dielectric material are deposited in layers onto superstrate carrier 230.

[0051] Along with being transparent and capable of serving as a carrier for the layersdescribed below, superstate carrier 230 may also have other optical and / or mechanical properties as may be desirable for a particular implementation. For example, superstrate carrier 230 may be relatively thin (e.g., with a thickness less than 100 microns, less than 40 microns, etc.) and the material from which it is constructed may be insulative. Additionally, superstrate carrier 230 may have any suitable shape desired for the display assembly and may be constructed of a flexible material configured to allow the display assembly, when flexed, to bend without being damaged. A flexible display may be useful for bending around edges (e.g., to reduce or eliminate bezels, etc.), for contouring to non-flat surfaces on which displays may be desired, and so forth.

[0052] As further shown in FIG. 4A, a set of optical devices 232 may be integrated within superstrate carrier 230. These optical devices 232 may be configured to manipulate the light emitted through the transparent material of superstrate carrier 230 by the set of pixel emitters in any suitable manner. For instance, optical devices 232 may represent microlenses imprinted into the material of superstrate carrier 230 and configured to collect light produced by the pixel emitters that will be coupled to superstrate carrier 230 at each of the optical devices 232. In this way. the light produced by microscopic pixel emitters may be somewhat amplified or made to seem brighter as less light will scatter and more light will be directed to the user who is viewing the display. As such, optical devices 232 may help increase the brightness efficiency of the display or may otherwise help improve the display’s overall appearance or functionality (e.g., by reducing reflection / glare, etc.).

[0053] In FIG. 4B, a step 400-B involves the coupling of the set of pixel emitters 210 to superstrate carrier 230 (e.g., as transferred from the donor wafer, as described above). The pixel emitters 210 may be attached to superstrate carrier 230 using any suitable adhesive or bonding technique and, as shown, may be distributed to align with the optical devices 232 imprinted into the superstrate carrier 230 (i.e., with one pixel emitter 210 being disposed directly behind each optical device 232). As was illustrated and described in relation to FIG. 1, the set of pixel emitters may have been fabricated at a first pixel pitch (e.g., pixel pitch 114-1) that is relatively small. For instance, modem lithographic fabrication techniques may allow for a pixel pitch in the range of 2-4 microns, which, as mentioned above, is far too small to be resolved by the human visual system. Accordingly, part of the goal of transferring the set of pixel emitters at operation 302 may be to increase the pixel pitch to be more appreciable by human visual capabilities for direct-viewing applications (though it will be understood that the resulting direct- view screen could still be small and appear to the user to be extremely detailed and high resolution). As such, the set of pixel emitters coupled tosuperstate carrier 230 at step 400-B may be distributed onto the superstrate carrier at a second pixel pitch (e.g., pixel pitch 114-2) that is greater than the first pixel pitch.

[0054] FIG. 4B shows that pixel emitters 210 are at least somewhat further apart than they would have been when fabricated, but it will be understood that the spacing of pixel emitters 210 in FIG. 4B and other figures below may well not be to scale for the degree of pitch expansion used in some implementations. This pitch expansion factor (i.e., how much greater the second pixel pitch is than the first pixel pitch) may be dependent on several considerations. For example, the techniques and technology used to fabricate the pixel emitters on the wafer donor may determine how small the first pixel pitch is. Additionally, the type of direct-view display assembly being constructed would also influence how much the pixel pitch is to be expanded from the fabricated pitch. For example, a smartwatch display may have different pixel density requirements (due to being viewed, typically, in close proximity) than a large television would have (due to being viewed, typically, from across the room). In one example, the first pixel pitch could be 4 microns, and the transferring could increase this by a factor of 20, so that the second pixel pitch is 80 microns. In other examples, the transfer could increase by a factor of 2 (or even a factor less than 2 and greater than 1). a factor of 5, a factor of 10, a factor of 40, a factor of 100 or another suitable factor.

[0055] At FIG. 4C, a step 400-C involves depositing a first dielectric layer 234 to the superstrate carrier 230. More particularly, as shown, an interlayer dielectric (ILD) of an insulative material is applied so as to enclose and protect the pixel emitters and, as will be illustrated below, to support a first metal layer that will provide contact for the pixel emitters to fan out to the driver circuits (as emitter traces 220).

[0056] Returning to FIG. 3, at operation 304, the display fabrication system may deposit emitter traces to couple the pixel emitters 210 to driver circuits that will be bonded later (e.g., driver circuit 216). More particularly, subsequent to the transferring of the set of pixel emitters at operation 302, operation 304 may be performed to deposit: 1) a first set of emitter traces configured to electrically couple a first driver circuit to a first subset of the set of pixel emitters. 2) a second set of emitter traces configured to electrically couple a second driver circuit to a second subset of the set of pixel emitters, and 3) other respective sets of emitter traces configured to electrically couple other driver circuits to their own subset of the set of pixel emitters. FIG. 2 and FIGS. 4A-4K show an example of a single subset of pixel emitters (i.e., subset 218) and a single set of emitter traces (i.e., emitter traces 220), though it will be understood that operation 304 is performed throughout the display assembly to connect the entire set of pixel emitters 210 to respective driver circuits assigned thereto. Tofurther illustrate operation 304, FIGS. 4D-4F show illustrative aspects of various intermediate steps that may be performed in furtherance of operation 304.

[0057] In FIG. 4D, a step 400-D involves depositing the first metal layer implementing emitter traces 220 and controller trace 224 onto the first dielectric layer 234 deposited at step 400-C. As was shown and described in relation to FIG. 2, the relatively limited number of pixel emitters 210 in subset 218 makes it possible for all of the emitter traces 220 to be routed on a same layer as one another and as controller trace 224 in this example. Where this is possible, implementing traces on a single metal layer in this way (or on as few layers as possible) is advantageous as it leads to a thinner display assembly, less risk or complication of thermal issues, less cost and complexity of manufacturing, and so forth. However, it will be understood that in certain implementations that assign driver circuits to larger subsets of pixel emitters (e.g., implementations using subsets with hundreds of pixel emitters serv ed by each driver circuit, etc.) it may not be possible to accomplish all the routing on a single metal layer such as shown in FIG. 4E.

[0058] Accordingly, in certain implementations, various sets of emitter traces such as the set of emitter traces 220 may be deposited on (e.g., distributed between) a plurality of layers separated by dielectric material to allow the routing to cross and overlap without the traces touching. Additionally, controller traces such as controller trace 224 may be implemented on yet another layer or another plurality of layers as may serve a particular implementation.

[0059] As shown, the first metal layer illustrated in FIG. 4D includes traces configured to electrically couple to the pixel emitters 210, to run under the first dielectric layer 234 to the driver circuits (not shown in FIG. 4D), and to go between the driver circuits and the controller circuit (also not shown in FIG. 4D). While the fanout of emitter traces 220 is not visible from side view 200-2 and the corresponding views in FIGS. 4A-4K, it will be understood that emitter traces 220 and controller trace 224 deposited at step 400-D may fan out in a manner such as is illustrated in implementation 100 and top view 200-1 shown above. Emitter traces 220 may be constructed of any suitable conductive material (e.g., copper, aluminum, etc.) and may be deposited using any suitable technique (e.g.. a photolithography process, etc ).

[0060] In FIG. 4E, a step 400-E involves depositing a second dielectric layer 234 to the superstate carrier 230. More particularly, as shown, insulative ILD material may be applied at step 400-E to enclose and support the metal layer comprising the emitter traces 220 and controller trace 224 that w ere deposited at step 400-D.

[0061] In FIG. 4F, a step 400-F involves depositing another metal layer to prepare emitter traces 220 and controller trace 224 to bond with the driver circuits and controller circuit when they are placed.

[0062] Returning to FIG. 3, at operation 306, the display fabrication system may attach (e.g., bonding or otherwise physically and electrically coupling) the first driver circuit to the first set of emitter traces and the second driver circuit to the second set of emitter traces. For example, this attaching of the driver circuits may be performed subsequent to the depositing of the first set of emitter traces and the second set of emitter traces at operation 304. To further illustrate operation 306, FIGS. 4G-4I show illustrative aspects of various intermediate steps that may be performed in furtherance of operation 306. More particularly, FIGS. 4G and 4H show example aspects of one approach for attaching the driver circuits to display assembly under construction, while FIG. 41 shows example aspects of an alternative approach for doing the same.

[0063] In FIG. 4G, a step 400-G involves bonding driver circuit 216 to the connections prepared at step 400-F. As such, once step 400-G is complete, each pixel emitter 210 becomes electrically coupled to the driver circuit 216 by way of one or more of the emitter traces 220.

[0064] In FIG. 4H, a step 400-H involves encapsulating driver circuit 216 in a third dielectric layer 234. In this way, driver circuit 216 may be protected from dust and debris as it is encased in the dielectric material. Additionally, the attaching and embedding of driver circuit 216 in steps 400-G and 400-H results in the driver circuit 216 being integrated with the rest of the display assembly so that the display can serve as a discrete, self-sufficient component as it is deployed within the designs of various types of devices (e g., installed in a smartwatch along with other components such as a processor, memory, a power supply, and so forth).

[0065] In the discrete type of display assembly described up to this point, a carrier sheet (i.e., superstate carrier 230) may receive depositions, in a series of layers, of elements such as a set of pixel emitters (e.g., pixel emitters 210), multiple sets of emitter traces (e.g., emitter traces 220), a plurality of driver circuits (e.g., driver circuit 216), a set of controller traces (e.g., controller trace 224), and dielectric material (e.g., in dielectric layers 234). In other types of implementations, however, a display assembly with these same elements could be distributed between a partial assembly associated with the carrier sheet and a printed circuit board (PCB) on which the rest of the elements are disposed. More particularly, for example, a two-part display assembly may include: a superstrate carrier onto which istransferred the set of pixel emitters, as well as a printed circuit board to which the first driver circuit and the second driver circuit are attached. In this type of implementation, the first set of emitter traces, the second set of emitter traces, and the set of controller traces may be included either entirely on the superstrate carrier or the PCB, or they may be distributed between the superstrate carrier and the PCB.

[0066] To illustrate, FIG. 41 shows a step 400-1 in which a partial assembly 402 and a PCB 404 that, collectively, include all the elements described above, are combined (as indicated by an arrow 406) to complete the functional display assembly. More particularly, as shown, the partial assembly 402, in this example, includes the superstrate carrier 230 with the optical devices 232, the pixel emitters 210, and the emitter traces 220 encased in layers of first dielectric layer 234 as has been described. However, the driver circuit 216 and the controller trace 224 (heading outside the scope of the drawing to the controller that is not shown in FIG. 41 (“To Controller”) are both shown to be implemented separately from the rest of these elements. Specifically, driver circuit 216 and controller trace 224 are shown to be produced within one or more layers 408 of PCB 404, which may be constructed in any suitable ways, including ways similar to those described for display assemblies herein (e.g., by interleaving layers of metal traces and dielectric material, etc ). This type of approach may be especially useful if there is not a desire for the display assembly to be flexible (since typical PCBs may be inflexible) and if there is significant routing such that the design can be simplified by moving some of it to the PCB instead of the carrier superstrate and the partial assembly 402.

[0067] While not explicitly illustrated by FIG. 41, it will be understood that other alternative approaches to those explicitly illustrated herein may also be possible. For example, in the same way that a partial assembly 402 may be installed on a PCB 404 to complete the full display assembly, the construction of a display assembly could be accomplished by preforming partial assemblies (also referred to as preforms) and combining these preforms, rather than laying down each layer sequentially as has been described in relation to FIGS. 4A-4H. For example, one preform could be constructed from a superstrate carrier such as superstrate carrier 230 and could include the same elements as partial assembly 402 in FIG. 41, while another preform could be constructed from a substrate carrier (such as will be described in more detail below ) to include the elements shown on PCB 404. Building and then combining these types of preforms may be another suitable way to construct the final display assembly.

[0068] Returning to FIG. 3, at operation 308, the display fabrication system maydeposit a set of controller traces (e.g., including controller trace 224) configured to electrically couple a controller circuit to the plurality of driver circuits (e.g., including driver circuit 216). As has been described and illustrated above, this operation may, in some cases, be performed in parallel with operation 304, where the emitter traces 220 are deposited. In other examples (e.g., when there is insufficient routing space on a single layer), operation 308 may be performed at a different time, such as subsequent to the attachment of driver circuit 216 at operation 306. To further illustrate operation 308, FIGS. 4J-4K show illustrative aspects of steps that may be performed in furtherance of operation 308. More particularly, FIG. 4J shows example aspects of a first approach for depositing the controller traces in examples where through silicon vias (TSVs) are not included within driver circuit 216. while FIG. 4K shows example aspects of an alternative approach for doing the same when driver circuit 216 does include TSVs (so as to allow for electrical connections on both sides of the chip).

[0069] In FIG. 4J, a step 400-J includes depositing a metal layer below the third dielectric layer 234 (i.e., on a separate layer from emitter traces 220 and driver circuit 216). For example, this layer may be dedicated to routing between the controller circuit and the various driver circuits to allow for signaling and power to be distributed from a centralized power supply and controller logic to the various individual driver circuits driving the subsets of pixel emitters. In other examples, if there is sufficient routing space, this routing could be performed on the same layer as the routing of emitter traces 220 (as described above).

[0070] In the example of FIG. 4J, the driver circuits (e g., including driver circuit 216) may be fabricated without through-silicon vias (TSVs) that would support a doublesided routing scheme. As such, FIG. 4J shows that not only the emitter traces 220 but also the controller trace 224 may be implemented (or at least partially routed) in one or more layers on a same side of the driver circuits (i.e., above the driver circuits in this example). In other words, as shown, without TSVs, controller trace 224 connects to the top of driver circuit 216 with the emitter traces 220, then drops down to its own layer elsewhere to be routed to the controller (“To Controller’).

[0071] In contrast. FIG. 4K shows a step 400-K. (e.g.. an alternative to step 400-J) in which the first driver circuit and the second driver circuit are fabricated with through-silicon vias configured to support a double-sided routing scheme. As a result, in this example, the sets of emitter traces 220 may be implemented in one or more layers on a first side of the driver circuits (e.g., above the chips on the top side, as shown), and the controller trace 224 may be implemented in one or more layers on a second side of the driver circuits opposite thefirst side (e.g., below the chips on the bottom side, as shown). In some examples, parts of the controller routing could be achieved on the first side (i.e.. the top side) while other routing could connect to the second side (i.e., the bottom side). For example, logic signaling could be performed on one or more planes above the controller circuit while power and ground could be routed on one or more planes below the controller circuit (connecting to the silicon by way of the TSVs).

[0072] Returning to FIG. 3, each of the operations has been described in relation to further illustration in FIGS. 4A-4K. It will also be understood that other operations not explicitly shown in FIG. 3 or FIGS. 4A-4K may be part of method 300 in certain implementations. For instance, an operation involving fabricating the set of pixel emitters 210 on the donor wafer may be performed prior to the transferring of the set of pixel emitters to the superstrate carrier at operation 302. As another example, operations involving finishing the display assembly and installing it for use in an electronic device (e.g., a smartwatch or other suitable device) could be performed subsequent to operation 308.

[0073] As described above, FIGS. 2-4K relate to the top-down approach of constructing a display assembly starting from a superstrate. However, this is not the only suitable way to construct a display assembly such as display assembly 102. Accordingly, FIGS. 5-7G, which are somewhat similar and generally parallel to FIGS. 2-4K, will now be described to illustrate the bottom-up approach of constructing a display assembly starting from a substrate.

[0074] FIG. 5 shows atop view 500-1 and a corresponding side view 500-2 depicting certain aspects of a portion of a display assembly constructed from a substrate using a bottom-up approach in accordance with principles described herein. As shown, top view 500- I depicts similar elements as top view 200-1 and as shown within one of the subsets 118-1 or 1 18-2 of the set of pixel emitters 110 of FIG. 1 described above. Again, the reference numbers used for these elements are similar to those used in previous examples. For instance, a subset 518 of an overall set of pixel emitters 510 is shown in the illustrated portion of the display assembly to be electrically coupled to a driver circuit 516 by a set of emitter traces 520. Additionally, a controller trace 524 is shown that will be understood to electrically couple driver circuit 516 to a controller circuit, though that controller circuit is not explicitly shown in FIG. 5. At the bottom of top view 500-1, an indicator show s the perspective of side view 500-2, which is then depicted below top view 500-1 with a similar indicator showing the perspective of top view 500-1.

[0075] In side view 500-2, certain elements are depicted, from the perspective of theside view, that have already been illustrated and described from the perspective of the top view. For example, 4 pixel emitters 510 are shown from the side view along with several layers in which emitter traces 520 electrically couple the pixel emitters 510 to a driver circuit 516. Controller trace 524 is also show n to be routed on these layers and to go out of view to the (non-depicted) controller circuit (“To Controller”). Along with the elements common to top view 500-1, side view 500-2 also illustrates additional elements that are not explicitly drawn or labeled from the top view 500-1. including various dielectric layers 534 of dielectric material encapsulating other elements (e.g., the set of emitter traces 520, the driver circuit 516, etc.) and a substrate carrier 540 below driver circuit 516.

[0076] To illustrate how the display assembly of FIG. 5 may be constructed (i.e. , assembled, fabricated, manufactured, etc.) a method 600 illustrated in FIG. 6 for constructing a direct-view display assembly with sparse distribution of pixel emitters will now be described with reference to individual process steps illustrated by FIGS. 7A-7G.

[0077] FIG. 6 show s method 600 for constructing the display assembly of FIG. 5 from a substrate carrier using a bottom-up approach in accordance with principles described herein. It will be understood that method 600, as with method 300 described above and other similar methods described herein (and / or variants of method 600) may, in certain examples, be encoded in instructions stored by a non-transitory computer-readable medium, and that, when executed, cause a processor of a computing device (e.g., a display fabrication system) to perform one or more of the operations of method 600.

[0078] While FIG. 6 shows illustrative operations 602-610 according to a specific implementation, it will be understood that other implementations of this method may omit, add to, reorder, and / or modify any of operations 602-610 that are explicitly represented in FIG. 6. Additionally, while operations shown in FIG. 6 are illustrated with arrows suggestive of a sequential order of operation, it will be understood that some or all of the operations of method 600 may be performed concurrently (e.g., in parallel) with one another. Each of the operations of these methods will now7be described in more detail as the operations may be performed by a system such as a display fabrication system. Additionally, as mentioned above, further detail related to certain of the operations will be given with reference to FIGS. 7A-7G.

[0079] At operation 602, a display fabrication system may attach a first driver circuit and a second driver circuit to a substrate carrier. For example, as an alternative to the superstate used in the top-down approach described above in relation to FIGS. 2-4K, the bottom-up approach may involve building the same or a similar assembly starting from asubstrate at the bottom that is similarly configured to hold the assembly together and provide a platform for the construction. To further illustrate operation 602, FIGS. 7A and 7B show illustrative aspects of various intermediate steps that may be performed in furtherance of operation 602.

[0080] In FIG. 7 A, a step 700- A illustrates a substrate carrier 540 that may be produced, constructed, or otherwise obtained. In contrast to superstate carrier 230 described above, there may not be any particular advantage to constructing substrate carrier 540 from a transparent material (e.g., glass or plastic) since substrate carrier 540 forms the bottom of the display assembly, such that the pixel emitters will not emit light therethrough. However, similar to superstate carrier 230, substrate carrier 540 may also serve as a carrier sheet that helps to mechanically hold the display assembly together as sets of emitter traces and controller traces, circuitry (e.g., driver circuits and controller circuit), and dielectric material are deposited in layers onto substrate carrier 540. Additionally, like superstrate carrier 230, substrate carrier 540 may have other desirable mechanical properties such as being relatively thin (e.g., with a thickness less than 100 microns, less than 40 microns, etc.), being constructed from insulative material, forming a desirable shape (including irregular and non- rectangular shapes in some examples), and being constructed of a flexible material configured to allow the display assembly, when flexed, to bend without being damaged.

[0081] Upon obtaining or constructing substrate carrier 540, step 700-A illustrates that driver circuit 516 may be attached to the substrate carrier. This may be performed using any suitable bonding technique, adhesive, of the like.

[0082] In FIG. 7B, a step 700-B involves depositing a first dielectric layer 534 to the substrate carrier 540. More particularly, as shown, an interlayer dielectric (ILD) of an insulative material is applied so as to enclose and protect driver circuit 516 and, as will be illustrated below, to support a metal layer that will provide contact for the driver circuit to fan out to the pixel emitters (as emitter traces 520).

[0083] Returning to FIG. 6, operations 604-608 may be performed to deposit various traces subsequent to the attaching of the driver circuits at operation 602. More particularly, at operation 604, the display fabrication system may deposit a set of controller traces configured to electrically couple a controller circuit to the first driver circuit and the second driver circuit. At operation 606, the display fabrication system may deposit a first set of emitter traces configured to electrically couple the first driver circuit to a first subset of a set of pixel emitters. Similarly, at operation 608, the display fabrication system may deposit a second set of emitter traces configured to electrically couple the second driver circuit to a second subsetof the set of pixel emitters. It will be understood that these operations may be performed in parallel (e.g.. as part of the same metal layer) in certain implementations, while in other implementations, operation 604 may be performed separately from operation 606 and 608 (e.g., in the event that the controller trace 524 is on a different layer than the set of emitter traces 520). Moreover, at the time of performing these operations, it will be understood that the display fabrication system may also deposit other respective sets of emitter traces configured to electncally couple other dnver circuits to their own subset of the set of pixel emitters.

[0084] FIG. 5 and FIGS. 7A-7G show an example of a single subset of pixel emitters (i.e., subset 518) and a single set of emitter traces (i.e., emitter traces 520), though it will be understood that operations 604-608 may be performed throughout the display assembly to connect the entire set of pixel emitters 510 to respective driver circuits assigned thereto. To further illustrate operations 604-608, FIGS. 7C-7E show illustrative aspects of various intermediate steps that may be performed in furtherance of operations 604-608.

[0085] In FIG. 7C, a step 700-C involves depositing a first metal layer implementing emitter traces 520 and controller trace 524 onto the first dielectric layer 534 deposited at step 700-B. As in the example of FIG. 2 described above, the relatively limited number of pixel emitters 510 in subset 518 of FIG. 5 makes it possible for all of the emitter traces 520 to be routed on a same layer as one another and as controller trace 524 in this example. As shown, the first metal layer illustrated in FIG. 7C includes traces configured to electrically couple to the driver circuit 516 and to then run over the first dielectric layer 534 to fan out to the pixel emitters 510 and controller circuit (not shown in FIG. 7C). While the fanout of emitter traces 520 is not visible from side view 500-2 and the corresponding views in FIGS. 7A-7G, it will be understood that emitter traces 520 and controller trace 524 deposited at step 700-C may fan out in a manner such as is illustrated in implementation 100 and top view 500-1 shown above. As with emitter traces 220, emitter traces 520 may be constructed of any suitable conductive material and may be deposited using any suitable technique.

[0086] In FIG. 7D. a step 700-D involves depositing a second dielectric layer 534 to the substrate carrier 540. More particularly, as shown, insulative 1LD material may be applied at step 700-D to enclose and support the metal layer comprising the emitter traces 520 and controller trace 524 that were deposited at step 700-C.

[0087] In FIG. 7E, a step 700-E involves depositing another metal layer to prepare emitter traces 520 to bond with the pixel emitters 510 when they are placed. As has been described, it will be understood that while a single metal layer is shown in this example to besufficient for all the routing, other implementations may employ two or more layers of metal and dielectric to achieve the routing of all the sets of emitter traces (including emitter traces 520) and the entire set of controller traces (including controller trace 524).

[0088] Returning to FIG. 6, at operation 610, the display fabrication system may transfer a set of pixel emitters from a donor wafer to the display assembly. For example, as was illustrated and described in relation to FIG. 1. the set of pixel emitters (e.g., the set of pixel emitters 110) may have been fabricated on the donor wafer (e.g., donor wafer 106) and then transferred to a display assembly being constructed on a carrier sheet (i.e., a substrate carrier in this example) so that the pixel emitters can be spread out for better direct viewing and for various other reasons (e.g., to allow for a flexible display, etc ). Because the displayassembly is being built from the bottom-up in this example, operation 610 may be performed subsequent to the depositing of the set of controller traces at operation 604, the first set of emitter traces at operation 606, and the second set of emitter traces at operation 608. In other words, operation 610 may be performed once the routing is already in place to the emitter and controller circuits so that, once the pixel emitters are bonded to the emitter traces 520, the electrical connections to the circuitry will be in place. FIG. 7F shows illustrative aspects to further illustrate operation 610.

[0089] In FIG. 7F, a step 700-F involves the coupling of the set of pixel emitters 510 to the emitter traces 520 that were prepared in step 700-E. In other words, at this step, the pixel emitters 510 may be transferred from the donor wafer and bonded to the dielectric layer 534 and emitter traces 520 using any suitable adhesive or bonding technique. As described and illustrated previously, the set of pixel emitters 510 may have been fabricated at a first pixel pitch (e.g., analogous to pixel pitch 114-1 in FIG. 1) that is relatively small and may- then be transferred to have a second pixel pitch (e.g., analogous to pixel pitch 114-2 in FIG. 1) on the display assembly (though this is not necessarily drawn to scale in FIG. 7F).

[0090] In some examples, the output of step 700-F shown in FIG. 7F may be considered to be complete and ready for use as a display assembly to be installed in a device such as a smartwatch or the like. In other examples, one or more additional layers may be added for various reasons. For instance, a transparent layer of material configured to protect pixel emitters 510 without interfering with the light they emit could be added above the top dielectric layer 534. As another example, a cover glass similar to superstrate carrier 230 illustrated above could be added to the display assembly to serve a similar purpose. The cover glass may be constructed of a transparent material through which the set of pixel emitters is configured to emit light, and, in some implementations, a set of optical devices similar tooptical devices 232 could be integrated within the cover glass and configured to manipulate the light emitted through the transparent material of the cover glass by the set of pixel emitters in a similar way as described above.

[0091] To illustrate, FIG. 7G shows a step 700-G in which a cover glass 530 (numbered to indicate the cover glass’s similarity with superstrate carrier 230) is applied to the display assembly as assembled in FIG. 7F. As shown, cover glass 530 includes a plurality of optical devices 532 that are configured to perform a similar role as the role of optical devices 232 described above (e g., manipulating light emitted through the transparent material of the cover glass by pixel emitters 510).

[0092] Returning to FIG. 6, each of the operations has been described in relation to further illustration in FIGS. 7A-7G. It will also be understood that other operations not explicitly shown in FIG. 6 or FIGS. 7A-7G may be part of method 600 in certain implementations. For instance, operations involving fabricating the set of pixel emitters 510 on the donor wafer may be performed prior to the transferring of the set of pixel emitters to the display assembly at operation 610. As another example, operations involving finishing the display assembly and installing it for use in an electronic device (e.g., a smartwatch or other suitable device) could be performed subsequent to operation 610.

[0093] The following examples describe implementations of direct-view display assemblies with sparse distributions of pixel emitters in accordance w ith principles described herein.

[0094] Example 1: A method comprising: transferring a set of pixel emitters from a donor w afer to a superstrate carrier, the set of pixel emitters being fabricated on the donor wafer at a first pixel pitch and distributed onto the superstrate carrier at a second pixel pitch greater than the first pixel pitch; subsequent to the transferring of the set of pixel emitters, depositing: a first set of emitter traces configured to electrically couple a first driver circuit to a first subset of the set of pixel emitters, and a second set of emitter traces configured to electrically couple a second driver circuit to a second subset of the set of pixel emitters; subsequent to the depositing of the first set of emitter traces and the second set of emitter traces, attaching the first dnver circuit to the first set of emitter traces and the second driver circuit to the second set of emitter traces; and depositing a set of controller traces configured to electrically couple a controller circuit to the first driver circuit and the second driver circuit.

[0095] Example 2: The method of any of Examples 1 to 2, wherein: the superstrate carrier is constructed of a transparent material through which the set of pixel emitters isconfigured to emit light; and a set of optical devices is integrated within the supers irate carrier and configured to manipulate the light emitted through the transparent material of the superstate earner by the set of pixel emitters.

[0096] Example 3: The method of any of Examples 1 to 3, wherein the first set of emitter traces and the second set of emitter traces are deposited on a plurality of layers separated by dielectric material.

[0097] Example 4: The method of any of Examples 1 to 4, wherein: the superstrate carrier is constructed of a flexible material; the first driver circuit and the second driver circuit are implemented by complementary -metal-oxide-semiconductor (CMOS) chips; and the set of pixel emitters are implemented by micro light emitting diodes (microLEDs).

[0098] Example 5: The method of any of any of the preceding examples, wherein the first subset of the set of pixel emitters includes pixel emitters in a non-rectilinear arrangement.

[0099] Example 6: The method of any of Examples 1 to 5, wherein the first driver circuit and the second driver circuit are fabricated with through-silicon vias configured to support a double-sided routing scheme in which: the first set of emitter traces and the second set of emitter traces are implemented in one or more layers on a first side of the first driver circuit and the second driver circuit; and the set of controller traces are implemented in one or more layers on a second side of the first driver circuit and the second driver circuit, the second side opposite the first side.

[0100] Example 7: The method of any of Examples 1 to 6, wherein: the first driver circuit and the second driver circuit are attached to a printed circuit board; and the first set of emitter traces, the second set of emitter traces, and the set of controller traces are deposited to the superstrate carrier, are deposited to the printed circuit board, or are distributed between the superstrate carrier and the printed circuit board.

[0101] Example 8: The method of any of Examples 1 to 7, further comprising fabricating the set of pixel emitters on the donor wafer prior to the transferring of the set of pixel emitters to the superstrate carrier.

[0102] Example 9: A method comprising: attaching a first driver circuit and a second driver circuit to a substrate carrier; subsequent to the attaching of the first driver circuit and the second driver circuit, depositing: a set of controller traces configured to electrically couple a controller circuit to the first driver circuit and the second driver circuit, a first set of emitter traces configured to electrically couple the first driver circuit to a first subset of a set of pixel emitters, and a second set of emitter traces configured to electrically couple thesecond driver circuit to a second subset of the set of pixel emitters; and subsequent to the depositing of the set of controller traces, the first set of emitter traces, and the second set of emitter traces, transferring the first subset and the second subset of the set of pixel emitters from a donor wafer to couple, respectively, with the first set of emitter traces and the second set of emitter traces on the substrate carrier, the pixel emitters being fabricated on the donor wafer at a first pixel pitch and distributed onto the substrate carrier at a second pixel pitch greater than the first pixel pitch.

[0103] Example 10: The method of Example 9, further comprising applying, subsequent to the transferring of the first subset and the second subset of the set of pixel emitters, a cover glass to the set of pixel emitters, the cover glass being constructed of a transparent material through which the set of pixel emitters is configured to emit light; wherein a set of optical devices is integrated within the cover glass and configured to manipulate the light emitted through the transparent material of the cover glass by the pixel emitters.

[0104] Example 11 : The method of any of Examples 9 to 10, wherein the first set of emitter traces and the second set of emitter traces are deposited on a plurality of layers separated by dielectric material.

[0105] Example 12: The method of any of Examples 9 to 11, wherein: the substrate carrier is constructed of a flexible material; the first driver circuit and the second driver circuit are implemented by complementary -metal-oxide-semiconductor (CMOS) chips; and the set of pixel emitters are implemented by micro light emitting diodes (microLEDs).

[0106] Example 13: The method of any of any of Examples 9 to 12, wherein the first subset of the set of pixel emitters includes pixel emitters in a non-rectilinear arrangement.

[0107] Example 14: The method of any of Examples 9 to 13, wherein the first driver circuit and the second driver circuit are fabricated with through-silicon vias configured to support a double-sided routing scheme in which: the first set of emitter traces and the second set of emitter traces are implemented in one or more layers on a first side of the first driver circuit and the second driver circuit; and the set of controller traces are implemented in one or more layers on a second side of the first driver circuit and the second driver circuit, the second side opposite the first side.

[0108] Example 15: The method of any of Examples 9 to 14, further comprising fabricating the set of pixel emitters on the donor wafer prior to the transferring of the first subset and the second subset of the set of pixel emitters.

[0109] Example 16: A display assembly comprising: a set of pixel emitters disposedin the display assembly, the set of pixel emitters being transferred to the display assembly from a donor wafer on which the set of pixel emitters were fabricated, the set of pixel emitters fabricated at a first pixel pitch and distributed within the display assembly at a second pixel pitch greater than the first pixel pitch; a first driver circuit electrically coupled to a first subset of the set of pixel emitters via a first set of emitter traces; a second driver circuit electrically coupled to a second subset of the set of pixel emitters via a second set of emitter traces; and a controller circuit electrically coupled to the first driver circuit and the second driver circuit via a set of controller traces.

[0110] Example 17: The display assembly of Example 16, further comprising a supers Irate carrier constructed of a transparent material; wherein: the set of pixel emitters is transferred to the superstrate carrier from the donor wafer and configured to emit light through the transparent material of the superstrate carrier, and the first set of emitter traces, the second set of emitter traces, the set of controller traces, and dielectric material are deposited in layers onto the superstrate carrier.

[0111] Example 18: The display assembly of Example 17, further comprising a set of optical devices integrated within the superstrate earner and configured to manipulate the light emitted through the transparent material of the superstrate carrier by the set of pixel emitters.

[0112] Example 19: The display assembly of Example 16, further comprising a substrate carrier to which the first driver circuit and the second driver circuit are attached; wherein the set of controller traces, the first set of emitter traces, the second set of emitter traces, and dielectric material are deposited in layers onto the substrate carrier.

[0113] Example 20: The display assembly of Example 19, further comprising: a cover glass constructed of a transparent material through which the set of pixel emitters is configured to emit light; and a set of optical devices integrated within the cover glass and configured to manipulate the light emitted through the transparent material of the cover glass by the set of pixel emitters.

[0114] Example 21 : The display assembly of any of Examples 16 to 20, wherein the display assembly is configured for use as a smartwatch display.

[0115] Various implementations of the systems and techniques described herein can be realized in digital electronic circuitry, integrated circuitry, specially designed ASICs (application specific integrated circuits), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose.coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0116] A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the description and claims. In addition, the logic flows depicted in the figures do not require the particular order shown, or sequential order, to achieve desirable results. In addition, other steps may be provided, or steps may be eliminated, from the described flows, and other components may be added to, or removed from, the described systems. Accordingly, other implementations are within the scope of the following claims.

[0117] Specific structural and functional details disclosed herein are merely representative for purposes of describing example implementations. Example implementations, however, may be embodied in many alternate forms and should not be construed as limited to only the implementations set forth herein.

[0118] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. A first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the implementations of the disclosure. As used herein, the term and / or includes any and all combinations of one or more of the associated listed items.

[0119] The terminology used herein is for the purpose of describing particular implementations only and is not intended to be limiting of the implementations. As used herein, the singular forms “a,” “an,’' and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and / or “including,” when used in this specification, specify the presence of the stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0120] It will be understood that when an element is referred to as being “coupled.” “connected,” or “responsive” to, or “on,” another element, it can be directly coupled, connected, or responsive to, or on, the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly coupled,” “directly connected,” or “directly responsive” to, or “directly on,” another element, there are nointervening elements present. As used herein the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0121] Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature in relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 130 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0122] Unless otherwise defined, the terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which these concepts belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0123] Further to the descriptions above, a user may be provided with controls allowing the user to make an election as to both if and when systems, programs, or features described herein may enable collection of user information (e.g., information about a user's social network, social actions, or activities, profession, a user's preferences, or a user's current location), and if the user is sent content or communications from a server. In addition, certain data may be treated in one or more ways before it is stored or used, so that personally identifiable information is removed. For example, a user's identity may be treated so that no personally identifiable information can be determined for the user, or a user's geographic location may be generalized, or location information may be obtained (such as to a city, zip code, or state level), so that a particular location of a user cannot be determined. Thus, the user may have control over what information is collected about the user, how- that information is used, and what information is provided to the user.

[0124] While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes, and equivalents may occur to those skilled in the art. It is therefore to be understood that the appended claims areintended to cover such modifications and changes as fall within the scope of the implementations. It will be understood that they have been presented by way of example only, not limitation, and various changes in form and details may be made. Any portion of the apparatus and / or methods described herein may be combined in any combination, except mutually exclusive combinations. The implementations described herein can include various combinations and / or sub-combinations of the functions, components, and / or features of the different implementations described. As such, the scope of the present disclosure is not limited to the particular combinations hereafter claimed, but instead extends to encompass any combination of features or example implementations described herein irrespective of whether or not that particular combination has been specifically enumerated in the accompanying claims at this time.

Claims

WHAT IS CLAIMED IS:

1. A method comprising: transferring a set of pixel emitters from a donor wafer to a superstrate carrier, the set of pixel emitters being fabricated on the donor wafer at a first pixel pitch and distributed onto the superstrate carrier at a second pixel pitch greater than the first pixel pitch; subsequent to the transferring of the set of pixel emitters, depositing: a first set of emitter traces configured to electrically couple a first driver circuit to a first subset of the set of pixel emitters, and a second set of emitter traces configured to electrically couple a second driver circuit to a second subset of the set of pixel emitters; subsequent to the depositing of the first set of emitter traces and the second set of emitter traces, attaching the first driver circuit to the first set of emitter traces and the second driver circuit to the second set of emitter traces; and depositing a set of controller traces configured to electrically couple a controller circuit to the first driver circuit and the second driver circuit.

2. The method of claim 1, wherein: the superstrate carrier is constructed of a transparent material through which the set of pixel emitters is configured to emit light; and a set of optical devices is integrated within the superstrate carrier and configured to manipulate the light emitted through the transparent material of the superstrate carrier by the set of pixel emitters.

3. The method of any of claims 1 to 2, wherein the first set of emitter traces and the second set of emitter traces are deposited on a plurality of layers separated by dielectric material.

4. The method of any of claims 1 to 3, wherein: the superstrate carrier is constructed of a flexible material; the first driver circuit and the second driver circuit are implemented by complementary-metal-oxide-semiconductor (CMOS) chips: and the set of pixel emitters are implemented by micro light emitting diodes (microLEDs).

5. The method of any of claims 1 to 4, wherein the first subset of the set of pixel emitters includes pixel emitters in a non-rectilinear arrangement.

6. The method of any of claims 1 to 5, wherein the first driver circuit and the second driver circuit are fabricated with through-silicon vias configured to support a doublesided routing scheme in which: the first set of emitter traces and the second set of emitter traces are implemented in one or more layers on a first side of the first driver circuit and the second driver circuit: and the set of controller traces are implemented in one or more layers on a second side of the first driver circuit and the second driver circuit, the second side opposite the first side.

7. The method of any of claims 1 to 6, wherein: the first driver circuit and the second driver circuit are attached to a printed circuit board; and the first set of emitter traces, the second set of emitter traces, and the set of controller traces are deposited to the superstrate carrier, are deposited to the printed circuit board, or are distributed between the superstrate carrier and the printed circuit board.

8. The method of any of claims 1 to 7, further comprising fabricating the set of pixel emitters on the donor wafer prior to the transferring of the set of pixel emitters to the superstrate carrier.

9. A method comprising: attaching a first driver circuit and a second driver circuit to a substrate carrier; subsequent to the attaching of the first driver circuit and the second driver circuit, depositing: a set of controller traces configured to electrically couple a controller circuit to the first driver circuit and the second driver circuit, a first set of emitter traces configured to electrically couple the first driver circuit to a first subset of a set of pixel emitters, and a second set of emitter traces configured to electrically couple the second driver circuit to a second subset of the set of pixel emitters; and subsequent to the depositing of the set of controller traces, the first set of emitter traces, and the second set of emitter traces, transferring the first subset and the second subsetof the set of pixel emitters from a donor wafer to couple, respectively, with the first set of emitter traces and the second set of emitter traces on the substrate carrier, the pixel emitters being fabricated on the donor wafer at a first pixel pitch and distributed onto the substrate carrier at a second pixel pitch greater than the first pixel pitch.

10. The method of claim 9. further comprising applying, subsequent to the transferring of the first subset and the second subset of the set of pixel emitters, a cover glass to the set of pixel emitters, the cover glass being constructed of a transparent material through which the set of pixel emitters is configured to emit light; wherein a set of optical devices is integrated within the cover glass and configured to manipulate the light emitted through the transparent material of the cover glass by the pixel emitters.

11. The method of any of claims 9 to 10, wherein the first set of emitter traces and the second set of emitter traces are deposited on a plurality of layers separated by dielectric material.

12. The method of any of claims 9 to 11, wherein: the substrate carrier is constructed of a flexible material; the first driver circuit and the second driver circuit are implemented by complementary-metal-oxide-semiconductor (CMOS) chips; and the set of pixel emitters are implemented by micro light emitting diodes (microLEDs).

13. The method of any of claims 9 to 12. wherein the first subset of the set of pixel emitters includes pixel emitters in a non-rectilinear arrangement.

14. The method of any of claims 9 to 13, wherein the first driver circuit and the second driver circuit are fabricated with through-silicon vias configured to support a doublesided routing scheme in which: the first set of emitter traces and the second set of emitter traces are implemented in one or more layers on a first side of the first driver circuit and the second driver circuit; and the set of controller traces are implemented in one or more layers on a second side of the first driver circuit and the second driver circuit, the second side opposite the first side.

15. The method of any of claims 9 to 14, further comprising fabricating the set of pixel emitters on the donor wafer prior to the transferring of the first subset and the second subset of the set of pixel emitters.

16. A display assembly comprising: a set of pixel emitters disposed in the display assembly, the set of pixel emitters being transferred to the display assembly from a donor wafer on which the set of pixel emitters were fabricated, the set of pixel emitters fabricated at a first pixel pitch and distributed within the display assembly at a second pixel pitch greater than the first pixel pitch; a first driver circuit electrically coupled to a first subset of the set of pixel emitters via a first set of emitter traces; a second driver circuit electrically coupled to a second subset of the set of pixel emitters via a second set of emitter traces; and a controller circuit electrically coupled to the first driver circuit and the second driver circuit via a set of controller traces.

17. The display assembly of claim 16, further comprising a superstrate carrier constructed of a transparent material; wherein: the set of pixel emitters is transferred to the superstrate carrier from the donor wafer and configured to emit light through the transparent material of the superstrate carrier, and the first set of emitter traces, the second set of emitter traces, the set of controller traces, and dielectric material are deposited in layers onto the superstrate carrier.

18. The display assembly of claim 17, further comprising a set of optical devices integrated within the superstrate carrier and configured to manipulate the light emitted through the transparent material of the superstrate carrier by the set of pixel emitters.

19. The display assembly of claim 16, further comprising a substrate carrier to which the first driver circuit and the second driver circuit are attached; wherein the set of controller traces, the first set of emitter traces, the second set of emitter traces, and dielectric material are deposited in layers onto the substrate carrier.

20. The display assembly of claim 19, further comprising: a cover glass constructed of a transparent material through which the set of pixel emitters is configured to emit light; and a set of optical devices integrated within the cover glass and configured to manipulate the light emitted through the transparent material of the cover glass by the set of pixel emitters.

21. The display assembly of any of claims 16 to 20, wherein the display assembly is configured for use as a smartwatch display.ABSTRACTDirect-view display assemblies with sparse distributions of pixel emitters are described herein, along with methods for their construction. One example display assembly includes a set of pixel emitters that are transferred to the display assembly from a donor wafer on which the pixel emitters were fabricated. While fabricated at a first pixel pitch, these pixel emitters are distributed within the display assembly at a second pixel pitch greater than the first pixel pitch. The display assembly further includes a first driver circuit electrically coupled to a first subset of the set of pixel emitters via a first set of emitter traces, a second driver circuit electrically coupled to a second subset of the set of pixel emitters via a second set of emitter traces, and a controller circuit electrically coupled to the first driver circuit and the second driver circuit via a set of controller traces.WHAT IS CLAIMED IS:

1. A method comprising: transferring a set of pixel emitters from a donor wafer to a superstrate carrier, the set of pixel emitters being fabricated on the donor wafer at a first pixel pitch and distributed onto the superstrate carrier at a second pixel pitch greater than the first pixel pitch; subsequent to the transferring of the set of pixel emitters, depositing: a first set of emitter traces configured to electrically couple a first driver circuit to a first subset of the set of pixel emitters, and a second set of emitter traces configured to electrically couple a second driver circuit to a second subset of the set of pixel emitters; subsequent to the depositing of the first set of emitter traces and the second set of emitter traces, attaching the first driver circuit to the first set of emitter traces and the second driver circuit to the second set of emitter traces; and depositing a set of controller traces configured to electrically couple a controller circuit to the first driver circuit and the second driver circuit.

2. The method of claim 1, wherein: the superstrate carrier is constructed of a transparent material through which the set of pixel emitters is configured to emit light; and a set of optical devices is integrated within the superstrate carrier and configured to manipulate the light emitted through the transparent material of the superstrate carrier by the set of pixel emitters.

3. The method of any of claims 1 to 2, wherein the first set of emitter traces and the second set of emitter traces are deposited on a plurality of layers separated by dielectric material.

4. The method of any of claims 1 to 3, wherein: the superstrate carrier is constructed of a flexible material; the first driver circuit and the second driver circuit are implemented by complementary-metal-oxide-semiconductor (CMOS) chips: and the set of pixel emitters are implemented by micro light emitting diodes (microLEDs).

5. The method of any of claims 1 to 4, wherein the first subset of the set of pixel emitters includes pixel emitters in a non-rectilinear arrangement.

6. The method of any of claims 1 to 5, wherein the first driver circuit and the second driver circuit are fabricated with through-silicon vias configured to support a doublesided routing scheme in which: the first set of emitter traces and the second set of emitter traces are implemented in one or more layers on a first side of the first driver circuit and the second driver circuit: and the set of controller traces are implemented in one or more layers on a second side of the first driver circuit and the second driver circuit, the second side opposite the first side.

7. The method of any of claims 1 to 6, wherein: the first driver circuit and the second driver circuit are attached to a printed circuit board; and the first set of emitter traces, the second set of emitter traces, and the set of controller traces are deposited to the superstrate carrier, are deposited to the printed circuit board, or are distributed between the superstrate carrier and the printed circuit board.

8. The method of any of claims 1 to 7, further comprising fabricating the set of pixel emitters on the donor wafer prior to the transferring of the set of pixel emitters to the superstrate carrier.

9. A method comprising: attaching a first driver circuit and a second driver circuit to a substrate carrier; subsequent to the attaching of the first driver circuit and the second driver circuit, depositing: a set of controller traces configured to electrically couple a controller circuit to the first driver circuit and the second driver circuit, a first set of emitter traces configured to electrically couple the first driver circuit to a first subset of a set of pixel emitters, and a second set of emitter traces configured to electrically couple the second driver circuit to a second subset of the set of pixel emitters; and subsequent to the depositing of the set of controller traces, the first set of emitter traces, and the second set of emitter traces, transferring the first subset and the second subset35of the set of pixel emitters from a donor wafer to couple, respectively, with the first set of emitter traces and the second set of emitter traces on the substrate carrier, the pixel emitters being fabricated on the donor wafer at a first pixel pitch and distributed onto the substrate carrier at a second pixel pitch greater than the first pixel pitch.

10. The method of claim 9. further comprising applying, subsequent to the transferring of the first subset and the second subset of the set of pixel emitters, a cover glass to the set of pixel emitters, the cover glass being constructed of a transparent material through which the set of pixel emitters is configured to emit light; wherein a set of optical devices is integrated within the cover glass and configured to manipulate the light emitted through the transparent material of the cover glass by the pixel emitters.

11. The method of any of claims 9 to 10, wherein the first set of emitter traces and the second set of emitter traces are deposited on a plurality of layers separated by dielectric material.

12. The method of any of claims 9 to 11, wherein: the substrate carrier is constructed of a flexible material; the first driver circuit and the second driver circuit are implemented by complementary-metal-oxide-semiconductor (CMOS) chips; and the set of pixel emitters are implemented by micro light emitting diodes (microLEDs).

13. The method of any of claims 9 to 12. wherein the first subset of the set of pixel emitters includes pixel emitters in a non-rectilinear arrangement.

14. The method of any of claims 9 to 13, wherein the first driver circuit and the second driver circuit are fabricated with through-silicon vias configured to support a doublesided routing scheme in which: the first set of emitter traces and the second set of emitter traces are implemented in one or more layers on a first side of the first driver circuit and the second driver circuit; and the set of controller traces are implemented in one or more layers on a second side of the first driver circuit and the second driver circuit, the second side opposite the first side.3615. The method of any of claims 9 to 14, further comprising fabricating the set of pixel emitters on the donor wafer prior to the transferring of the first subset and the second subset of the set of pixel emitters.

16. A display assembly comprising: a set of pixel emitters disposed in the display assembly, the set of pixel emitters being transferred to the display assembly from a donor wafer on which the set of pixel emitters were fabricated, the set of pixel emitters fabricated at a first pixel pitch and distributed within the display assembly at a second pixel pitch greater than the first pixel pitch; a first driver circuit electrically coupled to a first subset of the set of pixel emitters via a first set of emitter traces; a second driver circuit electrically coupled to a second subset of the set of pixel emitters via a second set of emitter traces; and a controller circuit electrically coupled to the first driver circuit and the second driver circuit via a set of controller traces.

17. The display assembly of claim 16, further comprising a superstrate carrier constructed of a transparent material; wherein: the set of pixel emitters is transferred to the superstrate carrier from the donor wafer and configured to emit light through the transparent material of the superstrate carrier, and the first set of emitter traces, the second set of emitter traces, the set of controller traces, and dielectric material are deposited in layers onto the superstrate carrier.

18. The display assembly of claim 17, further comprising a set of optical devices integrated within the superstrate carrier and configured to manipulate the light emitted through the transparent material of the superstrate carrier by the set of pixel emitters.

19. The display assembly of claim 16, further comprising a substrate carrier to which the first driver circuit and the second driver circuit are attached; wherein the set of controller traces, the first set of emitter traces, the second set of emitter traces, and dielectric material are deposited in layers onto the substrate carrier.3720. The display assembly of claim 19, further comprising: a cover glass constructed of a transparent material through which the set of pixel emitters is configured to emit light; and a set of optical devices integrated within the cover glass and configured to manipulate the light emitted through the transparent material of the cover glass by the set of pixel emitters.

21. The display assembly of any of claims 16 to 20, wherein the display assembly is configured for use as a smartwatch display.38

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