Die offset correction method, computer storage medium and manufacturing method for chip device

Abstract

The present application discloses a die offset correction method, a computer storage medium, and a manufacturing method for a chip device. The die offset correction method comprises: acquiring offset data of each die in a bare die unit, wherein the bare die unit comprises a plurality of dies; acquiring an original interconnection line graph between the dies in the bare die unit; determining a wiring area on the basis of ideal position data of each die in the bare die unit; and on the basis of the offset data of each die, performing offset correction on a line, located in the wiring area, in the original interconnection line graph.

Description

Grain deviation correction method, computer storage medium and chip device preparation method

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on November 16, 2023, with application number 202311545908.6 and entitled “Grain Correction Method, Computer Storage Medium and Chip Device Preparation Method,” the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of chip technology, and in particular to a method for preparing a grain deviation correction method, a computer storage medium, and a chip device. Background Art

[0004] Chiplet technology involves splitting a bare chip into multiple dies and then packaging them. During this process, multiple dies are attached to a substrate using a placement machine. This can cause the dies to shift, and the accuracy of the placement machine determines the amount of displacement between the dies. However, even high-precision placement machines cannot prevent dies from shifting, resulting in inter-die communication and data transmission issues.

[0005] Public content

[0006] This application aims to solve at least one of the technical problems existing in the prior art. To this end, one purpose of this application is to propose a die-to-die correction method that can correct the offset data between dies within the routable area, enabling communication and data transmission between dies to be restored, thereby reducing the dependence on high-precision placement equipment.

[0007] A second objective of this application is to provide a computer storage medium.

[0008] A third objective of this application is to provide a method for preparing a chip device.

[0009] In order to solve the above problems, the first embodiment of the present application provides a grain correction method, including: obtaining offset data of each grain in a bare chip unit, wherein the bare chip unit includes multiple grains; obtaining an original diagram of interconnection lines between grains on the bare chip unit; determining a routable area based on the ideal position data of each grain in the bare chip unit; and correcting the lines in the original diagram of interconnection lines located in the routable area based on the offset data of each grain.

[0010] According to the die correction method of the embodiment of the present application, the offset data of each die in the bare chip unit is used to change the direction, position or shape of the line located in the routable area in the original diagram of the interconnection line, that is, the original diagram of the interconnection line is rewired and adjusted, so as to complete the correction of the offset data between the die in the routable area. At this time, the die can be reconnected through the adjusted interconnection line, so that communication and data transmission can be realized between the die, thereby reducing the dependence on high-precision placement equipment.

[0011] In some embodiments, the width of the routable area is greater than a reference value, and the reference value is a maximum allowable offset when a patch device performs a patch process on the die.

[0012] In some embodiments, the width of the routable area is greater than or equal to a reference value, where the reference value is equal to a maximum allowable offset of a patch device when performing a patch process on the die*2.

[0013] In some embodiments, the offset data includes at least relative displacement data and relative rotation angle between the current position data of each of the grains and the ideal position data of the grains, and the interconnection lines located in the routable area are corrected according to the offset data of each of the grains, including: correcting the interconnection lines located in the routable area according to the relative displacement data and the relative rotation angle.

[0014] In some embodiments, the shape of the routable area is polygonal.

[0015] In some embodiments, the number of the routable regions is less than or equal to the number of the dies.

[0016] In some embodiments, the number of the routable areas is equal to the number of the dies, each of the routable areas is disposed around the periphery of the corresponding die, and a gap exists between a boundary of the routable area and a boundary of the die.

[0017] A second aspect of the present application provides a computer storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the grain deviation correction method described in the above embodiment.

[0018] A third aspect of the present application provides a method for preparing a chip device, including: providing a packaging substrate and a bare chip unit; obtaining a bare chip unit circuit diagram after correction using the grain correction method described in the above embodiment; exposing the bare chip unit according to the bare chip unit circuit diagram to obtain an exposed bare chip unit; and packaging the exposed bare chip unit on the packaging substrate to obtain a chip device.

[0019] According to the preparation method of the chip device of the embodiment of the present application, the grain correction method of the above embodiment is executed to obtain the bare chip unit circuit diagram after correction, and then a single bare chip unit is subjected to splicing exposure through the bare chip unit circuit diagram, or a plurality of bare chip units are subjected to full-plate pattern exposure, so that the full-plate pattern can be exposed at one time, thereby improving the production capacity of the mask exposure equipment and reducing the cost, and using the bare chip unit circuit diagram after correction for exposure to improve the chip interconnection yield.

[0020] In some embodiments, there are multiple bare chip units, and obtaining the bare chip unit circuit diagram after correction using the grain correction method described in the above embodiment includes: obtaining the interconnection circuit diagram corresponding to each of the bare chip units, the interconnection circuit diagram being the circuit diagram after correction using the grain correction method; and combining all the interconnection circuit diagrams to form the bare chip unit circuit diagram.

[0021] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0023] FIG1 is a flow chart of a method for correcting grain deviation according to an embodiment of the present application;

[0024] FIG2 is a schematic diagram of a die shift in a die unit according to an embodiment of the present application;

[0025] FIG3 is a schematic diagram of a die unit according to one embodiment of the present application;

[0026] FIG4 is a schematic diagram of an original diagram of interconnection lines according to one embodiment of the present application;

[0027] FIG5 is a schematic diagram of a die shift in a die unit according to another embodiment of the present application;

[0028] FIG6 is a schematic diagram of an interconnection circuit after correction according to an embodiment of the present application;

[0029] FIG7 is a schematic diagram of a routable area according to one embodiment of the present application;

[0030] FIG8 is a schematic diagram of a routable area according to another embodiment of the present application;

[0031] FIG9 is a flow chart of a method for preparing a chip device according to one embodiment of the present application;

[0032] FIG10 is a schematic diagram of a die unit according to another embodiment of the present application;

[0033] FIG11 is a schematic diagram of an exposed die unit according to one embodiment of the present application;

[0034] FIG12 is a schematic diagram of a chip package according to an embodiment of the present application.

[0035] Reference numerals: Bare die unit 5 . DETAILED DESCRIPTION

[0036] The embodiments described with reference to the accompanying drawings are exemplary, and embodiments of the present application are described in detail below.

[0037] RDL (Redistribution Layer) is a technology used in electronic product packaging. Composed of a metal layer and a substrate, it connects external circuits to the chip's internal circuitry, forming tiny metal pins on the substrate to connect different circuits. RDL Interposer packaging technology can reduce the distance between chip-to-chip circuit connections, resulting in higher chip packaging density and significantly reducing signal trace width and spacing, thereby increasing signal density per unit area and improving circuit performance.

[0038] The semiconductor industry has consistently advanced according to Moore's Law, with chip performance doubling every 18 months thanks to iterations in chip manufacturing processes. However, as chip manufacturing processes advanced to the 5nm and 3nm nodes, increasing transistor density became increasingly challenging. Furthermore, due to the high level of integration, the following technical challenges emerged: The increased short-channel effect and quantum tunneling effects led to increasingly severe heat and leakage issues; large-area chips were more likely to contain defects than small-area chips, resulting in a direct correlation between chip yield and chip area; How to achieve lower energy consumption and higher performance, shorten line transmission distances, improve command response speed, and reduce parasitic capacitance and inductance; How to quickly reuse IP to reduce design cost and complexity, thereby facilitating rapid product iteration; How to use different chip processes for different cores, thereby reducing chip costs. To address these challenges, chiplet technology modularizes chips produced using different processes and then integrates them together through advanced packaging technology into a heterogeneous integrated chip, thereby improving performance while achieving low cost and high yield.

[0039] Chiplet technology is a key approach to continuously improving integration and chip computing power in the current era of SoC integration, as Moore's Law gradually slows. It splits a feature-rich, large bare chip (die) into multiple chiplets, combining these specialized chiplets through advanced packaging to form a system-on-chip. Its advantages include reduced complexity, reduced processing costs, and increased scalability. However, after chiplet technology splits the bare chip into multiple dies, the die will shift during packaging as they are attached to the substrate using bonding equipment. Furthermore, a series of connections are added directly to each die to facilitate data exchange between all modules. Consequently, maintaining the integrity of the data connection electrical signals during processing or multiple processing steps, as well as rapidly measuring and automatically applying data, have become new bottlenecks restricting the development of this technology.

[0040] In order to solve the above problems, the first embodiment of the present application provides a grain correction method, which can complete the correction of the offset data between grains within the routable area, so that communication and data transmission can be restored between grains, thereby reducing dependence on high-precision placement equipment.

[0041] The following describes a method for correcting grain deviation according to an embodiment of the present application with reference to FIG1 . As shown in FIG1 , the method at least includes steps S1 to S4 .

[0042] Step S1 , obtaining offset data of each die in a die unit, where the die unit includes a plurality of die.

[0043] Specifically, after a plurality of dies are attached to a substrate by a chip mounting device, a bare chip unit is formed. However, when the chip mounting device attaches the dies to the substrate, the dies will shift, as shown in the schematic diagram of the dies shifting in FIG2 . The bare chip unit is placed on a chip displacement measurement device to measure the offset data of each die in the bare chip unit. Among them, the offset data of each die includes at least: position offset data, angle offset data and expansion and contraction data, i.e., horizontal tilt data, etc., and there is no limitation on this. The multiple dies in the bare chip unit can be cores of different types or the same type. Moreover, the characteristics of the cores such as size, number of pins and usage type (storage / drive) can be different. Exemplarily, as shown in FIG2 and FIG3 , the bare chip unit includes die 1, die 2 and die 3.

[0044] Step S2: obtaining an original diagram of interconnection lines between dies on a bare die unit.

[0045] Specifically, the dies on a die unit are connected via interconnection lines. When designing the interconnection lines between dies, they must be laid out and routed according to a certain shape to enable communication and data transmission between the dies. This requires obtaining the original diagram of the interconnection lines between the dies on the die unit. FIG4 shows the original diagram of the interconnection lines, where the original diagram of the interconnection lines can be designed as Line, Shape, and Via land. A Line shape generally refers to a straight line or line used to connect two or more dies together; a Shape shape can be a specific collective image or structure, such as a T-shaped structure; and a Via land shape generally refers to a structure of a connection hole or connection point. The Via land shape can be a specific type of metallized hole on the substrate, or a specific geometric shape on the dies. When designing the interconnection lines for multiple dies within a single die, they can be arrayed in C columns and R rows.

[0046] Step S3 , determining a routable area according to the ideal position data of each die in the die unit.

[0047] Specifically, a routable area is determined based on the ideal position data of each die in the die unit. The routable area is a virtual area within the interconnection region between the die. That is, the layout of each die in the die unit is determined based on the ideal position data of each die in the die unit. Based on the layout of each die in the die unit, a routable area is designed or reasonably identified where circuit correction can be performed. The routable area can be reserved at the beginning of the die unit design or dynamically planned based on the die layout. For example, when the interconnection lines between the die are complex, such as when some of the interconnection lines between each die are in a zigzag area or when the interconnection lines near the chip area are complex, changing the interconnection lines between the die is very difficult. Adjusting the lines within these areas may affect signal transmission and the normal operation and stability of the chip. Therefore, in this application, a routable area is designed where the interconnection lines between the die are simple and easy to adjust. For example, a routable area is set in an area where the interconnection lines between the die are straight or in an area far from the chip, so that circuit correction can be performed within the routable area. Based on this, in this application, the line is corrected only in the routable area and not in other areas, thereby improving the convenience of line adjustment and avoiding the problems of signal integrity and electromagnetic interference caused by adjusting the line in the non-routable area, thereby preventing the operation of the chip and data transmission from being affected.

[0048] Step S4 , correcting the deviation of the circuits in the original interconnection circuit diagram that are located in the routable area according to the deviation data of each die.

[0049] Specifically, at present, in the process of packaging multiple dies, the dies will be offset when they are attached to the substrate by the chip mounting equipment, and the precision of the chip mounting equipment determines the displacement between the dies. However, even high-precision chip mounting equipment cannot avoid the dies from offsetting, and due to the repeatability limitation of the chip mounting equipment, the displacement between each dies in different bare chip units is also different, which causes the chip die and the designed interconnection circuit diagram to change, thereby making it impossible to achieve communication and data transmission between the dies. In order to solve this problem, the present application corrects the lines located in the routable area in the original diagram of the interconnection circuit according to the offset data of each dies, for example, the lines located in the routable area are corrected by a deformation model or direct application, that is, when the dies cannot be connected through the interconnection circuit after the dies are offset, the present application changes the direction, position or shape of the lines located in the routable area in the original diagram of the interconnection circuit according to the offset data of each dies. For example, the shape of the lines within the routable area can be changed to straight lines or geometric shapes, and the line shape changes within the routable area are calculated in real time by a real-time processing unit such as a computer server. Furthermore, based on the measured offset data for each die, the lines in the original interconnection diagram within the routable area are rerouted and adjusted. This measured offset data can then be intelligently applied to the design layer, thereby correcting the offset data between the die within the routable area. At this point, the original diagram of the interconnection lines between the die has changed, meaning that the die can be reconnected via the adjusted interconnection lines, enabling communication and data transmission between the die to be restored, thereby reducing reliance on high-precision placement equipment. Furthermore, because the lines in the routable area are relatively simple, rerouting and adjusting the lines within the original diagram of the interconnection lines within the routable area can effectively reduce the amount of calculation required to adjust the lines, thus avoiding any impact on chip operation and data transmission.

[0050] For example, a bare die unit includes three dies, as shown in FIG5 . After the die shifts, die 1, die 2, and die 3 cannot be connected via interconnection lines, and the interconnection lines are also changed. Based on the layout design of each die, routable areas 1, routable areas 2, and routable areas 3 are designed for die 1, die 2, and die 3, respectively. Based on the offset data of each die, the lines located in routable areas 1, routable areas 2, and routable areas 3 in the original interconnection line diagram are changed and adjusted. As shown in FIG6 , the dies can be reconnected through the adjusted interconnection lines, enabling communication and data transmission between the dies to be restored, thereby reducing the dependence on high-precision placement equipment.

[0051] According to the grain correction method of the embodiment of the present application, the offset data of each grain in the bare chip unit is used to change the direction, position or shape of the line located in the routable area in the original diagram of the interconnection line, that is, the original diagram of the interconnection line is rewired and adjusted, so as to complete the correction of the offset data between the grains in the routable area. At this time, the grains can be reconnected through the adjusted interconnection lines, so that communication and data transmission can be realized between the grains again, thereby reducing the dependence on high-precision patch equipment. Moreover, since the lines in the routable area are relatively simple, the amount of calculation for adjusting the lines can be effectively reduced, thereby avoiding affecting the operation and data transmission of the chip.

[0052] In some embodiments, the width of the routable area is greater than a reference value, and the reference value is the maximum allowable offset of the patch equipment when performing patch processing on the die, wherein the maximum allowable offset is the maximum offset of the patch equipment when performing patch processing on the die. Specifically, when the offset data of the die is much larger than the width of the routable area, the offset between the die cannot be eliminated during the line correction in the routable area, which means that the line routing in the routable area has failed. Therefore, the design and selection of the routable area must take into account the offset data of the die, that is, the width of the routable area should be greater than the maximum allowable offset of the patch equipment when performing patch processing on the die, so as to ensure that the offset data between the die can be corrected within the routable area.

[0053] In some embodiments, the width of the routable area is greater than or equal to a reference value, where the reference value is equal to the maximum allowable offset of the die during placement processing by the placement equipment * 2. In other words, the width of the routable area is greater than or equal to the maximum allowable offset of the die during placement processing by the placement equipment * 2, thereby ensuring that offset data between dies can be corrected within the routable area. Furthermore, the routable area has width and height, etc.

[0054] In an embodiment, dicing streets are designed or reserved between die units.

[0055] In some embodiments, the offset data includes at least relative displacement data and relative rotation angle between the current position data of each grain and the ideal position data of the grain, and the interconnection lines located in the routable area are corrected according to the offset data of each grain, including: correcting the interconnection lines located in the routable area according to the relative displacement data and the relative rotation angle.

[0056] In an embodiment, the offset data includes at least the relative displacement data and relative rotation angle between the current position data of each grain and the ideal position data of the grain, that is, the relative displacement data and relative rotation angle of each grain are obtained by calculating the theoretical position data of each grain and the current position data of each grain.

[0057] It can be seen from Table 1 that the offset data of grain 1 is calculated based on the theoretical position data of grain 1 and the current position data of grain 1, wherein the current position data and theoretical position data of the grain include the grain position coordinates (X_pos, Y_pos) and the grain rotation angle. Therefore, the relative displacement data of grain 1 calculated based on the theoretical position data and current position data of grain 1 is (-6.1, -2.1) and the relative rotation angle is 0.0216; the relative displacement data of grain 2 calculated based on the current position data and theoretical position data of grain 2 is (7.2, -3.4) and the relative rotation angle is -0.0011; the relative displacement data of grain 3 calculated based on the current position data and theoretical position data of grain 3 is (-5.4, -3.4) and the relative rotation angle is -0.00536.

[0058] Specifically, the magnitude and direction of the displacement deformation of each grain are determined based on the relative displacement data and the relative rotation angle, and then a deformation function model is fitted based on the magnitude and direction of the displacement deformation of each grain, so as to correct the interconnection lines or graphics located in the routable area according to the deformation function model. Therefore, in this application, the interconnection lines located in the routable area are corrected by the relative displacement data and the relative rotation angle, that is, the relative displacement data between the grains is corrected in the routable area, so that the grains can be reconnected through the adjusted interconnection lines, thereby re-establishing communication and data transmission between the grains, reducing dependence on high-precision patch equipment, and does not involve changes to the entire die unit, does not affect the peripheral cutting path of the die unit, and because the lines in the routable area are relatively simple, when the lines in the original interconnection line diagram located in the routable area are re-routed and adjusted, the amount of calculation required to adjust the lines can be effectively reduced, thereby avoiding affecting the operation and data transmission of the chip.

[0059] In an embodiment, the relative displacement data of each die relative to other die is modified based on the routing rules, thereby correcting the relative displacement data between the die within the routing area. The routing rules are set based on the offset data of each die and the interconnection layout. The routing rules include: removing, avoiding, and deforming characteristic patterns within the routing area; replacing bare die unit patterns; and avoiding sharp angles, changes in line impedance, and impacts on circuit physical properties such as differential signals when rerouting the original interconnection diagram.

[0060] In an embodiment, when the relative displacement data between two dies in a die unit exceeds a preset threshold, the circuits in the routable area are no longer skewed.

[0061] In some embodiments, the shape of the routable area is a polygon, wherein the polygon is a rectangle, a quadrilateral, a regular polygon, an irregular polygon, a convex polygon, a concave polygon, a triangle, a parallelogram, a rhombus, a square, a trapezoid, a pentagon, or a hexagon, without limitation. Alternatively, the shape of the routable area may be a polygonal ring.

[0062] In some embodiments, there are one or more routable regions. As shown in FIG7 , when there is one routable region, different dies share one routable region, such as Die 1 and Die 2 share routable region 4. Alternatively, there are multiple routable regions, as shown in FIG8 , where each die has its own routable region: Die 1 has routable region 1, Die 2 has routable region 2, and Die 3 has routable region 3.

[0063] In some embodiments, the number of routable areas is less than or equal to the number of dies. For example, some of all dies are not designed with routable areas. In this case, the number of routable areas is less than the number of dies.

[0064] In some embodiments, the number of routable areas is equal to the number of dies, and each routable area surrounds the periphery of the corresponding die. As shown in FIG8 , two quadrilaterals of different sizes are nested together to surround the periphery of the die, and there is a gap between the boundary of the routable area and the boundary of the die.

[0065] In some embodiments, the routable region may be located in the middle or at other locations between different dies. For example, when a die has an independent routable region, the routable region may be located between two dies, such as in the middle of the two dies; or the routable regions corresponding to the two dies may overlap; or one side of the routable regions corresponding to the two dies may overlap; or there may be a gap between the routable regions corresponding to the two dies.

[0066] A second aspect of the present application provides a computer storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the grain deviation correction method of the above embodiment is implemented.

[0067] A third embodiment of the present application provides a method for preparing a chip device, as shown in FIG9 , the method at least includes: steps S5 to S8 .

[0068] Step S5: providing a packaging substrate and a bare die unit.

[0069] In an embodiment, a package substrate (PKG) and a die unit are provided, wherein the die unit may be one or more. For example, as shown in FIG10 , a die unit with C columns and R rows repeated is designed on the package substrate, where C and R are natural numbers greater than or equal to 2, and each repeated die unit can deploy M dies, where M is a natural number greater than or equal to 1. The die unit is stacked on top of the interposer as designed by a chip transfer device. In addition, cutting paths can be designed / reserved between multiple die units.

[0070] Step S6 , obtaining a bare die unit circuit diagram after correction using the die correction method of the above embodiment.

[0071] Step S7 , performing exposure processing on the bare die unit according to the bare die unit circuit diagram to obtain an exposed bare die unit.

[0072] In an embodiment, a die unit circuit diagram is used to expose the die unit to obtain an exposed die unit. When the die unit is exposed according to the die unit circuit diagram, the die unit circuit diagram is transferred into the die unit. The die unit circuit diagram includes circuits connecting each die and circuits connecting the die to other die units. For example, as shown in Figures 4 and 11, the circuits connecting each die are transferred between the die, enabling communication and data transmission between multiple die within the die unit.

[0073] Specifically, chiplet technology splits the bare chip into multiple dies, thereby increasing the complexity of the packaging and wiring of multiple dies. Currently, the whole-plate exposure is completed by repeatedly using the process of exposing a single (type) chip wiring in a single time. However, this process seriously reduces the production capacity of the mask exposure equipment. In order to solve this problem, the bare chip unit is exposed according to the bare chip unit circuit diagram in this application, that is, a single bare chip unit is subjected to splicing exposure through the bare chip unit circuit diagram, wherein the splicing exposure is to splice multiple core particles together and expose the circuit between the core particles through exposure processing. The single bare chip unit can also be combined into a full-plate pattern for exposure, and the full plate is exposed at one time to improve the production capacity of the mask exposure equipment and reduce the cost, avoid the defective rate and low efficiency of multiple processing, save manpower, process and time costs, and improve the chip interconnection yield by exposing the bare chip unit circuit diagram after correction.

[0074] In step S8 , the exposed bare die unit is packaged on a packaging substrate to obtain a chip device.

[0075] Specifically, the exposed bare die unit is placed on a packaging substrate, and a plurality of dies in the bare die unit are connected to the packaging substrate through a bonding process to obtain a chip device.

[0076] According to the preparation method of the chip device of the embodiment of the present application, the grain correction method of the above embodiment is executed to obtain the bare chip unit circuit diagram after correction, and then a single bare chip unit is subjected to splicing exposure through the bare chip unit circuit diagram, or a plurality of bare chip units are subjected to full-plate pattern exposure, so that the full-plate pattern can be exposed at one time, thereby improving the production capacity of the mask exposure equipment and reducing the cost, and by exposing the bare chip unit circuit diagram after correction, the chip interconnection yield is improved.

[0077] In some embodiments, there are multiple bare chip units, and obtaining a bare chip unit circuit diagram after correction using the grain correction method of the above embodiment includes: obtaining an interconnection circuit diagram corresponding to each bare chip unit, the interconnection circuit diagram being a circuit diagram after correction using the grain correction method; and combining all interconnection circuit diagrams to form a bare chip unit circuit diagram.

[0078] Specifically, the entire plate exposure is currently completed by repeatedly using a process of exposing a single (type) chip wiring in a single pass. However, this process seriously reduces the production capacity of the mask exposure equipment. In order to solve this problem, in this application, multiple bare die units are exposed according to the bare die unit circuit diagram, so as to improve the production capacity of the mask exposure equipment and reduce costs by exposing the entire plate in one go. That is, the interconnection circuit diagram corresponding to each bare die unit is obtained, and the interconnection circuit diagram is a circuit diagram after correction using a grain correction method. All interconnection circuit diagrams are combined to form a bare die unit circuit diagram, and then the bare die unit circuit diagram is transferred to each bare die unit so that multiple grains in each bare die unit can achieve communication and data transmission. Therefore, in this application, all bare die units are exposed according to the bare die unit circuit diagram, and the production capacity of the mask exposure equipment and the cost are improved by exposing the entire plate in one go, avoiding the defective rate and low efficiency of multiple processing, saving manpower, process and time costs, and improving the chip interconnection yield by exposing the bare die unit circuit diagram after correction.

[0079] In an embodiment, as shown in FIG12 , the bare die units are stacked on top of an interposer and then processed through a chip packaging process. This process can expose the die pins or facilitate the next step. The process can be wafer-level packaging or panel-level packaging (PLP). The interposer is located between the die and the packaging substrate, enabling interconnection and communication between the dies.

[0080] Direct-write lithography is a technique for printing a characteristic composition on the surface of a photosensitive material (mostly a glue or film). The maskless lithography involved in this application uses a digital micromirror system to generate a composition. Through an optical projection element, the image is projected onto a light-sensitive substrate at a certain magnification to produce a characteristic composition.

[0081] Maskless lithography can effectively reduce the complexity of the lithography system (no need for a mask stage, mask transmission, and a simple frame structure) and the mask processing and maintenance costs. It is one of the development trends in large-scale substrate lithography. The maskless lithography method based on spatial light modulator (SLM) is increasingly used to manufacture printed circuit boards (PCBs), thin-film liquid crystal panels (TFTs), microelectromechanical systems (MEMS), as well as advanced packaging processes such as wafer-level packaging and panel packaging due to its advantages such as flexible manufacturing, high reliability and relatively high yield.

[0082] Therefore, in this application, the offset data of each grain in the bare chip unit is used to change the direction, position or shape of the line located in the routable area in the original diagram of the interconnection line, that is, the original diagram of the interconnection line is rewired and adjusted, so as to complete the correction of the offset data between the grains in the routable area. At this time, the grains can be reconnected through the adjusted interconnection lines, so that communication and data transmission can be realized between the grains again, thereby reducing the dependence on high-precision placement equipment.

[0083] In the description of the present application, any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes additional implementations in which functions may be performed in a different order than shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application belong.

[0084] The logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other system that can fetch instructions from and execute instructions on an instruction execution system, apparatus, or device). For purposes of this application, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection having one or more wires (electronic devices), a portable computer disk cartridge (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disc read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the above-mentioned program can be printed. For example, the above-mentioned program can be obtained electronically by optically scanning the paper or other medium, and then editing, interpreting or processing it in other suitable ways as necessary, and then storing it in the computer memory.

[0085] It should be understood that various parts of the present application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0086] Those skilled in the art will understand that all or part of the steps in the method for implementing the above-mentioned embodiment can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.

[0087] In addition, the functional units in the various embodiments of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into a module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0088] The storage medium mentioned above may be a read-only memory, a magnetic disk, or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application. Persons skilled in the art may make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

[0089] In the description of this application, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "example," "specific example," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of this application. In this application, the exemplary expressions of the above terms do not necessarily refer to the same embodiment or example.

[0090] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A grain correction method, It is characterized in that include: Acquire offset data of each die in a die unit, wherein the die unit includes a plurality of die; Acquire an original diagram of interconnection lines between dies on the die unit; Determine a routable area according to the ideal position data of each die in the die unit; as well as The circuits in the original diagram of the interconnected circuits located in the routable area are skewed according to the offset data of each die.

2. The grain deviation correction method according to claim 1, It is characterized in that The width of the routable area is greater than a reference value, and the reference value is a maximum allowable offset when a patch device performs a patch process on the die.

3. The grain deviation correction method according to claim 1, It is characterized in that The width of the routable area is greater than or equal to a reference value, where the reference value=a maximum allowable offset amount*2 when a patch device performs a patch process on the die.

4. The grain deviation correction method according to any one of claims 1 to 3, It is characterized in that The offset data at least includes relative displacement data and relative rotation angle between the current position data of each grain and the ideal position data of the grain, and correcting the interconnection lines located in the wiring area according to the offset data of each grain, including: correcting the interconnection lines located in the wiring area according to the relative displacement data and the relative rotation angle.

5. The grain deviation correction method according to any one of claims 1 to 4, It is characterized in that The shape of the routable area is a polygon.

6. The grain deviation correction method according to any one of claims 1 to 5, It is characterized in that The number of the routable areas is less than or equal to the number of the dies.

7. The grain deviation correction method according to any one of claims 1 to 6, It is characterized in that The number of the routable areas is equal to the number of the die, each of the routable areas is arranged around the outer periphery of the corresponding die, and there is a gap between the boundary of the routable area and the boundary of the die.

8. A computer storage medium having a computer program stored thereon, It is characterized in that When the computer program is executed by a processor, the grain deviation correction method described in any one of claims 1 to 7 is implemented.

9. A method for preparing a chip device, It is characterized in that include: Providing packaging substrates and bare die units; Obtaining a bare chip unit circuit diagram after correction using the grain correction method described in any one of claims 1 to 7; Performing an exposure process on the bare die unit according to the bare die unit circuit diagram to obtain an exposed bare die unit; The exposed bare die unit is packaged on the packaging substrate to obtain the chip device.

10. The method for preparing the chip device according to claim 9, It is characterized in that There are multiple bare chip units, and obtaining a bare chip unit circuit diagram after correction by the grain correction method according to any one of claims 1 to 7 comprises: Obtaining an interconnection circuit diagram corresponding to each of the bare die units, wherein the interconnection circuit diagram is a circuit diagram corrected by using the grain correction method; and All of the interconnection diagrams are combined to form the die unit diagram.

Images