Die-to-die interconnect-based semiconductor package and method

Abstract

A die-to-die interconnect-based semiconductor package and a method. The package comprises: a package substrate (401) having a first surface; a plurality of input / output semiconductor dies (101, 301) provided on the first surface of the package substrate (401) and arranged along the periphery of the package substrate (401), wherein each input / output semiconductor die (101, 301) has first interconnect portions (101a) which are vertically and directly connected to adjacent semiconductor dies; and core semiconductor dies (201) provided on the first surface of the package substrate (401) and located in a region defined by the plurality of input / output semiconductor dies (101, 301), wherein each core semiconductor die (201) has second interconnect portions (203) which are vertically and directly connected to adjacent semiconductor dies, and the first interconnect portions (101a) are interconnected with the second interconnect portions (203).

Description

Semiconductor packaging and method based on die interconnection

[0001] This application claims priority to Chinese Patent Application No. 202311508563.7 filed on November 13, 2023, and the contents of the above-mentioned Chinese patent application disclosure are hereby cited in their entirety as part of this application. Technical Field

[0002] The embodiments of the present disclosure relate to a semiconductor package and method based on die interconnection. Background Art

[0003] As processor core counts continue to increase, the size of processor dies (also known as crystal grains in Chinese) continues to grow, resulting in a decrease in yield. Furthermore, large dies are inherently limited by reticle size. Even without considering yield costs, dies that are too large cannot be processed.

[0004] Therefore, if a large-sized die is divided into the same or different small-sized dies and interconnected through packaging, the yield of the die can be greatly improved, thereby reducing costs.

[0005] Summary of the Invention

[0006] In view of this, the embodiments of the present disclosure provide a semiconductor package and method based on die interconnection, which facilitates further reducing the size of a single die, thereby improving the manufacturing yield.

[0007] In order to achieve the above-mentioned disclosure purpose, the following technical solutions are adopted:

[0008] An embodiment of the present application provides a semiconductor package, comprising:

[0009] A packaging substrate having a first surface;

[0010] a plurality of input / output semiconductor dies disposed on the first surface of the package substrate and arranged along the periphery of the package substrate, wherein each input / output semiconductor die has a first interconnection portion vertically and directly connected to an adjacent semiconductor die;

[0011] a core semiconductor die disposed on the first surface of the package substrate and located in a region surrounded by the plurality of input / output semiconductor die, wherein each core semiconductor die has a second interconnect portion vertically and directly connected to an adjacent semiconductor die;

[0012] The first interconnection portion is interconnected with the second interconnection portion.

[0013] According to a specific implementation of an embodiment of the present disclosure, the multiple input / output semiconductor grains include at least two input / output semiconductor grains with different structural types, wherein one type of input / output semiconductor grains is arranged at least on a first side of the packaging substrate, and the other type of input / output semiconductor grains is arranged at least on a second side of the packaging substrate, and the first side and the second side are two adjacent or opposite sides.

[0014] According to a specific implementation of an embodiment of the present disclosure, the multiple input / output semiconductor grains include at least two different structural types of input / output semiconductor grains, wherein one type of input / output semiconductor grains are separately arranged on the first side of the packaging substrate, and the other type of input / output semiconductor grains are integrated with the core semiconductor grains and located on the second side of the packaging substrate, and the first side and the second side are two adjacent or opposite sides.

[0015] According to a specific implementation of the embodiment of the present disclosure, each type of input / output semiconductor grain includes at least one input / output portion, which is arranged at the outer edge of the input / output semiconductor grain.

[0016] According to a specific implementation of the embodiment of the present disclosure, the core semiconductor grains are an odd number or an even number, and adjacent core semiconductor grains are directly connected vertically through the second interconnection portion.

[0017] According to a specific implementation of the embodiment of the present disclosure, each core semiconductor crystal grain further includes: a silicon substrate for carrying the semiconductor device, and the second interconnection portion is respectively provided along the top, bottom, left and right sides of the silicon substrate; or,

[0018] The second interconnection portion is respectively provided along the upper and lower sides of the silicon substrate; or,

[0019] The second interconnection portions are respectively arranged along the left and right sides of the silicon substrate;

[0020] At least one computing core is arranged in the central area of ​​the silicon substrate.

[0021] According to a specific implementation of the embodiment of the present disclosure, the first interconnection part and the second interconnection part are respectively PHY interfaces, the signal receiving end of the first interconnection part is arranged opposite to the signal transmitting end of the second interconnection part, and the signal transmitting end of the first interconnection part is arranged opposite to the signal receiving end of the second interconnection part.

[0022] According to a specific implementation of the embodiment of the present disclosure, the receiving end and the transmitting end of the first interconnection part located on the same side of the packaging substrate are set in the same direction, and the receiving end and the transmitting end of the second interconnection part located on the same side of the packaging substrate are set in the same direction.

[0023] In a second aspect, an embodiment of the present disclosure further provides a method for forming a semiconductor package, comprising the steps of:

[0024] Providing a packaging substrate, wherein a conductive trace is arranged on the packaging substrate;

[0025] Arrange a plurality of input / output semiconductor dies on the package substrate along at least a portion of a periphery of the package substrate, wherein each input / output semiconductor die has a first interconnection portion that is vertically and directly connected to an adjacent semiconductor die;

[0026] and disposing core semiconductor dies on the package substrate in an area surrounded by the plurality of input / output semiconductor dies, wherein each core semiconductor dies has a second interconnection portion that is vertically and directly connected to an adjacent semiconductor dies;

[0027] The first interconnection portion and the second interconnection portion are interconnected through the conductive trace.

[0028] According to a specific implementation of the embodiment of the present disclosure, the plurality of input / output semiconductor grains include at least two input / output semiconductor grains of different structural types;

[0029] Arranging a plurality of input / output semiconductor grains on the packaging substrate along at least a portion of the periphery of the packaging substrate includes: arranging one type of input / output semiconductor grains at least on a first side of the packaging substrate, and arranging another type of input / output semiconductor grains at least on a second side of the packaging substrate; wherein the first side and the second side are two adjacent or opposite sides.

[0030] According to a specific implementation of the embodiment of the present disclosure, the plurality of input / output semiconductor grains include at least two input / output semiconductor grains of different structural types;

[0031] Arranging a plurality of input / output semiconductor dies on the package substrate along at least a portion of the periphery of the package substrate comprises: separately arranging one type of input / output semiconductor dies on a first side of the package substrate; and

[0032] Another type of input / output semiconductor die is integrated with the core semiconductor die and attached to the second side of the package substrate; wherein the first side and the second side are two adjacent or opposite sides.

[0033] According to a specific implementation of the embodiment of the present disclosure, the first interconnection part and the second interconnection part are respectively PHY interfaces;

[0034] Interconnecting the first interconnection portion and the second interconnection portion through the conductive trace includes: arranging a signal receiving end of the first interconnection portion opposite to a signal transmitting end of the second interconnection portion; and arranging the signal transmitting end of the first interconnection portion opposite to a signal receiving end of the second interconnection portion;

[0035] Furthermore, between adjacent input / output semiconductor grains and core semiconductor grains on the same side, corresponding signal receiving ends and transmitting ends are arranged in the same direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0037] FIG1 is a schematic diagram of a semiconductor package structure according to an embodiment of the present disclosure.

[0038] FIG2 is a schematic diagram of a semiconductor package structure according to another embodiment of the present disclosure.

[0039] FIG3 is a schematic diagram of a semiconductor package structure according to another embodiment of the present disclosure;

[0040] FIG4 is a schematic diagram of a semiconductor package structure according to another embodiment of the present disclosure;

[0041] FIG5 is a schematic diagram of a semiconductor package structure according to another embodiment of the present disclosure;

[0042] FIG6 is a schematic diagram of a semiconductor package structure according to another embodiment of the present disclosure;

[0043] FIG7 is a schematic diagram of the interconnection structure of the first interconnection part and the second interconnection part (arranged oppositely in the north-south direction) in one embodiment of the present disclosure;

[0044] FIG8 is a schematic diagram of the interconnection structure of the first interconnection part and the second interconnection part (arranged relative to each other in the east-west direction) in one embodiment of the present disclosure;

[0045] FIG9 is a schematic longitudinal cross-sectional view of a semiconductor package structure according to an embodiment of the present disclosure;

[0046] FIG10 is a schematic longitudinal cross-sectional view of a semiconductor package structure according to another embodiment of the present disclosure;

[0047] FIG11 is a schematic diagram of the back side of a package substrate according to an embodiment of the present disclosure; and

[0048] FIG. 12 is a schematic diagram of a process for forming a semiconductor package structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0049] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0050] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the present disclosure. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which additional components may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0051] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another (or more) elements or components as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented, for example, rotated 90 degrees or at other orientations, and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0052] Figures 1 through 6 illustrate schematic diagrams of semiconductor package structures according to various embodiments of the present disclosure. Referring to Figures 1 through 6, the semiconductor package (generally referred to as an integrated circuit, also referred to as a chip package) includes a package substrate 401 having a first surface. Package substrate 401 can be an organic substrate formed from a material such as glass fiber reinforced resin (ABF), or an inorganic substrate formed from a material such as silicon or ceramic.

[0053] As shown in FIG9 , conductive traces are arranged on the package substrate 401. The conductive traces may include metal traces located within the package substrate 401, joints 402 located on the first surface of the package substrate 401, and BGA / LGA pins 403 located on the second surface. The metal traces, joints 402, and BGA / LGA pins 403 may be formed of conductive materials such as copper, aluminum, tin, lead, or alloys thereof.

[0054] Continuing to refer to Figures 1 to 6, a plurality of input / output semiconductor dies (IO Dies, which will also be referred to and described in English herein), including input / output semiconductor dies 101 and 301, are disposed on the first surface of the package substrate 401 and arranged along the periphery of the package substrate 401, wherein each input / output semiconductor dies has a first interconnection portion 101a that is vertically and directly connected to an adjacent semiconductor dies. As can be seen from Figures 1 to 6, the adjacent semiconductor dies here include the IO Dies that are adjacent in the horizontal direction and the Core Dies that are adjacent in the vertical direction as shown. It should be noted that the term "periphery" here can refer to each side of the package substrate or to a portion of the side of the package substrate.

[0055] The core semiconductor die (Core Die, also described in this article by this English term) 201 is arranged on the first surface of the packaging substrate 401 and is located in the area surrounded by the multiple input / output semiconductor die, wherein each core semiconductor die 201 has a second interconnection portion directly connected to the adjacent semiconductor die; the first interconnection portion 101a is interconnected with the second interconnection portion.

[0056] To help understand the technical solutions provided by the embodiments of the present disclosure, the embodiment shown in FIG1 is described in detail as follows:

[0057] In some related technologies, although large-size dies are split, the IO interfaces are still all integrated on the Core Die. The size of a single chip is still large, the yield is still low, and it is not convenient to further expand and interconnect more dies.

[0058] As shown in Figure 1, in the embodiment of the present disclosure, the interface part used for input and output is separated to form a separate IO Die, and the IO Die is divided into a serial 101 and a parallel 301, which are placed on the four sides of the top, bottom, left, and right (also referred to as the directions in the chip field as east, south, west, and north). On the one hand, this reduces the size of the Die, and on the other hand, the IO terminals 102 and terminals 303 of each IO Die are placed outside the entire chipset, close to the edge of the package. When interconnected with external devices or electronic devices, the routing distance between IO102 and 303 and them can be reduced, thereby improving the signal transmission quality.

[0059] Generally speaking, serial IO Die refers to a chip that uses one or more pairs of signal lines to transmit data and instructions, transmitting one or several bits at a time, but can achieve higher data rates and longer transmission distances. Parallel IO Die refers to a chip that uses multiple pairs of signal lines to transmit data and instructions, which can transmit multiple bits at a time, but usually requires a lower data rate and shorter transmission distance. Although parallel IO Die has a low transmission rate, its bit width is large.

[0060] In terms of physical structure, the main difference between serial IO dies and parallel IO dies lies in the number and arrangement of signal lines. Serial IO dies typically use fewer signal lines, which are tightly packed together to achieve higher edge density and area density, that is, data throughput per millimeter or per square millimeter. Parallel IO dies, on the other hand, typically use more signal lines, meaning they have a larger bit width, and their signal lines typically require greater spacing to reduce crosstalk and delay mismatch between signal lines.

[0061] In terms of electrical structure, the main difference between serial I / O dies and parallel I / O dies lies in the signal drive and recovery methods. Serial I / O dies typically use low voltage and unterminated single-ended signals to reduce power consumption and noise. Parallel I / O dies typically use higher voltage and terminated differential signals to improve signal robustness and fault tolerance.

[0062] Please refer to Figures 1 to 6. Similarly, a large-size Core Die is split into multiple small-size Core Dies 201. On the one hand, the size of the Die is reduced. On the other hand, any required number of them can be inserted into the middle of the area enclosed by the IO Die as needed, thereby expanding the interconnection of more grains and achieving high-density interconnection.

[0063] Furthermore, IO Dies 101 and 301 are connected to Core Die 201, Core Die 201 to Core Die 201, and even to adjacent IO Dies using a short, regular grid interconnect. The use of short, vertical direct connections increases the number of lines, thereby increasing bandwidth. This reduces the number of narrow-bit-width register operations within the chip, converting them to wide-bit-width registers, thus reducing latency and ensuring that cross-die latency and non-uniform memory access (NUMA) performance meet requirements.

[0064] Therefore, in the disclosed embodiments, by splitting a large die into IO dies and core dies based on their functions, arranging multiple input / output semiconductor dies along the perimeter of the package substrate, and locating the core semiconductor die 201 in the area surrounding the I / O semiconductor dies, the size of individual dies can be further reduced, thereby improving manufacturing yield. Furthermore, the direct-connect topology shortens signal transmission paths. This solution achieves high-density, high-performance, low-power, and low-cost semiconductor packaging.

[0065] Referring to Figures 1 to 3, in some embodiments, the input / output semiconductor die may include at least two different structural types of input / output semiconductor die, for example, a serial input / output semiconductor die 101 and a parallel input / output semiconductor die 301. The serial input / output semiconductor die 101 may include a serial input / output interface 102 for implementing high-speed serial communication, wherein the serial input / output interface 102 may include a transceiver for receiving and transmitting signals. The parallel input / output semiconductor die 301 may include a parallel input / output terminal interface 303 for implementing high-speed parallel communication. One type of input / output semiconductor die is disposed at least on a first side of the package substrate, and the other type of input / output semiconductor die is disposed at least on a second side of the package substrate, wherein the first side and the second side are adjacent or opposite sides.

[0066] For example, as shown in Figure 1, one type of input / output semiconductor die 101 is located on the top edge of the package substrate, while another type of input / output semiconductor die 301 is located on the left edge of the package substrate, with the top and left edges being adjacent. As shown in Figures 2 and 3, one type of input / output semiconductor die 101 is located on both the top and bottom edges of the package substrate, while another type of input / output semiconductor die 301 is located on at least the left and right edges of the package substrate. Of course, one type of input / output semiconductor die can be located on the top edge of the package substrate, while another type of input / output semiconductor die can be located on the bottom edge of the package substrate, depending on the packaging requirements. However, due to space limitations, this is not illustrated in the figures.

[0067] According to the comparison of the solutions shown in Figures 1 to 3, in the embodiment of the present disclosure, by separating the IO Die and providing the first interconnection part 101a in the direction of interconnection between Dies, more Dies can be expanded to achieve high-density interconnection.

[0068] As shown in Figures 4 to 6, in some other embodiments, the multiple input / output semiconductor grains include at least two different structural types of input / output semiconductor grains, wherein one type of input / output semiconductor grain 101 or 301 is separately arranged on the first side of the packaging substrate, and the other type of input / output semiconductor grain 301 or 101 is integrated with the core semiconductor grain 201 and is located on the second side of the packaging substrate 401, and the first side and the second side are two adjacent or opposite sides.

[0069] For example, in Figure 4, one type of I / O semiconductor die 101 is separately disposed on the upper and lower sides of the package substrate 401, while another type of I / O semiconductor die 301 is integrated with the core semiconductor die and disposed on the left and right sides of the package substrate, respectively. One type of I / O semiconductor die can include multiple separately disposed I / O semiconductor die, interconnected by first interconnecting portions 101a, as shown in Figures 2, 3, and 4. Alternatively, it can include multiple integrated I / O semiconductor die 101, as shown in Figures 5 and 6.

[0070] Specifically, each type of I / O semiconductor die 101 or 301 includes at least one I / O portion, located on the outer edge of the I / O semiconductor die. For example, as shown in FIG1 , the IO terminals 102 and 303 of the IO die are located outside the entire chipset, close to the package edge. This reduces the routing distance of the IO terminals 102 and 303 and improves signal quality.

[0071] As shown in FIG1 , the first interconnection portion 101a may include micro solder balls or metal bumps, wherein the micro solder balls or metal bumps may be formed of materials such as tin, lead, copper, silver, or alloys thereof. The first interconnection portion 101a may connect the input / output semiconductor die to corresponding locations on the package substrate 401 using a flip chip method. For example, the serial input / output semiconductor die 101 may be disposed on the top and bottom sides of the package substrate 401, wherein each serial input / output semiconductor die 101 has an input / output portion located at its outer edge. The parallel input / output semiconductor die 301 may be disposed on the left and right sides of the package substrate 401, wherein each parallel input / output semiconductor die 301 has a parallel input / output portion located at its outer edge. The first interconnection portion 101a may be disposed along the top, bottom, left, and right sides of the input / output semiconductor die to achieve vertical direct connection with adjacent semiconductor dies.

[0072] As shown in Figure 2, for example, serial I / O semiconductor die 101 can be disposed on the top edge of a packaging substrate 401. Each serial I / O semiconductor die 101 has an I / O portion located on its outer edge and a second interconnect portion, such as a PHY interface, located on its inner edge for inter-die interconnection. Specifically, this interface can be implemented by a PHY chip. When describing an interface as implemented by a PHY chip, it means that the PHY chip contains all the circuits and functions required to implement the PHY interface. A PHY interface is a specification or standard that defines how data is transmitted at the physical layer. A PHY chip is the specific device that implements these specifications, including a series of functions such as conversion, encoding, and decoding to meet the requirements of the PHY interface for inter-die interconnection. Parallel I / O semiconductor die 301 can be disposed on the left side of the packaging substrate 401. Each parallel I / O semiconductor die 301 has a parallel I / O portion located on its outer edge and a second interconnect portion located on its inner edge.

[0073] In some embodiments, referring to Figures 1 to 6 , core semiconductor dies 201 are disposed on a packaging substrate 401 in an area surrounded by a plurality of input / output semiconductor dies, wherein each core semiconductor dies 201 has a second interconnection portion 203 that is vertically and directly connected to an adjacent semiconductor dies. The core semiconductor dies 201 may include a computing core 202 for performing computing tasks, such as a processor, memory, accelerator, etc. As shown in Figures 1 to 6 , the number of core semiconductor dies 201 may be odd or even, so that they can be flexibly inserted between IO dies as needed to achieve greater expansion. As shown in Figures 1 to 6 , adjacent core semiconductor dies 201 may be vertically and directly connected via the second interconnection portion 203. The second interconnection portion 203 has substantially the same structure and implementation as the first interconnection portion 101a, and will not be further described.

[0074] As shown in Figures 1 to 6, each core semiconductor grain further includes: a silicon substrate for carrying semiconductor devices, and the second interconnection part 203 is respectively arranged along the top, bottom, left and right sides of the silicon substrate, as shown in the examples of Figures 2 and 3.

[0075] Alternatively, the second interconnection portion 203 is respectively provided along the upper and lower sides of the silicon substrate.

[0076] Alternatively, the second interconnection portion 203 is disposed along the left and right sides of the silicon substrate, respectively.

[0077] Alternatively, the second interconnection portions 203 are respectively arranged along three adjacent azimuth edges of the silicon substrate, as shown in FIG. 4 to FIG. 6 .

[0078] At least one computing core 202 is disposed in the central area of ​​the silicon substrate.

[0079] For example, since the core dies 201 need to be interconnected, the upper, lower left and right portions of the core dies should be set as inter-die interconnect PHY 203 , with the computing core 202 in the middle.

[0080] Since the Core Dies are interconnected with each other in the upper and lower parts, and the Core Dies and IO Dies in the upper and lower parts are interconnected with each other, the PHY direction needs to be opposite. Therefore, in some embodiments, the first interconnection part 101a and the second interconnection part 203 are respectively PHY interfaces, and the signal receiving end of the first interconnection part 101a and the signal sending end of the second interconnection part 203 are arranged relative to each other, and the signal sending end of the first interconnection part 101a and the signal receiving end of the second interconnection part 203 are arranged relative to each other.

[0081] In some embodiments, the receiving end and transmitting end of the first interconnection portion 101a located on the same side of the package substrate 401 are arranged in the same direction, and the receiving end and transmitting end of the second interconnection portion 203 located on the same side of the package substrate 401 are arranged in the same direction. For example, as shown in FIG7 , R represents receive and T represents transmit. The top and bottom edges 203 of the core die 201 are opposite. When interconnecting core dies east and west, the core die 203 automatically becomes opposite after rotating 180 degrees, so the east and west edges are also opposite.

[0082] For IO Die 101, since it needs to be connected to Core Die 201 and the adjacent IO Die 101, its bottom and right are the inter-die interconnection PHY103, and the top is usually a serial IO interface. After rotation, the left and right IOs can also be interconnected.

[0083] For IO Die 302, since it needs to be connected to Core Die 201, its right side and upper and lower sides are inter-die interconnection PHY interfaces, and the left side is usually a parallel IO interface. After being placed up and down, they can be interconnected through their upper and lower PHYs.

[0084] It is understood that a semiconductor package may also include other packaging components. For example, a protective layer may be formed on the package substrate 401 to cover the input / output semiconductor die and the core semiconductor die 201, thereby protecting the components within the package from the external environment. However, to highlight the innovative principles of this disclosure, this article focuses on the sections most closely related to this disclosure, and the remaining sections are omitted or briefly described.

[0085] As shown in Figure 9 , the die interconnections mentioned in the previous embodiment are directly connected. Specifically, BGA / LGA pins 403 are provided on the second surface of the package substrate. A first metal trace and first via 404 are arranged on the package substrate. Joints 402 for soldering are provided on the first surface of the package substrate for the input / output semiconductor die and the core semiconductor die, respectively. These joints can be metal pads or metal bumps, such as C4 solder balls. The metal traces and vias 404 connect the joints for die interconnection, and the remaining IO interfaces and power ground are connected to the BGA / LGA pins 403 through metal traces and vias.

[0086] As shown in FIG10 , to increase bandwidth, in some embodiments, an interposer 501 is provided on the junction 402. The interposer is provided with a second metal trace and a second via 502. The second metal trace has a smaller diameter than the first metal trace, thereby increasing interconnection density. The second metal trace and the second via 502 are used to connect the micro solder balls 503 corresponding to the die interconnects of the chip. Other IO and power ground micro solder balls 503 are connected to the junction 402 via the second metal trace in the interposer 501. The junction 402 can be a C4 solder ball. The BGA / LGA pins 403 are then connected via the first metal trace and vias in the package substrate 401.

[0087] For example, the die can increase interconnection density through thinner second metal traces and vias 502 in a 2.5D interposer (interposer) 501 (the insulating medium can be silicon or polyimide, etc.), connecting the micro solder balls 503 corresponding to the inter-die interconnections of the chip. The c4 solder balls 402 of the inter-die interconnections are connected through metal traces and vias 404 in the ABF substrate 401. At the same time, the other IO and power micro solder balls 503 are connected to the c4 solder balls 402 through the first metal traces in the interposer 501, and then connected to the BGA / LGA pins 403 through the metal traces and vias in the ABF substrate 401.

[0088] Referring to FIG. 11 , in some embodiments, the pins 601 on the second surface of the package substrate are staggered to facilitate motherboard wiring. Specifically, the second surface of the package substrate 401 includes a first pin area 401a, a second pin area 401b, a third pin area 401c, and a fourth pin area 401d. The first pin area 401a is located on the left side of the second surface of the package substrate 401, the second pin area 401b is located on the upper portion of the second surface of the package substrate 401, the third pin area is located on the right side of the second surface of the package substrate 401, and the fourth pin area 401d is located on the lower portion of the second surface of the package substrate 401. A decoupling capacitor is provided in a central area 603 surrounded by the first, second, third, and fourth pin areas 401a, 401b, 401c, and 401d to optimize power supply performance.

[0089] Among them, the pins arranged on the first pin area 401a are distributed from top to bottom on the left side to ensure parallel IO connection channels. The pins arranged on the third pin area 401c are distributed from bottom to top on the left side, and the multiple IO Dies corresponding to this area are rotated 180 degrees to ensure parallel IO connection channels, and the overall distribution is symmetrical.

[0090] For example, a central area 603 is left empty in the middle of the second surface of the package substrate to increase decoupling capacitance and optimize power supply performance. To support the parallel IO PHY 303 output of the conventional parallel IO Die 301, its IO PIN 602 is distributed on the left and right sides of the substrate. Specifically, the parallel channels on the multiple IO Dies on the left have corresponding pins on the substrate distributed from top to bottom on the left side to ensure parallel IO connection channels. The multiple IOD Dies on the right are rotated 180 degrees, and the parallel IO channels on the substrate are distributed from bottom to top on the right side to ensure parallel IO connection channels. To support the serial IO PHY 102 output of the conventional serial IO Die 101, its IO PIN 604 is distributed on the upper and lower sides of the substrate, and the serial channel PINs are also distributed on the upper and lower sides. In this way, the two types of high-speed signals, serial channel and parallel channel, are guaranteed not to interfere with each other, while facilitating output.

[0091] The semiconductor package based on die interconnection provided by the embodiments of the present disclosure further splits the die and separates the IO die, thereby further reducing the size, which can greatly improve the yield of a single small die and significantly reduce the total cost.

[0092] Furthermore, by placing the IO die's external IO interface on the outer edge of the package substrate and interconnecting the dies with a grid-like direct wiring pattern, the distance between external IO and internal interconnects can be reduced, improving signal quality. Furthermore, by saving a significant amount of substrate wiring area, the constraints imposed by the package on the total die area can be alleviated, allowing the number of chip cores to be increased, significantly improving performance.

[0093] Furthermore, in the present disclosure, by splitting the die into smaller dies, it is convenient to flexibly combine and change the package interconnection structure without changing the chip, thereby greatly enhancing the scalability.

[0094] FIG12 is a schematic diagram of a process for forming a semiconductor package structure according to an embodiment of the present disclosure. Referring to FIG1 and FIG12 , an embodiment of the present disclosure further provides a method for forming a semiconductor package structure, which includes the following steps:

[0095] S210: Provide a packaging substrate 401 having conductive traces disposed thereon. A corresponding packaging substrate is shown in the semiconductor packaging structure shown in FIG9 . The packaging substrate 401 can be formed of glass, ceramic, organic material, or other suitable materials. In some embodiments, the packaging substrate is an ABF substrate. The conductive traces can be formed by photolithography and etching processes.

[0096] S220. Arrange a plurality of input / output semiconductor dies (IO Dies) 101 and 301 on a packaging substrate 401 along at least a portion of the periphery of the packaging substrate 401, wherein each input / output semiconductor die 101 has a first interconnection portion 101a and 302 that is vertically and directly connected to an adjacent semiconductor die for interconnection between dies.

[0097] The multiple input / output semiconductor dies include at least two different structural types. For example, FIG1 shows that the input / output semiconductor dies 101 are of one type, while the input / output semiconductor dies 301 are of another type. Specifically, arranging the multiple input / output semiconductor dies along at least a portion of the periphery of the packaging substrate 401 on the packaging substrate 401 includes: disposing the input / output semiconductor dies 101 of one type at least on a first side of the packaging substrate 401, and disposing the input / output semiconductor dies 301 of another type at least on a second side of the packaging substrate 401; wherein the first side and the second side are adjacent or opposite sides.

[0098] S230. Core semiconductor die 201 is disposed on the package substrate 401 in an area surrounded by multiple input / output semiconductor die. Each core semiconductor die 201 has a second interconnect 203 that is vertically and directly connected to an adjacent semiconductor die. The core semiconductor die 201 may include a computing core, which may be a central processing unit (CPU) die, a microcontroller unit (MCU) die, or the like. The second interconnect 203 is connected to adjacent semiconductor die by welding or metal-to-metal direct bonding to achieve inter-die interconnection. As shown in FIG9 , in some embodiments, inter-die connection is achieved through metal wires and vias 404.

[0099] It should be noted that steps S230 and S240 can be interchanged or performed simultaneously. S230 and S240 are only for the convenience of description. It should be understood that the description of the steps does not limit the order of the specific processes.

[0100] S240 , interconnecting the first interconnection portion and the second interconnection portion through the conductive trace.

[0101] According to some embodiments of the present disclosure, the first interconnecting portions 101a and 302 and the second interconnecting portion 203 each serve as a PHY interface. Interconnecting the first interconnecting portions 101a and 302 with the second interconnecting portion 203 via conductive traces includes: arranging the signal receiving end of the first interconnecting portion 101a opposite the signal transmitting end of the second interconnecting portion 203; arranging the signal transmitting end of the first interconnecting portion 101a opposite the signal receiving end of the second interconnecting portion 203; and arranging the corresponding signal receiving ends and transmitting ends in the same direction between adjacent input / output semiconductor die and between core semiconductor die 201 on the same side. This enables high-speed, low-power, and low-interference signal transmission.

[0102] It should be noted that the method provided in this embodiment can be implemented by a device. When a user uses this device to form a semiconductor package, they can reproduce the method flow described in the embodiments of this disclosure. In addition, since the various embodiments of this disclosure share common technical concepts and are described in a related manner, they can be referenced from each other and will not be repeated here.

[0103] In summary, the semiconductor packaging and method based on chip-die interconnection provided by the embodiments of the present disclosure separates the IO Die and splits it into multiple IO Dies, which are placed around the periphery of the package substrate, thereby further reducing the size of a single die and improving the manufacturing yield:

[0104] Furthermore, by placing the IO interface (i.e., input / output portion) outside the entire chipset, close to the edge of the package, the IO routing distance can be reduced and the signal quality can be improved.

[0105] Furthermore, by splitting the Core Die into multiple Dies, on the one hand, the size of the Die is reduced, and on the other hand, it can be flexibly inserted into the area surrounded by the IO Die according to needs, thereby facilitating expansion and interconnection of more Dies and achieving high-density interconnection.

[0106] Finally, the interconnections between dies all use short-distance regular grid vertical interconnections, which can increase the number of lines and thus increase the bandwidth, so as to reduce a large number of narrow-bit-width register operations inside the chip to wide-bit-width register operations, thereby reducing latency and ensuring that cross-die latency and non-uniform memory access performance meet the requirements.

[0107] It should be noted that, in this article, the emphasis of the schemes described in the various embodiments is different, but the various embodiments have a certain interrelated relationship. When understanding the scheme of the present disclosure, the various embodiments can refer to each other; in addition, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or measurement control unit including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or measurement control unit 103. In the absence of further restrictions, the elements defined by the sentence "comprise a..." do not exclude the presence of other identical elements in the process, method, article or measurement control unit including the elements.

[0108] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A semiconductor package, comprising: A packaging substrate having a first surface; A plurality of input / output semiconductor dies are disposed on the first surface of the package substrate and arranged along the periphery of the package substrate, wherein each input / output semiconductor dies has a first interconnection portion directly connected to an adjacent semiconductor dies; A core semiconductor die is disposed on the first surface of the package substrate and is located in the region surrounded by the plurality of input / output semiconductor die, wherein each core semiconductor die has a second interconnection portion directly connected to an adjacent semiconductor die; Wherein, the first interconnection part is interconnected with the second interconnection part.

2. The semiconductor package according to claim 1, wherein The multiple input / output semiconductor grains include at least two different structural types of input / output semiconductor grains, wherein one type of input / output semiconductor grains are at least arranged on a first side of the packaging substrate, and another type of input / output semiconductor grains are at least arranged on a second side of the packaging substrate, and the first side and the second side are two adjacent or opposite sides.

3. The semiconductor package according to claim 1, wherein: The multiple input / output semiconductor grains include at least two different structural types of input / output semiconductor grains, wherein one type of input / output semiconductor grains are separately arranged on a first side of the packaging substrate, and another type of input / output semiconductor grains are integrated with the core semiconductor grains and located on a second side of the packaging substrate, and the first side and the second side are two adjacent or opposite sides.

4. The semiconductor package according to any one of claims 1 to 3, wherein: Each type of input / output semiconductor die includes at least one input / output portion disposed at an outer edge of the input / output semiconductor die.

5. The semiconductor package according to any one of claims 1 to 4, wherein: The number of the core semiconductor crystal grains is an odd number or an even number, and adjacent core semiconductor crystal grains are vertically and directly connected through the second interconnection portion.

6. The semiconductor package according to claim 1 or 5, wherein: Each core semiconductor crystal grain further includes: a silicon substrate for carrying the semiconductor device, wherein the second interconnection portion is respectively arranged along the top, bottom, left and right sides of the silicon substrate; or, The second interconnection portion is respectively arranged along the upper and lower sides of the silicon substrate; or, The second interconnection portions are respectively arranged along the left and right sides of the silicon substrate; At least one computing core is arranged in the central area of ​​the silicon substrate.

7. The semiconductor package according to any one of claims 1 to 6, wherein: The first interconnection part and the second interconnection part are PHY interfaces respectively, a signal receiving end of the first interconnection part and a signal sending end of the second interconnection part are arranged opposite to each other, and a signal sending end of the first interconnection part and a signal receiving end of the second interconnection part are arranged opposite to each other.

8. The semiconductor package according to claim 7, wherein: The receiving end and the transmitting end of the first interconnection part located on the same side of the packaging substrate are arranged in the same direction, and the receiving end and the transmitting end of the second interconnection part located on the same side of the packaging substrate are arranged in the same direction.

9. A method of forming a semiconductor package, comprising: A packaging substrate is provided, wherein a conductive trace is arranged on the packaging substrate; Arrange a plurality of input / output semiconductor dies on the packaging substrate along at least a portion of the periphery of the packaging substrate, wherein each input / output semiconductor dies has a first interconnection portion vertically and directly connected to an adjacent semiconductor dies; and, on the packaging substrate, arranging core semiconductor grains in the region surrounded by the plurality of input / output semiconductor grains, wherein each core semiconductor grain has a second interconnection portion that is vertically and directly connected to an adjacent semiconductor grain; The first interconnection portion and the second interconnection portion are interconnected through the conductive trace.

10. The method according to claim 9, wherein: The plurality of input / output semiconductor grains include at least two input / output semiconductor grains of different structural types; Arranging a plurality of input / output semiconductor grains on the packaging substrate along at least a portion of the periphery of the packaging substrate includes: arranging one type of input / output semiconductor grains at least on a first side of the packaging substrate, and arranging another type of input / output semiconductor grains at least on a second side of the packaging substrate; wherein the first side and the second side are two adjacent or opposite sides.

11. The method according to claim 9, wherein: The plurality of input / output semiconductor grains include at least two input / output semiconductor grains of different structural types; Arranging a plurality of input / output semiconductor crystals on the packaging substrate along at least a portion of the periphery of the packaging substrate comprises: separating and arranging a type of input / output semiconductor crystals; on a first side of the packaging substrate; and Another type of input / output semiconductor die is integrated with the core semiconductor die and attached to the second side of the package substrate; wherein the first side and the second side are two adjacent or opposite sides.

12. The method according to any one of claims 9 to 11, wherein: The first interconnection part and the second interconnection part are PHY interfaces respectively; The interconnecting the first interconnection part and the second interconnection part through the conductive trace comprises: arranging the signal receiving end of the first interconnection part opposite to the signal sending end of the second interconnection part; and arranging the signal sending end of the first interconnection part opposite to the signal receiving end of the second interconnection part; Furthermore, between adjacent input / output semiconductor grains and core semiconductor grains on the same side, corresponding signal receiving ends and transmitting ends are arranged in the same direction.

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