Logic chip, memory chip, chip stack structure, and memory

Abstract

The present disclosure provides a logic chip, a memory chip, a chip stack structure, and a memory. The logic chip is provided with a plurality of channel signal areas; conductive through holes in the channel signal areas are grouped to form a plurality of repair unit groups; each repair unit group comprises four repair units; a first repair unit and a second repair unit are symmetrical along a first axis, a third repair unit and a fourth repair unit are symmetrical along the first axis, and the first repair unit and the fourth repair unit are symmetrical along a second axis.

Description

Logic chip, memory chip, chip stacking structure and memory

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on November 15, 2023, with application number 202311543580.4 and application name “A logic chip, a memory chip, a chip stacking structure and a memory”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and in particular to a logic chip, a memory chip, a chip stacking structure, and a memory. Background Art

[0004] With the development of integrated circuit technology, the production process of semiconductor devices has made significant progress. However, in recent years, the development of two-dimensional semiconductor technology has encountered various challenges: physical limits, limits of existing development technology, and limits of storage electron density. In this context, in order to solve the difficulties encountered by two-dimensional semiconductor devices and pursue lower production costs per unit memory unit, bonding processes (such as hybrid bonding, bumping, and wire bonding) can be used to stack multiple chips to form three-dimensional semiconductor devices. However, for three-dimensional semiconductor devices, the connection structure between different chips still has problems such as large parasitic capacitance and large parasitic resistance, which affect the quality of signal transmission.

[0005] Summary of the Invention

[0006] Embodiments of the present disclosure provide a logic chip, a memory chip, a chip stacking structure, and a memory.

[0007] In a first aspect, an embodiment of the present disclosure provides a logic chip, wherein the logic chip includes m channel signal areas arranged in sequence along a first direction, the logic chip has a chip axis extending along a second direction and passing through the center of the logic chip, and the m channel signal areas are symmetrical about the chip axis; m is a positive integer; each of the channel signal areas has a first axis and a second axis, the first axis extends along the first direction or the second direction, the second axis and the first axis are perpendicular to each other and intersect at the center of the corresponding channel signal area; each of the channel signal areas is penetrated by a plurality of conductive through-holes along a third direction, the first direction, the second direction and the third direction are perpendicular to each other, the first direction and the second direction are parallel to the top surface of the logic chip, and the third direction is perpendicular to the top surface of the logic chip; for each of the channel signal areas, the plurality of conductive through-holes therein are divided into a plurality of repair unit groups; each of the repair unit groups includes a first repair unit, a second repair unit, a third repair unit and a fourth repair unit; the first repair unit and the second repair unit are arranged along the corresponding channel signal area. The first repair unit and the fourth repair unit are symmetrical along the first axis of the channel signal area to which they belong, the first repair unit and the fourth repair unit are symmetrical along the second axis of the channel signal area to which they belong; each of the repair units includes at least one redundant conductive via and at least one normal conductive via. When any of the normal conductive vias is damaged, the valid signal transmitted by the normal conductive via is switched to the next conductive via in the same repair unit along a preset signal switching direction; any conductive via in any of the repair units is electrically connected to the internal circuit of the logic chip when used to transmit a valid signal; the normal conductive via in the first repair unit and the normal conductive via in the second repair unit correspond one-to-one and are symmetrical along the first axis of the channel signal area to which they belong, the normal conductive via in the third repair unit and the normal conductive via in the fourth repair unit correspond one-to-one and are symmetrical along the first axis of the channel signal area to which they belong, and the normal conductive via in the first repair unit and the normal conductive via in the fourth repair unit correspond one-to-one and are symmetrical along the second axis of the channel signal area to which they belong.

[0008] In a second aspect, an embodiment of the present disclosure provides a memory chip, wherein the memory chip includes m channels, the m channels are arranged in sequence along a first direction, the memory chip has a chip axis extending in a second direction and passing through the center of the memory chip, and the m channels are symmetrical about the chip axis; each of the channels includes a first memory array area, a channel signal area, and a second memory array area distributed in sequence along the second direction, and the center of each channel signal area coincides with the center of the corresponding channel, and m is a positive integer; each of the channel signal areas has a first axis and a second axis, the first axis extends along the first direction or the second direction, the second axis and the first axis are perpendicular to each other and intersect at the center of the corresponding channel signal area; each of the channel signal areas is penetrated by a plurality of conductive through-holes along a third direction, the first direction, the second direction, and the third direction are perpendicular to each other, the first direction and the second direction are parallel to the top surface of the memory chip, and the third direction is perpendicular to the top surface of the memory chip; for each of the channel signal areas, the plurality of conductive through-holes therein are divided into a plurality of repair unit groups; each of the repair unit groups includes a first repair unit, a second repair unit, and a third repair unit. unit and a fourth repair unit; the first repair unit and the second repair unit are symmetrical along the first axis of the channel signal area to which they belong, the third repair unit and the fourth repair unit are symmetrical along the first axis of the channel signal area to which they belong, and the first repair unit and the fourth repair unit are symmetrical along the second axis of the channel signal area to which they belong; each of the repair units includes at least one redundant conductive via and at least one normal conductive via. When any of the normal conductive vias is damaged, the valid signal transmitted by the normal conductive via is switched to the next conductive via in the same repair unit along a preset signal switching direction; any conductive via in the first repair unit is electrically connected to the internal circuit of the memory chip when used to transmit a valid signal; the normal conductive via in the first repair unit and the normal conductive via in the second repair unit correspond one-to-one and are symmetrical along the first axis of the channel signal area to which they belong, the normal conductive via in the third repair unit and the normal conductive via in the fourth repair unit correspond one-to-one and are symmetrical along the first axis of the channel signal area to which they belong, and the normal conductive via in the first repair unit and the normal conductive via in the fourth repair unit correspond one-to-one and are symmetrical along the second axis of the channel signal area to which they belong.

[0009] In a third aspect, an embodiment of the present disclosure provides a chip stacking structure, which includes a logic chip as described in the first aspect and at least one stacking unit, and the logic chip and the at least one stacking unit are stacked in sequence along a third direction; each of the stacking units includes a first memory chip, a second memory chip, a third memory chip and a fourth memory chip stacked in sequence along the third direction, and the third direction is perpendicular to the top surface of each chip; the first memory chip, the second memory chip, the third memory chip and the fourth memory chip are all memory chips as described in the second aspect; the first memory chip and the second memory chip are stacked face to face, the second memory chip and the third memory chip are stacked back to back, and the third memory chip and the fourth memory chip are stacked face to face; the logic chip and the first memory chip are stacked back to back; or, the logic chip and the first memory chip are stacked face to back.

[0010] In a fourth aspect, an embodiment of the present disclosure provides a memory comprising a chip stacking structure as described in any one of the third aspects.

[0011] The embodiments of the present disclosure provide a logic chip, a memory chip, a chip stacking structure, and a memory. There are multiple channel signal areas in each chip, and there are symmetrically arranged conductive through-holes in each channel signal area, so that the chip stacking structure formed by the memory chip achieves a signal rotation transmission effect through the direct connection configuration of the conductive through-holes, and the parasitic resistance and parasitic capacitance are relatively small; at the same time, repair units are also symmetrically divided in each channel signal area, which can realize the redundant repair function of the above chip stacking structure and improve the stability of the memory chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG1 is a schematic diagram of the structure of a chip;

[0013] FIG2A is a schematic diagram showing the composition of a chip stacking structure;

[0014] FIG2B is a schematic diagram showing the composition of a chip stacking structure;

[0015] FIG3 is a schematic diagram of a logic chip provided in an embodiment of the present disclosure;

[0016] FIG4A / FIG4B are schematic diagrams of a logic chip provided in an embodiment of the present disclosure;

[0017] 5 to 6D are schematic diagrams of a repair unit in a logic chip provided by an embodiment of the present disclosure;

[0018] 7 to 8D are schematic diagrams of another repair unit in a logic chip provided by an embodiment of the present disclosure;

[0019] FIG9 is a schematic diagram of a memory chip provided in an embodiment of the present disclosure;

[0020] FIG10A / FIG10B are schematic diagrams of a memory chip provided in an embodiment of the present disclosure;

[0021] 11 to 12D are schematic diagrams of a repair unit in a memory chip provided by an embodiment of the present disclosure;

[0022] 13 to 14D are schematic diagrams of another repair unit in a memory chip provided by an embodiment of the present disclosure;

[0023] FIG15 is a schematic diagram of the composition structure of a chip stacking structure provided by an embodiment of the present disclosure;

[0024] FIG16A / FIG16B are schematic diagrams showing the positions of repair units in a chip stacking structure provided by an embodiment of the present disclosure;

[0025] FIG17A / FIG17B / FIG17C are specific schematic diagrams of a first chip stacking structure provided by an embodiment of the present disclosure;

[0026] FIG18A / FIG18B are specific schematic diagrams of a second chip stacking structure provided by an embodiment of the present disclosure;

[0027] FIG19A / FIG19B are specific schematic diagrams of a third chip stacking structure provided by an embodiment of the present disclosure;

[0028] FIG20A / FIG20B are specific schematic diagrams of a fourth chip stacking structure provided by an embodiment of the present disclosure;

[0029] FIG21 is a schematic diagram of signal transmission of a chip stacking structure provided by an embodiment of the present disclosure;

[0030] 22A / 22B are schematic diagrams of a chip stacking structure repair process according to an embodiment of the present disclosure;

[0031] FIG23 is a schematic diagram of signal transmission of another chip stacking structure provided by an embodiment of the present disclosure;

[0032] 24A / 24B are schematic diagrams showing a repair process of another chip stack structure provided by an embodiment of the present disclosure;

[0033] FIG25 is a schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are only used to explain the related applications and are not intended to limit the present disclosure. It should also be noted that for ease of description, only the portions relevant to the related applications are shown in the drawings.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0036] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0037] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0038] Before introducing the embodiments of the present disclosure, three directions that may be used to describe a three-dimensional structure in the plane involved in the following embodiments are defined. Taking the Cartesian coordinate system as an example, the three directions may include a first direction, a second direction, and a third direction.

[0039] Referring to Figure 1 , a semiconductor chip (specifically, a memory chip or a logic chip) may include a top surface on the front side and a bottom surface on the back side opposite the front side. Ignoring the flatness of the top and bottom surfaces, a direction intersecting (e.g., perpendicular to) the top and bottom surfaces of the semiconductor chip is defined as a third direction. Two mutually perpendicular directions, namely a first direction and a second direction, are defined on the top surface of the semiconductor chip. The first direction is perpendicular to one edge of the semiconductor chip, and the second direction is perpendicular to the other edge of the semiconductor chip.

[0040] Please refer to Figure 1. The semiconductor chip includes a substrate. The substrate has an active surface on one side used to make devices (such as transistors, capacitors, etc.). Multiple metal layers are distributed between the substrate and the top surface, such as M1, M2, M3... Figure 1 also shows two types of conductive through-holes (for example: through-silicon vias TSV), both of which are used to achieve signal connection between different stacked chips.

[0041] As shown in FIG. 1 , a type 1 conductive via penetrates the bottom surface and the top surface along a third direction, and is connected to an internal circuit of the chip through a metal layer.

[0042] As shown in Figure 1, Type 2 conductive vias only penetrate the substrate in the third direction and require a contact structure that penetrates the top surface in the third direction to achieve signal transmission. The contact structure and the conductive via are not directly electrically connected, but are indirectly electrically connected through the metal layer. For example, the contact structure in Figure 1 is connected to M4, which is then connected to M1 via M3 and M2, and M1 is connected to the conductive via. Of course, in other embodiments, the contact structure and the conductive via can also be designed to be directly electrically connected.

[0043] Meanwhile, the types of conductive vias are not limited to the two described above; the above are merely examples. In particular, the illustrations presented in this disclosure are not intended to be actual views of any particular microelectronic device or its components, but are merely idealized representations used to describe illustrative embodiments. Therefore, the drawings are not necessarily to scale.

[0044] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0045] In one embodiment, a memory chip and a logic chip are provided. Each memory chip and the logic chip include multiple conductive vias extending through the chip along a third direction. The conductive vias are used to transmit signals between different chips. All conductive vias can be located at any position. In particular, every four conductive vias can be functionally considered a conductive via group, but the positions of the four conductive vias are not limited.

[0046] In a specific embodiment, eight of the aforementioned memory chips and one logic chip are stacked to form a 3D memory device. The conductive vias of the eight memory chips are aligned along a third direction, and the nine conductive vias aligned along the third direction are connected to form an electrical path. Please refer to FIG2A , which shows a schematic diagram of signal transmission in a chip stacking structure. As shown in FIG2A , the chip stacking structure includes memory chips 0 to 7 and a logic chip. FIG2A shows only four conductive vias D0 to D3 for each memory chip, and these four conductive vias D0 to D3 belong to the same conductive via group. At this time, the conductive vias D0 in the eight memory chips and one logic chip are all aligned to form one electrical path, and the conductive vias D1 in the eight memory chips and one logic chip are all aligned to form one electrical path... The remaining conductive vias are similar.

[0047] At the same time, each memory chip and logic chip is also equipped with multiple drive circuits (only one of these drive circuits is shown in a dotted box in Figure 2A; the remaining drive circuits are not framed), and each conductive via is connected to a drive circuit. Each memory chip is also equipped with multiple data selectors (for example, mux0-7 in Figure 2A), with each conductive via group corresponding to one data selector. That is, all conductive vias in a conductive via group are connected to the data port of the data selector through their respective drive circuits. In other words, the data selector can select which conductive via transmits the signal to output to the memory chip or to which conductive via the signal output by the memory chip is output.

[0048] For the overall memory device, different areas in different memory chips will be divided into different channels (for example: CH0, CH1, CH4, CH5) for management. The signal Signal_CH0 of channel CH0 is transmitted through the electrical path formed by "the conductive through hole D0 in the logic chip, the conductive through hole D0 in memory chip 0 - the conductive through hole D0 in memory chip 1 - the conductive through hole D0 in memory chip 2 - the conductive through hole D0 in memory chip 3 - the conductive through hole D0 in memory chip 4 - the conductive through hole D0 in memory chip 5 - the conductive through hole D0 in memory chip 6 - the conductive through hole D0 in memory chip 7", and the selection signals of the data selector mux0 in memory chip 0 and the data selector mux4 in memory chip 4 are both SEL_C0, that is, the signal Signal_CH0 can enter the memory chip 0 and the memory chip 4 through the aforementioned electrical path; the signal output process can be understood similarly.

[0049] From the above, it can be seen that memory chip 0 only needs to obtain signals from conductive through-hole D0, and memory chip 1 only needs to obtain signals from conductive through-hole D1... That is, each memory chip only needs to obtain signals from one of the conductive through-holes in a conductive through-hole group. It is worth noting that different memory chips may need to obtain signals from different conductive through-holes. However, since all memory chips need to be designed into exactly the same structure during process manufacturing (so as to maximize cost and manpower savings), all conductive through-holes in the memory chip need to be designed with corresponding drive structures and data selectors to achieve structural consistency. Further, when the chip stacking structure shown in FIG2A is adopted, each conductive through-hole corresponds to a drive circuit; during the operation of the chip stacking structure, it is necessary to drive all drive circuits in all memory chips in the same channel, the load is large and the parasitic capacitance is large, which seriously affects the performance of the chips, restricts transmission efficiency and increases power consumption, and also restricts the number of chips stacked in the three-dimensional device.

[0050] In another embodiment, please refer to FIG2B , which shows a schematic diagram of signal transmission of another chip stacking structure. In particular, FIG2B only labels some of the conductive through holes (D0 to D3), and omits the others. However, for FIG4A , the labels of the conductive through holes aligned along the third direction are the same. As shown in FIG2B , the chip stacking structure also includes 8 memory chips and 1 logic chip aligned along the third direction, but the conductive through holes in each memory chip are rotationally connected to another conductive through hole at a different position in another memory chip, realizing a spiral upward connection as a whole, that is, the signal Signal_CH0 of channel CH0 is transmitted through "conductive through hole D0 in the logic chip - conductive through hole D1 in memory chip 0 - conductive through hole D2 in memory chip 1 - conductive through hole D3 in memory chip 2 - conductive through hole D0 in memory chip 3 - conductive through hole D1 in memory chip 4 - conductive through hole D2 in memory chip 5 - conductive through hole D3 in memory chip 6 - conductive through hole D0 in memory chip 7", and the remaining signals are similar.

[0051] In this way, memory chip 0 can obtain signal Signal_CH0 through the output end of the conductive through hole D0 in the logic chip, memory chip 1 can obtain signal Signal_CH1 through the input end of the conductive through hole D0 in memory chip 0, memory chip 2 can obtain signal Signal_CH4 through the input end of the conductive through hole D0 in memory chip 1, and memory chip 3 can obtain signal Signal_CH5 through the input end of the conductive through hole D0 in memory chip 2... For each memory chip, only one conductive through hole in each conductive through hole group is required to connect to the driving circuit, and there is no need to set a data selector, which can reduce the number of devices and thus reduce parasitic capacitance. However, compared to the conductive via direct connection configuration of FIG2A , the process of the conductive via rotational connection in FIG2B is more complicated. Specifically, a horizontal interconnection structure needs to be set between adjacent conductive vias in each memory chip in FIG2B (only one of them is marked with a five-pointed star in FIG2B ). The signal interconnection structure can be a metal interconnection line, a conductive via, etc. In order to achieve the conductive via rotational connection, the input signal signal_CH0 must first be transmitted upward from the conductive via D0 of the logic chip to the interconnection structure below the conductive via D0 of the memory chip 0 (not connected to the conductive via D0 of the memory chip 0), and then horizontally transmitted from the interconnection structure below the conductive via D0 of the memory chip 0 to the conductive via D1 of the memory chip 0. That is, the structure shown in FIG2B also needs to pass through the interconnection structure in each memory chip during the signal process, and the output signal is similar. This will inevitably lead to an increase in parasitic resistance and also increase the complexity of the process.

[0052] In particular, in the chip stacking structure of Figures 2A and 2B, all chips are active-side up, that is, different memory chips are stacked back to back, and memory chips and logic chips are also stacked back to back, that is, the bottom surface of the upper chip is in contact with the top surface of the lower chip.

[0053] In summary, on the one hand, the chip stacking structure of Figure 2A requires more conductive vias to transmit the corresponding signals, and the corresponding drive circuit and data selector result in larger loads and parasitic capacitances. The chip stacking structure of Figure 2B has a larger parasitic resistance due to the rotational configuration. On the other hand, both the stacking structures of Figures 2A and 2B have certain problems and cannot be directly applied to face-to-face stacking structures. Specifically, if you want to further realize a face-to-face chip stacking structure, one way is to use two sets of masks to make two different chips as chips with the active surface facing up and the active surface facing down. This method has a high process complexity and uncontrollable costs. Another way is to make an extra set of conductive vias and connect both sets of conductive vias to the same drive circuit in the memory chip. However, this will make the internal wiring of the memory chip complicated, which will not only increase the process complexity but also increase power consumption.

[0054] In one embodiment of the present disclosure, FIG3 illustrates a schematic diagram of an active surface of a logic chip 10. As shown in FIG3 , the logic chip 10 includes m channel signal regions arranged sequentially along a first direction ( FIG3 illustrates m=4 as an example). The logic chip 10 has a chip axis YY' extending along a second direction and passing through the center of the logic chip 10. The m channel signal regions are symmetrical about the chip axis YY'.

[0055] As shown in Figure 3, the center of the active surface of logic chip 10 and its adjacent areas are also defined as global signal areas. Here, the first channel signal area 11, the second channel signal area 12, the global signal area, the third channel signal area 13, and the fourth channel signal area 14 are sequentially arranged along a first direction. The upper and lower sides of the channel signal areas of logic chip 10 are used to distribute some logic control circuits of the stacked memory.

[0056] FIG3 is shown using m=4 as an example, and the following description also uses m=4 as an example, but m can be any positive integer. Specifically, if m is an even number, then m / 2 channel signal areas are located on one side of the global signal area along the first direction, and the remaining m / 2 channel signal areas are located on the other side of the global signal area along the first direction; if m is an odd number, then the (m+1) / 2th channel signal area needs to be divided into two parts and located on both sides of the global signal area along the first direction, while the other (m-1) / 2 channel signal areas are located on one side of the global signal area along the first direction, and the remaining (m-1) / 2 channel signal areas are located on the other side of the global signal area along the first direction.

[0057] It should be noted that during the chip manufacturing process, in order to distinguish different channel signal areas of the chip, a positioning structure can be made in the reference channel signal area (for example, the first channel signal area) of the logic chip 10, so that during subsequent packaging, the position of the reference channel can be identified through the positioning structure, and other channels can be identified in combination with the active surface orientation of the chip.

[0058] It should be noted that both the global signal area and the channel signal area are penetrated by many conductive vias along the third direction, and the third direction is perpendicular to the active surface, that is, the first direction, the second direction and the third direction are perpendicular to each other. Here, the conductive via can be a through silicon via (TSV), which is specifically a vertical interconnection structure that penetrates the silicon wafer / chip, or, in other embodiments, it can also be other conductive vias with conductive functions, which is not specifically limited. In addition, the conductive via can be in the form of the aforementioned type 1, or in the form of the aforementioned type 2.

[0059] For the global signal area, each conductive through-hole is used to transmit the global signal, and the global signal is shared by all areas of the corresponding memory chip. Global signals include but are not limited to: reset signal, power-on signal, stack identification signal SID / CID, power-related signal Voltage Monitor, timing-related signal Timing Aligner. In some cases, the global signal area may also refer to the pad area. The global signal can be a test signal of Design For Test (DFT), through which the working status of the internal circuit of the chip and the transmission status of related signals can be known. In addition, because the pin pad (PAD) of the DFT in the logic chip is generally located in the middle of the chip, the conductive through-holes of global signals such as DFT are preferably located in the narrower area in the middle of the chip, that is, the position of the global signal area as shown in Figure 3.

[0060] That is, the global signal transmitted by the global signal area is used by m channels in all memory chips in the subsequent stacking structure; while the channel control signal transmitted by each channel signal area is only used by a specific channel in all memory chips in the subsequent stacking structure.

[0061] Referring to FIG4A , each channel signal region includes a first axis AA' and a second axis BB'. The first axis AA' extends along the first direction or the second direction. The second axis BB' and the first axis AA' are perpendicular to each other and intersect at the center of the corresponding channel signal region. For example, in FIG3 , the first axis AA' extends along the first direction and the second axis BB' extends along the second direction. In other embodiments, the first axis AA' may extend along the second direction and the second axis BB' may extend along the first direction. FIG4A temporarily omits the global signal region. As shown in FIG4A , each channel signal region is penetrated by a plurality of conductive vias (D0, D1, D2, D3) along the third direction. Each conductive via is used to transmit the aforementioned channel control signal. The first direction, the second direction, and the third direction are perpendicular to each other. The first direction and the second direction are parallel to the top surface of the logic chip 10, and the third direction is perpendicular to the top surface of the logic chip 10.

[0062] In the embodiment of the present disclosure, please refer to Figure 4B. For each channel signal area, the (all or part of) conductive vias therein are divided into multiple repair unit groups. Each repair unit group includes a first repair unit, a second repair unit, a third repair unit, and a fourth repair unit; the first repair unit and the second repair unit are symmetrical along the first axis AA' of the channel signal area to which they belong, the third repair unit and the fourth repair unit are symmetrical along the first axis AA' of the channel signal area to which they belong, and the first repair unit and the fourth repair unit are symmetrical along the second axis BB' of the channel signal area to which they belong. The above symmetry characteristics can be called four-quadrant symmetry. In particular, the various repair unit groups in Figure 4B are only for illustration, and the shapes of the actual repair unit groups can be in various forms.

[0063] Each repair unit (unless otherwise specified) includes at least one redundant conductive via and at least one normal conductive via. A normal conductive via is a conductive via designed to transmit valid signals, while a redundant conductive via is a conductive via not designed to transmit any signals. However, if any normal conductive via is damaged, the redundant conductive via can be converted to a normal conductive via for transmitting valid signals, allowing the memory to continue functioning normally. That is to say, for the same repair unit, when any normal conductive via is damaged, the effective signal transmitted by the normal conductive via is switched to the next conductive via in the same repair unit along the preset signal switching direction. Specifically: (1) If the next conductive via to be switched is a redundant conductive via, the repair is completed, and the redundant conductive via becomes the new normal conductive via; (2) If the next conductive via to be switched is another normal conductive via, the signal originally transmitted by the switched normal conductive via continues to be switched to its next conductive via along the preset switching direction until it is switched to a redundant conductive via.

[0064] In particular, the logic chip 10 also includes multiple signal selection circuits (which may specifically include a data selector Mux and a driving unit). Taking signal output as an example, the signal to be transmitted generated inside the logic chip 10 is sent to the input end of the signal selection circuit, and the output end of the signal selection circuit is respectively connected to multiple conductive through-holes; at this time, the signal selection circuit only sends the signal to be transmitted to one of the conductive through-holes. When the conductive through-hole is damaged, the signal selection circuit can send the signal to be transmitted to another conductive through-hole, thereby realizing the switching of the conductive through-holes (that is, the switching of the signal transmission channel); please adapt to understand the corresponding structure of the signal input.

[0065] Thus, through the signal selection circuit, any conductive via in any repair unit is electrically connected to the internal circuit of logic chip 10 when transmitting a valid signal, and any conductive via in any repair unit is electrically isolated from the internal circuit of logic chip 10 when not transmitting a valid signal. Alternatively, it can be understood that any conductive via in any repair unit is electrically connected to the internal circuit of logic chip 10 when functioning as a normal conductive via, and any conductive via in any repair unit is electrically isolated from the internal circuit of logic chip 10 when not functioning as a normal conductive via.

[0066] The number of redundant conductive vias and the number of normal conductive vias in each repair unit can be flexibly determined. For example, if each repair unit includes four different conductive vias, the ratio of normal conductive vias to redundant conductive vias is 2:2, or 1:3, or 3:1. For example, if each repair unit includes six different conductive vias, the ratio of normal conductive vias to redundant conductive vias is 4:2, or 3:3. These ratios can be selected based on the actual application scenario.

[0067] In the embodiment of the present disclosure, the normal conductive vias in the repair units have the following symmetrical relationship: the normal conductive vias in the first repair unit and the normal conductive vias in the second repair unit correspond one-to-one and are symmetrical along the first axis AA' of the channel signal area to which they belong; the normal conductive vias in the third repair unit and the normal conductive vias in the fourth repair unit correspond one-to-one and are symmetrical along the first axis AA' of the channel signal area to which they belong; the normal conductive vias in the first repair unit and the normal conductive vias in the fourth repair unit correspond one-to-one and are symmetrical along the second axis BB' of the channel signal area to which they belong, that is, the positions of the normal conductive vias also have the characteristics of four-quadrant symmetry.

[0068] In this way, the repair units in the logic chip 10 have a four-quadrant symmetrical relationship, and the normal conductive through-holes therein also have a four-quadrant symmetrical relationship, so that the chip stacking structure formed by the logic chip and the memory chip (which also has this feature) can achieve a signal rotation transmission effect through the direct connection configuration of the conductive through-holes, and the parasitic resistance and parasitic capacitance are relatively small. Please refer to the subsequent description for details; at the same time, through the four-quadrant symmetrical arrangement of the repair units, the redundant repair function of the above structure can also be realized, thereby improving the stability of the chip; at the same time, the distribution of the conductive through-hole groups and repair units in different channel signal areas is the same, and the same mask plate can be used.

[0069] In the embodiment of the present disclosure, for each repair unit group, the preset switching direction of the conductive via in the first repair unit and the preset switching direction of the conductive via in the second repair unit are symmetrical along the first axis AA' of the channel signal area to which they belong; the preset switching direction of the conductive via in the third repair unit and the preset switching direction of the conductive via in the fourth repair unit are symmetrical along the first axis AA' of the channel signal area to which they belong; the preset switching direction of the conductive via in the first repair unit and the preset switching direction of the conductive via in the fourth repair unit are symmetrical along the second axis BB' of the channel signal area to which they belong; the preset switching direction of the conductive via in the second repair unit and the preset switching direction of the conductive via in the third repair unit are symmetrical along the second axis BB' of the channel signal area to which they belong.

[0070] Referring to Figure 4A , each channel signal region is divided into 2×2 signal zones, namely, a first signal zone 21, a second signal zone 22, a third signal zone 23, and a fourth signal zone 24. The conductive vias (all or part of) each signal zone are divided into n conductive via groups with identical distribution positions, where n is a positive integer. Each dotted box in Figure 4A represents a conductive via group. As shown in Figure 4A , the conductive via groups in the first signal zone 21 and the conductive via groups in the second signal zone 22 correspond one-to-one and are symmetrical along the first axis AA' of their respective channel signal regions. The conductive via groups in the third signal zone 23 and the conductive via groups in the fourth signal zone 24 correspond one-to-one and are symmetrical along the first axis AA' of their respective channel signal regions. The conductive via groups in the first signal zone 21 and the conductive via groups in the fourth signal zone 24 correspond one-to-one and are symmetrical along the second axis BB' of their respective channel signal regions. This means that the conductive via groups are also four-quadrant symmetrical. Figure 4A shows only one conductive via group per signal zone, but in reality, each signal zone has many conductive via groups.

[0071] As shown in FIG4A , each conductive via group includes a first conductive via D0 , a second conductive via D1 , a third conductive via D2 , and a fourth conductive via D3 , and has the following symmetrical relationship:

[0072] (1) In the same channel signal region, the first conductive through hole D0 in a conductive through hole group in the first signal region 21, the second conductive through hole D1 in a corresponding conductive through hole group in the second signal region 22, the third conductive through hole D2 in a corresponding conductive through hole group in the third signal region 23, and the fourth conductive through hole D3 in a corresponding conductive through hole group in the fourth signal region 24 are formed as a whole, which is symmetrical along the first axis AA' and symmetrical along the second axis BB';

[0073] (2) In the same channel signal region, the whole formed by the second conductive through-hole D1 in a conductive through-hole group in the first signal region 21, the first conductive through-hole D0 in the corresponding conductive through-hole group in the second signal region 22, the fourth conductive through-hole D3 in the corresponding conductive through-hole group in the third signal region 23, and the third conductive through-hole D2 in the corresponding conductive through-hole group in the fourth signal region 24 is symmetrical along the first axis AA' and symmetrical along the second axis BB';

[0074] (3) In the same channel signal region, the entirety formed by the third conductive through-hole D2 in a conductive through-hole group in the first signal region 21, the fourth conductive through-hole D3 in a corresponding conductive through-hole group in the second signal region 22, the first conductive through-hole D0 in a corresponding conductive through-hole group in the third signal region 23, and the second conductive through-hole D1 in a corresponding conductive through-hole group in the fourth signal region 24 is symmetrical along the first axis AA' and symmetrical along the second axis BB';

[0075] (4) In the same channel signal area, the whole formed by the fourth conductive through hole D3 in a conductive through hole group in the first signal area 21, the third conductive through hole D2 in the corresponding conductive through hole group in the second signal area 22, the second conductive through hole D1 in the corresponding conductive through hole group in the third signal area 23, and the first conductive through hole D0 in the corresponding conductive through hole group in the fourth signal area 24 is symmetrical along the first axis AA' and symmetrical along the second axis BB'.

[0076] It should be understood that in FIG. 4A , the four conductive vias in each conductive via group are distributed in a 2×2 array, but in other embodiments, the four conductive vias in each conductive via group may be distributed arbitrarily, as long as the above symmetry principle is observed.

[0077] Due to limited space, the subsequent figures only use one channel signal area as an example to illustrate the composition and principle of the repair unit group, but in fact, the structure of all channel signal areas is the same, that is, the channel signal area in the figures can be understood as any one of channel signal area 11, channel signal area 12, channel signal area 13, and channel signal area 14.

[0078] In some embodiments, the B conductive via groups in each signal area are referred to as a conductive via combination. The conductive via group b in the corresponding conductive via combinations in all signal areas is symmetrical along the first axis AA' and symmetrical along the second axis BB'. B is a positive integer less than or equal to n, and b is a natural number less than B.

[0079] The corresponding conductive via combination in each signal area of ​​the same channel signal area constitutes a total of 4 repair unit groups:

[0080] (1) For the first repair unit group, the first repair unit includes: the first conductive via D0 of each of all conductive via groups in the conductive via combination in the first signal area 21; the second repair unit includes: the second conductive via D1 of each of all conductive via groups in the conductive via combination in the second signal area 22; the third repair unit includes: the third conductive via D2 of each of all conductive via groups in the conductive via combination in the third signal area 23; the fourth repair unit includes: the fourth conductive via D3 of each of all conductive via groups in the conductive via combination in the fourth signal area 24;

[0081] (2) For the second repair unit group, the first repair unit includes: the first conductive via D0 of each of all conductive via groups in the conductive via combination in the second signal area 22; the second repair unit includes: the second conductive via D1 of each of all conductive via groups in the conductive via combination in the first signal area 21; the third repair unit includes: the third conductive via D2 of each of all conductive via groups in the conductive via combination in the fourth signal area 24; and the fourth repair unit includes: the fourth conductive via D3 of each of all conductive via groups in the conductive via combination in the third signal area 23;

[0082] (3) For the third repair unit group, the first repair unit includes: the first conductive via D0 of each of all conductive via groups in the conductive via combination in the third signal area 23; the second repair unit includes: the second conductive via D1 of each of all conductive via groups in the conductive via combination in the fourth signal area 24; the third repair unit includes: the third conductive via D2 of each of all conductive via groups in the conductive via combination in the first signal area 21; the fourth repair unit includes: the fourth conductive via D3 of each of all conductive via groups in the conductive via combination in the second signal area 22;

[0083] (4) For the fourth repair unit group, the first repair unit includes: the first conductive through hole D0 of each of all conductive through hole groups in the conductive through hole combination in the fourth signal area 24; the second repair unit includes: the second conductive through hole D1 of each of all conductive through hole groups in the conductive through hole combination in the third signal area 23; the fourth repair unit includes: the third conductive through hole D2 of each of all conductive through hole groups in the conductive through hole combination in the second signal area 22; and the fourth repair unit includes: the fourth conductive through hole D3 of each of all conductive through hole groups in the conductive through hole combination in the first signal area 21.

[0084] It should be noted that for the same logic chip 10, B can have multiple values. For example, the same logic chip 10 may have a conductive via combination consisting of four conductive via groups, a conductive via combination consisting of six conductive via groups, or even more. However, regardless of the number of conductive via groups, each conductive via combination must form four repair unit groups.

[0085] In the first specific embodiment, referring to FIG5 , B=3, and b is 0, 1, or 2. That is, the entirety formed by conductive via group 0 in the first signal region 21, conductive via group 0 in the second signal region 22, conductive via group 0 in the third signal region 23, and conductive via group 0 in the fourth signal region 24 is symmetrical along the first axis AA' and along the second axis BB'; the entirety formed by conductive via group 1 in the first signal region 21, conductive via group 1 in the second signal region 22, conductive via group 1 in the third signal region 23, and conductive via group 1 in the fourth signal region 24 is symmetrical along the first axis AA' and along the second axis BB'; ...

[0086] The conductive via group 0 to the conductive via group 2 in each signal area of ​​the same channel signal area constitute a total of 4 repair unit groups:

[0087] Please refer to FIG6A , for the first repair unit group_1: (1) the first repair unit_1 includes: the first conductive vias of conductive via group 0, conductive via group 1, and conductive via group 2 in the first signal area 21, i.e., D0 / 0, D0 / 1, and D0 / 2 in the first signal area 21; (2) the second repair unit_1 includes: the second conductive vias of conductive via group 0, conductive via group 1, and conductive via group 2 in the second signal area 22, i.e., D1 / 0, D1 / 1, and D1 / 2 in the second signal area 22. D1 / 1, D1 / 2; (3) the third repair unit_1 includes: the third conductive through holes of conductive through hole group 0, conductive through hole group 1, and conductive through hole group 2 in the third signal area 23, that is, D2 / 0, D2 / 1, and D2 / 2 in the third signal area 23; (4) the fourth repair unit_1 includes: the fourth conductive through holes of conductive through hole group 0, conductive through hole group 1, and conductive through hole group 2 in the fourth signal area 24, that is, D3 / 0, D3 / 1, and D3 / 2 in the fourth signal area 24.

[0088] Please refer to FIG6B . For the second repair unit group_2, (1) the first repair unit_2 includes: the first conductive vias of the conductive via group 0, the conductive via group 1, and the conductive via group 2 in the second signal area 22, i.e., D0 / 0, D0 / 1, and D0 / 2 in the second signal area 22; (2) the second repair unit_2 includes: the second conductive vias of the conductive via group 0, the conductive via group 1, and the conductive via group 2 in the first signal area 21, i.e., D1 / 0, D2 / 1, and D3 / 2 in the first signal area 21. D1 / 1, D1 / 2; (3) the third repair unit_2 includes: the third conductive through holes of conductive through hole group 0, conductive through hole group 1, and conductive through hole group 2 in the fourth signal area 24, that is, D2 / 0, D2 / 1, and D2 / 2 in the fourth signal area 24; (4) the fourth repair unit_2 includes: the fourth conductive through holes of conductive through hole group 0, conductive through hole group 1, and conductive through hole group 2 in the third signal area 23, that is, D3 / 0, D3 / 1, and D3 / 2 in the third signal area 23.

[0089] Please refer to FIG6C . For the third repair unit group_3, (1) the first repair unit_3 includes: the first conductive vias of conductive via group 0, conductive via group 1, and conductive via group 2 in the third signal area 23, i.e., D0 / 0, D0 / 1, and D0 / 2 in the third signal area 23; (2) the second repair unit_3 includes: the second conductive vias of conductive via group 0, conductive via group 1, and conductive via group 2 in the fourth signal area 24, i.e., D1 / 0, D1 / 1, and D1 / 2 in the fourth signal area 24. D1 / 1, D1 / 2; (3) the third repair unit_3 includes: the third conductive through hole of each of the conductive through hole group 0, the conductive through hole group 1, and the conductive through hole group 2 in the first signal area 21, that is, D2 / 0, D2 / 1, and D2 / 2 in the first signal area 21; (4) the fourth repair unit_3 includes: the fourth conductive through hole of each of the conductive through hole group 0, the conductive through hole group 1, and the conductive through hole group 2 in the second signal area 22, that is, D3 / 0, D3 / 1, and D3 / 2 in the second signal area 22.

[0090] Please refer to FIG6D . For the fourth repair unit group_4, (1) the first repair unit_4 includes: the first conductive vias of the conductive via group 0, the conductive via group 1, and the conductive via group 2 in the fourth signal area 24, i.e., D0 / 0, D0 / 1, and D0 / 2 in the fourth signal area 24; (2) the second repair unit_4 includes: the second conductive vias of the conductive via group 0, the conductive via group 1, and the conductive via group 2 in the third signal area 23, i.e., D2 / 0, D2 / 1, and D2 / 2 in the third signal area 23. D2 / 1, D2 / 2; (3) the third repair unit_4 includes: the third conductive through holes of conductive through hole group 0, conductive through hole group 1, and conductive through hole group 2 in the second signal area 22, that is, D2 / 0, D2 / 1, and D2 / 2 in the second signal area 22; (4) the fourth repair unit_4 includes: the fourth conductive through holes of conductive through hole group 0, conductive through hole group 1, and conductive through hole group 2 in the first signal area 21, that is, D3 / 0, D3 / 1, and D3 / 2 in the first signal area 21.

[0091] It should be noted that: as shown in FIG6A , for the first repair unit group, the first repair unit _1 (D0 / 0, D0 / 1, D0 / 2 of the first signal area 21) and the second repair unit _1 (D1 / 0, D1 / 1, D1 / 2 of the first signal area 22) are symmetrical along the first axis AA', and the third repair unit _1 (D2 / 0, D2 / 1, D2 / 2 of the third signal area 23) and the fourth repair unit _1 (D3 / 0, D3 / 1, D3 / 2 of the fourth signal area 24) are symmetrical along the first axis AA'. 2) Symmetrical along the first axis AA': the first repair unit_1 (D0 / 0, D0 / 1, D0 / 2 of the first signal area 21) and the fourth repair unit_1 (D3 / 0, D3 / 1, D3 / 2 of the fourth signal area 24) are symmetrical along the second axis BB'; the second repair unit_1 (D1 / 0, D1 / 1, D1 / 2 of the first signal area 22) and the third repair unit_1 (D2 / 0, D2 / 1, D2 / 2 of the third signal area 23) are symmetrical along the second axis BB'. Simultaneously, the second to fourth repair unit groups also have similar characteristics.

[0092] The following provides an example of a preset switching direction to facilitate a better understanding of the above description, but the following example is not the only solution.

[0093] Assume that all conductive through-holes in conductive through-hole group 0 are normal conductive through-holes; the preset switching direction of the conductive through-holes in the Xth repair unit is: the Xth conductive through-hole in conductive through-hole group 0 is allowed to switch to the Xth conductive through-hole in conductive through-hole group 1 in the same signal area, and the Xth conductive through-hole in conductive through-hole group 1 is allowed to switch to the Xth conductive through-hole in conductive through-hole group 2 in the same signal area; X is one, two, three or four.

[0094] That is to say, referring to Figure 6A, for the first repair unit group, the preset switching direction of the conductive via in the first repair unit_1 is: D0 / 0-D0 / 1-D0 / 2 in the first signal area 21; the preset switching direction of the conductive via in the second repair unit_1 is: D1 / 0-D1 / 1-D1 / 2 in the second signal area 22; the preset switching direction of the conductive via in the third repair unit_1 is: D2 / 0-D2 / 1-D2 / 2 in the third signal area 23; the preset switching direction of the conductive via in the fourth repair unit_1 is: D3 / 0-D3 / 1-D3 / 2 in the fourth signal area 24.

[0095] Please refer to Figure 6B. For the second repair unit group, the preset switching direction of the conductive through-hole in the first repair unit_2 is: D0 / 0-D0 / 1-D0 / 2 in the second signal area 22; the preset switching direction of the conductive through-hole in the second repair unit_2 is: D1 / 0-D1 / 1-D1 / 2 in the first signal area 21; the preset switching direction of the conductive through-hole in the third repair unit_2 is: D2 / 0-D2 / 1-D2 / 2 in the fourth signal area 24; the preset switching direction of the conductive through-hole in the fourth repair unit_2 is: D3 / 0-D3 / 1-D3 / 2 in the third signal area 23.

[0096] Please refer to Figure 6C. For the third repair unit group, the preset switching direction of the conductive through-hole in the first repair unit_3 is: D0 / 0-D0 / 1-D0 / 2 in the third signal area 23; the preset switching direction of the conductive through-hole in the second repair unit_3 is: D1 / 0-D1 / 1-D1 / 2 in the fourth signal area 22; the preset switching direction of the conductive through-hole in the third repair unit_3 is: D2 / 0-D2 / 1-D2 / 2 in the first signal area 21; the preset switching direction of the conductive through-hole in the fourth repair unit_3 is: D3 / 0-D3 / 1-D3 / 2 in the second signal area 22.

[0097] Please refer to Figure 6D. For the fourth repair unit group, the preset switching direction of the conductive through-hole in the first repair unit_4 is: D0 / 0-D0 / 1-D0 / 2 in the fourth signal area 24; the preset switching direction of the conductive through-hole in the second repair unit_4 is: D1 / 0-D1 / 1-D1 / 2 in the third signal area 22; the preset switching direction of the conductive through-hole in the third repair unit_4 is: D2 / 0-D2 / 1-D2 / 2 in the second signal area 23; the preset switching direction of the conductive through-hole in the fourth repair unit_4 is: D3 / 0-D3 / 1-D3 / 2 in the second signal area 21.

[0098] It should be noted that, for each of the above-mentioned repair units, the ratio of the number of normal conductive vias to the number of redundant conductive vias can be set arbitrarily, such as 1:2, 2:1, etc.

[0099] For ease of understanding, the following provides a specific description of the signal switching related circuit using the repair ratio of normal conductive vias to redundant conductive vias = 2:1 as an example. In order to implement the above switching process, please refer to Figures 6A, 6B, 6C and 6D. The logic chip 10 also includes a plurality of signal selection circuits 100 for implementing the switching of the above conductive vias. Specifically, each signal selection circuit 100 is composed of a data selector and a plurality of driving units. The data selector in the signal selection circuit 100 is connected to a plurality of conductive via groups, and the driving circuit in the signal selection circuit 100 is connected to the internal circuit of the logic chip 10. Therefore, through the signal selection circuit 100, a designated conductive via can be selected to be electrically connected to the internal circuit of the logic chip 10, so that the switching of the conductive vias can be performed.

[0100] Taking the first repair unit_1 of the first repair unit group (D0 / 0, D0 / 1, D0 / 2 in the first signal area 21) as an example, see Figure 6A. D0 / 0 and D0 / 1 are connected to the first signal selection circuit 100, and the first signal selection circuit 100 connects D0 / 0 to the internal circuit of the logic circuit 10; D0 / 1 and D0 / 2 are connected to the second signal selection circuit 100, and the second signal selection circuit 100 connects D0 / 1 to the internal circuit of the logic circuit 10; then, if D0 / 0 is damaged, the first signal selection circuit 100 connects D0 / 1 to the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D0 / 0 will be transmitted by D0 / 1; at the same time, the second signal selection circuit 100 connects D0 / 2 to the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D0 / 1 will be transmitted by D0 / 2. Please refer to this for understanding of the remaining repair units.

[0101] It should be noted that Figures 6A to 6D are only examples of preset switching directions; the preset switching directions actually have very flexible options. Taking the first repair unit_1 as an example, it can currently switch along D0 / 0, D0 / 1, and D0 / 2 in sequence, or it can switch along D0 / 2, D0 / 1, and D0 / 0, or use D0 / 1 as the switching starting point, and so on. Of course, the four repair units must follow the aforementioned symmetry characteristics, that is, if the first repair unit_1 adopts other switching forms and the definition of normal conductive through-holes, then the second repair unit_1, the third repair unit_1, and the fourth repair unit_1 must also adopt corresponding switching forms and the definition of normal through-holes.

[0102] In this way, the conductive through-hole positions and preset switching directions of different repair units maintain the above-mentioned symmetrical relationship, so that the chip stacking structure formed subsequently can realize signal rotation transmission through a direct connection configuration. Please refer to the subsequent instructions for details.

[0103] In the second specific embodiment, see FIG7 , B=6, and b is 0, 1, 2, 3, 4, or 5. At this time, conductive via group 0 to conductive via group 5 in each signal area of ​​the same channel signal area constitute a total of 4 repair unit groups:

[0104] The six conductive via groups in each signal area are referred to as conductive via groups 0 to 5, respectively. The entirety formed by conductive via group b in all signal areas is symmetrical along the first axis AA' and the second axis BB'; b≤5; that is, the entirety formed by conductive via group 0 in the first signal area 21, conductive via group 0 in the second signal area 22, conductive via group 0 in the third signal area 23, and conductive via group 0 in the fourth signal area 24 is symmetrical along the first axis AA' and the second axis BB'; the entirety formed by conductive via group 1 in the first signal area 21, conductive via group 1 in the second signal area 22, conductive via group 1 in the third signal area 23, and conductive via group 1 in the fourth signal area 24 is symmetrical along the first axis AA' and the second axis BB'; ...

[0105] The conductive via group 0 to the conductive via group 5 in each signal area of ​​the same channel signal area constitute a total of 4 repair unit groups:

[0106] Please refer to FIG8A , for the first repair unit group_A: (1) the first repair unit_A includes: the first conductive vias of each of the conductive via group 0 to the conductive via group 5 in the first signal area 21, i.e., D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, and D0 / 5 in the first signal area 21; (2) the second repair unit_A includes: the second conductive vias of each of the conductive via group 0 to the conductive via group 5 in the second signal area 22, i.e., D1 / 0, D1 / 1, D1 / 2, D1 / 3, D1 / 4, D1 / 5; (3) the third repair unit _A includes: the third conductive through holes of each of the conductive through hole group 0 to the conductive through hole group 5 in the third signal area 23, that is, D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, D2 / 5 in the third signal area 23; (4) the fourth repair unit _A includes: the fourth conductive through holes of each of the conductive through hole group 0 to the conductive through hole group 5 in the fourth signal area 24, that is, D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, D3 / 5 in the fourth signal area 24.

[0107] Please refer to FIG8B . For the second repair unit group_B, (1) the first repair unit_B includes: the first conductive vias of each of the conductive via group 0 to the conductive via group 5 in the second signal area 22, i.e., D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, and D0 / 5 in the second signal area 22; (2) the second repair unit_B includes: the second conductive vias of each of the conductive via group 0 to the conductive via group 5 in the first signal area 21, i.e., D1 / 0, D1 / 1, D1 / 2, D1 / 3, D1 / 4, D1 / 5; (3) the third repair unit _B includes: the third conductive through holes of conductive through hole group 0 to conductive through hole group 5 in the fourth signal area 24, that is, D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, D2 / 5 in the fourth signal area 24; (4) the fourth repair unit _B includes: the fourth conductive through holes of conductive through hole group 0 to conductive through hole group 5 in the third signal area 23, that is, D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, D3 / 5 in the third signal area 23.

[0108] Please refer to FIG8C . For the third repair unit group_C, the first repair unit_C includes: the first conductive vias of each of the conductive via group 0 to the conductive via group 5 in the third signal area 23, i.e., D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, and D0 / 5 in the third signal area 23; (2) the second repair unit_C includes: the second conductive vias of each of the conductive via group 0 to the conductive via group 5 in the fourth signal area 24, i.e., D1 / 0, D1 / 1, D1 / 2, D1 / 3, D1 / 4, and D1 / 5 in the fourth signal area 24. 1 / 4, D1 / 5; (3) the third repair unit _C includes: the third conductive through holes of each of the conductive through hole group 0 to the conductive through hole group 5 in the first signal area 21, that is, D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, and D2 / 5 in the first signal area 21; (4) the fourth repair unit _C includes: the fourth conductive through holes of each of the conductive through hole group 0 to the conductive through hole group 5 in the second signal area 22, that is, D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, and D3 / 5 in the second signal area 22.

[0109] Please refer to FIG8D . For the fourth repair unit group_D, the first repair unit includes: the first conductive vias of each of the conductive via group 0 to the conductive via group 5 in the fourth signal area 24, i.e., D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, and D0 / 5 in the fourth signal area 24; (2) the second repair unit_D includes: the second conductive vias of each of the conductive via group 0 to the conductive via group 5 in the third signal area 23, i.e., D1 / 0, D1 / 1, D1 / 2, D1 / 3, D1 / 4, and D1 / 5 in the third signal area 23. 1 / 4, D1 / 5; (3) the fourth repair unit _D includes: the third conductive through holes of each of the conductive through hole group 0 to the conductive through hole group 5 in the second signal area 22, that is, D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, and D2 / 5 in the second signal area 22; the fourth repair unit _D includes: the fourth conductive through holes of each of the conductive through hole group 0 to the conductive through hole group 5 in the first signal area 21, that is, D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, and D3 / 5 in the first signal area 21.

[0110] It should be noted that, as shown in FIG8A , the first repair unit _A (D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, D0 / 5 in the first signal area 21) and the second repair unit _A (D1 / 0, D1 / 1, D1 / 2, D1 / 3, D1 / 4, D1 / 5 in the second signal area 22) are symmetrical along the first axis AA', and the fourth repair unit _A (D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, D3 / 5 in the fourth signal area 24) and the third repair unit _A (D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, D2 / 5 in the third signal area 23) are symmetrical along the first axis AA'. ) are symmetrical along the first axis AA', the first repair unit_A (D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, D0 / 5 in the first signal area 21) and the fourth repair unit_A (D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, D3 / 5 in the fourth signal area 24) are symmetrical along the second axis BB', and the second repair unit_A (D1 / 0, D1 / 1, D1 / 2, D1 / 3 in the second signal area 22) and the third repair unit_A (D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, D2 / 5 in the third signal area 23) are symmetrical along the second axis BB'. At the same time, the second to fourth repair unit groups also have similar characteristics.

[0111] The following provides an example of a preset switching direction to facilitate a better understanding of the above description, but the following example is not the only solution.

[0112] Assume that all conductive through-holes in the conductive through-hole group 2 in all signal areas are normal conductive through-holes; the preset switching direction of the conductive through-holes in the Xth repair unit is: the Xth conductive through-hole in the conductive through-hole group 2 is allowed to switch to the Xth conductive through-hole in the conductive through-hole group 3 in the same signal area, the Xth conductive through-hole in the conductive through-hole group 3 is allowed to switch to the Xth conductive through-hole in the conductive through-hole group 4 in the same signal area, and the Xth conductive through-hole in the conductive through-hole group 4 is allowed to switch to the Xth conductive through-hole in the conductive through-hole group 1 in the same signal area; the Xth conductive through-hole in the conductive through-hole group 1 is allowed to switch to the Xth conductive through-hole in the conductive through-hole group 0 in the same signal area; the Xth conductive through-hole in the conductive through-hole group 0 is allowed to switch to the Xth conductive through-hole in the conductive through-hole group 5 in the same signal area.

[0113] Referring to FIG8A , the description of the preset switching direction of the first repair unit group_A is as follows:

[0114] (a) The preset switching direction of the conductive vias in the first repair unit_A is: D0 / 2——D0 / 3——D0 / 4——D0 / 1——D0 / 0——D0 / 5 in the first signal area 21; (b) The preset switching direction of the conductive vias in the second repair unit_A is: D1 / 2——D1 / 3——D1 / 4——D1 / 1——D1 / 0——D1 / 5 in the second signal area 22; (c) The preset switching direction of the conductive vias in the third repair unit_A is: D2 / 2——D2 / 3——D2 / 4——D2 / 1——D2 / 0——D2 / 5 in the third signal area 23; (d) The preset switching direction of the conductive vias in the fourth repair unit_A is: D3 / 2——D3 / 3——D3 / 4——D3 / 1——D3 / 0——D3 / 5 in the fourth signal area 24;

[0115] Referring to FIG8B , the description of the preset switching direction of the second repair unit group_B is as follows:

[0116] (a) The preset switching direction of the conductive vias in the first repair unit_B is: D0 / 2——D0 / 3——D0 / 4——D0 / 1——D0 / 0——D0 / 5 in the second signal area 22; (b) The preset switching direction of the conductive vias in the second repair unit_B is: D1 / 2——D1 / 3——D1 / 4——D1 / 1——D1 / 0——D1 / 5 in the first signal area 21; (c) The preset switching direction of the conductive vias in the third repair unit_B is: D2 / 2——D2 / 3——D2 / 4——D2 / 1——D2 / 0——D2 / 5 in the fourth signal area 24; (d) The preset switching direction of the conductive vias in the fourth repair unit_B is: D3 / 2——D3 / 3——D3 / 4——D3 / 1——D3 / 0——D3 / 5 in the third signal area 23;

[0117] Referring to FIG8C , the description of the preset switching direction of the third repair unit group_C is as follows:

[0118] (a) The preset switching direction of the conductive vias in the first repair unit_C is: D0 / 2——D0 / 3——D0 / 4——D0 / 1——D0 / 0——D0 / 5 in the third signal area 23; (b) The preset switching direction of the conductive vias in the second repair unit_C is: D1 / 2——D1 / 3——D1 / 4——D1 / 1——D1 / 0——D1 / 5 in the fourth signal area 24; (c) The preset switching direction of the conductive vias in the second repair unit_C is: D2 / 2——D2 / 3——D2 / 4——D2 / 1——D2 / 0——D2 / 5 in the first signal area 21; (d) The preset switching direction of the conductive vias in the fourth repair unit_C is: D3 / 2——D3 / 3——D3 / 4——D3 / 1——D3 / 0——D3 / 5 in the second signal area 22;

[0119] Referring to FIG8D , the description of the preset switching direction of the fourth repair unit group_C is as follows:

[0120] (a) The preset switching direction of the conductive vias in the first repair unit_D is: D0 / 2——D0 / 3——D0 / 4——D0 / 1——D0 / 0——D0 / 5 in the fourth signal area 24; (b) The preset switching direction of the conductive vias in the second repair unit_D is: D1 / 2——D1 / 3——D1 / 4——D1 / 1——D1 / 0——D1 / 5 in the third signal area 23; (c) The preset switching direction of the conductive vias in the second repair unit_D is: D2 / 2——D2 / 3——D2 / 4——D2 / 1——D2 / 0——D2 / 5 in the second signal area 22; (d) The preset switching direction of the conductive vias in the fourth repair unit_D is: D3 / 2——D3 / 3——D3 / 4——D3 / 1——D3 / 0——D3 / 5 in the first signal area 21;

[0121] The following provides a specific description of a signal switching related circuit by taking a repair ratio of normal conductive vias to redundant conductive vias = 4:2 as an example. Taking the first repair unit_A of the first repair unit group (D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, D0 / 5 of the first signal area 21) as an example, please refer to Figure 8A, D0 / 2, D0 / 3, D0 / 4 are connected to the ① first signal selection circuit 100, and the ① first signal selection circuit 100 connects D0 / 2 to the internal circuit of the logic circuit 10; D0 / 3, D0 / 4, D0 / 1 are connected to the ② first signal selection circuit 100, and the ② first signal selection circuit 100 connects D0 / 3 to the internal circuit of the logic circuit 10; D0 / 4, D0 / 1, D0 / 0 are connected to the ③ first signal selection circuit 100, and the ③ first signal selection circuit 100 connects D0 / 3 to the internal circuit of the logic circuit 10, and D0 / 1, D0 / 0, D0 / 5 are connected to the ④ first signal The fourth signal selection circuit 100 connects D0 / 1 to the internal circuit of the logic circuit 10. If D0 / 2 is damaged, the first signal selection circuit 100 connects D0 / 3 to the internal circuit of the logic circuit 10, meaning that the signal originally transmitted by D0 / 2 will be transmitted by D0 / 3 instead. Simultaneously, the second signal selection circuit 100 connects D0 / 4 to the internal circuit of the logic circuit 10, meaning that the signal originally transmitted by D0 / 3 will be transmitted by D0 / 4 instead. The third signal selection circuit 100 connects D0 / 1 to the internal circuit of the logic circuit 10, meaning that the signal originally transmitted by D0 / 4 will be transmitted by D0 / 1 instead. Simultaneously, the fourth signal selection circuit 100 connects D0 / 0 to the internal circuit of the logic circuit 10, meaning that the signal originally transmitted by D0 / 4 will be transmitted by D0 / 0 instead. Please refer to this for understanding the remaining repair units.

[0122] Similarly, FIG. 8A to FIG. 8D are only examples of preset switching directions; the preset switching directions also have very flexible selection.

[0123] It should also be noted that, in the aforementioned examples, in each signal area, conductive through-hole group 0, conductive through-hole group 1, and conductive through-hole group 2 are aligned along the first direction; conductive through-hole group 3, conductive through-hole group 4, and conductive through-hole group 5 are aligned along the first direction, conductive through-hole group 2 and conductive through-hole group 3 are aligned along the second direction, conductive through-hole group 1 and conductive through-hole group 4 are aligned along the second direction, and conductive through-hole group 0 and conductive through-hole group 5 are aligned along the second direction, but this is only an example, and through-hole group 1 to through-hole group 5 can be located at any position in the same signal area.

[0124] In this way, the conductive through-hole positions and preset switching directions of different repair units maintain the above-mentioned symmetrical relationship, so that the chip stacking structure formed subsequently can realize signal rotation transmission through a direct connection configuration. Please refer to the subsequent instructions for details.

[0125] It should be noted that, for the same logic chip, it may adopt the repair unit shown in FIG5 , or the repair unit shown in FIG7 , or adopt both the repair units shown in FIG5 and FIG7 at the same time, or include more types of repair units.

[0126] It should also be noted that the conductive vias mentioned above can at least be embodied as through silicon vias (TSVs), specifically a vertical interconnect structure that penetrates the silicon wafer / memory chip, such as type 1 in Figure 1. Of course, the conductive vias can also be type 2 in Figure 1, which together with the contact structure realize signal transmission. In other embodiments, other electrical connection structures can also be selected as the conductive vias.

[0127] Conductive vias can be fabricated using one or more of the following processes: via-first, via-mid, via-last, and via-back. A via-first process involves fabricating the via structure before manufacturing the device structure, such as a metal oxide semiconductor field effect transistor (MOSFET). A via-mid process involves forming the via structure during the manufacturing process, often after the device is formed but before the stack is fabricated. A via-last process involves forming the via from the front side of the wafer after the back-end of line (BEOL) processing is complete. A via-back process involves forming the via structure from the back side of the wafer after the BEOL processing is complete. In other words, a via-first process can involve fabricating the via first, followed by the circuit; a via-mid process can involve fabricating the circuit and some metal layers first, then the via, and finally the remaining via. Both a via-last and via-back process involve fabricating the circuit and metal layers first, followed by the via.

[0128] In summary, the embodiments of the present disclosure provide a logic chip, in which the repair unit group, normal conductive through-holes, and preset switching directions in each channel signal area have special symmetry, which can be directly applied to a face-to-face stacking structure without the need for two sets of masks or two sets of through-holes; the chip stacking structure formed by the logic chip and the memory chip (which also has this feature) can achieve a signal rotation transmission effect through the direct connection configuration of the conductive through-holes, and the parasitic resistance and parasitic capacitance are relatively small; at the same time, through the symmetrically arranged repair units, the redundant repair function of the above structure can be realized, thereby improving the stability of the memory chip.

[0129] In another embodiment of the present disclosure, see FIG9 , which shows a schematic structural diagram of a memory chip 30 provided by an embodiment of the present disclosure, which can be specifically understood as a cross-sectional diagram of the active surface. As shown in FIG9 , the memory chip 30 includes m channels ( FIG3 is illustrated using m=4 as an example), the m channels are arranged sequentially along the first direction, the memory chip 30 has a chip axis YY' extending along the second direction and passing through the center of the memory chip, and the m channels are symmetrical about the chip axis YY'; each channel includes a first memory array area, a channel signal area, and a second memory array area sequentially distributed along the second direction, and the center of each channel signal area coincides with the center of the corresponding channel. Here, the area of ​​the channel signal area in the logic chip 10 is the same as the area of ​​the channel signal area in the memory chip 30. In particular, the area of ​​the active surface of the logic chip 10 and the area of ​​the active surface of the memory chip 30 may be the same, or the area of ​​the active surface of the logic chip 10 may be larger than the area of ​​the active surface of the memory chip 30.

[0130] It should be noted that during the chip manufacturing process, in order to distinguish different channels of the chip, a positioning structure can be made in the reference channel (for example, the first channel) of the storage chip 30, so that during subsequent packaging, the position of the reference channel can be identified through the positioning structure, and other channels can be identified in combination with the active surface orientation of the chip.

[0131] Figure 9 uses m=4 as an example, and the following description also uses m=4 as an example, but m can be any positive integer. Specifically, if m is an even number, then m / 2 channels are located on one side of the global signal area along the first direction, and the remaining m / 2 channels are located on the other side of the global signal area along the first direction; if m is an odd number, then the (m+1) / 2th channel needs to be divided into two parts and located on both sides of the global signal area along the first direction, while the remaining (m-1) / 2 channels are located on one side of the global signal area along the first direction, and the remaining (m-1) / 2 channels are located on the other side of the global signal area along the first direction.

[0132] Figure 9 can be viewed as a cross-sectional view of the active surface of memory chip 30. As shown in Figure 9, the center of the active surface of memory chip 30 and its adjacent area are defined as the global signal area. Here, the first channel, second channel, global signal area, third channel, and fourth channel are sequentially distributed along a first direction. The signals transmitted by the global signal area are shared by all m channels of the memory chip; whereas the signals transmitted by each channel signal area are used only by the corresponding channel.

[0133] Please refer to Figure 10A, which specifically shows a schematic diagram of the channel signal area 11 of the first channel, the channel signal area 12 of the second channel, the channel signal area 13 of the third channel, and the channel signal area 14 of the fourth channel. Figure 10A omits the global signal area.

[0134] As shown in Figure 10A , each channel signal region has a first axis AA' and a second axis BB'. The first axis AA' extends along the first direction or the second direction, and the second axis BB' is perpendicular to the first axis AA' and intersects at the center of the corresponding channel signal region. Figure 4A illustrates the example of the first axis AA' extending along the first direction. Other scenarios should be interpreted adaptively.

[0135] Due to limited space, the subsequent figures only use one channel signal area as an example to illustrate the composition and principle of the repair unit group, but in fact, the structure of all channel signal areas is the same, that is, the channel signal area in the figures can be understood as any one of channel signal area 11, channel signal area 12, channel signal area 13, and channel signal area 14.

[0136] Referring to FIG. 10A , each channel signal region includes a first axis AA' and a second axis BB'. The first axis AA' is parallel to the first side of the memory chip, and the first axis AA' and the second axis BB' intersect perpendicularly at the center point of the corresponding channel signal region. In FIG. 11 , the first axis AA' extends along a first direction, and the second axis BB' extends along a second direction. However, this is merely an example and does not constitute a specific limitation. As shown in FIG. 10A , each channel signal region is penetrated by a plurality of conductive vias along a third direction. The first and second directions are parallel to the top surface of the memory chip 30, and the third direction is perpendicular to the top surface of the memory chip 30.

[0137] The memory chip 30 also has a structure similar to the repair unit in the aforementioned logic chip 10, which is described in detail as follows.

[0138] Please refer to Figure 10B. For each channel signal area, the multiple conductive through-holes therein are divided into multiple repair unit groups; each repair unit group includes a first repair unit, a second repair unit, a third repair unit and a fourth repair unit; the first repair unit and the second repair unit are symmetrical along the first axis AA' of the channel signal area to which they belong, the third repair unit and the fourth repair unit are symmetrical along the first axis AA' of the channel signal area to which they belong, and the first repair unit and the fourth repair unit are symmetrical along the second axis BB' of the channel signal area to which they belong.

[0139] Each repair unit includes at least one redundant conductive via and at least one normal conductive via. When any normal conductive via is damaged, the effective signal transmitted by the normal conductive via is switched to the next conductive via in the same repair unit along the preset signal switching direction; the normal conductive vias in the first repair unit and the normal conductive vias in the second repair unit correspond one-to-one and are symmetrical along the first axis AA' of the channel signal area to which they belong, the normal conductive vias in the third repair unit and the normal conductive vias in the fourth repair unit correspond one-to-one and are symmetrical along the first axis AA' of the channel signal area to which they belong, and the normal conductive vias in the first repair unit and the normal conductive vias in the fourth repair unit correspond one-to-one and are symmetrical along the second axis BB' of the channel signal area to which they belong.

[0140] Specifically, for logic chip 10, the normal conductive vias in each repair unit are electrically connected to the internal circuitry of logic chip 10. In other words, referring to Figures 6A-6D and 8A-8D, each repair unit is connected to a corresponding signal selection circuit 100, and any conductive via therein, when selected as a normal conductive via, is electrically connected to the interior of the logic chip.

[0141] However, for memory chip 30, only the conductive vias in the first repair unit are electrically connected to the internal circuitry of memory chip 30 when used to transmit valid signals. That is, only the conductive vias in the first repair unit are electrically connected to the internal circuitry of memory chip 30 when they are normal. For example, referring to subsequent Figures 12A to 12D or 14A to 14D, only the first repair unit is connected to the corresponding signal selection circuit 100, so that the conductive vias in the first repair unit are electrically connected to the interior of the logic chip when selected as normal conductive vias. All the conductive vias in the remaining second to fourth repair units are completely independent of the internal circuitry of memory chip 30 and will not be electrically connected to the interior of memory chip 30 even if they are selected as normal conductive vias.

[0142] In the embodiment of the present disclosure, for each repair unit group, the preset switching direction of the conductive via in the first repair unit and the preset switching direction of the conductive via in the second repair unit are symmetrical along the first axis AA' of the channel signal area to which they belong; the preset switching direction of the conductive via in the third repair unit and the preset switching direction of the conductive via in the fourth repair unit are symmetrical along the first axis AA' of the channel signal area to which they belong; the preset switching direction of the conductive via in the first repair unit and the preset switching direction of the conductive via in the fourth repair unit are symmetrical along the second axis BB' of the channel signal area to which they belong; the preset switching direction of the conductive via in the second repair unit and the preset switching direction of the conductive via in the third repair unit are symmetrical along the second axis BB' of the channel signal area to which they belong.

[0143] In some embodiments, referring to FIG10A , each channel signal area is divided into 2×2 signal areas, and the conductive through-holes in each signal area are divided into n conductive through-hole groups with the same distribution position, where n is a positive integer, and the conductive through-hole groups in the first signal area 21 and the conductive through-hole groups in the second signal area 22 correspond one-to-one and are symmetrical along the first axis AA', the conductive through-hole groups in the third signal area 23 and the conductive through-hole groups in the fourth signal area 24 correspond one-to-one and are symmetrical along the first axis AA', and the conductive through-hole groups in the first signal area 21 and the conductive through-hole groups in the fourth signal area 24 correspond one-to-one and are symmetrical along the second axis BB'; each conductive through-hole group includes a first conductive through-hole, a second conductive through-hole D1, a third conductive through-hole D2, and a fourth conductive through-hole D3 distributed in a 2×2 array.

[0144] The conductive vias in each signal area have the following characteristics:

[0145] (1) In the same channel signal region, the first conductive via in a conductive via group in the first signal region 21, the second conductive via D1 in the corresponding conductive via group in the second signal region 22, the third conductive via D2 in the corresponding conductive via group in the third signal region 23, and the fourth conductive via D3 in the corresponding conductive via group in the fourth signal region 24 constitute a whole which is symmetrical along the first axis AA' and symmetrical along the second axis BB';

[0146] (2) In the same channel signal region, the whole formed by the second conductive through hole D1 in a conductive through hole group in the first signal region 21, the first conductive through hole in the corresponding conductive through hole group in the second signal region 22, the fourth conductive through hole D3 in the corresponding conductive through hole group in the third signal region 23, and the third conductive through hole D2 in the corresponding conductive through hole group in the fourth signal region 24 is symmetrical along the first axis AA' and symmetrical along the second axis BB';

[0147] (3) In the same channel signal area, the entirety formed by the third conductive through hole D2 in a conductive through hole group in the first signal area 21, the fourth conductive through hole D3 in the corresponding conductive through hole group in the second signal area 22, the first conductive through hole in the corresponding conductive through hole group in the third signal area 23, and the second conductive through hole D1 in the corresponding conductive through hole group in the fourth signal area 24 is symmetrical along the first axis AA' and symmetrical along the second axis BB';

[0148] (4) In the same channel signal area, the whole formed by the fourth conductive through hole D3 in a conductive through hole group in the first signal area 21, the third conductive through hole D2 in the corresponding conductive through hole group in the second signal area 22, the second conductive through hole D1 in the corresponding conductive through hole group in the third signal area 23, and the first conductive through hole in the corresponding conductive through hole group in the fourth signal area 24 is symmetrical along the first axis AA' and symmetrical along the second axis BB'.

[0149] It should be understood that in FIG. 10A , the four conductive vias in each conductive via group are distributed in a 2×2 array, but in other embodiments, the four conductive vias in each conductive via group may be distributed arbitrarily, as long as the above symmetry principle is observed.

[0150] For better understanding, the subsequent figures only use one channel signal area as an example to illustrate the composition and principle of the repair unit group. In particular, all channel signal areas adopt exactly the same structure, that is, the channel signal area in the figures can be understood as any one of channel signal area 11, channel signal area 12, channel signal area 13, and channel signal area 14.

[0151] In some embodiments, the B conductive via groups in each signal area are referred to as a conductive via combination. The conductive via group b in the corresponding conductive via combinations in all signal areas is symmetrical along the first axis AA' and symmetrical along the second axis BB'. B is a positive integer less than or equal to n, and b is a natural number less than B.

[0152] The corresponding conductive via combination in each signal area of ​​the same channel signal area constitutes a total of 4 repair unit groups:

[0153] (1) For the first repair unit group, the first repair unit includes: the first conductive via D0 of each of all conductive via groups in the conductive via combination in the first signal area 21; the second repair unit includes: the second conductive via D1 of each of all conductive via groups in the conductive via combination in the second signal area 22; the third repair unit includes: the third conductive via D2 of each of all conductive via groups in the conductive via combination in the third signal area 23; the fourth repair unit includes: the fourth conductive via D3 of each of all conductive via groups in the conductive via combination in the fourth signal area 24;

[0154] (2) For the second repair unit group, the first repair unit includes: the first conductive via D0 of each of all conductive via groups in the conductive via combination in the second signal area 22; the second repair unit includes: the second conductive via D1 of each of all conductive via groups in the conductive via combination in the first signal area 21; the third repair unit includes: the third conductive via D2 of each of all conductive via groups in the conductive via combination in the fourth signal area 24; and the fourth repair unit includes: the fourth conductive via D3 of each of all conductive via groups in the conductive via combination in the third signal area 23;

[0155] (3) For the third repair unit group, the first repair unit includes: the first conductive via D0 of each of all conductive via groups in the conductive via combination in the third signal area 23; the second repair unit includes: the second conductive via D1 of each of all conductive via groups in the conductive via combination in the fourth signal area 24; the third repair unit includes: the third conductive via D2 of each of all conductive via groups in the conductive via combination in the first signal area 21; the fourth repair unit includes: the fourth conductive via D3 of each of all conductive via groups in the conductive via combination in the second signal area 22;

[0156] (4) For the fourth repair unit group, the first repair unit includes: the first conductive through hole D0 of each of all conductive through hole groups in the conductive through hole combination in the fourth signal area 24; the second repair unit includes: the second conductive through hole D1 of each of all conductive through hole groups in the conductive through hole combination in the third signal area 23; the fourth repair unit includes: the third conductive through hole D2 of each of all conductive through hole groups in the conductive through hole combination in the second signal area 22; and the fourth repair unit includes: the fourth conductive through hole D3 of each of all conductive through hole groups in the conductive through hole combination in the first signal area 21.

[0157] It should be noted that for the same logic chip 10, B can have multiple values. For example, the same logic chip 10 may have a conductive via combination consisting of four conductive via groups, a conductive via combination consisting of six conductive via groups, or even more. However, regardless of the number of conductive via groups, each conductive via combination must form four repair unit groups.

[0158] In the first specific embodiment, see FIG11 , B=3, and b is 0, 1, or 2. At this time, conductive via group 0 to conductive via group 2 in each signal area of ​​the same channel signal area constitute a total of 4 repair unit groups:

[0159] Please refer to FIG12A , for the first repair unit group_1: (1) the first repair unit_1 includes: the first conductive vias of conductive via group 0, conductive via group 1, and conductive via group 2 in the first signal area 21, i.e., D0 / 0, D0 / 1, and D0 / 2 in the first signal area 21; (2) the second repair unit_1 includes: the second conductive vias of conductive via group 0, conductive via group 1, and conductive via group 2 in the second signal area 22, i.e., D1 / 0 in the second signal area 22. , D1 / 1, D1 / 2; (3) the third repair unit_1 includes: the third conductive through holes of conductive through hole group 0, conductive through hole group 1, and conductive through hole group 2 in the third signal area 23, that is, D2 / 0, D2 / 1, and D2 / 2 in the third signal area 23; (4) the fourth repair unit_1 includes: the fourth conductive through holes of conductive through hole group 0, conductive through hole group 1, and conductive through hole group 2 in the fourth signal area 24, that is, D3 / 0, D3 / 1, and D3 / 2 in the fourth signal area 24.

[0160] Please refer to FIG12B . For the second repair unit group_2, (1) the first repair unit_2 includes: the first conductive vias of conductive via group 0, conductive via group 1, and conductive via group 2 in the second signal area 22, i.e., D0 / 0, D0 / 1, and D0 / 2 in the second signal area 22; (2) the second repair unit_2 includes: the second conductive vias of conductive via group 0, conductive via group 1, and conductive via group 2 in the first signal area 21, i.e., D1 / 0 in the first signal area 21. , D1 / 1, D1 / 2; (3) the third repair unit_2 includes: the third conductive through holes of conductive through hole group 0, conductive through hole group 1, and conductive through hole group 2 in the fourth signal area 24, that is, D2 / 0, D2 / 1, and D2 / 2 in the fourth signal area 24; (4) the fourth repair unit_2 includes: the fourth conductive through holes of conductive through hole group 0, conductive through hole group 1, and conductive through hole group 2 in the third signal area 23, that is, D3 / 0, D3 / 1, and D3 / 2 in the third signal area 23.

[0161] Please refer to FIG12C . For the third repair unit group_3, (1) the first repair unit_3 includes: the first conductive vias of each of the conductive via group 0, conductive via group 1, and conductive via group 2 in the third signal area 23, i.e., D0 / 0, D0 / 1, and D0 / 2 in the third signal area 23; (2) the second repair unit_3 includes: the second conductive vias of each of the conductive via group 0, conductive via group 1, and conductive via group 2 in the fourth signal area 24, i.e., D1 / 0 in the fourth signal area 24. , D1 / 1, D1 / 2; (3) the third repair unit_3 includes: the third conductive through holes of conductive through hole group 0, conductive through hole group 1, and conductive through hole group 2 in the first signal area 21, that is, D2 / 0, D2 / 1, and D2 / 2 in the first signal area 21; (4) the fourth repair unit_3 includes: the fourth conductive through holes of conductive through hole group 0, conductive through hole group 1, and conductive through hole group 2 in the second signal area 22, that is, D3 / 0, D3 / 1, and D3 / 2 in the second signal area 22.

[0162] Please refer to FIG12D . For the fourth repair unit group_4, (1) the first repair unit_4 includes: the first conductive vias of each of the conductive via group 0, the conductive via group 1, and the conductive via group 2 in the fourth signal area 24, i.e., D0 / 0, D0 / 1, and D0 / 2 in the fourth signal area 24; (2) the second repair unit_4 includes: the second conductive vias of each of the conductive via group 0, the conductive via group 1, and the conductive via group 2 in the third signal area 23, i.e., D2 / 0 in the third signal area 23. , D2 / 1, D2 / 2; (3) the third repair unit_4 includes: the third conductive through holes of conductive through hole group 0, conductive through hole group 1, and conductive through hole group 2 in the second signal area 22, that is, D2 / 0, D2 / 1, and D2 / 2 in the second signal area 22; (4) the fourth repair unit_4 includes: the fourth conductive through holes of conductive through hole group 0, conductive through hole group 1, and conductive through hole group 2 in the first signal area 21, that is, D3 / 0, D3 / 1, and D3 / 2 in the first signal area 21.

[0163] The following provides an example of a preset switching direction to facilitate a better understanding of the above description, but the following example is not the only solution.

[0164] In some embodiments, see FIG11 , all conductive vias in conductive via group 0 are normal conductive vias. As previously mentioned, only the normal conductive vias in the first repair unit are connected to the interior of the memory chip. Therefore, the preset switching direction of the conductive vias in any first repair unit is: the first conductive via in conductive via group 0 is allowed to switch to the first conductive via in conductive via group 1 in the same signal region, and the first conductive via in conductive via group 1 is allowed to switch to the first conductive via in conductive via group 2 in the same signal region.

[0165] That is to say, please refer to Figure 12A, for the first repair unit group, the preset switching direction of the conductive through hole in the first repair unit_1 is: D0 / 0-D0 / 1-D0 / 2 in the first signal area 21; please refer to Figure 12B, for the second repair unit group, the preset switching direction of the conductive through hole in the first repair unit_2 is: D0 / 0-D0 / 1-D0 / 2 in the second signal area 22; please refer to Figure 12C, for the third repair unit group, the preset switching direction of the conductive through hole in the first repair unit_3 is: D0 / 0-D0 / 1-D0 / 2 in the third signal area 23; please refer to Figure 12D, for the fourth repair unit group, the preset switching direction of the conductive through hole in the first repair unit_4 is: D0 / 0-D0 / 1-D0 / 2 in the fourth signal area 24.

[0166] For ease of understanding, a specific description of a signal switching related circuit is provided below using a repair ratio of normal conductive vias to redundant conductive vias = 2:1 as an example.

[0167] In order to realize the above-mentioned switching process, please refer to Figures 12A to 12D. The memory chip 30 also includes a plurality of signal selection circuits 100 for realizing the switching of the above-mentioned conductive through holes. Taking the first repair unit_1 of the first repair unit group as an example, please refer to Figure 12A. D0 / 0 and D0 / 1 are connected to the first signal selection circuit 100, and the first signal selection circuit 100 connects D0 / 0 to the internal circuit of the logic circuit 10; D0 / 1 and D0 / 2 are connected to the second signal selection circuit 100, and the second signal selection circuit 100 connects D0 / 1 to the internal circuit of the logic circuit 10; then, if D0 / 0 is damaged, the first signal selection circuit 100 connects D0 / 1 to the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D0 / 0 will be transmitted by D0 / 1; at the same time, the second signal selection circuit 100 connects D0 / 2 to the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D0 / 1 will be transmitted by D0 / 2. However, for the second to fourth repair units, the signal selection circuit 100 is not set, and the conductive through holes therein, whether they are normal conductive through holes or redundant conductive through holes, are not connected to the memory chip 30. Therefore, the switching of the conductive through holes for transmitting signals in the repair unit of the memory chip is only carried out due to the switching of the conductive through holes for transmitting signals in the logic chip 10, which is actually imperceptible to the memory chip 30. Therefore, this embodiment only emphasizes the preset switching direction of the first repair unit.

[0168] Please refer to the rest of the repair units for understanding.

[0169] It should be noted that Figures 12A to 12D are only examples of the preset switching direction; the preset switching direction is actually very flexible. Taking the first repair unit_1 as an example, it can currently switch along D0 / 0, D0 / 1, and D0 / 2 in sequence, or it can switch along D0 / 2, D0 / 1, and D0 / 0, or use D0 / 1 as the switching starting point, and so on.

[0170] In this way, the conductive through-hole positions and preset switching directions of different repair units maintain the above-mentioned symmetrical relationship to ensure that the chip stacking structure formed subsequently can realize signal rotation transmission through a direct connection configuration. Please refer to the subsequent instructions for details.

[0171] In the second specific embodiment, see FIG13 , B=6, and b is 0, 1, 2, 3, 4, or 5. At this time, conductive via group 0 to conductive via group 5 in each signal area of ​​the same channel signal area constitute a total of 4 repair unit groups:

[0172] Please refer to FIG14A , for the first repair unit group_A: (1) the first repair unit_A includes: the first conductive vias of each of the conductive via group 0 to the conductive via group 5 in the first signal area 21, i.e., D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, and D0 / 5 in the first signal area 21; (2) the second repair unit_A includes: the second conductive vias of each of the conductive via group 0 to the conductive via group 5 in the second signal area 22, i.e., D1 / 0, D1 / 1, D1 / 2, D1 / 3, D1 / 4, and D1 / 5 in the second signal area 22. 1 / 4, D1 / 5; (3) the third repair unit _A includes: the third conductive through holes of each of the conductive through hole group 0 to the conductive through hole group 5 in the third signal area 23, that is, D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, D2 / 5 in the third signal area 23; (4) the fourth repair unit _A includes: the fourth conductive through holes of each of the conductive through hole group 0 to the conductive through hole group 5 in the fourth signal area 24, that is, D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, D3 / 5 in the fourth signal area 24.

[0173] Please refer to FIG14B . For the second repair unit group_B, (1) the first repair unit_B includes: the first conductive vias of each of the conductive via group 0 to the conductive via group 5 in the second signal area 22, i.e., D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, and D0 / 5 in the second signal area 22, i.e., D1 / 0, D1 / 1, D1 / 2, D1 / 3, D1 / 4, and D1 / 5 in the second signal area 22; (2) the second repair unit_B includes: the second conductive vias of each of the conductive via group 0 to the conductive via group 5 in the first signal area 21, i.e., (3) the third repair unit _B includes: the third conductive through holes of each of the conductive through hole group 0 to the conductive through hole group 5 in the fourth signal area, that is, D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, D2 / 5 in the fourth signal area 24; (4) the fourth repair unit _B includes: the fourth conductive through holes of each of the conductive through hole group 0 to the conductive through hole group 5 in the third signal area 23, that is, D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, D3 / 5 in the third signal area 23.

[0174] Please refer to FIG14C , for the third repair unit group_C, the first repair unit_C includes: the first conductive vias of each of the conductive via group 0 to the conductive via group 5 in the third signal area 23, i.e., D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, and D0 / 5 in the third signal area 23; (2) the second repair unit_C includes: the second conductive vias of each of the conductive via group 0 to the conductive via group 5 in the fourth signal area 24, i.e., D1 / 0, D1 / 1, D1 / 2, D1 / 3, D1 / 4, and D1 / 5 in the fourth signal area 24. 1 / 4, D1 / 5; (3) the third repair unit _C includes: the third conductive through holes of each of the conductive through hole group 0 to the conductive through hole group 5 in the first signal area 21, that is, D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, D2 / 5 in the first signal area 21; (4) the fourth repair unit _C includes: the fourth conductive through holes of each of the conductive through hole group 0 to the conductive through hole group 5 in the second signal area 22, that is, D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, D3 / 5 in the second signal area 22.

[0175] Please refer to FIG14D , for the fourth repair unit group_D, the first repair unit includes: the first conductive vias of each of the conductive via group 0 to the conductive via group 5 in the fourth signal area 24, that is, D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, and D0 / 5 in the fourth signal area 24; (2) the second repair unit_D includes: the second conductive vias of each of the conductive via group 0 to the conductive via group 5 in the third signal area 23, that is, D1 / 0, D1 / 1, D1 / 2, D1 / 3, D1 / 4, D1 / 5; (3) the fourth repair unit _D includes: the third conductive through holes of each of the conductive through hole group 0 to the conductive through hole group 5 in the second signal area 22, that is, D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, D2 / 5 in the second signal area 22; the fourth repair unit _D includes: the fourth conductive through holes of each of the conductive through hole group 0 to the conductive through hole group 5 in the first signal area 21, that is, D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, D3 / 5 in the first signal area 21.

[0176] The following provides an example of a preset switching direction to facilitate a better understanding of the above description, but the following example is not the only solution.

[0177] Assuming that the conductive through holes in the conductive through hole group 0 of all signal areas are normal conductive through holes, please refer to Figures 14A to 14D. The preset switching direction of the conductive through holes in the first repair unit is: the first conductive through hole in the conductive through hole group 2 is allowed to switch to the first conductive through hole in the conductive through hole group 3 in the same signal area, the first conductive through hole in the conductive through hole group 3 is allowed to switch to the first conductive through hole in the conductive through hole group 4 in the same signal area, and the first conductive through hole in the conductive through hole group 4 is allowed to switch to the first conductive through hole in the conductive through hole group 1 in the same signal area; the first conductive through hole in the conductive through hole group 1 is allowed to switch to the first conductive through hole in the conductive through hole group 0 in the same signal area; the first conductive through hole in the conductive through hole group 0 is allowed to switch to the first conductive through hole in the conductive through hole group 5 in the same signal area.

[0178] That is to say, please refer to Figure 14A, the preset switching direction of the conductive through-hole in the first repair unit_A is: D0 / 2-D0 / 3-D0 / 4-D0 / 1-D0 / 0-D0 / 5 in the first signal area 21; please refer to Figure 14B, the preset switching direction of the conductive through-hole in the first repair unit_B is: D0 / 2-D0 / 3-D0 / 4-D0 / 1-D0 / 0-D0 / 5 in the second signal area 22; please refer to Figure 14C, the preset switching direction of the conductive through-hole in the first repair unit_C is: D0 / 2-D0 / 3-D0 / 4-D0 / 1-D0 / 0-D0 / 5 in the third signal area 23; please refer to Figure 14D, the preset switching direction of the conductive through-hole in the first repair unit_D is: D0 / 2-D0 / 3-D0 / 4-D0 / 1-D0 / 0-D0 / 5 in the fourth signal area 24.

[0179] The following provides a specific description of the signal switching related circuits, taking the repair ratio of normal conductive vias to redundant conductive vias = 4:2 as an example. Taking the first repair unit_A of the first repair unit group as an example, see Figure 14A, D0 / 2, D0 / 3, and D0 / 4 are connected to the ① signal selection circuit 100, and the ① signal selection circuit 100 connects D0 / 2 to the internal circuit of the logic circuit 10; D0 / 3, D0 / 4, and D0 / 1 are connected to the ② signal selection circuit 100, and the ② signal selection circuit 100 connects D0 / 3 to the internal circuit of the logic circuit 10; D0 / 4, D0 / 1, and D0 / 0 are connected to the ③ signal selection circuit 100, and the ③ signal selection circuit 100 connects D0 / 3 to the internal circuit of the logic circuit 10, and D0 / 1, D0 / 0, and D0 / 5 are connected to the ④ signal selection circuit 100, and the ④ signal selection circuit 100 connects D0 / 1 to the internal circuit of logic circuit 10. If D0 / 2 is damaged, the first signal selection circuit 100 connects D0 / 3 to the internal circuit of logic circuit 10, meaning that the signal originally transmitted by D0 / 2 will be transmitted by D0 / 3 instead. Simultaneously, the second signal selection circuit 100 connects D0 / 4 to the internal circuit of logic circuit 10, meaning that the signal originally transmitted by D0 / 3 will be transmitted by D0 / 4 instead. The third signal selection circuit 100 connects D0 / 1 to the internal circuit of logic circuit 10, meaning that the signal originally transmitted by D0 / 4 will be transmitted by D0 / 1 instead. Simultaneously, the fourth signal selection circuit 100 connects D0 / 0 to the internal circuit of logic circuit 10, meaning that the signal originally transmitted by D0 / 4 will be transmitted by D0 / 0 instead. Please refer to the rest of the repair units for further details.

[0180] Similarly, for the memory chip 30, only the conductive vias in the first repair unit (i.e., the conductive vias filled with pure white patterns) are connected to the corresponding signal selection circuit 100; similarly, for the second to fourth repair units, no matter whether the conductive vias therein are normal conductive vias or redundant conductive vias, they are not connected to the memory chip 30. Therefore, the switching of the conductive vias for transmitting signals in the repair unit of the memory chip is only due to the switching of the conductive vias for transmitting signals in the logic chip 10, which is actually imperceptible to the memory chip 30. Therefore, this embodiment only emphasizes the preset switching direction of the first repair unit.

[0181] An embodiment of the present disclosure provides a memory chip 30, wherein the conductive through-holes in each channel signal area are symmetrical about the first axis AA' and about the second axis BB', and the switching direction of the repair unit further composed of the conductive through-holes also follows the principle of symmetry. When the above memory chip forms a chip stacking structure, it not only has smaller parasitic capacitance and parasitic resistance, but also realizes a face-to-face stacking method; at the same time, the embodiment of the present disclosure also provides a related mechanism for redundant repair under this structure.

[0182] In another embodiment of the present disclosure, see FIG15 , which illustrates a schematic diagram of the composition of a chip stacking structure 40 provided in an embodiment of the present disclosure. As shown in FIG15 , the chip stacking structure 40 includes the aforementioned logic chip 10 and at least one stacking unit, wherein the logic chip 10 and the at least one stacking unit are stacked sequentially along a third direction. Each stacking unit includes a first memory chip 31, a second memory chip 32, a third memory chip 33, and a fourth memory chip 34 stacked along the third direction. The logic chip 10, and the structures of the first memory chip 31, the second memory chip 32, the third memory chip 33, and the fourth memory chip 34 are all the aforementioned memory chips 30. The third direction is perpendicular to the top surface of each chip.

[0183] For each stacking unit, the first memory chip 31 and the second memory chip 32 are stacked face to face, the second memory chip 32 and the third memory chip 33 are stacked back to back, and the third memory chip 33 and the fourth memory chip 34 are stacked face to face; the first memory chip 31 and the logic chip 10 in the first stacking unit are stacked back to back, or the first memory chip 31 and the logic chip 10 in the first stacking unit are stacked back to back.

[0184] In the embodiments of the present disclosure, face-to-face stacking means that the top surfaces of the two chips are approximately aligned along the third direction, and the center points, first axis AA', and second axis BB' of the top surfaces of the two chips are all aligned along the third direction. Back-to-back stacking means that the top surfaces of the two chips are approximately aligned along the third direction. Back-to-back stacking means that the top surface of one chip is approximately aligned with the bottom surface of the other chip along the third direction. When logic chip or memory chip is not specified, "chip" can refer to both logic chip and memory chip.

[0185] It should be noted that, in one possibility, for two chips connected face to face, the bonding surfaces of the two chips (the positions where the conductive vias are aligned along the third direction) are electrically connected through a hybrid bonding structure (Hyperbonding, also known as bonding columns); for two chips connected back to back or back to face, the bonding surfaces of the two chips (the positions where the conductive vias are aligned along the third direction) are electrically connected through conductive bumps (UBumps, also known as microbumps).

[0186] In another possibility, for two chips connected face to face or for two chips connected back to back or for two chips connected back to face, both bonding surfaces (positions where conductive vias are aligned along the third direction) are connected through a hybrid bonding structure.

[0187] In another possibility, for two chips connected face to face or for two chips connected back to back or for back to face connection, both bonding surfaces (where the conductive vias are aligned along the third direction) are connected via conductive bumps.

[0188] Here, the above chip may refer to a logic chip 10 or a memory chip 30 .

[0189] It should be noted that compared to the conductive bump process, the face-to-face connection using the hybrid bonding process can make the adjacent memory chips fit more closely, with essentially no gaps, thereby significantly reducing the height of the chip stacking structure. This is also one of the advantages of face-to-face stacking. Of course, two memory chips connected back to back can also be connected using a hybrid bonding structure, but its connection performance is weaker than when connected using the conductive bump process. Thus, in the disclosed embodiment, the chip stacking structure supports face-to-face stacking and has better performance.

[0190] As mentioned above, the logic chip 10 and each memory chip have n repair unit groups, and the n repair unit groups in the logic chip 10, the n repair unit groups in each first memory chip 31, the n repair unit groups in each second memory chip 32, the n repair unit groups in each third memory chip 33, and the n repair unit groups in each fourth memory chip 34 correspond one to one and are aligned along the third direction, so that when a conductive through hole is damaged, the logic chip 10 and each memory chip 0 will synchronously perform signal switching operations.

[0191] In some embodiments, the logic chip 10 includes m channel signal areas arranged along a first direction, each memory chip has m channels arranged along the first direction, and each channel includes a first memory array area, a channel signal area, and a second memory array area distributed in sequence along a second direction; the first direction, the second direction, and the third direction are perpendicular to each other, and the first direction and the second direction are parallel to the top surface of each chip.

[0192] In particular, two second directions are shown in FIG15 . This is because, for the sake of clarity, the perspective angles of two adjacent chips are different, and thus each chip corresponds to a second direction.

[0193] It should be understood that the logic chip 10 or each memory chip can be divided into a high-bit transmission region and a low-bit transmission region. The arrows in the subsequent figures are all directed to the high-bit transmission region of the chip. In particular, the high-bit transmission region and the low-bit transmission region in the disclosed embodiments merely distinguish two regions of the memory chip and do not impose any additional limitations. They have no relation to the high-bit data and low-bit data commonly used in data transmission.

[0194] In the first specific embodiment, referring to FIG17A , when the logic chip 10 and the first memory chip 31 are stacked back to back, and the first axis AA' of the logic chip 10 and each of the memory chips 30 extends along the first direction (i.e., the second axis AA' divides the corresponding chip into a high-order transmission area and a low-order transmission area), the high-order transmission area of ​​the logic chip 10, the high-order transmission area of ​​the first memory chip 31, the low-order transmission area of ​​the second memory chip 32, the low-order transmission area of ​​the third memory chip 33, and the high-order transmission area of ​​the fourth memory chip 34 are aligned along the third direction; the low-order transmission area of ​​the logic chip 10, the low-order transmission area of ​​the first memory chip 31, the high-order transmission area of ​​the second memory chip 32, the high-order transmission area of ​​the third memory chip 33, and the low-order transmission area of ​​the fourth memory chip 34 are aligned along the third direction.

[0195] The channel signal areas of each chip have the following alignment relationship: the mi-th channel signal area in the logic chip 10 is aligned along the third direction with the channel signal area in the i+1-th channel in the first memory chip 31, the channel signal area in the i+1-th channel in the second memory chip 32, the channel signal area in the mi-th channel in the third memory chip 33, and the channel signal area in the mi-th channel in the fourth memory chip 34; where i is a natural number less than m.

[0196] FIG17A shows an example of m=4. In this case:

[0197] (1) the fourth channel signal region 14 in the logic chip 10 and the channel signal region 11 in the first channel of the first memory chip 31 are aligned along the third direction, the channel signal region 11 in the first channel of the second memory chip 32 is aligned along the third direction, the channel signal region 14 in the fourth channel of the third memory chip 33 is aligned along the third direction, and the channel signal region 14 in the fourth channel of the fourth memory chip 34 is aligned along the third direction;

[0198] (2) the third channel signal region 13 in the logic chip 10 and the channel signal region 12 in the second channel of the first memory chip 31 are aligned along the third direction, the channel signal region 12 in the second channel of the second memory chip 32 is aligned along the third direction, the channel signal region 13 in the third channel of the third memory chip 33 is aligned along the third direction, and the channel signal region 13 in the third channel of the fourth memory chip 34 is aligned along the third direction;

[0199] (3) the second channel signal region 12 in the logic chip 10 and the channel signal region 13 in the third channel of the first memory chip 31 are aligned along the third direction, the channel signal region 13 in the third channel of the second memory chip 32 is aligned along the third direction, the channel signal region 12 in the second channel of the third memory chip 33 is aligned along the third direction, and the channel signal region 12 in the second channel of the fourth memory chip 34 is aligned along the third direction;

[0200] (4) The first channel signal region 11 in the logic chip 10 and the channel signal region 14 in the fourth channel in the first memory chip 31 are aligned along the third direction, the channel signal region 14 in the fourth channel in the second memory chip 32 is aligned along the third direction, the channel signal region 11 in the first channel in the third memory chip 33 is aligned along the third direction, and the channel signal region 11 in the first channel in the fourth memory chip 34 is aligned along the third direction.

[0201] In a second specific embodiment, referring to FIG. 18A (illustrated using m=4 as an example), when the logic chip 10 and the first memory chip 31 are stacked back-to-back, and the second axis BB' of the logic chip 10 and each memory chip extends along the first direction (i.e., the second axis BB' divides the respective chips into a high-order transmission area and a low-order transmission area), the low-order transmission area of ​​the logic chip 10, the high-order transmission area of ​​the first memory chip 31, the high-order transmission area of ​​the second memory chip 32, the low-order transmission area of ​​the third memory chip 33, and the low-order transmission area of ​​the fourth memory chip 34 are aligned along the third direction; the high-order transmission area of ​​the logic chip 10, the low-order transmission area of ​​the first memory chip 31, the low-order transmission area of ​​the second memory chip 32, the high-order transmission area of ​​the third memory chip 33, and the high-order transmission area of ​​the fourth memory chip 34 are aligned along the third direction.

[0202] Specifically, the channel signal areas of each chip have the following symmetrical relationship: the i+1th channel signal area in the logic chip 10 is aligned along the third direction with the channel signal area in the i+1th channel of the first memory chip 31, the channel signal area in the mith channel of the second memory chip 32, the channel signal area in the mith channel of the third memory chip 33, and the channel signal area in the i+1th channel of the fourth memory chip 34; wherein i is a natural number less than m.

[0203] FIG18A shows an example of m=4. In this case:

[0204] (1) the first channel signal region 11 in the logic chip 10, the channel signal region 11 in the first channel of the first memory chip 31, the channel signal region 14 in the fourth channel of the second memory chip 32, the channel signal region 14 in the fourth channel of the third memory chip 33, and the channel signal region 11 in the first channel of the fourth memory chip 34 are aligned along a third direction;

[0205] (2) the second channel signal region 12 in the logic chip 10, the channel signal region 12 in the second channel of the first memory chip 31, the channel signal region 13 in the third channel of the second memory chip 32, and the channel signal region 13 in the third channel of the third memory chip 33 are aligned along a third direction, and the channel signal region 12 in the second channel of the fourth memory chip 34 is aligned along the third direction;

[0206] (3) the third channel signal region 13 in the logic chip 10, the channel signal region 13 in the third channel of the first memory chip 31, the channel signal region 12 in the second channel of the second memory chip 32, the channel signal region 12 in the second channel of the third memory chip 33, and the channel signal region 13 in the third channel of the fourth memory chip 34 are aligned along a third direction;

[0207] (4) The fourth channel signal region 14 in the logic chip 10, the channel signal region 14 in the fourth channel of the first memory chip 31, the channel signal region 11 in the first channel of the second memory chip 32, the channel signal region 11 in the first channel of the third memory chip 33, and the channel signal region 14 in the fourth channel of the fourth memory chip 34 are aligned along the third direction.

[0208] In short, with respect to FIG. 17A to FIG. 18B , the logic chip 10 and the fourth memory chip 34 are arranged in the same manner.

[0209] It should also be noted that the channel signal area in each channel of the memory chip 30 and the logic chip 31 is divided into a 2×2 signal area distributed in an array. Referring to FIG. 17B or FIG. 18B , the multiple channel signal areas aligned along the third direction have the following characteristics:

[0210] (1) The fourth signal area 24 of the logic chip 10, the first signal area 21 of the first memory chip 31, the second signal area 22 of the second memory chip 32, the third signal area 23 of the third memory chip 33, and the fourth signal area 24 of the fourth memory chip 34 are aligned along the third direction;

[0211] (2) The third signal area 23 of the logic chip 10, the second signal area 22 of the first memory chip 31, the first signal area 21 of the second memory chip 32, the fourth signal area 24 of the third memory chip 33, and the third signal area 23 of the fourth memory chip 34 are aligned along the third direction;

[0212] (3) The second signal area 22 of the logic chip 10, the third signal area 23 of the first memory chip 31, the fourth signal area 24 of the second memory chip 32, the first signal area 21 of the third memory chip 33, and the second signal area 22 of the fourth memory chip 34 are aligned along the third direction;

[0213] (4) The first signal area 21 belonging to the logic chip 10, the fourth signal area 24 belonging to the first memory chip 31, the third signal area 23 belonging to the second memory chip 32, the second signal area 22 belonging to the third memory chip 33, and the first signal area 21 belonging to the fourth memory chip 34 are aligned along the third direction.

[0214] In some embodiments, each signal region includes n conductive via groups with identical distribution positions. In each channel signal region, the conductive via regions of the first signal region and the conductive via groups of the second signal region correspond one-to-one and are symmetrical about the first axis. The conductive via regions of the third signal region and the conductive via groups of the fourth signal region correspond one-to-one and are symmetrical about the first axis. The conductive via regions of the first signal region and the conductive via groups of the fourth signal region correspond one-to-one and are symmetrical about the second axis. Furthermore, the conductive via groups in different channel signal regions correspond one-to-one and are identically distributed (relative to the center of their respective signal regions). Each conductive via group includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via.

[0215] Please refer to FIG. 17B or FIG. 18B for multiple signal areas aligned along the third direction:

[0216] (1) The fourth conductive via D3 of the logic chip 10, the first conductive via D0 of the first memory chip 31, the second conductive via D1 of the second memory chip 32, the third conductive via D2 of the third memory chip 33, and the fourth conductive via D3 of the fourth memory chip 34 are aligned along the third direction;

[0217] (2) The third conductive via D2 of the logic chip 10, the second conductive via D1 of the first memory chip 31, the first conductive via D0 of the second memory chip 32, the fourth conductive via D3 of the third memory chip 33, and the third conductive via D2 of the fourth memory chip 34 are aligned along the third direction;

[0218] (3) The second conductive via D1 of the logic chip 10, the third conductive via D2 of the first memory chip 31, the fourth conductive via D3 of the second memory chip 32, the first conductive via D0 of the third memory chip 33, and the second conductive via D1 of the fourth memory chip 34 are aligned along the third direction;

[0219] (4) The first conductive through hole D0 of the logic chip 10, the fourth conductive through hole D3 of the first memory chip 31, the third conductive through hole D2 of the second memory chip 32, the second conductive through hole D1 of the third memory chip 33, and the first conductive through hole D0 of the fourth memory chip 34 are aligned along a third direction; wherein the plurality of conductive through holes aligned along the third direction are coupled to form a signal transmission channel.

[0220] Referring to FIG. 16A , when stacking according to the first and second specific embodiments, the repair units of each chip have the following relationship:

[0221] (a) A fourth repair unit in the logic chip 10, a first repair unit in the first memory chip 31, a second repair unit in the second memory chip 32, a third repair unit in the third memory chip 33, and a fourth repair unit in the fourth memory chip 34 are aligned along a third direction and a conductive via switching operation is performed synchronously;

[0222] (b) A third repair unit in the logic chip 10, a second repair unit in the first memory chip 31, a first repair unit in the second memory chip 32, a fourth repair unit in the third memory chip 33, and a third repair unit in the fourth memory chip 34 are aligned along a third direction and the conductive via switching operation is performed synchronously;

[0223] (c) A second repair unit in the logic chip 10, a third repair unit in the first memory chip 31, a fourth repair unit in the second memory chip 32, a first repair unit in the third memory chip 33, and a second repair unit in the fourth memory chip 34 are aligned along a third direction and the conductive via switching operation is performed synchronously;

[0224] (d) A first repair unit in the logic chip 10, a fourth repair unit in the first memory chip 31, a third repair unit in the second memory chip 32, a second repair unit in the third memory chip 33, and a first repair unit in the fourth memory chip 34 are aligned along a third direction, and the conductive via switching operation is performed synchronously.

[0225] It should be noted that, for the logic chip 10, each repair unit therein is coupled to the internal circuit, that is, the normal conductive vias in each repair unit are electrically connected to the internal circuit of the logic chip 10; but for the memory chip, only the first repair unit is coupled to the internal circuit, that is, only the normal conductive vias in the first repair unit are electrically connected to the internal circuit of the memory chip, and all conductive vias in the second repair unit, the third repair unit and the fourth repair unit are isolated from the internal circuit of the logic chip 10.

[0226] Figure 17C illustrates a schematic diagram of the symmetry and switching direction of a repair unit group in logic chip 10, along with the first repair unit in each corresponding memory chip, using the division of the repair unit groups shown in Figures 5 and 11 and the stacking arrangement of the first specific embodiment as an example. Other repair units are omitted. That is, in Figure 17C , the first, second, third, and fourth repair units indicated by curved arrows in logic chip 10 are all coupled to the internal circuitry; however, for the memory chips, only the first repair unit indicated by the curved arrow is coupled to the internal circuitry.

[0227] The chip stacking structure formed by the repair unit groups in Figures 7 and 13 also has the above characteristics, please understand accordingly.

[0228] In this way, the repair units of the chip stack structure 40 are aligned along the third direction and have symmetrical switching directions, thereby achieving the same switching function.

[0229] In a third specific embodiment, referring to FIG. 19A (illustrated using m=4 as an example), when the logic chip 10 and the first memory chip 31 are stacked back to back, and the first axis AA' of the logic chip 10 and each memory chip extends along the first direction (i.e., the first axis AA' divides the corresponding chip into a high-order transmission area and a low-order transmission area), the low-order transmission area of ​​the logic chip 10, the high-order transmission area of ​​the first memory chip 31, the low-order transmission area of ​​the second memory chip 32, the low-order transmission area of ​​the third memory chip 33, and the high-order transmission area of ​​the fourth memory chip 34 are aligned along the third direction; the high-order transmission area of ​​the logic chip 10, the low-order transmission area of ​​the first memory chip 31, the high-order transmission area of ​​the second memory chip 32, the high-order transmission area of ​​the third memory chip 33, and the low-order transmission area of ​​the fourth memory chip 34 are aligned along the third direction.

[0230] Specifically, the channel signal areas of each chip have the following symmetrical relationship: the i+1th channel signal area in the logic chip 10 is aligned along the third direction with the channel signal area in the i+1th channel in the first memory chip 31, the channel signal area in the i+1th channel in the second memory chip 32, the channel signal area in the mi-th channel in the third memory chip 33, and the channel signal area in the mi-th channel in the fourth memory chip 34; where i is a natural number less than m.

[0231] FIG19A illustrates the diagram using m=4 as an example. In this case:

[0232] (1) the first channel signal region 11 in the logic chip 10, the channel signal region 11 in the first channel of the first memory chip 31, the channel signal region 11 in the first channel of the second memory chip 32, the channel signal region 14 in the fourth channel of the third memory chip 33, and the channel signal region 14 in the fourth channel of the fourth memory chip 34 are aligned along a third direction;

[0233] (2) the second channel signal region 12 in the logic chip 10, the channel signal region 12 in the second channel of the first memory chip 31, the channel signal region 12 in the second channel of the second memory chip 32, the channel signal region 13 in the third channel of the third memory chip 33, and the channel signal region 13 in the third channel of the fourth memory chip 34 are aligned along a third direction;

[0234] (3) the third channel signal region 13 in the logic chip 10, the channel signal region 13 in the third channel of the first memory chip 31, the channel signal region 13 in the third channel of the second memory chip 32, the channel signal region 12 in the second channel of the third memory chip 33, and the channel signal region 12 in the second channel of the fourth memory chip 34 are aligned along the third direction;

[0235] (4) The fourth channel signal region 14 in the logic chip 10, the channel signal region 14 in the fourth channel of the first memory chip 31, the channel signal region 14 in the fourth channel of the second memory chip 32, the channel signal region 11 in the first channel of the third memory chip 33, and the channel signal region 11 in the first channel of the fourth memory chip 34 are aligned along the third direction.

[0236] In a fourth specific embodiment, referring to FIG. 20A (illustrated using m=4 as an example), when m=4 and the logic chip 10 and the first memory chip 31 are stacked back to back, and the second axis BB' of the logic chip 10 and each memory chip extends along the first direction (i.e., the second axis BB' divides the corresponding chip into a high-order transmission area and a low-order transmission area), the high-order transmission area of ​​the logic chip 10, the high-order transmission area of ​​the first memory chip 31, the high-order transmission area of ​​the second memory chip 32, the low-order transmission area of ​​the third memory chip 33, and the low-order transmission area of ​​the fourth memory chip 34 are aligned along the third direction; the low-order transmission area of ​​the logic chip 10, the low-order transmission area of ​​the first memory chip 31, the low-order transmission area of ​​the second memory chip 32, the high-order transmission area of ​​the third memory chip 33, and the high-order transmission area of ​​the fourth memory chip 34 are aligned along the third direction.

[0237] Specifically, the channel signal areas of each chip have the following symmetrical relationship: the mi-th channel signal area in the logic chip 10 is aligned along the third direction with the channel signal area in the i+1-th channel in the first memory chip 31, the channel signal area in the mi-th channel in the second memory chip 32, the channel signal area in the mi-th channel in the third memory chip 33, and the channel signal area in the i+1-th channel in the fourth memory chip 34; where i is a natural number less than m.

[0238] (1) the fourth channel signal region 14 in the logic chip 10, the channel signal region 11 in the first channel of the first memory chip 31, the channel signal region 14 in the fourth channel of the second memory chip 32, the channel signal region 14 in the fourth channel of the third memory chip 33, and the channel signal region 11 in the first channel of the fourth memory chip 34 are aligned along a third direction;

[0239] (2) the third channel signal region 13 in the logic chip 10, the channel signal region 12 in the second channel of the first memory chip 31, the channel signal region 13 in the third channel of the second memory chip 32, the channel signal region 13 in the third channel of the third memory chip 33, and the channel signal region 12 in the second channel of the fourth memory chip 34 are aligned along the third direction;

[0240] (3) the second channel signal region 12 in the logic chip 10, the channel signal region 13 in the third channel of the first memory chip 31, the channel signal region 12 in the second channel of the second memory chip 32, the channel signal region 12 in the second channel of the third memory chip 33, and the channel signal region 13 in the third channel of the fourth memory chip 34 are aligned along the third direction;

[0241] (4) The first channel signal region 11 in the logic chip 10, the channel signal region 14 in the fourth channel of the first memory chip 31, the channel signal region 11 in the first channel of the second memory chip 32, the channel signal region 11 in the first channel of the third memory chip 33, and the channel signal region 14 in the fourth channel of the fourth memory chip 34 are aligned along the third direction.

[0242] In short, with respect to FIG. 19A to FIG. 20B , the logic chip 10 and the second memory chip 32 are arranged in the same manner.

[0243] In some embodiments, referring to Figures 19B and 20B , the channel signal area in each channel of the memory chip and the logic chip 10 is divided into 2×2 signal areas distributed in an array. Referring to Figures 19B and 19B , for multiple channel signal areas aligned along the third direction:

[0244] (1) The second signal area 22 of the logic chip 10, the first signal area 21 of the first memory chip 31, the second signal area 22 of the second memory chip 32, the third signal area 23 of the third memory chip 33, and the fourth signal area 24 of the fourth memory chip 34 are aligned along the third direction;

[0245] (2) The first signal area 21 of the logic chip 10, the second signal area 22 of the first memory chip 31, the first signal area 21 of the second memory chip 32, the fourth signal area 24 of the third memory chip 33, and the third signal area 23 of the fourth memory chip 34 are aligned along the third direction;

[0246] (3) The fourth signal area 24 of the logic chip 10, the third signal area 23 of the first memory chip 31, the fourth signal area 24 of the second memory chip 32, the first signal area 21 of the third memory chip 33, and the second signal area 22 of the fourth memory chip 34 are aligned along the third direction;

[0247] (4) The third signal area 23 belonging to the logic chip 10, the fourth signal area 24 belonging to the first memory chip 31, the third signal area 23 belonging to the second memory chip 32, the second signal area 22 belonging to the third memory chip 33, and the first signal area 21 belonging to the fourth memory chip 34 are aligned along the third direction.

[0248] 19B or 19B , each signal region of the memory chip and the logic chip 10 includes n conductive via groups with the same distribution positions, and each conductive via group includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via.

[0249] For multiple signal areas aligned along the third direction:

[0250] (1) The second conductive via D1 of the logic chip 10, the first conductive via D0 of the first memory chip 31, the second conductive via D1 of the second memory chip 32, the third conductive via D2 of the third memory chip 33, and the fourth conductive via D3 of the fourth memory chip 34 are aligned along the third direction;

[0251] (2) the first conductive via D0 of the logic chip 10, the second conductive via D1 of the first memory chip 31, the first conductive via D0 of the second memory chip 32, the fourth conductive via D3 of the third memory chip 33, and the third conductive via D2 of the fourth memory chip 34 are aligned along the third direction;

[0252] (3) The fourth conductive via D3 of the logic chip 10, the third conductive via D2 of the first memory chip 31, the fourth conductive via D3 of the second memory chip 32, the first conductive via D0 of the third memory chip 33, and the second conductive via D1 of the fourth memory chip 34 are aligned along the third direction;

[0253] (4) The third conductive via D2 of the logic chip 10, the fourth conductive via D3 of the first memory chip 31, the third conductive via D2 of the second memory chip 32, the second conductive via D1 of the third memory chip 33, and the first conductive via D0 of the fourth memory chip 34 are aligned along the third direction;

[0254] Wherein, a plurality of conductive through holes aligned along the third direction are coupled to form a signal transmission channel.

[0255] Referring to FIG. 16B , for the third and fourth specific embodiments, the repair units of each chip have the following relationship:

[0256] (a) A second repair unit in the logic chip 10, a first repair unit in the first memory chip 31, a second repair unit in the second memory chip 32, a third repair unit in the third memory chip 33, and a fourth repair unit in the fourth memory chip 34 are aligned along a third direction and perform a conductive via switching operation simultaneously;

[0257] (b) A first repair unit in the logic chip 10, a second repair unit in the first memory chip 31, a first repair unit in the second memory chip 32, a fourth repair unit in the third memory chip 33, and a third repair unit in the fourth memory chip 34 are aligned along a third direction and the conductive via switching operation is performed synchronously;

[0258] (c) A fourth repair unit in the logic chip 10, a third repair unit in the first memory chip 31, a fourth repair unit in the second memory chip 32, a first repair unit in the third memory chip 33, and a second repair unit in the fourth memory chip 34 are aligned along the third direction and the conductive via switching operation is performed synchronously;

[0259] (d) A third repair unit in the logic chip 10, a fourth repair unit in the first memory chip 31, a third repair unit in the second memory chip 32, a second repair unit in the third memory chip 33, and a first repair unit in the fourth memory chip 34 are aligned along a third direction, and the conductive via switching operation is performed synchronously.

[0260] Likewise, the repair units of the chip stacking structure 40 are aligned along the third direction and have symmetrical switching directions, thereby achieving the same switching function.

[0261] To facilitate understanding of the signal switching process within the chip stack structure 40, the following describes signal switching for a specific operating scenario: The chip stack structure 40 is formed by stacking the logic chip 10 shown in FIG5 and the memory chip 30 shown in FIG11 in the manner shown in FIG17A . Assuming that each repair unit performs a 2:1 repair, please refer to FIG21 , which provides a schematic diagram of signal transmission within the chip stack structure 40.

[0262] Figure 21 shows one of the repair unit groups in each chip. For each repair unit group, there are only two signal selection circuits 100 for each memory chip, so that only the two conductive through-holes in the first repair unit in the repair unit group are connected to the internal circuit of the memory chip, that is, only the signal channel composed of two conductive through-holes is connected to the internal circuit of the memory chip, and there are 8 signal selection circuits in the logic chip 10, so that the two conductive through-holes in each repair unit in the repair unit group are connected to the internal circuit of the logic chip, that is, the signal channel composed of a total of 8 conductive through-holes in the four repair units is connected to the internal circuit of the logic chip, so that the logic chip 10 can be connected to the corresponding memory chip through two signal conductions for signal interaction.

[0263] Please refer to Figures 21-22B for the following exemplary working scenarios:

[0264] Taking the fourth repair unit composed of D3 / 0, D3 / 1, and D3 / 2 in the fourth signal area of ​​the logic chip 10, the first repair unit composed of D0 / 0, D0 / 1, and D0 / 2 in the first signal area of ​​the first storage chip 31, the second repair unit composed of D1 / 0, D1 / 1, and D1 / 2 in the second signal area of ​​the second storage chip 32, the third repair unit composed of D2 / 0, D2 / 1, and D2 / 2 in the third signal area of ​​the third storage chip 33, and the fourth repair unit composed of D3 / 0, D3 / 1, and D3 / 2 in the fourth signal area of ​​the fourth storage chip 34 as examples, the specific process of signal switching is explained.

[0265] As shown in FIG21 , D3 / 0 in the fourth signal area of ​​the logic chip 10, D0 / 0 in the first signal area of ​​the first memory chip 31, D1 / 0 in the second signal area of ​​the second memory chip 32, D2 / 0 in the third signal area of ​​the third memory chip 33, and D3 / 0 in the fourth signal area of ​​the fourth memory chip 34 are connected to form a signal channel (a first normal signal channel); at the same time, D3 / 1 in the fourth signal area of ​​the logic chip 10, D0 / 1 in the first signal area of ​​the first memory chip 31, D1 / 1 in the second signal area of ​​the second memory chip 32, and D2 / 0 in the third signal area of ​​the third memory chip 33 are connected to form a signal channel (a first normal signal channel). D2 / 1 in the third signal area of ​​the memory chip 33 and D3 / 1 in the fourth signal area of ​​the fourth memory chip 34 are connected to form a signal channel (a second normal signal channel), and all of the above are normal conductive through-holes. At the same time, D3 / 2 in the fourth signal area of ​​the logic chip 10, D0 / 2 in the first signal area of ​​the first memory chip 31, D1 / 2 in the second signal area of ​​the second memory chip 32, D2 / 2 in the third signal area of ​​the third memory chip 33, and D3 / 2 in the fourth signal area of ​​the fourth memory chip 34 are connected to form a signal channel (a first redundant signal channel).

[0266] When all conductive vias are functioning normally, as shown in FIG22A , the signal selection circuit 100a in the logic chip 10 connects D3 / 0 to the internal circuit, and the signal selection circuit 100c in the first memory chip 31 connects D0 / 0 to the internal circuit. As a result, the first normal signal channel is used to transmit a valid signal (denoted as signal1). The logic chip 10 can send and receive the valid signal signal1 from D3 / 0 via the signal selection circuit 100a, and the first memory chip 31 can send and receive the valid signal signal1 from D0 / 0 via the signal selection circuit 100c.

[0267] Similarly, the signal selection circuit 100b in the logic chip 10 connects D3 / 1 to the internal circuit, and the second normal signal channel sends / receives another valid signal (denoted as signal2). The signal selection circuit 100d in the first memory chip 31 connects D0 / 1 to the internal circuit, thereby receiving / sending the valid signal signal2.

[0268] Please refer to Figure 22B. Assume that any conductive through-hole in the first normal signal channel is damaged, that is, the corresponding first normal signal channel cannot be used. In this case, the redundant signal channel needs to be used for repair. Then, for the logic chip 10, the signal selection circuit 100a connects D0 / 1 to the internal circuit to replace the original D0 / 0 to send / receive the valid signal signal1; the signal selection circuit 100b connects D0 / 2 to the internal circuit to replace the original D0 / 1 to send / receive the valid signal signal2; at the same time, for the first memory chip 31, the signal selection circuit 100c connects D0 / 1 to the internal circuit to replace the original D0 / 0 to receive / send the valid signal signal1; the signal selection circuit 100d connects D0 / 2 to the internal circuit to replace the original D0 / 1 to receive / send the valid signal signal12; thereby completing the switching from the first normal signal channel to the second normal signal channel and the switching from the second normal signal channel to the first redundant signal channel.

[0269] The following describes signal switching in detail for the following specific operating scenario: Using the logic chip 10 shown in FIG7 and the memory chip 30 shown in FIG13 , a chip stack structure 40 is formed by stacking the chip as shown in FIG17A , assuming that each repair unit performs a 4:2 repair. Please refer to FIG23 , which provides a schematic diagram of signal transmission within the chip stack structure 40.

[0270] Please refer to Figures 23-24B for the following exemplary working scenarios:

[0271] Taking the fourth repair unit composed of D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, and D3 / 5 in the fourth signal area of ​​the logic chip 10, the first repair unit composed of D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, and D0 / 5 in the first signal area of ​​the first storage chip 31, the second repair unit composed of D1 / 0, D1 / 1, D1 / 2, D1 / 3, D0 / 4, and D1 / 5 in the second signal area of ​​the second storage chip 32, the third repair unit composed of D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, and D2 / 5 in the third signal area of ​​the third storage chip 33, and the fourth repair unit composed of D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, and D3 / 5 in the fourth signal area of ​​the fourth storage chip 34 as examples, the specific process of signal switching is explained.

[0272] As shown in FIG23 , D3 / 2 in the fourth signal area of ​​the logic chip 10, D0 / 2 in the first signal area of ​​the first memory chip 31, D1 / 2 in the second signal area of ​​the second memory chip 32, D2 / 2 in the third signal area of ​​the third memory chip 33, and D3 / 2 in the fourth signal area of ​​the fourth memory chip 34 are connected to form a signal channel (a first normal signal channel); D3 / 3 in the fourth signal area of ​​the logic chip 10, D0 / 3 in the first signal area of ​​the first memory chip 31, D1 / 3 in the second signal area of ​​the second memory chip 32, D2 / 3 in the third signal area of ​​the third memory chip 33, and D3 / 3 in the fourth signal area of ​​the fourth memory chip 34 are connected to form a signal channel (a second normal signal channel); D3 / 4 in the fourth signal area of ​​the chip 10, D0 / 4 in the first signal area of ​​the first memory chip 31, D1 / 4 in the second signal area of ​​the second memory chip 32, D2 / 4 in the third signal area of ​​the third memory chip 33, and D3 / 4 in the fourth signal area of ​​the fourth memory chip 34 are connected to form a signal channel (a third normal signal channel); D3 / 1 in the fourth signal area of ​​the logic chip 10, D0 / 1 in the first signal area of ​​the first memory chip 31, D1 / 1 in the second signal area of ​​the second memory chip 32, D2 / 1 in the third signal area of ​​the third memory chip 33, and D3 / 0 in the fourth signal area of ​​the fourth memory chip 34 are connected to form a signal channel (a fourth normal signal channel); and all of the above are normal conductive through holes;

[0273] At the same time, D3 / 0 in the fourth signal area of ​​the logic chip 10, D0 / 0 in the first signal area of ​​the first memory chip 31, D1 / 0 in the second signal area of ​​the second memory chip 32, D2 / 0 in the third signal area of ​​the third memory chip 33, and D3 / 0 in the fourth signal area of ​​the fourth memory chip 34 are connected to form a signal channel (a first redundant signal channel); D3 / 5 in the fourth signal area of ​​the logic chip 10, D0 / 5 in the first signal area of ​​the first memory chip 31, D1 / 5 in the second signal area of ​​the second memory chip 32, D2 / 5 in the third signal area of ​​the third memory chip 33, and D3 / 5 in the fourth signal area of ​​the fourth memory chip 34 are connected to form a signal channel (a second redundant signal channel);

[0274] When all conductive vias are functioning normally, as shown in FIG24A , the signal selection circuit 100A in the logic chip 10 connects D3 / 2 to the internal circuit, and the signal selection circuit 100E in the first memory chip 31 connects D0 / 2 to the internal circuit. Thus, the first normal signal channel is used to transmit a valid signal (denoted as signal1). Specifically, the logic chip 10 can send / receive the valid signal signal1 from D2 / 6 via the signal selection circuit 100A, and the first memory chip 31 can send / receive the valid signal signal1 from D1 / 1 via the signal selection circuit 100E.

[0275] Similarly, the signal selection circuit 100B in the logic chip 10 connects D3 / 3 to the internal circuit, and the second normal signal channel sends / receives another valid signal (denoted as signal2). The signal selection circuit 100F in the first memory chip 31 connects D0 / 3 to the internal circuit, thereby receiving / sending the valid signal signal2. The signal selection circuit 100C in the logic chip 10 connects D3 / 4 to the internal circuit, and the second normal signal channel sends / receives another valid signal (denoted as signal3). The signal selection circuit 100G in the first memory chip 31 connects D0 / 4 to the internal circuit, thereby receiving / sending the valid signal signal3. The signal selection circuit 100D in the logic chip 10 connects D3 / 4 to the internal circuit, and the second normal signal channel sends / receives another valid signal (denoted as signal4). The signal selection circuit 100H in the first memory chip 31 connects D0 / 4 to the internal circuit, thereby receiving / sending the valid signal signal4.

[0276] Referring to FIG. 24B , assuming that the first normal signal channel is unusable and needs to be repaired using a redundant signal channel, for logic chip 10, signal selection circuit 100A connects D3 / 3 to the internal circuit to replace D3 / 2 in transmitting / receiving the valid signal signal1; signal selection circuit 100B connects D3 / 4 to the internal circuit to replace D3 / 3 in transmitting / receiving the valid signal signal2; signal selection circuit 100C connects D3 / 1 to the internal circuit to replace D3 / 4 in transmitting / receiving the valid signal signal3; signal selection circuit 100D connects D3 / 0 to the internal circuit to replace D3 / 1 in transmitting / receiving the valid signal signal4.

[0277] At the same time, for the first memory chip 31, the signal selection circuit 100E connects D0 / 3 to the internal circuit to receive / send the valid signal signal1 instead of the original D1 / 2. The signal selection circuit 100F connects D0 / 4 to the internal circuit to receive / send the valid signal signal12 instead of the original D0 / 3. The signal selection circuit 100G connects D0 / 1 to the internal circuit to receive / send the valid signal signal13 instead of the original D0 / 4. The signal selection circuit 100H connects D0 / 0 to the internal circuit to receive / send the valid signal signal15 instead of the original D0 / 1.

[0278] Thus, the switching work of the first normal signal channel to the second normal signal channel, the second normal signal channel to the third normal signal channel, the third normal signal channel to the fourth normal signal channel, and the fourth normal signal channel to the first redundant signal channel is completed.

[0279] At the same time, it can be seen from Figures 17B, 18B, 19B, 20B, and 21-24B that for the chip stacking structure 40, the bottom-up signal transmission path will be similar to the following form: Please refer to Figures 17B and 18B, the fourth conductive through hole D3 in the logic chip 10 (or the fourth conductive through hole D1 in the logic chip 10, please refer to Figures 19B and 20B) - the first conductive through hole D0 in the first memory chip 31 - the second conductive through hole D1 in the second memory chip 32 - the third conductive through hole D2 in the third memory chip 33 - the fourth conductive through hole D3 in the fourth memory chip 34..." for transmission. That is, for the chip stacking structure 40, from From a physical perspective, the conductive vias are still in a direct-connect configuration, but from the absolute position of the conductive vias on the active surface, the conductive vias can be considered as a functionally rotated configuration, that is, a signal transmission effect similar to that of FIG2B is achieved through a physical direct-connect configuration (i.e., a rotational transmission effect such as conductive via D0-conductive via D1-conductive via D2-conductive via D3...). Simply put, the chip stacking structure 40 in FIG2B requires a physical spiral structure, which necessarily includes a horizontal interconnection structure. However, the chip stacking structure 40 in the embodiment of the present disclosure is physically a direct-connect structure, which does not require a horizontal interconnection structure, greatly reducing parasitic resistance and significantly improving transmission speed and transmission performance.

[0280] In another embodiment of the present disclosure, referring to Figure 25 , a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure is shown. As shown in Figure 25 , the memory 70 includes the chip stacking structure 40 of the aforementioned embodiment.

[0281] In some embodiments, the chip stacking structure 40 can be applied to a memory 70. The memory 70 can be, for example, a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), etc., which is not specifically limited here.

[0282] In the embodiment of the present disclosure, for the memory 70, the chip area can be reduced and the chip manufacturing cost can be reduced.

[0283] Details not disclosed in the embodiments of the present disclosure may be understood by referring to the description of the aforementioned embodiments.

[0284] The above are only preferred embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure.

[0285] It should be noted that, in this disclosure, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0286] The serial numbers of the above-mentioned embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments.

[0287] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0288] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0289] The features disclosed in several method or device embodiments provided in this disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0290] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A logic chip (10), comprising m channel signal areas (11, 12, 13, 14) arranged in sequence along a first direction, the logic chip (10) having a chip axis extending along a second direction and passing through the center of the logic chip (10), the m channel signal areas (11, 12, 13, 14) being symmetrical about the chip axis; m is a positive integer; Each of the channel signal regions (11, 12, 13, 14) has a first axis and a second axis, the first axis extends along the first direction or the second direction, the second axis and the first axis are perpendicular to each other and intersect at the center of the corresponding channel signal region (11, 12, 13, 14); Each of the channel signal regions (11, 12, 13, 14) is penetrated by a plurality of conductive through holes along a third direction, the first direction, the second direction and the third direction are perpendicular to each other, the first direction and the second direction are parallel to the top surface of the logic chip (10), and the third direction is perpendicular to the top surface of the logic chip (10); For each of the channel signal areas (11, 12, 13, 14), the plurality of conductive vias therein are divided into a plurality of repair unit groups; Each of the repair unit groups comprises a first repair unit, a second repair unit, a third repair unit and a fourth repair unit; the first repair unit and the second repair unit are symmetrical along a first axis of the channel signal area (11, 12, 13, 14) to which they belong, the third repair unit and the fourth repair unit are symmetrical along the first axis of the channel signal area (11, 12, 13, 14) to which they belong, and the first repair unit and the fourth repair unit are symmetrical along a second axis of the channel signal area (11, 12, 13, 14) to which they belong; Each of the repair units includes at least one redundant conductive via and at least one normal conductive via. When any of the normal conductive vias is damaged, the effective signal transmitted by the normal conductive via is switched to the next conductive via in the same repair unit along a preset signal switching direction. Any conductive through hole in any of the repair units is electrically connected to an internal circuit of the logic chip (10) when used to transmit a valid signal; The normal conductive vias in the first repair unit and the normal conductive vias in the second repair unit correspond one-to-one and are symmetrical along the first axis of the channel signal area (11, 12, 13, 14) to which they belong; the normal conductive vias in the third repair unit and the normal conductive vias in the fourth repair unit correspond one-to-one and are symmetrical along the first axis of the channel signal area (11, 12, 13, 14) to which they belong; the normal conductive vias in the first repair unit and the normal conductive vias in the fourth repair unit correspond one-to-one and are symmetrical along the second axis of the channel signal area (11, 12, 13, 14) to which they belong.

2. The logic chip (10) according to claim 1, wherein: For each of the repair unit groups, the preset switching direction of the conductive via in the first repair unit and the preset switching direction of the conductive via in the second repair unit are symmetrical along the first axis of the channel signal area (11, 12, 13, 14) to which they belong; the preset switching direction of the conductive via in the third repair unit and the preset switching direction of the conductive via in the fourth repair unit are symmetrical along the first axis of the channel signal area (11, 12, 13, 14) to which they belong; the preset switching direction of the conductive via in the first repair unit and the preset switching direction of the conductive via in the fourth repair unit are symmetrical along the second axis of the channel signal area (11, 12, 13, 14) to which they belong; the preset switching direction of the conductive via in the second repair unit and the preset switching direction of the conductive via in the third repair unit are symmetrical along the second axis of the channel signal area (11, 12, 13, 14) to which they belong.

3. The logic chip (10) according to claim 2, wherein: Each of the channel signal areas (11, 12, 13, 14) is divided into 2×2 signal areas, and the conductive through holes in each of the signal areas are divided into n conductive through hole groups with the same distribution position, where n is a positive integer; in the same channel signal area (11, 12, 13, 14), the conductive through hole group in the first signal area (21) and the conductive through hole group in the second signal area (22) correspond one-to-one and are symmetrical along a first axis of the corresponding channel signal area (11, 12, 13, 14); the conductive through hole group in the third signal area (23) and the conductive through hole group in the fourth signal area (24) correspond one-to-one and are symmetrical along the first axis of the corresponding channel signal area (11, 12, 13, 14); and the conductive through hole group in the first signal area (21) and the conductive through hole group in the fourth signal area (24) correspond one-to-one and are symmetrical along a second axis of the corresponding channel signal area (11, 12, 13, 14); Each of the conductive via groups includes a first conductive via, a second conductive via, a third conductive via and a fourth conductive via; In the same channel signal area (11, 12, 13, 14), a first conductive through hole in a conductive through hole group in the first signal area (21), a second conductive through hole in a corresponding conductive through hole group in the second signal area (22), a third conductive through hole in a corresponding conductive through hole group in the third signal area (23), and a fourth conductive through hole in a corresponding conductive through hole group in the fourth signal area (24) form a whole which is symmetrical along the first axis and symmetrical along the second axis; In the same channel signal area (11, 12, 13, 14), the whole formed by the second conductive through hole in a conductive through hole group in the first signal area (21), the first conductive through hole in the corresponding conductive through hole group in the second signal area (22), the fourth conductive through hole in the corresponding conductive through hole group in the third signal area (23), and the third conductive through hole in the corresponding conductive through hole group in the fourth signal area (24) is symmetrical along the first axis and symmetrical along the second axis; In the same channel signal area (11, 12, 13, 14), a whole formed by a third conductive through hole in a conductive through hole group in the first signal area (21), a fourth conductive through hole in a corresponding conductive through hole group in the second signal area (22), a first conductive through hole in a corresponding conductive through hole group in the third signal area (23), and a second conductive through hole in a corresponding conductive through hole group in the fourth signal area (24) is symmetrical along the first axis and symmetrical along the second axis; In the same channel signal area (11, 12, 13, 14), a fourth conductive through hole in a conductive through hole group in the first signal area (21), a third conductive through hole in a corresponding conductive through hole group in the second signal area (22), The whole formed by the second conductive through hole in the corresponding conductive through hole group in the third signal area (23) and the first conductive through hole in the corresponding conductive through hole group in the fourth signal area (24) is symmetrical along the first axis and symmetrical along the second axis.

4. The logic chip (10) according to claim 3, wherein: The B conductive via groups in each of the signal areas are referred to as a conductive via combination, and the conductive via group b in the corresponding conductive via combinations in all signal areas constitutes a whole, which is symmetrical along the first axis and symmetrical along the second axis, B is a positive integer less than or equal to n, and b is a natural number less than B; The corresponding one conductive through hole combination in each signal area in the same channel signal area (11, 12, 13, 14) constitutes a total of four repair unit groups: For the first repair unit group, the first repair unit includes: the first conductive via of each of all the conductive via groups in the conductive via combination in the first signal area (21); the second repair unit includes: the second conductive via of each of all the conductive via groups in the conductive via combination in the second signal area (22); the third repair unit includes: the third conductive via of each of all the conductive via groups in the conductive via combination in the third signal area (23); the fourth repair unit includes: the fourth conductive via of each of all the conductive via groups in the conductive via combination in the fourth signal area (24); For the second repair unit group, the first repair unit includes: the first conductive via of each of all the conductive via groups in the conductive via combination in the second signal area (22); the second repair unit includes: the second conductive via of each of all the conductive via groups in the conductive via combination in the first signal area (21); the third repair unit includes: the third conductive via of each of all the conductive via groups in the conductive via combination in the fourth signal area (24); the fourth repair unit includes: the fourth conductive via of each of all the conductive via groups in the conductive via combination in the third signal area (23); For the third repair unit group, the first repair unit includes: the first conductive via of each of all the conductive via groups in the conductive via combination in the third signal area (23); the second repair unit includes: the second conductive via of each of all the conductive via groups in the conductive via combination in the fourth signal area (24); the third repair unit includes: the third conductive via of each of all the conductive via groups in the conductive via combination in the first signal area (21); the fourth repair unit includes: the fourth conductive via of each of all the conductive via groups in the conductive via combination in the second signal area (22); For the fourth repair unit group, the first repair unit includes: the first conductive vias of all the conductive via groups in the conductive via combination in the fourth signal area (24); the second repair unit includes: the second conductive vias of all the conductive via groups in the conductive via combination in the third signal area (23); the fourth repair unit includes: the second conductive vias of all the conductive via groups in the conductive via combination in the second signal area (22); There is a third conductive via in each of the conductive via groups; wherein the fourth repair unit comprises: the fourth conductive via in each of all the conductive via groups in the conductive via combination in the first signal area (21).

5. The logic chip (10) according to claim 4, wherein: When B=3, the value of b is 0, 1 or 2; all the conductive vias in the conductive via group 0 are normal conductive vias; The preset switching direction of the conductive vias in the Xth repair unit is: the Xth conductive via in the conductive via group 0 is allowed to switch to the Xth conductive via in the conductive via group 1 in the same signal area, and the Xth conductive via in the conductive via group 1 is allowed to switch to the Xth conductive via in the conductive via group 2 in the same signal area; X is one, two, three or four.

6. The logic chip (10) according to claim 4, wherein: When B=6, the value of b is 0, 1, 2, 3, 4 or 5; all conductive vias in the conductive via group 2 of the signal area are normal conductive vias; The preset switching direction of the conductive via in the Xth repair unit is: the Xth conductive via in the conductive via group 2 is allowed to switch to the Xth conductive via in the conductive via group 3 in the same signal area, the Xth conductive via in the conductive via group 3 is allowed to switch to the Xth conductive via in the conductive via group 4 in the same signal area, the Xth conductive via in the conductive via group 4 is allowed to switch to the Xth conductive via in the conductive via group 1 in the same signal area; the Xth conductive via in the conductive via group 1 is allowed to switch to the Xth conductive via in the conductive via group 0 in the same signal area; the Xth conductive via in the conductive via group 0 is allowed to switch to the Xth conductive via in the conductive via group 5 in the same signal area.

7. The logic chip (10) according to claim 6, wherein: In each signal area, the conductive via group 0, the conductive via group 1, and the conductive via group 2 are aligned along a first direction; the conductive via group 3, the conductive via group 4, and the conductive via group 5 are aligned along the first direction; the conductive via group 0 and the conductive via group 5 are aligned along a second direction, the conductive via group 1 and the conductive via group 4 are aligned along the second direction, and the conductive via group 2 and the conductive via group 3 are aligned along the second direction.

8. The logic chip (10) according to any one of claims 1 to 7, wherein: The conductive vias are prepared by any one or more of the following processes: via-first, via-middle, via-last, and back side via-last; and different conductive vias in the same logic chip (10) are electrically isolated.

9. A memory chip (30), the memory chip (30) comprising m channels, the m channels being arranged in sequence along a first direction, the memory chip (30) having a chip axis extending in a second direction and passing through the center of the memory chip (30), the m channels being symmetrical about the chip axis; each of the channels comprising a first memory array region, a channel signal region (11, 12, 13, 14) and a second memory array region which are sequentially distributed along the second direction, and the center of each channel signal region (11, 12, 13, 14) coincides with the center of the corresponding channel, and m is a positive integer; Each of the channel signal regions (11, 12, 13, 14) has a first axis and a second axis, the first axis extends along the first direction or the second direction, the second axis and the first axis are perpendicular to each other and intersect at the center of the corresponding channel signal region (11, 12, 13, 14); Each of the channel signal regions (11, 12, 13, 14) is penetrated by a plurality of conductive through holes along a third direction, the first direction, the second direction and the third direction are perpendicular to each other, the first direction and the second direction are parallel to the top surface of the memory chip (30), and the third direction is perpendicular to the top surface of the memory chip (30); for each of the channel signal regions (11, 12, 13, 14), the plurality of conductive through holes therein are divided into a plurality of repair unit groups; each of the repair unit groups comprises a first repair unit, a second repair unit, a third repair unit and a fourth repair unit; the first repair unit and the second repair unit are symmetrical along a first axis of the channel signal region (11, 12, 13, 14) to which they belong, the third repair unit and the fourth repair unit are symmetrical along a first axis of the channel signal region (11, 12, 13, 14) to which they belong, and the first repair unit and the fourth repair unit are symmetrical along a second axis of the channel signal region (11, 12, 13, 14) to which they belong; Each of the repair units comprises at least one redundant conductive via and at least one normal conductive via. When any of the normal conductive vias is damaged, the effective signal transmitted by the normal conductive via is switched to the next conductive via in the same repair unit along a preset signal switching direction; any conductive via in the first repair unit is electrically connected to the internal circuit of the memory chip (30) when used to transmit an effective signal; The normal conductive vias in the first repair unit and the normal conductive vias in the second repair unit correspond one-to-one and are symmetrical along the first axis of the channel signal area (11, 12, 13, 14) to which they belong, the normal conductive vias in the third repair unit and the normal conductive vias in the fourth repair unit correspond one-to-one and are symmetrical along the first axis of the channel signal area (11, 12, 13, 14) to which they belong, and the normal conductive vias in the first repair unit and the normal conductive vias in the fourth repair unit correspond one-to-one and are symmetrical along the second axis of the channel signal area (11, 12, 13, 14) to which they belong.

10. The memory chip (30) according to claim 9, wherein: For each of the repair unit groups, the preset switching direction of the conductive via in the first repair unit and the preset switching direction of the conductive via in the second repair unit are symmetrical along the first axis of the corresponding channel signal area (11, 12, 13, 14); the preset switching direction of the conductive via in the third repair unit and the preset switching direction of the conductive via in the fourth repair unit are symmetrical along the first axis of the corresponding channel signal area (11, 12, 13, 14); the preset switching direction of the conductive via in the first repair unit and the preset switching direction of the conductive via in the fourth repair unit are symmetrical along the second axis of the corresponding channel signal area (11, 12, 13, 14); the preset switching direction of the conductive via in the second repair unit and the preset switching direction of the conductive via in the third repair unit are symmetrical along the second axis of the corresponding channel signal area (11, 12, 13, 14).

11. The memory chip (30) according to claim 10, wherein: Each of the channel signal areas (11, 12, 13, 14) is divided into 2×2 signal areas, and the conductive through holes in each of the signal areas are divided into n conductive through hole groups with the same distribution position, where n is a positive integer; in the same channel signal area (11, 12, 13, 14), the conductive through hole group in the first signal area (21) and the conductive through hole group in the second signal area (22) correspond one-to-one and are symmetrical along a first axis, the conductive through hole group in the third signal area (23) and the conductive through hole group in the fourth signal area (24) correspond one-to-one and are symmetrical along the first axis, and the conductive through hole group in the first signal area (21) and the conductive through hole group in the fourth signal area (24) correspond one-to-one and are symmetrical along the second axis; Each of the conductive via groups includes a first conductive via, a second conductive via, a third conductive via and a fourth conductive via; For the same channel signal area, the whole formed by the first conductive through hole in a conductive through hole group in the first signal area (21), the second conductive through hole in the corresponding conductive through hole group in the second signal area (22), the third conductive through hole in the corresponding conductive through hole group in the third signal area (23), and the fourth conductive through hole in the corresponding conductive through hole group in the fourth signal area (24) is symmetrical along the first axis and symmetrical along the second axis; In the same channel signal area (11, 12, 13, 14), the whole formed by the second conductive through hole in a conductive through hole group in the first signal area (21), the first conductive through hole in the corresponding conductive through hole group in the second signal area (22), the fourth conductive through hole in the corresponding conductive through hole group in the third signal area (23), and the third conductive through hole in the corresponding conductive through hole group in the fourth signal area (24) is symmetrical along the first axis and symmetrical along the second axis; In the same channel signal area (11, 12, 13, 14), a whole formed by a third conductive through hole in a conductive through hole group in the first signal area (21), a fourth conductive through hole in a corresponding conductive through hole group in the second signal area (22), a first conductive through hole in a corresponding conductive through hole group in the third signal area (23), and a second conductive through hole in a corresponding conductive through hole group in the fourth signal area (24) is symmetrical along the first axis and symmetrical along the second axis; In the same channel signal area (11, 12, 13, 14), a whole formed by a fourth conductive through hole in a conductive through hole group in the first signal area (21), a third conductive through hole in a corresponding conductive through hole group in the second signal area (22), a second conductive through hole in a corresponding conductive through hole group in the third signal area (23), and a first conductive through hole in a corresponding conductive through hole group in the fourth signal area (24) is symmetrical along the first axis and symmetrical along the second axis.

12. The memory chip (30) according to claim 11, wherein: The B conductive via groups in each of the signal areas are referred to as a conductive via combination, and the conductive via group b in the corresponding conductive via combinations in all signal areas constitutes a whole, which is symmetrical along the first axis and symmetrical along the second axis, B is a positive integer less than or equal to n, and b is a natural number less than B; A conductive through hole corresponding to each signal area in the same channel signal area (11, 12, 13, 14) The combination constitutes a total of 4 repair unit groups: For the first repair unit group, the first repair unit includes: the first conductive via of each of all the conductive via groups in the conductive via combination in the first signal area (21); the second repair unit includes: the second conductive via of each of all the conductive via groups in the conductive via combination in the second signal area (22); the third repair unit includes: the third conductive via of each of all the conductive via groups in the conductive via combination in the third signal area (23); the fourth repair unit includes: the fourth conductive via of each of all the conductive via groups in the conductive via combination in the fourth signal area (24); For the second repair unit group, the first repair unit includes: the first conductive via of each of all the conductive via groups in the conductive via combination in the second signal area (22); the second repair unit includes: the second conductive via of each of all the conductive via groups in the conductive via combination in the first signal area (21); the third repair unit includes: the third conductive via of each of all the conductive via groups in the conductive via combination in the fourth signal area (24); the fourth repair unit includes: the fourth conductive via of each of all the conductive via groups in the conductive via combination in the third signal area (23); For the third repair unit group, the first repair unit includes: the first conductive via of each of all the conductive via groups in the conductive via combination in the third signal area (23); the second repair unit includes: the second conductive via of each of all the conductive via groups in the conductive via combination in the fourth signal area (24); the third repair unit includes: the third conductive via of each of all the conductive via groups in the conductive via combination in the first signal area (21); the fourth repair unit includes: the fourth conductive via of each of all the conductive via groups in the conductive via combination in the second signal area (22); For the fourth repair unit group, the first repair unit includes: the first conductive via of each of all the conductive via groups in the conductive via combination in the fourth signal area (24); the second repair unit includes: the second conductive via of each of all the conductive via groups in the conductive via combination in the third signal area (23); the fourth repair unit includes: the third conductive via of each of all the conductive via groups in the conductive via combination in the second signal area (22); the fourth repair unit includes: the fourth conductive via of each of all the conductive via groups in the conductive via combination in the first signal area (21).

13. The memory chip (30) according to claim 12, wherein: When B=3, the value of b is 0, 1 or 2; the conductive through holes in the conductive through hole group 0 are all normal conductive through holes; The preset switching direction of the conductive vias in any of the first repair units is: the first conductive via in the conductive via group 0 is allowed to switch to the first conductive via in the conductive via group 1 in the same signal area, and the first conductive via in the conductive via group 1 is allowed to switch to the first conductive via in the conductive via group 2 in the same signal area.

14. The memory chip (30) according to claim 13, wherein: When B=6, the value of b is 0, 1, 2, 3, 4 or 5; all conductive vias in the conductive via group 0 of the signal area are normal conductive vias; The preset switching direction of the conductive vias in the first repair unit is: the first conductive via in the conductive via group 2 is allowed to switch to the first conductive via in the conductive via group 3 in the same signal area, the first conductive via in the conductive via group 3 is allowed to switch to the first conductive via in the conductive via group 4 in the same signal area, the first conductive via in the conductive via group 4 is allowed to switch to the first conductive via in the conductive via group 1 in the same signal area; the first conductive via in the conductive via group 1 is allowed to switch to the first conductive via in the conductive via group 0 in the same signal area; the first conductive via in the conductive via group 0 is allowed to switch to the first conductive via in the conductive via group 5 in the same signal area.

15. A chip stacking structure (40), comprising a logic chip (10) as claimed in any one of claims 1 to 8 and at least one stacking unit, wherein the logic chip (10) and the at least one stacking unit are stacked in sequence along a third direction; each of the stacking units comprises a first memory chip (31), a second memory chip (32), a third memory chip (33) and a fourth memory chip (34) stacked in sequence along the third direction, wherein the third direction is perpendicular to a top surface of each chip; the first memory chip (31), the second memory chip (32), the third memory chip (33) and the fourth memory chip (34) are all memory chips (30) as claimed in any one of claims 9 to 14; The first memory chip (31) and the second memory chip (32) are stacked face to face, the second memory chip (32) and the third memory chip (33) are stacked back to back, and the third memory chip (33) and the fourth memory chip (34) are stacked face to face; The logic chip (10) and the first memory chip (31) are stacked in a back-to-back manner; or, the logic chip (10) and the first memory chip (31) are stacked in a face-to-back manner.

16. The chip stacking structure (40) according to claim 15, wherein: The logic chip (10) comprises m channel signal areas (11, 12, 13, 14) arranged along a first direction, each of the memory chips (30) has m channels arranged along the first direction, and each of the channels comprises a first memory array area, a channel signal area (11, 12, 13, 14) and a second memory array area sequentially distributed along a second direction; the first direction, the second direction and the third direction are perpendicular to each other, and the first direction and the second direction are parallel to the top surface of each chip; When the logic chip (10) and the first memory chip (31) are stacked back to back, and the first axis of the logic chip (10) and each of the memory chips (30) extends along a first direction, The mi-th channel signal area (11, 12, 13, 14) in the logic chip (10) is aligned along a third direction with the channel signal area (11, 12, 13, 14) in the i+1-th channel in the first memory chip (31), the channel signal area (11, 12, 13, 14) in the i+1-th channel in the second memory chip (32), the channel signal area (11, 12, 13, 14) in the mi-th channel in the third memory chip (33), and the channel signal area (11, 12, 13, 14) in the mi-th channel in the fourth memory chip (34); wherein i is less than m A natural number.

17. The chip stacking structure (40) according to claim 16, wherein: The logic chip (10) comprises m channel signal areas (11, 12, 13, 14) arranged along a first direction, each of the memory chips (30) has m channels arranged along the first direction, and each of the channels comprises a first memory array area, a channel signal area (11, 12, 13, 14) and a second memory array area sequentially distributed along a second direction; When the logic chip (10) and the first memory chip (31) are stacked in a back-to-back manner, and the second axis of the logic chip (10) and each of the memory chips (30) extends along the first direction, The i+1th channel signal area (11, 12, 13, 14) in the logic chip (10) is aligned along a third direction with the channel signal area (11, 12, 13, 14) in the i+1th channel of the first memory chip (31), the channel signal area (11, 12, 13, 14) in the mith channel of the second memory chip (32), the channel signal area (11, 12, 13, 14) in the mith channel of the third memory chip (33), and the channel signal area (11, 12, 13, 14) in the i+1th channel of the fourth memory chip (34); wherein i is a natural number less than m.

18. The chip stacking structure (40) according to claim 16 or 17, wherein: The channel signal areas (11, 12, 13, 14) in each of the channels are divided into 2×2 signal areas distributed in an array; Only for the plurality of channel signal regions (11, 12, 13, 14) aligned along the third direction: The fourth signal area (24) belonging to the logic chip (10), the first signal area (21) belonging to the first memory chip (31), the second signal area (22) belonging to the second memory chip (32), the third signal area (23) belonging to the third memory chip (33), and the fourth signal area (24) belonging to the fourth memory chip (34) are aligned along a third direction; The third signal area (23) belonging to the logic chip (10), the second signal area (22) belonging to the first memory chip (31), the first signal area (21) belonging to the second memory chip (32), the fourth signal area (24) belonging to the third memory chip (33), and the third signal area (23) belonging to the fourth memory chip (34) are aligned along a third direction; The second signal area (22) belonging to the logic chip (10), the third signal area (23) belonging to the first memory chip (31), the fourth signal area (24) belonging to the second memory chip (32), the first signal area (21) belonging to the third memory chip (33), and the second signal area (22) belonging to the fourth memory chip (34) are aligned along a third direction; The first signal area (21) belonging to the logic chip (10), the fourth signal area (24) belonging to the first memory chip (31), the third signal area (23) belonging to the second memory chip (32), the second signal area (22) belonging to the third memory chip (33), the first signal area (24) belonging to the fourth memory chip (34), The signal area (21) is aligned along the third direction.

19. The chip stacking structure (40) according to claim 18, wherein: Each of the signal areas includes n conductive via groups with the same distribution positions, and each of the conductive via groups includes a first conductive via, a second conductive via, a third conductive via and a fourth conductive via; Only for the plurality of signal areas aligned along the third direction: The fourth conductive through hole belonging to the logic chip (10), the first conductive through hole belonging to the first memory chip (31), the second conductive through hole belonging to the second memory chip (32), the third conductive through hole belonging to the third memory chip (33), and the fourth conductive through hole belonging to the fourth memory chip (34) are aligned along a third direction; The third conductive through hole belonging to the logic chip (10), the second conductive through hole belonging to the first memory chip (31), the first conductive through hole belonging to the second memory chip (32), the fourth conductive through hole belonging to the third memory chip (33), and the third conductive through hole belonging to the fourth memory chip (34) are aligned along a third direction; The second conductive through hole belonging to the logic chip (10), the third conductive through hole belonging to the first memory chip (31), the fourth conductive through hole belonging to the second memory chip (32), the first conductive through hole belonging to the third memory chip (33), and the second conductive through hole belonging to the fourth memory chip (34) are aligned along a third direction; The first conductive through hole belonging to the logic chip (10), the fourth conductive through hole belonging to the first memory chip (31), the third conductive through hole belonging to the second memory chip (32), the second conductive through hole belonging to the third memory chip (33), and the first conductive through hole belonging to the fourth memory chip (34) are aligned along a third direction; Wherein, a plurality of conductive through holes aligned along the third direction are coupled to form a signal transmission channel.

20. The chip stacking structure (40) according to claim 19, wherein: One of the fourth repair units in the logic chip (10), one of the first repair units in the first memory chip (31), one of the second repair units in the second memory chip (32), one of the third repair units in the third memory chip (33), and one of the fourth repair units in the fourth memory chip (34) are aligned along a third direction, and a conductive through-hole switching operation is performed synchronously; One of the third repair units in the logic chip (10), one of the second repair units in the first memory chip (31), one of the first repair units in the second memory chip (32), one of the fourth repair units in the third memory chip (33), and one of the third repair units in the fourth memory chip (34) are aligned along a third direction, and a conductive through-hole switching operation is performed synchronously; One of the second repair units in the logic chip (10), one of the third repair units in the first memory chip (31), one of the fourth repair units in the second memory chip (32), one of the first repair units in the third memory chip (33), and one of the second repair units in the fourth memory chip (34) are aligned along a third direction, and a conductive through-hole switching operation is performed synchronously; One of the first repair units in the logic chip (10), one of the fourth repair units in the first memory chip (31), one of the third repair units in the second memory chip (32), one of the second repair units in the third memory chip (33), and one of the first repair units in the fourth memory chip (34) are aligned along a third direction, and a conductive through-hole switching operation is performed synchronously.

21. The chip stacking structure (40) according to claim 15, wherein: The logic chip (10) comprises m channel signal areas (11, 12, 13, 14) arranged along a first direction, each of the memory chips (30) has m channels arranged along the first direction, and each of the channels comprises a first memory array area, a channel signal area (11, 12, 13, 14) and a second memory array area sequentially distributed along a second direction; When the logic chip (10) and the first memory chip (31) are stacked back to back, and the first axis of the logic chip (10) and each of the memory chips (30) extends along a first direction, The i+1th channel signal area (11, 12, 13, 14) in the logic chip (10) is aligned along a third direction with the channel signal area (11, 12, 13, 14) in the i+1th channel in the first memory chip (31), the channel signal area (11, 12, 13, 14) in the i+1th channel in the second memory chip (32), the channel signal area (11, 12, 13, 14) in the mith channel in the third memory chip (33), and the channel signal area (11, 12, 13, 14) in the mith channel in the fourth memory chip (34); wherein i is a natural number less than m.

22. The chip stacking structure (40) according to claim 15, wherein: The logic chip (10) comprises m channel signal areas (11, 12, 13, 14) arranged along a first direction, each of the memory chips (30) has m channels arranged along the first direction, and each of the channels comprises a first memory array area, a channel signal area (11, 12, 13, 14) and a second memory array area sequentially distributed along a second direction; When the logic chip (10) and the first memory chip (31) are stacked in a back-to-back manner, and the second axis of the logic chip (10) and each of the memory chips (30) extends along the first direction, The mi-th channel signal area (11, 12, 13, 14) in the logic chip (10) is aligned with the channel signal area (11, 12, 13, 14) in the i+1-th channel in the first memory chip (31), the channel signal area (11, 12, 13, 14) in the mi-th channel in the second memory chip (32), the channel signal area (11, 12, 13, 14) in the mi-th channel in the third memory chip (33), and the channel signal area (11, 12, 13, 14) in the i+1-th channel in the fourth memory chip (34) along a third direction; wherein i is less than m. A natural number.

23. The chip stacking structure (40) according to claim 21 or 22, wherein: The channel signal areas (11, 12, 13, 14) in each of the channels are divided into 2×2 signal areas distributed in an array; Only for the plurality of channel signal regions (11, 12, 13, 14) aligned along the third direction: The second signal area (22) belonging to the logic chip (10), the first signal area (21) belonging to the first memory chip (31), the second signal area (22) belonging to the second memory chip (32), the third signal area (23) belonging to the third memory chip (33), and the fourth signal area (24) belonging to the fourth memory chip (34) are aligned along a third direction; The first signal area (21) belonging to the logic chip (10), the second signal area (22) belonging to the first memory chip (31), the first signal area (21) belonging to the second memory chip (32), the fourth signal area (24) belonging to the third memory chip (33), and the third signal area (23) belonging to the fourth memory chip (34) are aligned along a third direction; The fourth signal area (24) belonging to the logic chip (10), the third signal area (23) belonging to the first memory chip (31), the fourth signal area (24) belonging to the second memory chip (32), the first signal area (21) belonging to the third memory chip (33), and the second signal area (22) belonging to the fourth memory chip (34) are aligned along a third direction; The third signal area (23) belonging to the logic chip (10), the fourth signal area (24) belonging to the first memory chip (31), the third signal area (23) belonging to the second memory chip (32), the second signal area (22) belonging to the third memory chip (33), and the first signal area (21) belonging to the fourth memory chip (34) are aligned along a third direction.

24. The chip stacking structure (40) according to claim 23, wherein: Each of the signal areas includes n conductive via groups with the same distribution positions, and each of the conductive via groups includes a first conductive via, a second conductive via, a third conductive via and a fourth conductive via; For the plurality of signal areas aligned along the third direction: The second conductive through hole belonging to the logic chip (10), the first conductive through hole belonging to the first memory chip (31), the second conductive through hole belonging to the second memory chip (32), the third conductive through hole belonging to the third memory chip (33), and the fourth conductive through hole belonging to the fourth memory chip (34) are aligned along a third direction; The first conductive through hole belonging to the logic chip (10), the second conductive through hole belonging to the first memory chip (31), the first conductive through hole belonging to the second memory chip (32), the fourth conductive through hole belonging to the third memory chip (33), and the third conductive through hole belonging to the fourth memory chip (34) are connected along a third direction. Alignment; The fourth conductive through hole belonging to the logic chip (10), the third conductive through hole belonging to the first memory chip (31), the fourth conductive through hole belonging to the second memory chip (32), the first conductive through hole belonging to the third memory chip (33), and the second conductive through hole belonging to the fourth memory chip (34) are aligned along a third direction; The third conductive through hole belonging to the logic chip (10), the fourth conductive through hole belonging to the first memory chip (31), the third conductive through hole belonging to the second memory chip (32), the second conductive through hole belonging to the third memory chip (33), and the first conductive through hole belonging to the fourth memory chip (34) are aligned along a third direction; Wherein, a plurality of conductive through holes aligned along the third direction are coupled to form a signal transmission channel.

25. The chip stacking structure (40) according to claim 24, wherein: One of the second repair units in the logic chip (10), one of the first repair units in the first memory chip (31), one of the second repair units in the second memory chip (32), one of the third repair units in the third memory chip (33), and one of the fourth repair units in the fourth memory chip (34) are aligned along a third direction, and a conductive through-hole switching operation is performed synchronously; One of the first repair units in the logic chip (10), one of the second repair units in the first memory chip (31), one of the first repair units in the second memory chip (32), one of the fourth repair units in the third memory chip (33), and one of the third repair units in the fourth memory chip (34) are aligned along a third direction, and a conductive through-hole switching operation is performed synchronously; One of the fourth repair units in the logic chip (10), one of the third repair units in the first memory chip (31), one of the fourth repair units in the second memory chip (32), one of the first repair units in the third memory chip (33), and one of the second repair units in the fourth memory chip (34) are aligned along a third direction, and a conductive through-hole switching operation is performed synchronously; One of the third repair units in the logic chip (10), one of the fourth repair units in the first memory chip (31), one of the third repair units in the second memory chip (32), one of the second repair units in the third memory chip (33), and one of the first repair units in the fourth memory chip (34) are aligned along a third direction, and a conductive through-hole switching operation is performed synchronously.

26. The chip stacking structure (40) according to any one of claims 15 to 25, wherein: For two chips connected face to face, the positions where the conductive vias are aligned along the third direction are electrically connected by a hybrid bonding process; for two chips connected back to back or for two chips connected back to face, the positions where the conductive vias are aligned along the third direction are electrically connected by a conductive bump bonding process; or, For two chips connected face to face or two chips connected back to back or two chips connected back to face, the positions of the conductive through holes aligned along the third direction in both chips are electrically connected by a hybrid bonding process; or, For two chips connected face to face or two chips connected back to back or two chips connected back to face, the positions of the conductive through holes aligned along the third direction are both electrically connected through a conductive bump bonding process.

27. A memory (70), comprising the chip stacking structure (40) according to any one of claims 15 to 26.

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