Semiconductor device

Abstract

A channel layer (2), a barrier layer (3), and a cap layer (4) formed on a substrate (1) are formed in this order. N-type first and second contact layers (7, 8) are respectively formed in first and second recesses (5, 6) formed up to a part of the channel layer (2) through the cap layer (4) and the barrier layer (3). A source electrode (9) is formed on the first contact layer (7). A drain electrode (10) is formed on the second contact layer (8). A gate electrode (11) is formed on the cap layer (4) between the source electrode (9) and the drain electrode (10). The cross-sectional shape of the first recess (5) is a reverse taper, and the lateral width of the first contact layer (7) increases toward the bottom of the first recess (5).

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] A nitride semiconductor transistor has been proposed in which a recess is formed under each of the source electrode and the drain electrode, and an n-type contact layer is embedded in the recess to reduce resistance (see, for example, Patent Document 1).

[0003] Japanese Patent Application Publication No. 2019-33155

[0004] Conventionally, recesses have a straight or forward tapered structure, and the impurity concentration of the contact layer formed in such a recess is uniform. The higher the impurity concentration of the contact layer, the lower the resistance can be, but there is a problem in that the breakdown voltage characteristics of the device are reduced.

[0005] The present disclosure has been made to solve the above-mentioned problems, and its object is to obtain a semiconductor device that can achieve both low resistance and improved breakdown voltage characteristics.

[0006] The semiconductor device according to the present disclosure comprises a substrate, a channel layer formed on the substrate, a barrier layer formed on the channel layer, a cap layer formed on the barrier layer, first and second n-type contact layers formed in first and second recesses, respectively, that penetrate the cap layer and the barrier layer to a portion of the channel layer, a source electrode formed on the first contact layer, a drain electrode formed on the second contact layer, and a gate electrode formed on the cap layer between the source electrode and the drain electrode, wherein the cross-sectional shape of the first recess is inversely tapered, and the lateral width of the first contact layer becomes wider toward the bottom of the first recess.

[0007] In the present disclosure, an n-type first contact layer is formed in a first recess having a reverse-tapered cross section. In this case, the first contact layer has a locally higher impurity concentration at the edge of the bottom of the first recess than in other portions. This allows the impurity concentration of the first contact layer near the two-dimensional electron gas layer in the channel layer, which contributes to the electrical conduction of the transistor, to be sufficiently increased to reduce resistance, while maintaining the breakdown voltage without increasing the overall impurity concentration of the first contact layer too much. This allows both low resistance and improved breakdown voltage characteristics to be achieved.

[0008] 1 is a cross-sectional view showing a semiconductor device according to a first embodiment; 2 is a cross-sectional view showing a semiconductor device according to a second embodiment; 3 is a cross-sectional view showing a semiconductor device according to a third embodiment; 4 is a cross-sectional view showing a semiconductor device according to a fourth embodiment; 5 is a cross-sectional view showing a semiconductor device according to a fifth embodiment;

[0009] A semiconductor device according to an embodiment will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

[0010] 1 is a cross-sectional view showing a semiconductor device according to embodiment 1. This semiconductor device is a high electron mobility transistor (HEMT) using a gallium nitride (GaN)-based material.

[0011] The substrate 1 is made of, for example, semi-insulating SiC. A channel layer 2 is formed on the substrate 1. A barrier layer 3 is formed on the channel layer 2. A cap layer 4 is formed on the barrier layer 3. The channel layer 2 and the cap layer 4 are made of, for example, undoped GaN. The barrier layer 3 is made of, for example, undoped AlGaN.

[0012] The first and second recesses 5 and 6 are spaced apart from each other and formed through the cap layer 4 and the barrier layer 3 to reach a part of the channel layer 2. The first and second recesses 5 and 6 are formed by plasma etching. When the voltage (output) of the plasma etching is increased, the cross-sectional shapes of the first and second recesses 5 and 6 become inversely tapered. Specifically, when a voltage five times or more higher than that for making the recesses forwardly tapered is applied, the recesses become inversely tapered.

[0013] N-type first and second contact layers 7 and 8 are formed in the first and second recesses 5 and 6, respectively. The first and second contact layers 7 and 8 are made of, for example, n-type GaN. The n-type dopant is, for example, Si (silicon), Ge (germanium), Te (tellurium), etc. The first and second contact layers 7 and 8 cover the sidewalls of the barrier layer 3 and the sidewalls and upper surface of the channel layer 2 in the first and second recesses 5 and 6. The lateral widths of the first and second recesses 5 and 6 increase toward the bottoms of the first and second recesses 5 and 6. The lateral widths of the first and second contact layers 7 and 8 are, for example, 1 to 100 μm. The impurity concentrations of the first and second contact layers 7 and 8 are 10 １５ ~10 ２０ cm －３ is.

[0014] A source electrode 9 is formed on the first contact layer 7. A drain electrode 10 is formed on the second contact layer 8. The source electrode 9 and the drain electrode 10 are embedded in the first and second recesses 5 and 6, respectively. A gate electrode 11 is formed on the cap layer 4 between the source electrode 9 and the drain electrode 10.

[0015] Here, the first and second contact layers 7 and 8 are grown by chemical vapor deposition (MOCVD) to fill the inversely tapered first and second recesses 5 and 6. During this process, impurities tend to accumulate at the bottom edge portions of the first and second recesses 5 and 6. For this reason, the first contact layer 7 has a high impurity concentration region 12 at the bottom edge portion of the first recess 5, which has a higher impurity concentration than other portions of the first contact layer 7. Note that the impurity concentration in the central portion of the recess bottom is not high. The same applies to the second contact layer 8. A two-dimensional electron gas layer 13 in the channel layer 2 is generated in the vicinity of the high impurity concentration region 12. The impurity concentration of the high impurity concentration region 12 is 1×10 １９ cm －３ When an n-type semiconductor is grown by chemical vapor deposition in a straight or forward tapered recess, the impurity concentration becomes uniform, and it is not possible to form a high impurity concentration region locally.

[0016] As described above, in this embodiment, the n-type first contact layer 7 is formed in the first recess 5 having a reverse-tapered cross section. In this case, the impurity concentration of the first contact layer 7 is locally higher at the edge portion of the bottom of the first recess 5 than in other portions. Therefore, the impurity concentration of the first contact layer 7 near the two-dimensional electron gas layer 13 of the channel layer 2, which contributes to the electrical conduction of the transistor, can be sufficiently increased to reduce the resistance, while maintaining the withstand voltage without increasing the impurity concentration of the entire first contact layer 7 too much. Therefore, it is possible to achieve both low resistance and improved withstand voltage characteristics.

[0017] The cross-sectional shape of the second recess 6 is also inversely tapered, and the width of the second contact layer 8 increases toward the bottom of the second recess 6. This allows the impurity concentration of the second contact layer 8 near the two-dimensional electron gas layer 13 of the channel layer 2 to be sufficiently high, thereby reducing the resistance.

[0018] Second Embodiment Figure 2 is a cross-sectional view showing a semiconductor device according to a second embodiment. In this embodiment, the bottoms of the first and second recesses 5 and 6 are at the same height as the two-dimensional electron gas layer 13. The impurity concentrations of the first and second contact layers 7 and 8 are highest at the edge portions of the bottoms of the first and second recesses 5 and 6. Therefore, the parts of the first and second contact layers 7 and 8 with the highest impurity concentrations can be connected to the two-dimensional electron gas layer 13, thereby achieving a lower resistance than in the first embodiment. The other configurations and effects are the same as those of the first embodiment.

[0019] Third Embodiment. Figure 3 is a cross-sectional view showing a semiconductor device according to a third embodiment. In this embodiment, the first and second contact layers 7 and 8 also cover the sidewalls of the cap layer 4 in the first and second recesses 5 and 6. This makes the film thicknesses of the first and second contact layers 7 and 8 thicker than in the first embodiment, and therefore increases the amount of impurities doped into the first and second contact layers 7 and 8. This suppresses an increase in sheet resistance, making it possible to achieve a lower resistance than in the first embodiment. The other configurations and effects are the same as those of the first embodiment.

[0020] 4 is a cross-sectional view showing a semiconductor device according to a fourth embodiment. In this embodiment, the first and second contact layers 7 and 8 have overlapping portions 14 that extend outside the first and second recesses 5 and 6, respectively, and ride up onto the cap layer 4.

[0021] The width a of the overlap portion 14 is larger than the opening width b of the first and second recesses 5 and 6. That is, the overlap portion 14 is formed on the cap layer 4 with an area larger than the openings of the first and second recesses 5 and 6. This increases the contact area between the first and second contact layers 7 and 8 and the source electrode 9 and drain electrode 10, thereby reducing the contact resistance. However, as the width a of the overlap portion 14 increases, the overlap portion 14 becomes closer to the gate electrode 11, increasing the leakage current to the gate electrode 11. Therefore, the width a of the overlap portion 14 is made smaller than the width c of the bottoms of the first and second recesses 5 and 6.

[0022] Fifth Embodiment Figure 5 is a cross-sectional view showing a semiconductor device according to a fifth embodiment. In this embodiment, the second contact layer 8 covers the sidewall of the cap layer 4 in the second recess 6. The cross-sectional shape of the second recess 6 is forward tapered, and the lateral width of the second contact layer 8 narrows toward the bottom of the second recess 6. When the second recess 6 is forward tapered in this manner, the angle of the corner between the side surface of the second contact layer 8 and the upper surface of the cap layer 4 becomes obtuse. This increases the volume of the epitaxial structure of the cap layer 4 near the corner, mitigating the electric field applied there and improving the breakdown voltage of the element.

[0023] Since electrons flow from the source electrode 9 to the drain electrode 10 during transistor operation, the structure on the source electrode 9 side is dominant in reducing the resistance of the device. Therefore, as in the other embodiments, the first recess 5 on the source electrode 9 side is inversely tapered to reduce the resistance of the first contact layer 7. Other configurations and effects are the same as those of the third embodiment.

[0024] REFERENCE SIGNS LIST 1 substrate, 2 channel layer, 3 barrier layer, 4 cap layer, 5 first recess, 6 second recess, 7 first contact layer, 8 second contact layer, 9 source electrode, 10 drain electrode, 11 gate electrode, 12 high impurity concentration region, 13 two-dimensional electron gas layer, 14 overlapping portion

Claims

1. A semiconductor device comprising: a substrate; a channel layer formed on the substrate; a barrier layer formed on the channel layer; a cap layer formed on the barrier layer; first and second n-type contact layers formed in first and second recesses, respectively, which penetrate the cap layer and the barrier layer to a portion of the channel layer; a source electrode formed on the first contact layer; a drain electrode formed on the second contact layer; and a gate electrode formed on the cap layer between the source electrode and the drain electrode, wherein the cross-sectional shape of the first recess is inversely tapered, and the lateral width of the first contact layer becomes wider toward the bottom of the first recess.

2. The semiconductor device described in claim 1, characterized in that the first contact layer has a high impurity concentration region at the edge portion of the bottom of the first recess, the high impurity concentration region being higher than other portions of the first contact layer, and a two-dimensional electron gas layer in the channel layer is generated in the vicinity of the high impurity concentration region.

3. The impurity concentration of the high impurity concentration region is 1×10 １９ cm －３ 3. The semiconductor device according to claim 2, wherein:

4. A semiconductor device according to any one of claims 1 to 3, characterized in that the bottoms of the first and second recesses are at the same height as a two-dimensional electron gas layer of the channel layer.

5. A semiconductor device according to any one of claims 1 to 4, wherein the first and second contact layers cover side walls of the cap layer within the first and second recesses.

6. The semiconductor device according to claim 5, wherein the first and second contact layers have overlapping portions that extend outside the first and second recesses and onto the cap layer.

7. The semiconductor device according to claim 6, wherein the width of said overlapping portion is larger than the opening width of said first and second recesses and smaller than the width of the bottoms of said first and second recesses.

8. A semiconductor device according to any one of claims 1 to 7, characterized in that the cross-sectional shape of the second recess is inversely tapered, and the lateral width of the second contact layer becomes wider toward the bottom of the second recess.

9. A semiconductor device as described in any one of claims 1 to 7, characterized in that the second contact layer covers a sidewall of the cap layer within the second recess, the cross-sectional shape of the second recess is forward tapered, and the lateral width of the second contact layer narrows toward the bottom of the second recess.

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