Semiconductor storage device, method for manufacturing semiconductor storage device, method for writing storage data, method for reading storage data, and storage system

Abstract

Provided is a semiconductor storage device for STT-MRAM in which the circuit area is reduced to achieve high density. A semiconductor storage device 1000 comprises a memory cell array 10 in which a plurality of memory cells 100 are arranged in rows and columns. Each memory cell 100 includes: a magnetic tunnel junction element capable of data writing by spin transfer torque due to write current; a first electrode of a topological antiferromagnetic material provided so as to supply the write current to the magnetic tunnel junction element; and a switch element SW00 for opening and closing a supply path of the write current to the magnetic tunnel junction element. The semiconductor storage device 1000 further comprises a plurality of first wires WL0, WL1 provided in the row direction of the memory cell array to control the opening / closing of the switch element SW00. The switch element SW00 is a transistor, and an active layer continuously provided in memory cells adjacent to each other in the column direction includes a channel region of each of a plurality of transistors.

Description

Semiconductor memory device, semiconductor memory device manufacturing method, storage data writing method, storage data reading method, storage system

[0001] The present invention relates to a semiconductor memory device using a magnetic tunnel junction element, a method for manufacturing a semiconductor memory device, a method for writing stored data, a method for reading stored data, and a storage system.

[0002] (Background of magnetic random access memory)

[0003] A nonvolatile memory device using a magnetoresistive effect element (MRAM: Magnetic Random Access Memory or Magnetoresistive Random Access Memory) is attracting attention for its application to next-generation logic integrated circuits.

[0004] One example of such an MRAM configuration is known as spin transfer torque (STT) MRAM (see Patent Documents 1 and 2). STT-MRAM is a type of nonvolatile memory that retains information even when power is turned off. It is expected to be used in a wide range of applications, including artificial intelligence (AI), the Internet of Things (IoT), and automotive applications. In STT-MRAM, data is rewritten by passing a current through a storage element called a magnetoresistive tunnel junction (MTJ) element. An MTJ element traditionally has a structure in which two ferromagnetic layers sandwich a tunnel insulating film. The tunnel magnetoresistance effect is a phenomenon in which the resistance to a current flowing through this ferromagnetic layer / tunnel insulating film / ferromagnetic layer structure is small when the magnetic field directions of the two ferromagnetic layers are parallel, and large when they are antiparallel. STT-MRAM operates on the principle of reversing the magnetization direction of an MTJ element using the torque action of electron spin. One direction for the development of STT-MRAM is to replace caches embedded in microprocessors, for example. Current cache memories use volatile memory (SRAM: Static Random Access Memory). Replacing this with non-volatile STT-MRAM will enable the power supply to be shut off more frequently. This will result in a significant reduction in power consumption. Meanwhile, another direction for the development of STT-MRAM is to aim for it to partially replace DRAM (Dynamic Random Access Memory).

[0005] In this situation, antiferromagnetic materials are attracting attention as a replacement for ferromagnetic materials in MRAM, in the hope of further improving device performance. Antiferromagnetic materials have the following advantages: (i) they do not produce stray magnetic fields, allowing for high-density devices with simple structures, (ii) their spin resonance frequency is higher at THz than that of ferromagnetic materials (GHz), enabling higher speeds, and (iii) they offer greater freedom in material selection.

[0006] However, because antiferromagnets do not have spontaneous magnetization, it is generally difficult to detect and control the spontaneous response resulting from the spin structure.

[0007] In contrast, the topological antiferromagnetic metal Mn ３ Sn is being actively researched as a candidate material for nonvolatile memory that will lead to the realization of terahertz electronic devices.

[0008] Mn ３ Sn is an antiferromagnetic material in which a non-collinear spin structure, called the inverse 120-degree structure, appears at temperatures as high as 430 K. This antiferromagnetic spin structure exhibits a macroscopic broken time-reversal symmetry even in a zero-magnetization state, similar to the case of ferromagnetic order. This is due to the strongly ordered spin structure (cluster magnetic octupole) in which six spins, each consisting of three sublattices, are arranged in a two-layer kagome lattice.

[0009] Here, a "topological antiferromagnet" is a Weyl semimetal that exhibits a topological semimetal state in which the interior is semimetallic and the surface is metallic.

[0010] For example, it has been demonstrated that in Weyl antiferromagnets, information can be stored by the direction of a virtual magnetic field, i.e., the distribution of Weyl particles in momentum space, instead of by magnetization.

[0011] JP 2013-214768 A JP 2012-164754 A

[0012] https: / / www.issp.u-tokyo.ac.jp / maincontents / news2.html?pid=10521

[0013] However, conventional STT-MRAMs impose large voltages across the device's tunnel oxide during writes, resulting in a continuous trade-off between data retention, write endurance, and write speed.

[0014] In STT-MRAM, when the MTJ element is miniaturized through integration, it is possible to reduce the write current itself, but at present, it cannot be said that sufficient consideration has been given to the circuit configuration for high integration.

[0015] The present invention has been made to solve the above-mentioned problems, and has an object to provide a semiconductor memory device in an STT-MRAM that can reduce the circuit area and achieve high density.

[0016] Another object of the present invention is to provide a method for writing and reading data in an STT-MRAM, which is a semiconductor memory device that allows a reduction in circuit area.

[0017] Another object of the present invention is to provide a method for manufacturing an STT-MRAM, which is a semiconductor memory device that can reduce the circuit area.

[0018] (Item 1) According to one aspect of the present invention, there is provided a semiconductor memory device comprising: a memory cell array in which a plurality of memory cells are arranged in a matrix; each of the memory cells including: a magnetic tunnel junction element in which data can be written by a spin transfer torque caused by a write current; a first electrode made of a topological antiferromagnet provided to supply the write current to the magnetic tunnel junction element; and a switch element for opening and closing a supply path of the write current to the magnetic tunnel junction element; and further comprising: a plurality of first wirings provided in a row direction of the memory cell array for controlling opening and closing of the switch element; and the switch element is a transistor, and active layers provided continuously in the memory cells adjacent in a column direction include channel regions of each of the plurality of transistors.

[0019] (Item 2) Preferably, in the semiconductor memory device of the configuration of item 1, the magnetic tunnel junction element has a first node and a second node, and the data can be written by the write current flowing between the first node and the second node, and the semiconductor memory device further includes a plurality of second wirings (BL0, BL1) for supplying the write current to the first node (T1) of each of the magnetic tunnel junction elements (MTJ), and a plurality of third wirings (SL) connected to the second nodes of the plurality of magnetic tunnel junction elements (MTJ) via the plurality of transistors (TR001, TR002), respectively, for supplying a reference potential to the memory cell (100).

[0020] (Item 3) Preferably, in the configuration of item 2, the semiconductor memory device further comprises write selection means for selectively conducting the write current to the magnetic tunnel junction element of the selected memory cell to enable writing of data by spin transfer torque, wherein when performing a data write operation to the magnetic tunnel junction element, a predetermined potential difference is applied between the second wiring and the third wiring connected to the magnetic tunnel junction element of a selected memory cell among a plurality of memory cells, and an equipotential is maintained between the second wiring and the third wiring connected to the magnetic tunnel junction element of an unselected memory cell.

[0021] (Item 4) Preferably, in the configuration of item 2 or 3, the semiconductor memory device further comprises read selection means for making it possible to detect a resistance value between the first node and the second node of the selected memory cell, and when performing a data read operation to the magnetic tunnel junction element, a predetermined potential difference is applied between the second wiring and the third wiring connected to the magnetic tunnel junction element of a selected memory cell among the plurality of memory cells, and an equipotential is maintained between the second wiring and the third wiring connected to the magnetic tunnel junction element of an unselected memory cell.

[0022] (Item 5) Preferably, in the semiconductor memory device having the configuration of item 1 or 2, each of the switch elements has a first transistor and a second transistor, and the first transistor and the second transistor are connected in parallel to the magnetic tunnel junction element.

[0023] (Item 6) Preferably, in the semiconductor memory device of item 2 or 3, the plurality of transistors are formed on a semiconductor substrate, trenches are formed in the semiconductor substrate in the column direction of the memory cell array so as to be connectable to source regions of the transistors, and each of the plurality of third interconnections is embedded in the trench.

[0024] (Item 7) Preferably, in the configuration of item 2, the semiconductor memory device further includes strap wiring provided on the plurality of third wirings and connecting the source region of each of the transistors to the third wiring, the strap wiring being formed from the same metal layer as contact layers connecting the magnetic tunnel junction elements to the drain regions of the transistors.

[0025] (Item 8) Preferably, in the semiconductor memory device having the configuration of item 2, the first electrode (LEL) and a wiring that connects the drain region of the transistor are formed as an integrated wiring.

[0026] (Item 9) Preferably, in the semiconductor memory device of item 2, the switch element includes a first transistor, the plurality of second wirings supply a read current to the magnetic tunnel junction element during a read operation, each of the memory cells further includes a second transistor for opening and closing a path of the read current between the corresponding second wiring and the magnetic tunnel junction element, the plurality of first wirings include a write word line that is activated during a write operation of data to the magnetic tunnel junction element and a read word line that is activated during a read operation of data to the magnetic tunnel junction element, and the first transistor is controlled by the write word line, and the second transistor is controlled by the read word line.

[0027] (Item 10) Preferably, in the semiconductor memory device having the configuration of item 2 or 3, the first node of each of the magnetic tunnel junction elements is directly connected to the plurality of second wirings.

[0028] (Item 11) In the semiconductor memory device having the configuration of item 2, preferably, the first electrode is provided so as to be connected to the second node, and the plurality of second wirings are provided in the column direction of the memory cell array.

[0029] (Item 12) Preferably, in the configuration of item 2, the semiconductor memory device further includes a control unit that controls potentials of the plurality of first wirings, the plurality of second wirings, and the plurality of third wirings in a write operation and a read operation.

[0030] (Item 13) According to yet another aspect of the present invention, a storage system includes at least one semiconductor storage device according to item 1 or 2, and further includes a circuit that executes processing based on data stored in the semiconductor storage device.

[0031] (Item 14) According to yet another aspect of the present invention, there is provided a method for manufacturing a semiconductor memory device, the method including the steps of: forming a plurality of rectangular transistor active regions in parallel on a semiconductor substrate; forming a plurality of trench isolation grooves between the rectangular shapes; forming a plurality of word lines for controlling the transistors in a direction perpendicular to the plurality of trench isolation grooves; forming sidewalls on sides of the plurality of word lines to form source and drain regions of the transistors; forming a frame portion for forming a source line in each of the trench isolation grooves; burying a metal in each of the trench isolation grooves to form a source line; and forming a metal layer on an upper portion of the word line to serve as a lower electrode of a magnetic tunnel junction element. a step of forming a lower electrode layer; a step of forming a stacked film that becomes a magnetic tunnel junction element on an upper part of the lower electrode layer; a step of patterning the stacked film that becomes the magnetic tunnel junction element to form the magnetic tunnel junction element; a step of patterning and processing the lower electrode layer so as to leave a region that connects the source line and the source region and a region that connects the drain region and one node of the magnetic tunnel junction element; a step of forming a bit line on an upper part of the word line so as to intersect the word line and connect to the other node of the magnetic tunnel junction element; and a step of forming a connecting wiring layer that connects adjacent word lines among a plurality of the word lines.

[0032] (Item 15) Preferably, in the method for manufacturing a semiconductor memory device according to the configuration of item 14, a lower electrode of a laminated film that becomes the magnetic tunnel junction element and a region that connects the source line and the source region are formed of an integral metal layer.

[0033] (Item 16) According to yet another aspect of the present invention, there is provided a method for writing memory data to a semiconductor memory device as described in Item 2, comprising the steps of: selectively conducting the write current through the magnetic tunnel junction element of a selected memory cell to write memory data by spin transfer torque; and during the step of writing the memory data, applying a predetermined potential difference between the second wiring and the third wiring connected to the magnetic tunnel junction element of a selected memory cell among the plurality of memory cells, and maintaining an equipotential between the second wiring and the third wiring connected to the magnetic tunnel junction element of an unselected memory cell.

[0034] (Item 17) According to yet another aspect of the present invention, there is provided a method for reading stored data from a semiconductor memory device as described in Item 2, comprising the steps of: detecting a resistance value between the first node and the second node of a selected memory cell and reading the stored data; and applying a predetermined potential difference between the second wiring and the third wiring connected to the magnetic tunnel junction element of a selected memory cell among the plurality of memory cells and maintaining an equipotential between the second wiring and the third wiring connected to the magnetic tunnel junction element of an unselected memory cell during the step of reading the stored data.

[0035] According to the configuration of the semiconductor memory device of the present invention, in the STT-MRAM, it is possible to reduce the circuit area and increase the density.

[0036] Furthermore, according to the method for manufacturing a semiconductor memory device of the present invention, it is possible to manufacture an STT-MRAM that can reduce the circuit area and increase the density.

[0037] More specifically, in an STT-MRAM that can reduce the circuit area and increase the density, efficient data reading and writing becomes possible.

[0038] 1 is a conceptual diagram showing the configuration of a magnetic tunnel junction element constituting a memory cell. It is a circuit diagram of a comparative example for explaining the circuit configuration of an MRAM. It is a diagram showing an example of the planar shape of a lower electrode corresponding to an MTJ element in a memory cell, the position of a through-hole for connecting from the lower surface side of the lower electrode to the lower electrode, and the position of the lower surface of the MTJ element on the upper surface side of the lower electrode, in the STT-MRAM structure shown in FIG. 2. It is a diagram showing control of the potential of each signal line in read operation and write operation of the comparative example. It is a conceptual diagram for explaining the configuration of a memory cell array 90 and a circuit for controlling read and write in a semiconductor memory device of the comparative example. It is a circuit diagram for explaining the circuit configuration of a DRAM of the comparative example. It is a diagram showing an example of the layout of a DRAM of the comparative example. It is a circuit diagram for explaining the memory cell array and the circuit configuration of the memory cells in a semiconductor memory device of the first embodiment. It is a diagram showing control of the potential of each signal line in read operation and write operation in the semiconductor memory device of the first embodiment. It is a conceptual diagram for explaining the configuration of a memory cell array and a circuit for controlling read and write in the semiconductor memory device of the first embodiment. It is a plan view of an example of the layout of a memory cell array according to the present embodiment. It shows an example of a plan view and a cross-sectional view of an example of the layout of a memory cell array according to the present embodiment. 1 shows a plan view and a cross-sectional view of a layout of a memory cell array according to a first modification of the first embodiment of the present invention. FIG. 2 shows a plan view and a cross-sectional view of a layout of a memory cell array according to a second modification of the first embodiment of the present invention. FIG. 3 shows a manufacturing process of a semiconductor memory device according to a second modification of the first embodiment of the present invention. FIG. 4 is a circuit diagram for explaining the circuit configuration of a memory cell array and memory cells in a semiconductor memory device according to the second embodiment. FIG. 5 shows control of the potential of each signal line in a read operation and a write operation in the second embodiment. FIG. 6 is a conceptual diagram for explaining the configuration of a memory cell array and a circuit for controlling read and write in a semiconductor memory device according to the second embodiment. FIG. 7 shows a plan view and a cross-sectional view of a layout of a memory cell array according to a first modification of the second embodiment of the present invention. FIG. 8 shows a plan view and a cross-sectional view of a layout of a memory cell array according to a second modification of the second embodiment of the present invention. FIG. 9 shows a manufacturing process of a semiconductor memory device according to a second modification of the second embodiment of the present invention.1 shows a plan view and a cross-sectional view of a layout of a memory cell array according to a third modification of the second embodiment of the present invention. FIG. 2 shows an example of a manufacturing process of a semiconductor memory device according to the third modification of the second embodiment of the present invention. FIG. 3 shows an example of a manufacturing process of a semiconductor memory device according to the third modification of the second embodiment of the present invention. FIG. 4 shows an example of a manufacturing process of a semiconductor memory device according to the third modification of the second embodiment of the present invention. FIG. 5 shows an example of a manufacturing process of a semiconductor memory device according to the third modification of the second embodiment of the present invention. FIG. 6 shows an example of a manufacturing process of a semiconductor memory device according to the third modification of the second embodiment of the present invention. FIG. 7 shows an example of a manufacturing process of a semiconductor memory device according to the third modification of the second embodiment of the present invention.

[0039] The configuration of a semiconductor memory device according to an embodiment of the present invention will be described below. In the following embodiments, components and processing steps denoted by the same reference numerals are the same or equivalent, and unless necessary, their description will not be repeated.

[0040] [Embodiment 1] (Comparative Example of MRAM Circuit Configuration) Preferred embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that in this specification and the drawings, components having substantially the same functional configurations are denoted by the same reference numerals, and, as a general rule, descriptions thereof will not be repeated.

[0041] FIG. 1 is a conceptual diagram showing the configuration of a magnetic tunnel junction element (hereinafter referred to as an "MTJ element") that constitutes a memory cell.

[0042] In this embodiment, in the schematic diagram of the MTJ element shown in FIG. 1 , the rectangle between node T2 and the internal node Tint represents the bottom electrode LEL, and node T1 is the top electrode. Here, the "bottom electrode" is an example of a "first electrode" that passes a write current through that electrode during a write operation of the STT-MRAM. When the MTJ element is inverted as described below, the top electrode provided on the internal node corresponds to the "first electrode." As shown in FIG. 1 , the magnetic tunnel junction element MTJ has node T1 and the internal node Tint. The bottom electrode LEL is provided to be connected to the internal node Tint.

[0043] An MTJ element is formed on the lower electrode LEL via an internal node Tint. The node T1 corresponds to an example of a "first node." The internal node Tint corresponds to an example of a "second node."

[0044] In FIG. 1, the MTJ element is simplified and represented as a variable resistor.

[0045] FIG. 2 is a circuit diagram of a comparative example for explaining the circuit configuration of an MRAM.

[0046] 2 shows an example of a schematic diagram of memory cells 900 in a memory cell array 90. This is only a portion of the memory cells, and in reality, many more memory cells and corresponding signal lines are arranged in both the row and column directions, but these are not shown in FIG.

[0047] As shown in Figure 2, since the STT-type MRAM is a two-terminal element, in principle, a transistor must be placed at each node as a select gate. In this case, two transistors are required per memory cell.

[0048] The configuration of a memory cell 900 including an MTJ element MTJ00 will be described below as an example.

[0049] In contrast, as shown in FIG. 2, for example, by controlling the potential of one of the nodes (CTN002) with a select line that is selectively set to an active potential, it is possible to reduce the number of select transistors per memory cell to one. That is, a select transistor TR001 is provided corresponding to node CTN002. The gate potential of select transistor TR001 is controlled by word line WL0. With this configuration, one MTJ element, one select transistor, and two memory cell nodes can be provided per memory cell 900.

[0050] 3 is a diagram showing an example of the planar shape of the lower electrode LEL corresponding to the MTJ element MTJ00 in the memory cell 900 in the STT-MRAM structure shown in Fig. 2, the position of a through-hole for connection from the lower surface side of the lower electrode LEL to the lower electrode LEL (the portion connecting to the second node of the lower electrode via the through-hole is called a "contact portion"), and the position of the lower surface of the MTJ element on the upper surface side of the lower electrode LEL. Therefore, Fig. 3 virtually shows the state in which the lower surface of the MTJ element MTJ00 is viewed from the lower surface side of the lower electrode LEL through the lower electrode LEL.

[0051] As shown in FIG. 3, a through-hole is located directly below the lower electrode LEL so that a current flows in the vertical direction of the MTJ element MTJ00.

[0052] In the following description, the term "MTJ element (magnetic tunnel junction element)" refers to an element having a structure in which two ferromagnetic layers sandwich a tunnel insulating film. The resistance to a current passing through this ferromagnetic layer / tunnel insulating film / ferromagnetic layer structure is small when the magnetic field directions of the two ferromagnetic layers are parallel, and large when they are antiparallel, due to the tunnel magnetoresistance effect.

[0053] In an MTJ element, the direction of one of the two magnetic layers sandwiching the tunnel insulating film is fixed. This magnetic layer is called the "pinned layer." The direction of the other magnetic layer can be changed to be parallel or anti-parallel to the magnetic field direction of the magnetic layer of the pinned layer, selectively setting the resistance of the MTJ element to either low or high. This magnetic layer is called the "free layer."

[0054] Although the stacked structure of the MTJ element shown in FIGS. 1 to 3 is not particularly limited, in each embodiment described later, for example, a stacked structure of CoFeB / MgO / CoFeB is formed as a conventional ferromagnetic layer / tunnel insulating film / ferromagnetic layer, and further, a Mn ３ The structure is such that a Sn layer is provided. The Mn layer is provided under the CoFeB layer on the free layer side. ３ Preferably, the alloy is a non-collinear antiferromagnetic material, such as Sn, and has a chiral spin structure.

[0055] As mentioned above, the magnetic spin Hall effect ３ Surface spin accumulation occurs on the surface of Sn, which can generate spin torque on the magnetization of the adjacent ferromagnetic material. ３ It is believed that Sn has a structure that assists the spin reversal of the CoFeB in the free layer. As a result, the current density required for spin reversal can be reduced. This allows the advantages of the memory cell and memory array structures according to each embodiment to be further utilized.

[0056] The lower electrode of the MTJ element can be made of, for example, tungsten (W). However, the metal for the electrode is not limited to this. As for the antiferromagnetic material, any (non)collinear antiferromagnetic material that produces the anomalous Hall effect, such as Mn ３ The non-collinear antiferromagnetic material is not limited to Sn. For example, Mn ３ Ga, Mn ３ The ferromagnetic layer is not limited to CoFeB, and may be made of CoFe, for example. The tunnel insulating film (barrier layer) may be made of AlO, in addition to MgO. ｘ , TiO ｘ etc. may also be used.

[0057] Furthermore, the structure of the MTJ element is not particularly limited to the above configuration. For example, a non-collinear antiferromagnetic material (e.g., Mn ３ The MTJ element may have a structure in which Sn) is used as the free layer and / or the fixed layer.

[0058] FIG. 4 is a diagram showing control of the potential of each signal line in read and write operations in a comparative example.

[0059] FIG. 5 is a conceptual diagram for explaining the configuration of a memory cell array 90 and a circuit for controlling reading and writing in a semiconductor memory device 9000 of the comparative example.

[0060] 3 to 5 are diagrams showing an example of a comparative example. As shown in the figures, the STT-MRAM structure of the comparative example requires a large current for rewriting. Therefore, simply using the circuit pattern of a DRAM would result in a larger channel width for the transistor used to control the current in the memory cell, which would increase the memory cell area. Therefore, when considering replacing DRAM with STT-MRAM, circuit innovations are required to satisfy the specifications.

[0061] First, referring to FIG. 5, a semiconductor memory device 9000 includes a memory cell array 90, a row decoder 9030 for controlling the reading and writing of data from each memory cell 900 in the memory cell array 90, a source decoder 9040, a column decoder 9020, and sense amplifiers SA0 to SA1.

[0062] The row decoder 9030 is a decoder that selects and activates the word line WL of the memory cell 900 to be activated. For example, in a write operation to the memory cell 900, the row decoder 9030 selects and activates the word line WL of the memory cell 900 to be written to. For example, in a read operation to the memory cell 900, the row decoder 9030 selects and activates the word line WL of the memory cell 900 to be read from.

[0063] The source decoder 9040 is a decoder that generates a potential of the source line SL0 and controls the potential of the source line SL0. For example, when writing data to a selected memory cell, the source decoder 9040 switches the potential of the source line SL0 of the corresponding row between a high potential (e.g., a power supply potential (Vdd) level) and a low potential (e.g., a ground potential (Gnd) level). For example, when reading data, the source decoder 9040 controls the potential of the source line SL0 to a potential that is 1 / 2 of the power supply potential Vdd (hereinafter, represented by the symbol "1 / 2 Vdd").

[0064] The column decoder 9020 is a decoder that selects and activates a bit line BL for passing a current through a selected memory cell. For example, when writing data to a selected memory cell, the column decoder 9020 selects the bit line BL0 of the corresponding column (column selection) and switches the potential of the bit line BL0 between a high potential (e.g., power supply potential (Vdd) level) and a low potential (e.g., ground potential (Gnd) level) to pass a current through the lower electrode LEL in a direction corresponding to the write data. When reading data, the column decoder 9020 slightly activates the potential of the selected bit line BL0 (e.g., a potential of 1 / 2 the power supply potential Vdd + α (1 / 2 Vdd + α)). The sense amplifiers SA0-SA1 amplify the current flowing from the bit lines BL0-BL1 of the selected memory cell 900 and output it as read data.

[0065] 4 and 5, the control of the potentials of the word line, source line, and bit line during writing and reading in the comparative example will be described.

[0066] In the following description, it is assumed that the memory cell corresponding to the MTJ element MTJ00 is selected.

[0067] (Writing Data "0") First, when writing data "0" to a selected memory cell (Write-0 in FIG. 4), the row decoder 9030 sets the word line WL0 to a selected potential (high potential, for example, power supply potential Vdd). At this time, the source decoder 9040 sets the source line SL0 to an inactive potential (low potential, for example, ground potential GND).

[0068] In this state, the column decoder 9020 sets the bit line BL0 to an active potential (high potential). A current path is formed between the bit line BL0 and the source line SL0, and a current flows from the bit line BL0 to the source line SL0, thereby injecting spins into the MTJ element MTJ00.

[0069] (Writing Data "1") When writing data "1" to a selected memory cell (Write-1 in FIG. 4), the potential of the bit line BL0 and the potential of the source line SL0 are controlled in the opposite manner to when data "0" is written.

[0070] During the data write operation, in unselected memory cells (memory cells to which data is not written; in Figure 4, these are shown as standby state (St-by)), the bit line BL0 and the source line SL0 are maintained at the same potential (for example, a potential that is 1 / 2 of the power supply potential Vdd (1 / 2 Vdd)).

[0071] (Data Reading) When reading data from a selected memory cell, the row decoder 9030 sets the word line WL0 to a selected potential.

[0072] When the column decoder 9020 sets the potential of the bit line BL0 of the selected column to a slightly active potential, a current flows through the MTJ element MTJ00, and a current corresponding to the resistance value of the MTJ element MTJ00 flows through the source line SL0 of the selected column. At this time, the resistance value changes depending on whether the data written to the memory cell is "1" or "0." Therefore, the sense amplifier SA0 detects the current value of the source line SL0, thereby reading out the data.

[0073] (Circuit Configuration of DRAM of Comparative Example) The circuit configuration of the DRAM of the comparative example will be described with reference to FIGS. 6 and 7. FIG. 6 is a circuit diagram for explaining the circuit configuration of the DRAM of the comparative example. FIG. 7 is a diagram showing an example of the layout of the DRAM of the comparative example. In FIGS. 6 and 7, the word line direction is the row direction of the memory cell array 80, and the bit line direction is the column direction of the memory cell array 80. In FIG. 7, the bit line BL is omitted. In FIG. 7, contact CPCN indicates a contact to the capacitor CP. Contact BLCN indicates a contact to the bit line BL.

[0074] 6 shows an example of a schematic diagram of memory cells 800 in the memory cell array 80. This is only a portion of the memory cells, and in reality, many more memory cells and corresponding signal lines are arranged in both the row and column directions, but these are not shown in FIG.

[0075] As shown in FIG. 6 , the memory cell array 80 has a plurality of memory cells 800 arranged in a matrix. The memory cell array 80 includes a plurality of word lines WL1 to WL6, a plurality of bit lines BL1 to BL4, a plurality of capacitors CP21, CP41, and a plurality of transistors TR21, TR41. The plurality of word lines WL1 to WL6 are arranged in the row direction of the memory cell array 80. The plurality of bit lines BL1 to BL4 are arranged in the column direction of the memory cell array 80. The plurality of transistors TR21, TR41 are arranged corresponding to the plurality of capacitors CP21, CP41, respectively. This memory cell array 80 is a so-called 1Tr1Cap type (each dotted line frame corresponds to one memory cell).

[0076] The memory cell array 80 writes data by charging or discharging a plurality of capacitors CP21, CP41 corresponding to a plurality of transistors TR21, TR41 selected by a plurality of word lines WL1 to WL6.

[0077] The memory cell array 80 reads data in response to potential changes in the plurality of bit lines BL1 to BL4 corresponding to the selected plurality of transistors TR21 and TR41.

[0078] 7, a plurality of active layers AL are provided in the memory cell array 2. In FIG. 7, the active layers AL are indicated by vertical hatching.

[0079] The term "active layer" refers to a region in a MOS transistor with a semiconductor channel where a channel region in which a depletion layer is controlled by the potential of the gate electrode and where a source region and a drain region are formed on both sides of the gate electrode. Hereinafter, as an example, the term "active layer" in a "bulk planar MOSFET" is defined as a region on the surface side of the semiconductor substrate that includes a channel region under the gate electrode of the transistor and a source region and a drain region formed on both sides of the gate electrode by a technique such as ion implantation using the gate electrode (or the gate electrode and its insulating film sidewalls) as a mask.

[0080] The multiple active layers AL are provided so as to be separated from one another. In the example shown in Figure 7, the multiple active layers AL are arranged at predetermined intervals in the column direction and row direction. Here, the multiple active layers AL are arranged in a lattice pattern, with their positions shifted for each row. In other words, in the memory cell array 80, an element isolation region is provided between adjacent memory cells 100 to electrically isolate the active layers AL.

[0081] As described above, DRAM stores data by accumulating charge in a capacitor. Therefore, its configuration requires the provision of an isolation region. This is because, if an isolation region is not formed, there is a possibility of a "parasitic transistor" occurring that was not intended during design. For example, if a word line WL3 for controlling the gate potential of a transistor located separately from transistors TR21 and TR41 is located in the dotted-line region R31 in FIG. 6, an unintended transistor (parasitic transistor) may occur in the dotted-line region R31 in FIG. 6. If a parasitic transistor occurs, there is a possibility that the data (accumulated charge) stored in the capacitor may be interfered with (destroyed). Therefore, in DRAM, an isolation region is required to suppress the occurrence of parasitic transistors.

[0082] As described above, in the DRAM of the comparative example, it is necessary to provide an isolation region also in the column direction of the memory cell array 80. For this reason, in the DRAM of the comparative example, it is difficult to shorten the length of the memory cells 800 in the column direction. Therefore, it becomes difficult to reduce the circuit area of ​​the memory cells 800.

[0083] Furthermore, in the comparative example DRAM, the word lines generally need to use a boosted voltage. This requires the use of high-voltage transistors. This means that the gate oxide film of the transistors must be thick. However, this may result in a degradation of the transistor characteristics.

[0084] Furthermore, in the DRAM of the comparative example, heat treatment is required in the manufacturing process of the memory cells, which may result in a deterioration in the characteristics of the transistors compared to when no heat treatment is performed.

[0085] As described above, in the semiconductor memory device 9000 of the comparative example, the number of select transistors per memory cell can be reduced to 1. However, the channel width of the select transistor increases, and the circuit area is not sufficiently reduced.

[0086] Furthermore, in the circuit configuration (memory cell array 80) of the DRAM of the comparative example, it is necessary to provide an element isolation region, and therefore the circuit area is not sufficiently reduced.

[0087] In contrast to this, the following describes a circuit configuration in an STT-type MRAM having a memory cell array in which multiple memory cells are arranged in a matrix, in which active layers are provided continuously in adjacent memory cells in the column direction without providing element isolation regions, and which include the channel regions of each of the multiple transistors in the adjacent memory cells, thereby enabling the circuit area to be reduced.

[0088] In the following, a memory cell having an MTJ element MTJ00 in the memory cell array will be described as an example of a selected memory cell.

[0089] That is, as described above, the MTJ element has an internal node connected to the first node CTN0001 and the bottom electrode LEL00. The bottom electrode also has a second node CTN002 for causing a current to flow to the bottom electrode.

[0090] A plurality of first wirings (word lines) for controlling the opening and closing of the switch elements (selection transistors TR001, TR002) are provided in the row direction of the memory cell array, and a plurality of second wirings (bit lines BL0, BL1) for supplying write currents to first nodes CTN0001 of the magnetic tunnel junction elements (MTJ) are provided in the column direction of the memory cell array.

[0091] Then, during write and / or read operations, a plurality of third wirings (source lines SL) are provided in the column direction of the memory cell array 10, each connected to the lower electrode on the second node Tint side of the magnetic tunnel junction element (MTJ) for supplying a reference potential to the memory cell 100.

[0092] Here, the reference potential is a potential that serves as a reference when supplying a write current or detecting a read current in a write operation or a read operation, and is not particularly limited, but as will be described later, can be, for example, the power supply potential Vdd or an intermediate value of the power supply potential (Vdd / 2). However, the value of the reference potential can be changed depending on the circuit configuration, and is not limited to these values.

[0093] In the semiconductor memory device described below, the switch elements are transistors, and the active layers provided continuously in the memory cells adjacent in the column direction include the channel regions of each of the plurality of transistors.

[0094] Each memory cell is provided with a select transistor, and in a write operation, a driver circuit (row decoder) controls the gate potential of the select transistor of a selected memory cell via a corresponding word line to selectively conduct a write current to a magnetic tunnel junction element (MTJ), thereby writing data using spin-orbit torque. The word lines are provided in the row direction of the memory cell array.

[0095] In addition, in a read operation, a driver circuit (row decoder) controls the gate potential of the select transistor of a selected memory cell via a corresponding word line, thereby making it possible to detect the resistance between the first node CTN001 and the second node (internal node Tint) of the selected memory cell. A sense amplifier detects the resistance of the memory cell via second wiring (bit lines BL0 and BL1) provided corresponding to the selected memory cell, and data is read out.

[0096] First Embodiment FIG. 8 is a circuit diagram for explaining the circuit configuration of a memory cell array 10 and a memory cell 100 of a semiconductor memory device 1000 according to a first embodiment.

[0097] As in FIG. 2, FIG. 8 shows only a portion of the memory cells, and although in reality many more memory cells and corresponding signal lines are arranged in both the row and column directions, they are not shown in FIG. 8.

[0098] FIG. 9 is a diagram showing control of the potential of each signal line in the read operation and the write operation according to the first embodiment.

[0099] FIG. 10 is a conceptual diagram illustrating the configuration of memory cell array 10 and circuits for controlling reading and writing in semiconductor memory device 1000 according to the first embodiment.

[0100] Here again, the selected memory cell will be described by taking the memory cell 100 having the MTJ element MTJ00 in the memory cell array 10 as an example.

[0101] 8 and 10, a semiconductor memory device 1000 includes a memory cell array 10. The memory cell array 10 includes a plurality of memory cells 100 arranged in a matrix. The semiconductor memory device 1000 includes a plurality of bit lines BL0-BL1 arranged in the column direction of the memory cell array 10 and commonly connected to first nodes of the memory cells, a column decoder 1020 for selectively driving the bit line potential, a plurality of word lines WL0-WL1 arranged in the row direction of the memory cell array and set to an active potential in response to row selection, a row decoder 1030 for selectively driving the potential of the corresponding word lines WL0-WL1 in response to the row selection, a plurality of source lines SL, and a source decoder 1040 for generating a potential on the source lines SL to control the potential of the source lines SL. The word lines WL0-WL1 correspond to an example of a "first wiring." The bit lines BL0-BL1 correspond to an example of a "second wiring." The source line SL corresponds to an example of a "third wiring."

[0102] The memory cell 100 includes an MTJ element (magnetic tunnel junction element) MTJ00, a bottom electrode LEL00, and a switch element SW00. The other memory cells also include MTJ elements MTJ01 to MTJ11, bottom electrodes LEL01 to LEL11, and switch elements SW01 to SW11, respectively. Hereinafter, the MTJ elements MTJ00 to MTJ11 will be collectively referred to as the "MTJ element MTJ," the bottom electrodes LEL00 to LEL11 will be collectively referred to as the "bottom electrode LEL," and the switch elements SW00 to SW11 will be collectively referred to as the "switch element SW."

[0103] The MTJ element (magnetic tunnel junction element) MTJ can write data by spin transfer torque (STT) caused by a write current. Specifically, the MTJ element (magnetic tunnel junction element) MTJ can write data by a write current flowing between node T1 and internal node Tint. The lower electrode LEL is provided to supply a write current to the MTJ element MTJ. The MTJ element MTJ is a topological antiferromagnet. Using an MTJ element MTJ using a topological material can reduce the rewrite current. This allows the channel width of the transistor to be reduced. Furthermore, since the rewrite current can be reduced, a potential change can be applied to the BL, and the SL side can be set to a reference potential (e.g., Vdd / 2).

[0104] The switch element SW is an element for opening and closing a supply path of a write current to the MTJ element MTJ. In this embodiment, the switch element SW is a transistor. In this embodiment, the multiple memory cells 100 each include a switch element SW00, a switch element SW01, a switch element SW10, and a switch element SW11. Each switch element SW includes a first transistor and a second transistor as a selection transistor. For example, the switch element SW00 includes a transistor TR001 as the first transistor and a transistor TR002 as the second transistor. The first transistor and the second transistor are arranged in parallel between an internal node of the MTJ element MTJ00 and the source line SL. The other memory cells 100 include transistors TR101 and TR102, transistors TR011 and TR012, and transistors TR111 and TR112, respectively. In this specification, transistors TR001, TR002, TR101, TR102, TR011, TR012, TR111, and TR112 may be collectively referred to as transistor TR. In this manner, in this embodiment, the total channel width of the select transistors can be made smaller than that of the DRAM of the comparative example, and the select transistor is physically divided into two. This can improve the layout of the memory cell array 10. By reducing the required channel width, it is also possible to improve the efficiency of the layout by dividing the select transistor into two, with channels formed on both sides of the contact to the silicon substrate of the MTJ element.

[0105] The bit lines BL0 to BL1 are wirings for supplying a write current to the node T1 of each MTJ element MTJ. The bit lines BL0 to BL1 are arranged in the column direction of the memory cell array 10.

[0106] The word lines WL0 to WL1 are wirings for controlling the opening and closing of the switch elements SW.

[0107] The plurality of source lines SL are connected to the internal nodes Tint of the plurality of MTJ elements MTJ via the plurality of transistors TR. For example, the source line SL is connected to the internal node Tint of the MTJ element MTJ00 via the transistors TR001 and TR002. The plurality of source lines SL are wirings for supplying a reference potential to the memory cell 100. The plurality of source lines SL include a plurality of row source lines LSL and a plurality of column source lines RSL. Each of the plurality of row source lines LSL extends in the row direction. One end of each of the plurality of row source lines LSL is connected to the source decoder 1040. Each of the plurality of column source lines RSL extends in the column direction. The row source lines LSL and the column source lines RSL intersect. Here, the row source lines LSL and the column source lines RSL are orthogonal to each other. In FIGS. 8 and 10 , they are electrically connected to each other at the intersections. In this embodiment, the source lines SL are arranged in a lattice pattern. 8 and 10, the source line SL is provided in a grid pattern common to the multiple memory cells shown. However, if the multiple memory cells are configured to be divided into multiple sections, the source line SL may be separate for each section. By connecting the source lines SL of the entire memory cell array or within the same section to each other, it is possible to suppress voltage fluctuations in the source SL caused by current flow when the bit line BL is connected to the MTJ element of the selected memory cell.

[0108] The transistor TR is connected to the bottom electrode LEL of the MTJ element. For example, the transistors TR001 and TR002 are connected to the bottom electrode LEL00 of the MTJ element MTJ00. The transistor TR opens and closes a supply path for a write current to the MTJ element. The multiple transistors TR include a first transistor and a second transistor.

[0109] 8 and 10, the semiconductor memory device 1000 includes a read selection circuit that enables detection of the resistance value between the node T1 and the internal node Tint of the selected memory cell 100. More specifically, as the read selection circuit, the semiconductor memory device 1000 includes bit lines BL0 to BL1, a column decoder 1020, a row decoder 1030, a source decoder 1040, switch elements SW00, SW01, SW10, and SW11, a plurality of word lines WL0 to WL1, a plurality of bit lines BL0 to BL1, and a plurality of source lines SL.

[0110] The semiconductor memory device 1000 includes a write selection circuit for selectively conducting a write current to the MTJ element MTJ of a selected memory cell 100, thereby enabling data to be written by spin transfer torque (STT). More specifically, the write selection circuit of the semiconductor memory device 1000 includes bit lines BL0 to BL1, a column decoder 1020, a row decoder 1030, a source decoder 1040, switch elements SW00, SW01, SW10, and SW11, a plurality of word lines WL0 to WL1, a plurality of bit lines BL0 to BL1, and a plurality of source lines SL.

[0111] The column decoder 1020, row decoder 1030, and source decoder 1040 of the semiconductor memory device 1000 are collectively referred to as a control unit. The control unit controls the potentials of a plurality of word lines WL0 and WL1, a plurality of bit lines BL0 and BL1, and a plurality of source lines SL in write and read operations.

[0112] The other configuration is the same as that described with reference to FIG. 2, and therefore description thereof will not be repeated.

[0113] 9 and 10, the control of the potentials of the word line, source line, and bit line during writing and reading will be described.

[0114] In the following description, it is assumed that the memory cell corresponding to the MTJ element MTJ00 is selected.

[0115] (Writing Data "0") First, when writing data "0" to a selected memory cell (Write-0 in FIG. 9), the row decoder 1030 sets the word line WL0 to a selected potential (high potential, for example, power supply potential Vdd).

[0116] In this state, the column decoder 1020 sets the bit line BL0 to an active potential (high potential, for example, the power supply potential Vdd), and the source decoder 1040 sets the source line SL to an inactive potential (for example, a potential that is 1 / 2 the power supply potential Vdd (1 / 2·Vdd)) with respect to the bit line BL0. That is, when writing data of MTJ00 to the MTJ element, a predetermined potential difference is applied between the bit line BL0 and the source line SL connected to the MTJ element MTJ00 of a selected memory cell 100 out of the multiple memory cells 100. As a result, a current path is formed between the bit line BL0 and the source line SL, and a current flows from the bit line BL0 to the source line SL, thereby injecting spins into the MTJ element MTJ00.

[0117] (Writing Data "1") First, when writing data "1" to a selected memory cell (Write-1 in FIG. 9), the row decoder 1030 sets the word line WL0 to a selected potential (high potential, for example, power supply potential Vdd).

[0118] In this state, the column decoder 1020 sets the bit line BL0 to an inactive potential (low potential, for example, ground potential GND), and the source decoder 1040 sets the source line SL to an active potential (high potential, for example, half the potential of the power supply potential Vdd (1 / 2·Vdd)) with respect to the bit line BL0. That is, when writing data of MTJ00 to the MTJ element, a predetermined potential difference is applied between BL0 and SL, which are connected to the MTJ element MTJ00 of a selected memory cell 100 out of the multiple memory cells 100. As a result, a current path is formed between the bit line BL0 and the source line SL, and a current flows from the source line SL to the bit line BL0, thereby injecting spins into the MTJ element MTJ00.

[0119] During the data write operation, in non-selected memory cells (memory cells to which data is not written; in Figure 9, these are shown as standby state (St-by)), the potential between the bit line BL and the source line SL is maintained at an equal potential (for example, a potential that is 1 / 2 of the power supply potential Vdd (1 / 2 Vdd)).

[0120] (Reading Data) When reading data from a selected memory cell, the column decoder 1020 sets the word line RWL0 to a selected potential (high potential, for example, power supply potential Vdd).

[0121] The column decoder 1020 sets the potential of the bit line BL0 of the selected column to an active potential (for example, ½ the potential of the power supply potential Vdd+α (½·Vdd+α: for example, 0<α<Vdd / 2)) that is slightly higher than the source line SL. That is, when performing a data read operation on the MTJ junction element MTJ, a predetermined potential difference smaller than that during data write is applied between the bit line BL0 connected to the MTJ element MTJ00 of a selected memory cell 100 out of the multiple memory cells 100 and the source line SL. As a result, a current flows through the MTJ element MTJ00, and a current corresponding to the resistance value of the MTJ element MTJ00 flows through the bit line BL0 of the selected column. At this time, the resistance value changes depending on whether the data written to the memory cell is “1” or “0”. Therefore, the sense amplifier SA detects the current value of the bit line BL0, thereby reading out data.

[0122] During the data read operation, in the non-selected memory cells (memory cells from which data is not read; in Figure 9, these are shown as standby state (St-by)), the potential between the bit line BL and the source line SL is maintained at an equal potential (for example, a potential that is 1 / 2 of the power supply potential Vdd (1 / 2 Vdd)).

[0123] (Data Write Procedure in First Embodiment) As described above, the data write procedure in the first embodiment can be summarized as follows.

[0124] The method for writing data to the semiconductor memory device 1000 includes a step of writing data.

[0125] In the step of writing data, a write current is selectively passed through the MTJ element MTJ of the selected memory cell 100, and storage data is written by the spin transfer torque (STT).

[0126] During the step of writing memory data, a predetermined potential difference is applied between the bit lines BL0, BL1 connected to the MTJ element MTJ of a selected memory cell 100 out of the plurality of memory cells 100 and the source line SL, and the bit lines BL0, BL1 connected to the MTJ element MTJ of an unselected memory cell 100 and the source line SL are maintained at an equal potential.

[0127] (Data Read Procedure of First Embodiment) The data read procedure of the first embodiment can be summarized as follows.

[0128] The method for reading data from semiconductor memory device 1000 includes a step of reading data.

[0129] In the configuration of the semiconductor memory device 1000, the source decoder 1040 activates the word line corresponding to the selected memory cell, sets the bit line to a slightly active potential relative to the source line SL, and sets the source line to a potential half the power supply potential Vdd.

[0130] In the step of reading the stored data, the resistance value between the node T1 and the internal node Tint of the selected memory cell 100 is detected.

[0131] During the step of reading stored data, a predetermined potential difference smaller than that during data writing is applied between the bit lines BL0, BL1 connected to the MTJ element MTJ of a selected memory cell 100 out of the multiple memory cells 100 and the source line SL, and an equipotential is maintained between the bit lines BL0, BL1 connected to the MTJ element MTJ of an unselected memory cell and the source line SL.

[0132] Based on the change in the current value of the bit lines BL0 and BL1 connected to the MTJ element MTJ of the selected memory cell 100, the sense amplifier SA reads out the stored data.

[0133] (Layout of First Embodiment) With reference to FIGS. 11 and 12 , an example of the layout of the memory cell array 10 according to this embodiment will be described. FIG. 11 is a plan view of an example of the layout of the memory cell array 10 according to this embodiment. FIG. 12 shows an example of a plan view and a cross-sectional view of an example of the layout of the memory cell array 10 according to this embodiment. In FIG. 11 , a contact SLCN indicates a contact to the source line SL. A contact MTJCN indicates a contact to the MTJ element. In FIG. 11 , a channel width CHW indicates the channel width of the transistor TR defined by the channel region CHR. In FIG. 11 , a channel length CHL indicates the channel length of the channel region CHR defined by the gate length of the transistor TR. In FIGS. 11 and 12 , the source line SL is omitted.

[0134] As shown in FIG. 11 , the memory cell array 10 is a 1MTJ1Tr type (each dotted-line frame corresponds to one memory cell). In the memory cell array 10, the write word line and the read word line are not separate. That is, in the memory cell array 10, the write word line and the read word line are common. In FIG. 11 , the frame enclosed by the dashed line corresponds to the area for one memory cell. The word line WL1 is formed by dividing the channel on both sides of the contact to the silicon substrate of the MTJ element MTJ00. More specifically, the word line WL1 is formed by dividing into word lines WL11 and WL12. The word line WL11 is arranged on the left side of the contact MTJCN of the MTJ element. The word line WL12 is arranged on the right side of the contact MTJCN of the MTJ element. 12, the word line WL11 and the word line WL12 are connected as the word line WL1 (shunt word line) in a layer above the layer in which the word line WL11 and the word line WL12 are arranged. In this specification, the layer in which the word line WL1 is formed may be referred to as a connecting wiring layer.

[0135] A plurality of active layers AL are provided in the memory cell array 10. In Fig. 11, the active layers AL are indicated by vertical hatching. In Fig. 11, the plurality of active layers AL are shown as an active layer AL1, an active layer AL2, and an active layer AL3.

[0136] Each of the multiple active layers AL extends linearly along the column direction. Here, each of the multiple active layers AL extends linearly in a direction perpendicular to the direction in which the word lines WL0, WL1, and WL2 extend. Each of the multiple active layers AL is arranged at a predetermined interval from each other in the row direction. Each of the multiple active layers AL is provided continuously in memory cells 100 adjacent to each other in the column direction. In other words, the active layers AL of memory cells 100 adjacent to each other in the column direction are connected without providing an element isolation region. In other words, the active layers AL of memory cells 100 adjacent to each other in the column direction are integrated. Therefore, there is no gap in the column direction between the active layers AL of adjacent memory cells 100.

[0137] Each of the multiple active layers AL includes a channel region CHR of a transistor TR. For example, in the memory cell 100, the active layer AL2 includes a channel region CHR1 of a transistor TR001 and a channel region CHR2 of a transistor TR002. In the memory cell 100, if the channel length CHL is F, the channel width CHW is F, the separation distance between the active layers AL (the row-direction spacing between the active layers AL) is F, and the column-direction spacing between the word lines WL1 is F, then the row-direction length d1 is 2F and the column-direction length d2 is 4F. Therefore, the area of ​​the memory cell 100 is 8F2. Unlike the comparative example DRAM described with reference to FIGS. 6 and 7, the memory cell array 10 does not require an isolation region for the active layer AL in the column direction. Therefore, it is possible to shorten the spacing between adjacent memory cells 100 in the column direction. As a result, the length of the memory cell 100 in the column direction can be shortened.

[0138] Furthermore, in this embodiment, the transistor manufacturing process does not require heat treatment, as compared to the comparative example DRAM, which requires heat treatment. This improves the transistor characteristics. Therefore, it is possible to reduce the channel width CHW. As a result, the length of the memory cell 100 in the row direction can be reduced.

[0139] As described above, in the memory cell array 10 of this embodiment, the length of the memory cell 100 in both the column direction and the row direction can be made shorter than that of the DRAM of the comparative example. As a result, in the STT-MRAM, the circuit area can be reduced and high density can be achieved. For example, in the memory cell 100 shown in FIG. 10, the length d1 in the row direction is 2F, the length d2 in the column direction is 4F, and the area of ​​the memory cell 100 is 8F2, but the length d1 in the row direction and the length d2 in the column direction can be shortened.

[0140] As described above with reference to FIGS. 1 to 12, in the semiconductor memory device 1000, the switch element SW is a transistor TR, and the active layer AL provided continuously in adjacent memory cells 100 in the column direction includes the channel region CHR of each of the plurality of transistors TR. Therefore, it is not necessary to provide an isolation region for the active layer AL in the column direction. This makes it possible to shorten the spacing between adjacent memory cells 100 in the column direction. As a result, the length of the memory cells 100 in the column direction can be shortened. Therefore, in the STT-MRAM, the circuit area can be reduced, enabling higher density.

[0141] The magnetic tunnel junction element MTJ has a first node (node ​​T1) and a second node (internal node Tint), and data can be written by a write current flowing between the first node (node ​​T1) and the second node (internal node Tint). The semiconductor memory device further includes a plurality of second wirings (bit lines BL0, BL1) for supplying a write current to the first node (node ​​T1) of each magnetic tunnel junction element MTJ, and a plurality of third wirings (source lines SL) connected to supply a reference potential to the second nodes (internal nodes Tint) of the plurality of magnetic tunnel junction elements MTJ via a plurality of transistors (transistors TR001, TR002). Therefore, a potential difference can be applied between the first node (node ​​T1) and the second node (internal node Tint). As a result, desired data can be written to the magnetic tunnel junction element MTJ.

[0142] Furthermore, when performing a data write operation to the magnetic tunnel junction element MTJ, a predetermined potential difference is applied between the second wiring (bit lines BL0 and BL1) and the third wiring (source line SL) connected to the magnetic tunnel junction element MTJ of a selected memory cell 100 among the multiple memory cells 100. Therefore, in the memory cell 100 to which data is written, a current path is formed between the second wiring (bit lines BL0 and BL1) and the third wiring (source line SL), and a current flows from the second wiring (bit lines BL0 and BL1) to the third wiring (source line SL), thereby injecting spins into the MTJ element MTJ00. As a result, data is written to the memory cell 100 to which data is written. Meanwhile, the second wiring (bit lines BL0 and BL1) and the third wiring (source line SL) connected to the magnetic tunnel junction element MTJ of an unselected memory cell are maintained at an equipotential. Therefore, in the memory cell 100 to which data is not written, no current flows from the second wiring (bit lines BL0 and BL1) to the third wiring (source line SL). In this way, data can be written to the selected memory cell 100 while reducing the memory cell area and power consumption.

[0143] Furthermore, when performing a data read operation on the magnetic tunnel junction element MTJ, a predetermined potential difference smaller than that during data write is applied between the second wiring (bit lines BL0 and BL1) and the third wiring (source line SL) connected to the magnetic tunnel junction element MTJ of a selected memory cell 100 among the multiple memory cells 100. Therefore, stored data can be read based on a change in the current value of the bit lines BL0 and BL1 connected to the magnetic tunnel junction element MTJ of the selected memory cell 100. Meanwhile, the second wiring (BL0 and BL1) and the third wiring (SL) connected to the magnetic tunnel junction elements of unselected memory cells are maintained at an equipotential. Therefore, in the memory cell 100 to which data is not written, no current flows through the second wiring (bit lines BL0 and BL1). In this way, data can be read from the selected memory cell 100 while reducing the memory cell area and power consumption.

[0144] The first transistor TR001 and the second transistor TR002 are connected in parallel to the magnetic tunnel junction element MTJ, so that the necessary write current can be passed through the memory cell 100 while preventing the channel width of the transistor from increasing.

[0145] (First Modification of First Embodiment) A semiconductor memory device 1000 according to a first modification of the first embodiment of the present invention will be described with reference to Figure 13. Figure 13 shows a plan view and a cross-sectional view of the layout of the memory cell array 10 according to the first modification of the first embodiment of the present invention. The semiconductor memory device 1000 according to the first modification of the first embodiment has a similar configuration to the semiconductor memory device 1000 according to the first embodiment, except that the source lines SL are embedded in the trenches TL and the semiconductor memory device 1000 includes strap wirings ST, and therefore a description of the overlapping parts will be omitted.

[0146] As shown in FIG. 13 , multiple transistors TR are formed on a semiconductor substrate S. Trenches TL are formed in the semiconductor substrate S. The trenches TL can be formed, for example, by RIE (Reactive Ion Etching) technology for Si. The trenches TL are formed in the column direction of the memory cell array 10. The trenches TL are formed so as to be connectable to the source regions of the transistors TR. Source lines SL are provided as buried interconnects within the trenches TL. In the first embodiment, as shown in FIG. 12 , the source lines SL are routed upward toward the upper interconnect layer. In this case, the source lines SL must be routed while avoiding the bit lines BL. Therefore, after the first half of the process of forming a conventional silicon semiconductor MOS transistor, the second half of the process of forming an MTJ element must include the source line routing process. In contrast, in this modification, the source lines SL are routed within the trenches TL in the first half of the process. Therefore, the source lines SL do not need to be routed upward, which prevents the circuit area from increasing. As a result, in the STT-MRAM, the circuit area can be reduced and high density can be achieved.

[0147] The semiconductor memory device 1000 includes a strap wiring ST. The strap wiring ST is provided on the source line SL. The strap wiring ST connects the source region of each transistor TR to the source line SL. The strap wiring ST is formed of the same metal layer as the contact layer MTJCN connecting the MTJ element MTJ to the drain region of the transistor TR. The metal is not particularly limited, but tungsten (W), tantalum (Ta), or ruthenium (Ru), for example, can be used. Therefore, the source line SL can be connected to the source region of each transistor TR via the strap wiring ST. This eliminates the need to pull the source line SL upward.

[0148] (Second Modification of First Embodiment) A semiconductor memory device 1000 according to a second modification of the first embodiment of the present invention will be described with reference to Fig. 14. Fig. 14 shows a plan view and a cross-sectional view of the layout of the memory cell array 10 according to the second modification of the first embodiment of the present invention. The semiconductor memory device 1000 according to the second modification of the first embodiment has a similar configuration to the semiconductor memory device 1000 according to the first modification of the first embodiment, except that the wiring connecting the lower electrode LEL and the drain region of the transistor TR is formed as an integrated wiring, and therefore a description of the overlapping parts will be omitted.

[0149] 14, in the semiconductor memory device 1000 according to the second modification of the first embodiment of the present invention, the wiring connecting the lower electrode LEL and the drain region of the transistor TR is formed as an integrated wiring. Therefore, the area above the contact with the source line SL can be made larger. This allows the size of the memory cell 100 to be further reduced.

[0150] A manufacturing process of semiconductor memory device 1000 according to the second modification of the first embodiment of the present invention will be described with reference to Figure 15. Figure 15 is a diagram showing a manufacturing process of semiconductor memory device 1000 according to the second modification of the first embodiment of the present invention.

[0151] 15, first, a gate oxide film is formed on a Si substrate, and then a gate electrode layer and an insulating film layer (for example, a SiO layer) are formed, and then lithography and anisotropic etching are performed to form a pattern in which an insulating layer is stacked on the gates of word lines WL11 and WL12 in step S101. Then, an insulating film (for example, a SiO film) is again formed by deposition on the word line pattern, and anisotropic etching is performed to form sidewall insulating films IF1 on the side walls of word lines WL11 and WL12 while leaving the insulating film on the top of the word lines WL11 and WL12.

[0152] Next, in step S102, a metal wiring layer M1 is formed. The metal may be, for example, tungsten (W), tantalum (Ta), or ruthenium (Ru). The top surface of the wiring layer M1 is then planarized by, for example, chemical mechanical polishing (CMP) or the like.

[0153] Next, in step S103, a stacked film MTJF of a magnetic material containing a topological material is formed on the wiring layer M1. Note that the type and stacking method of the MTJ stacked film to be stacked here are not particularly limited. However, as described above, for example, a Mn ３ On the Sn layer, a CoFeB / MgO / CoFeB layer structure is formed. ３ The CoFeB layer immediately above the Sn layer is the free layer.

[0154] Next, in step S104, the MTJ stacked film MTJF is micro-fabricated to form an MTJ element pattern. For example, a resist pattern is formed to form an MTJ element portion on the MTJ stacked film MTJF. Next, the MTJ element MTJ is patterned by etching using the resist as a mask, for example, by RIE. Note that there are various process variations for patterning the MTJ element MTJ, such as reducing damage and taking care of side etching. The etching is stopped at the surface of the wiring layer M1. Next, after positioning an insulating film, anisotropic etching is performed to form an insulating film IF2 on the side of the MTJ element.

[0155] Next, in step S105, the metal layer M1 is patterned to form contact wiring to the lower electrode LEL of the MTJ element MTJ and the drain region of the select transistor, and a strap wiring SL to the source line SL. This short-distance wiring can also be used as short-distance wiring in the logic area. After this process, the bit line BL is formed by a known method or the like. [Embodiment 2]

[0156] Second Embodiment A semiconductor memory device 1000 according to a second embodiment of the present invention will be described with reference to FIGS.

[0157] FIG. 16 is a circuit diagram for illustrating the circuit configuration of the memory cell array 20 and the memory cells 200 of the semiconductor memory device 1000 according to the second embodiment.

[0158] As in FIG. 8, FIG. 16 shows only a portion of the memory cells, and although in reality many more memory cells and corresponding signal lines are arranged in both the row and column directions, they are not shown in FIG. 16.

[0159] FIG. 17 is a diagram showing control of the potential of each signal line in the read operation and the write operation according to the second embodiment.

[0160] FIG. 18 is a conceptual diagram illustrating the configuration of memory cell array 10 and circuits for controlling reading and writing in semiconductor memory device 1000 according to the second embodiment.

[0161] Here again, the selected memory cell will be described by taking the memory cell 200 having the MTJ element MTJ00 in the memory cell array 10 as an example.

[0162] 16, the semiconductor memory device 1000 according to the second embodiment is different from the semiconductor memory device 1000 according to the first embodiment mainly in that the transistors TR of the memory cells 200 are separated into those for writing and those for reading. Explanation of portions that overlap with the semiconductor memory device 1000 according to the first embodiment will be omitted. As shown in FIGS. 16 and 18, the memory cell array 20 is of a 1MTJ2Tr type (the dotted line frame corresponds to one memory cell).

[0163] 16 and 18, a semiconductor memory device 2000 includes a memory cell array 20. A plurality of memory cells 200 are arranged in a matrix in the memory cell array 20. The semiconductor memory device 2000 includes a plurality of bit lines BL0 to BL1, a column decoder 2020, a plurality of word lines WL, a plurality of source lines SL, and a source decoder 2040.

[0164] The memory cell 200 includes an MTJ element (magnetic tunnel junction element) MTJ, a lower electrode LEL, and a switch element SW. The switch element SW includes a first transistor as a selection transistor during data write. In this embodiment, the switch element SW00 includes a transistor TR001 as the first transistor. The switch elements SW01, SW10, and SW11 include transistors TR011, TR101, and TR111 as the first transistors, respectively.

[0165] The plurality of bit lines BL0-BL1 supply a read current to the MTJ element MTJ during a read operation. The memory cell 200 further includes a second transistor TR002 as a selection transistor during data read. The other memory cells also include second transistors TR012, TR102, and TR112, respectively. The second transistors TR002, TR012, TR102, and TR112 open and close the read current path between the corresponding source line SL and the MTJ element MTJ. In this embodiment, the second transistor TR002 opens and closes the read current path between the source line SL and the MTJ element MTJ00. The second transistors TR012, TR102, and TR112 open and close the read current path between the source line SL and the corresponding MTJ elements MTJ01, MTJ10, and MTJ11, respectively.

[0166] In this embodiment, as described above, the memory cell 200 is configured to be separated into a write transistor (first transistor) and a read transistor (second transistor).

[0167] The plurality of word lines WL include write word lines WWL0 and WWL1 and read word lines RWL0 and RWL1.

[0168] The write word lines WWL0 and WWL1 are activated to a selection potential when writing data to the MTJ elements MTJ. In this embodiment, the write word line WWL0 is activated when writing data to the MTJ elements MTJ00 and MTJ01. The write word line WWL1 is activated when writing data to the MTJ elements MTJ10 and MTJ11.

[0169] The read word lines RWL0 and RWL1 are activated to a selection potential when a data read operation is performed on the MTJ junction element MTJ. In this embodiment, the read word line RWL0 is activated when a data read operation is performed on the MTJ junction elements MTJ00 and MTJ01. The read word line RWL1 is activated when a data read operation is performed on the MTJ junction elements MTJ10 and MTJ11.

[0170] 17 and 18, the control of the potentials of the word line, source line, and bit line during writing and reading will be described.

[0171] In the following description, it is assumed that the memory cell corresponding to the MTJ element MTJ00 is selected.

[0172] (Writing Data "0") First, when writing data "0" to a selected memory cell (Write-0 in FIG. 17), the row decoder 2030 sets the write word line WWL0 to an active potential (high potential, for example, power supply potential Vdd). On the other hand, the row decoder 2030 sets the read word line RWL0 to an inactive potential (low potential, for example, ground potential GND).

[0173] In this state, the column decoder 2020 sets the bit line BL0 to an active potential (high potential, for example, the power supply potential Vdd), and the source decoder 2040 sets the source line SL to an inactive potential (reference potential, for example, a potential that is 1 / 2 the power supply potential Vdd (1 / 2·Vdd)) with respect to the bit line BL0. That is, when writing data of the MTJ00 to the MTJ element, a predetermined potential difference is applied between the bit line BL0 and the source line SL connected to the MTJ element MTJ00 of a selected memory cell 100 out of the multiple memory cells 100. As a result, a current path is formed between the bit line BL0 and the source line SL, and a current flows from the bit line BL0 to the source line SL, thereby injecting spins into the MTJ element MTJ00. (Writing Data "1") First, when writing data "1" to a selected memory cell (Write-1 in FIG. 17), the row decoder 2030 sets the write word line WWL0 to an active potential (high potential, for example, power supply potential Vdd). On the other hand, the row decoder 2030 sets the read word line RWL0 to an inactive potential (low potential, for example, ground potential GND).

[0174] In this state, the column decoder 2020 sets the bit line BL0 to an inactive potential (low potential, for example, ground potential GND), and the source decoder 2040 sets the source line SL to an active potential (reference potential, for example, half the potential of the power supply potential Vdd (1 / 2·Vdd)) with respect to the bit line BL0. That is, when writing data of MTJ00 to the MTJ element, a predetermined potential difference is applied between the bit line BL0 and the source line SL connected to the MTJ element MTJ00 of a selected memory cell 100 out of the multiple memory cells 100. As a result, a current path is formed between the bit line BL0 and the source line SL, and a current flows from the source line SL to the bit line BL0, thereby injecting spins into the MTJ element MTJ00.

[0175] During the data write operation, in non-selected memory cells (memory cells to which data is not written; in Figure 17, these are shown as standby state (St-by)), the potential between the bit line BL and the source line SL is maintained at an equal potential (for example, a potential that is 1 / 2 of the power supply potential Vdd (1 / 2 Vdd)).

[0176] (Data Reading) When reading data from a selected memory cell, the column decoder 1020 sets the read word line RWL0 to a selected potential. At this time, the source decoder 9040 sets the write word line WWL0 to an inactive potential (low potential, for example, ground potential GND).

[0177] The column decoder 1020 sets the potential of the bit line BL0 of the selected column to a slightly inactive potential (for example, half the potential of the power supply potential Vdd -α (½·Vdd-α)) with respect to the source line SL. In other words, when performing a data read operation on the MTJ junction element MTJ, a predetermined potential difference smaller than that during data write is applied between the bit line BL0 connected to the MTJ element MTJ00 of a selected memory cell 100 out of the multiple memory cells 100 and the source line SL. As a result, a current flows through the MTJ element MTJ00, and a current corresponding to the resistance value of the MTJ element MTJ00 flows through the bit line BL0 of the selected column. At this time, the resistance value changes depending on whether the data written to the memory cell is “1” or “0”. Therefore, the sense amplifier SA detects the current value of the bit line BL0, thereby reading out data.

[0178] During the data read operation, in the non-selected memory cells (memory cells from which data is not read; in Figure 17, this is shown as standby state (St-by)), the potential between the bit line BL0 and the source line SL is maintained at an equipotential (for example, a potential that is 1 / 2 of the power supply potential Vdd (1 / 2 Vdd)).

[0179] In this embodiment, as in the first embodiment, it is not necessary to provide an isolation region for the active layer AL in the column direction. Therefore, it is possible to shorten the interval between adjacent memory cells in the column direction. As a result, the length of the memory cell 100 in the column direction can be shortened. As a result, in the STT-MRAM, it is possible to reduce the circuit area and increase the density.

[0180] In this embodiment, the first transistor TR001 is controlled by the write word line WWL0, and the second transistor TR002 is controlled by the read word line RWL0. Therefore, the potentials can be controlled separately for reading data and writing data.

[0181] (First Modification of Second Embodiment) A semiconductor memory device 1000 according to a first modification of the second embodiment of the present invention will be described with reference to Fig. 19. Fig. 19 shows a plan view and a cross-sectional view of the layout of a memory cell array 20 according to the first modification of the second embodiment of the present invention.

[0182] Variation 1 of Embodiment 2 is a variation corresponding to Variation 1 of Embodiment 1. More specifically, in Variation 1 of Embodiment 2, the source line SL is provided buried in the trench TL, similar to Variation 1 of Embodiment 1. Furthermore, a description of the overlapping portion between the semiconductor memory device 1000 according to Embodiment 2 and the semiconductor memory device 1000 according to Variation 1 of Embodiment 1, in which the semiconductor memory device 1000 includes a strap wiring ST, will be omitted.

[0183] As shown in FIG. 19, the source line SL is provided in the trench TL. Therefore, it is not necessary to pull up the source line SL and wire it. This prevents the circuit area from increasing. As a result, in the STT-MRAM, the circuit area can be reduced and high density can be achieved.

[0184] Furthermore, the semiconductor memory device 1000 according to this modification includes strap wiring ST. Therefore, the source line SL can be connected to the source region of each transistor TR via the strap wiring ST without pulling the source line SL upward. This eliminates the need to pull the source line SL upward. This prevents the circuit area from becoming larger. As a result, the circuit area can be reduced and higher density can be achieved in the STT-MRAM.

[0185] (Second Modification of Second Embodiment) A semiconductor memory device 1000 according to a second modification of the second embodiment of the present invention will be described with reference to Figure 20. Figure 20 shows a plan view and a cross-sectional view of the layout of a memory cell array 20 according to the second modification of the second embodiment of the present invention.

[0186] Variation 2 of Embodiment 2 is a variation corresponding to Variation 2 of Embodiment 1. More specifically, in Variation 2 of Embodiment 2, similar to Variation 2 of Embodiment 1, the wiring connecting the lower electrode LEL and the drain region of the transistor TR is formed as an integrated wiring. Explanation of overlapping parts between the semiconductor memory device 1000 according to Embodiment 2 and the semiconductor memory device 1000 according to Variation 2 of Embodiment 1 will be omitted.

[0187] 20, in the semiconductor memory device 1000 according to the second modification of the first embodiment of the present invention, the wiring connecting the lower electrode LEL and the drain region of the transistor TR is formed as an integrated wiring. Therefore, the area above the contact with the source line SL can be made larger. This allows the size of the memory cell 100 to be further reduced.

[0188] FIG. 21 is a diagram showing a manufacturing process of a semiconductor memory device 1000 according to the second modification of the second embodiment of the present invention.

[0189] 21, a manufacturing process for semiconductor memory device 1000 according to Modification 2 of Embodiment 2 of the present invention will be described. Except for the fact that memory cell 200 transistors TR are manufactured separately for write and read, the manufacturing process for semiconductor memory device 1000 according to Modification 2 of Embodiment 2 of the present invention is the same as the manufacturing process for semiconductor memory device 1000 according to Modification 2 of Embodiment 1 of the present invention, and therefore, a description of overlapping parts will be omitted.

[0190] 21, in step S201, gates of the write word line WWL1 and the read word line RWL1 are formed. Then, an insulating film IF1 is formed around the write word line WWL1 and the read word line RWL1. Thereafter, steps S202 to S205 are the same as steps S102 to S105 shown in FIG.

[0191] 22 is a diagram showing a plan view and a cross-sectional view of a layout of a memory cell array 20 according to a third modification of the second embodiment of the present invention. A semiconductor memory device 1000 according to the third modification of the second embodiment of the present invention will be described with reference to FIG. 22. The semiconductor memory device 1000 according to the third modification of the second embodiment of the present invention has a similar configuration to the semiconductor memory device 1000 according to the second modification of the second embodiment, except that the select transistors connecting the lower electrodes of the MTJ elements to the source lines are separated into those for data writing and those for data reading, and therefore a description of the overlapping parts will be omitted.

[0192] 22, the node T1 of each MTJ element MTJ is directly connected to multiple bit lines BL. The process for forming contacts is omitted, which reduces costs. Furthermore, by omitting the process for openings for forming contacts, damage to the upper part of the MTJ during processing can also be reduced.

[0193] 23 to 33, an example of a manufacturing process for the semiconductor memory device 1000 according to the third modification of the second embodiment of the present invention will be described. Figures 23 to 33 are diagrams showing an example of a manufacturing process for the semiconductor memory device 1000 according to the third modification of the second embodiment of the present invention. In Figures 23 to 33, (a) shows a plan view, and (b) shows a cross-sectional view taken along line A-A'.

[0194] As shown in FIG. 23, in step S301, a plurality of rectangular transistor active regions AL are formed in parallel on a semiconductor substrate S, and a plurality of trench isolation grooves TL are formed between each of the rectangular shapes (isolation groove forming step).

[0195] Next, as shown in FIG. 24, in step S302, a plurality of word lines WWL1, RWL1 for controlling transistors are formed in a direction perpendicular to the plurality of trench isolation grooves TL (word line forming step).

[0196] 25, in step S303, sidewalls (cover insulating films) are formed on the sides of the word lines WWL1 and RWL1 (sidewall formation step), and the source region SR and the drain region DR of the transistor are formed by ion implantation and annealing steps. More specifically, the source region SR and the drain region DR are formed by self-alignment.

[0197] Next, as shown in FIG. 26, in step S304, a frame portion ED for forming a source line SL in each trench isolation groove TL is formed by anisotropic etching after depositing an insulating film (frame portion forming step).

[0198] Next, as shown in FIG. 27, in step S305, a metal is buried in each trench isolation groove TL to form a source line SL (buried source line forming step).

[0199] Next, as shown in FIG. 28, in step S306, a lower electrode layer LEL that will become the lower electrode LEL of the MTJ element MTJ is formed on the word lines WWL1 and RWL1 (lower electrode layer forming step).

[0200] Next, as shown in FIG. 29, in step S307, a stacked film MTJ that becomes the MTJ element MTJ is formed on the lower electrode layer LEL (magnetic tunnel junction element film forming step).

[0201] 30, in step S308, the stacked film MTJ that becomes the magnetic tunnel junction element MTJ is patterned to form the MTJ element MTJ (magnetic tunnel junction element forming step). Etching stops on the lower electrode layer LEL.

[0202] 31, in step S309, the lower electrode film LEL is patterned and processed so as to leave a region ST (strap ST) connecting the source line SL and the source region SR and a region connecting the drain region DR and one node of the MTJ element (strap and lower electrode formation step). The lower electrode of the stacked film MTJ that becomes the MTJ element and the region connecting the source line SL and the source region SR are formed of an integrated metal layer.

[0203] Next, as shown in FIG. 32, in step S310, a bit line BL is formed above the word lines WWL1 and RWL1 so as to intersect with the word lines WWL1 and RWL1 and connect to the other node of the magnetic tunnel junction element (bit line forming step).

[0204] Next, as shown in FIG. 33, in step S311, a connecting wiring layer WWL1 is formed to connect adjacent word lines WWL1 out of the plurality of word lines WWL1 (connecting wiring layer forming step).

[0205] 21 to 33, the method for manufacturing the semiconductor memory device 1000 includes the steps of forming an isolation trench (step S301), forming word lines (step S302), forming sidewalls (step S303), forming a frame portion (step S304), forming buried source lines (step S305), forming a lower electrode layer (step S306), forming a magnetic tunnel junction element film (step S307), forming an MTJ element (step S308), forming a strap and a lower electrode (step S309), forming bit lines (step S310), and forming an interconnect layer (step S311). According to the method for manufacturing the semiconductor memory device 1000, the step of forming contacts is omitted, thereby reducing costs.

[0206] Furthermore, the lower electrode of the stacked film MTJ that becomes the MTJ element and the region connecting the source line SL and the source region SR are formed from a single metal layer, which eliminates the need for a contact formation step and reduces costs.

[0207] (Example of a system including an MRAM described in each embodiment) The semiconductor memory device formed in the manner described in each embodiment above can be used as a memory device for a circuit that performs arithmetic processing of data.

[0208] For example, a central processing unit (CPU) has multiple levels of cache memory. For example, a hierarchical cache memory is typically provided, such as a level 1 (L1) primary cache memory, a level 2 (L2) secondary cache memory, a level 3 (L3) tertiary cache memory, and so on. In this case, cache memory has traditionally been implemented using static random access memory (SRAM). However, SRAM has drawbacks, such as low memory density (each memory cell is composed of six transistors) and relatively high standby power consumption (significant leakage current). Replacing SRAM with MRAM can reduce the silicon area per memory capacity and significantly reduce standby power consumption.

[0209] Therefore, for example, the semiconductor memory device of the MRAM according to each of the above-described embodiments can be employed as a last level cache such as an L3 cache or an L4 cache.

[0210] Furthermore, with the spread of new technologies such as AI, IoT, and 5G, there is a demand for high-speed, highly reliable memory solutions. Therefore, the applications of MRAM are not limited to the above, and it is expected that it will be used as a storage system in fields where high-speed, highly reliable memory is required, such as data storage in industrial automation systems, data storage in medical devices, and data centers.

[0211] According to the configuration of the semiconductor memory device of each embodiment as described above, in the STT-MRAM, it is possible to reduce the circuit area and increase the density.

[0212] Furthermore, according to the method for manufacturing a semiconductor memory device of the embodiment, it is possible to manufacture an STT-MRAM that can reduce the circuit area and increase the density.

[0213] More specifically, by employing the configuration of the semiconductor memory device according to each embodiment, efficient data reading and writing becomes possible in an STT-MRAM that allows for a reduced circuit area and higher density.

[0214] Finally, while various embodiments of the present disclosure have been described, they are presented as examples and are not intended to limit the scope of the invention. The novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. Such embodiments and modifications are intended to be included within the scope and spirit of the invention, as well as within the scope of the inventions and their equivalents as defined in the claims.

[0215] 10, 20 Memory cell array 100, 200 Memory cell 1000 Semiconductor memory device 1020, 2020 Column decoder 1030, 2030 Row decoder 1040, 2040 Source decoder AL, AL1, AL2, AL3 Active layer WL, WL0, WL1 Word line (first wiring) BL, BL0, BL1 Bit line (second wiring) SL Source line (third wiring) LEL Lower electrode (first electrode) MTJ Magnetic tunnel junction element SW, SW00, SW01, SW10, SW11 Switch element CHR, CHR1, CHR2 Channel region T1 Node (first node) Tint Internal node (second node) DR Drain region TR Transistor TR001 First transistor TR002 Second transistor ED Frame ST Strap wiring TL Trench

Claims

1. A semiconductor memory device comprising: a memory cell array in which a plurality of memory cells are arranged in a matrix, each of the memory cells including: a magnetic tunnel junction element in which data can be written by a spin transfer torque caused by a write current; a first electrode which is a topological antiferromagnet arranged to supply the write current to the magnetic tunnel junction element; and a switch element for opening and closing a supply path of the write current to the magnetic tunnel junction element, the semiconductor memory device further comprising a plurality of first wirings arranged in the row direction of the memory cell array for controlling the opening and closing of the switch elements, the switch elements being transistors, and active layers arranged continuously in the memory cells adjacent in the column direction include channel regions of each of the plurality of transistors.

2. The semiconductor memory device according to claim 1, wherein the magnetic tunnel junction element has a first node and a second node, and the data can be written by the write current flowing between the first node and the second node, and the semiconductor memory device further comprises: a plurality of second wirings for supplying the write current to the first node of each of the magnetic tunnel junction elements; and a plurality of third wirings respectively connected to the second nodes of a plurality of the magnetic tunnel junction elements via the plurality of transistors, for supplying a reference potential to the memory cell.

3. The semiconductor memory device according to claim 2, further comprising a write selection means for selectively conducting the write current to the magnetic tunnel junction element of a selected memory cell to enable writing of data by spin transfer torque, wherein when performing a data write operation to the magnetic tunnel junction element, a predetermined potential difference is applied between the second wiring and the third wiring connected to the magnetic tunnel junction element of a selected memory cell among a plurality of memory cells, and an equipotential is maintained between the second wiring and the third wiring connected to the magnetic tunnel junction element of an unselected memory cell.

4. A semiconductor memory device as described in claim 2 or 3, further comprising a read selection means for enabling detection of the resistance value between the first node and the second node of the selected memory cell, wherein when performing a data read operation to the magnetic tunnel junction element, a predetermined potential difference is applied between the second wiring and the third wiring connected to the magnetic tunnel junction element of a selected memory cell among a plurality of memory cells, and an equipotential is maintained between the second wiring and the third wiring connected to the magnetic tunnel junction element of an unselected memory cell.

5. The semiconductor memory device according to claim 1 or 2, wherein each of said switch elements has a first transistor and a second transistor, said first transistor and second transistor being connected in parallel to said magnetic tunnel junction element.

6. A semiconductor memory device as described in claim 2 or 3, wherein a plurality of said transistors are formed on a semiconductor substrate, a trench is formed in said semiconductor substrate in the column direction of said memory cell array so as to be connectable to a source region of each of said transistors, and each of said plurality of third wirings is embedded in said trench.

7. The semiconductor memory device according to claim 6, further comprising a strap wiring provided on said plurality of third wirings and connecting said source region of each of said transistors to said third wirings, said strap wiring being formed from the same metal layer as a contact layer for connecting said magnetic tunnel junction element to the drain region of said transistor.

8. The semiconductor memory device according to claim 2, wherein the wiring connecting said first electrode and the drain region of said transistor is formed as an integral wiring.

9. The semiconductor memory device according to claim 2, wherein the switch element includes a first transistor, the plurality of second wirings supply a read current to the magnetic tunnel junction element during a read operation, each of the memory cells further includes a second transistor for opening and closing a path of a read current between the corresponding second wiring and the magnetic tunnel junction element, the plurality of first wirings include a write word line that is activated during a write operation of data to the magnetic tunnel junction element, and a read word line that is activated when a read operation of data to the magnetic tunnel junction element is performed, the first transistor is controlled by the write word line, and the second transistor is controlled by the read word line.

10. The semiconductor memory device according to claim 2 or 3, wherein said first node of each of said magnetic tunnel junction elements is directly connected to said plurality of second wirings.

11. The semiconductor memory device according to claim 2, wherein the first electrode is provided so as to be connected to the second node, and the plurality of second wirings are provided in a column direction of the memory cell array.

12. The semiconductor memory device according to claim 2, further comprising a control section for controlling potentials of said plurality of first wirings, said plurality of second wirings and said plurality of third wirings in a write operation and a read operation.

13. A storage system comprising at least one semiconductor storage device according to claim 1 or 2, and further comprising a circuit for executing processing based on data stored in said semiconductor storage device.

14. A method for manufacturing a semiconductor memory device, comprising the steps of: forming a plurality of rectangular transistor active regions in parallel on a semiconductor substrate, and forming a plurality of trench isolation grooves between each of the rectangular shapes; forming a plurality of word lines for controlling the transistors in a direction perpendicular to the plurality of trench isolation grooves; forming sidewalls on the sides of the plurality of word lines to form source and drain regions of the transistors; forming a frame portion for forming a source line in each of the trench isolation grooves; embedding metal in each of the trench isolation grooves to form a source line; forming a lower electrode layer that becomes a lower electrode of a magnetic tunnel junction element on an upper portion of the word lines; forming a laminated film that becomes a magnetic tunnel junction element on an upper portion of the lower electrode layer; patterning the laminated film that becomes the magnetic tunnel junction element to form the magnetic tunnel junction element; patterning and processing the lower electrode film layer so as to leave a region connecting the source line and the source region, and a region connecting the drain region and one node of the magnetic tunnel junction element; A method for manufacturing a semiconductor memory device, comprising: a step of forming a bit line above the word line so as to intersect the word line and connect to the other node of the magnetic tunnel junction element; and a step of forming a connecting wiring layer that connects adjacent ones of the plurality of word lines.

15. The method for manufacturing a semiconductor memory device according to claim 14, wherein a lower electrode of the laminated film which becomes the magnetic tunnel junction element and a region which connects the source line and the source region are formed from an integral metal layer.

16. A method for writing memory data to a semiconductor memory device as described in claim 2, comprising the steps of: selectively conducting the write current through the magnetic tunnel junction element of the selected memory cell to write memory data by spin transfer torque; and during the step of writing the memory data, applying a predetermined potential difference between the second wiring and the third wiring connected to the magnetic tunnel junction element of a selected memory cell among the plurality of memory cells, and maintaining an equipotential between the second wiring and the third wiring connected to the magnetic tunnel junction element of an unselected memory cell.

17. A method for reading stored data in a semiconductor memory device as described in claim 2, comprising the steps of: detecting a resistance value between the first node and the second node of a selected memory cell and reading out the stored data; and during the step of reading out the stored data, applying a predetermined potential difference between the second wiring and the third wiring connected to the magnetic tunnel junction element of a selected memory cell among the plurality of memory cells, and maintaining an equal potential between the second wiring and the third wiring connected to the magnetic tunnel junction element of an unselected memory cell.

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