Power supply information communication method and system, electronic device and storage medium

Abstract

The present application provides a power supply information communication method and system, an electronic device and a storage medium, which are applied to at least one server power supply. The at least one server power supply comprising a first switch and a second switch, the first switch comprises a first clock line switch and a first data line switch, and the second switch comprises a second clock line switch and a second data line switch. The method comprises: in response to receiving an access request sent by a baseboard management controller via a first serial communication bus, returning response information to the baseboard management controller via the first serial communication bus, wherein the first serial communication bus comprises a first data line and a first clock line; on the basis of a polling cycle, determining whether working communication with the baseboard management controller is abnormal; and in response to the working communication with the baseboard management controller being abnormal, restoring communication with the baseboard management controller via one of the first serial communication bus and a second serial communication bus and one of the first switch and the second switch.

Description

Power supply information communication method, system, electronic device and storage medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on November 23, 2023, with application number 202311570979.1, and entitled “Communication method, system, electronic device and storage medium for power information”, all contents of which are incorporated by reference in this application. Technical Field

[0003] The present application relates to a method, system, electronic device and storage medium for communicating power information. Background Art

[0004] Server systems constantly need to read various parameters from the server PSU (Power Supply Unit) for power management and system optimization. These parameters can be categorized as voltage, current, temperature, power, fan speed, and more. The server uses a Baseboard Management Controller (BMC) to access the server PSU via the I2C (Inter-Integrated Circuit) Bus (hardware layer). It then uses the IPMI (Intelligent Platform Management Interface) command set (software layer) and the PMBus 1.2 (Power Management Bus) specification to obtain these readings from the server PSU. Figure 1 shows the server PSU and server BMC communication architecture. Numerous components on the I2C Bus are waiting to communicate with the BMC, which uses different addresses to identify the component being addressed. On average, the BMC accesses the component approximately every 10 milliseconds to 2 seconds (depending on the system's I2C Bus polling time) to obtain the required information. I2C Bus communication is bidirectional; a command must be sent before a response is received. However, if neither the PSU nor the BMC sends a request, the PSU will continue to wait for a command. The BMC, having received no response from the PSU, will continue to wait and will not send another command. This phenomenon is known as a "communication failure between the server power supply and the BMC." The BMC will also generate an alarm because it cannot read various parameters from the server PSU.

[0005] Summary of the Invention

[0006] According to an embodiment of the present application, in a first aspect, a method for communicating power supply information is provided, which is applied to at least one server power supply, wherein the at least one server power supply includes a first switch and a second switch, wherein the first switch includes a first clock line switch and a first data line switch, and the second switch includes a second clock line switch and a second data line switch. The method includes:

[0007] In response to receiving an access request sent by the baseboard management controller through the first serial communication bus, returning response information to the baseboard management controller through the first serial communication bus, wherein the first serial communication bus includes a first data line and a first clock line;

[0008] Determine whether the working communication with the baseboard management controller is abnormal according to the polling period set by the user; and

[0009] In response to an abnormality in working communication with the baseboard management controller, communication with the baseboard management controller is restored through one of a first serial communication bus and a second serial communication bus and a group of a first switch and a second switch, wherein the second serial communication bus includes a second data line and a second clock line, the first clock line and the second clock line are connected in parallel; the first data line and the second data line are connected in parallel.

[0010] According to an embodiment of the present application, in a second aspect, a power information communication method applied to a power information communication system is further provided, the method comprising:

[0011] In response to receiving a query instruction sent by the server system, the baseboard management controller determines at least one server power supply according to the query instruction and sends an access request to the at least one server power supply via the first serial communication bus;

[0012] In response to receiving an access request sent by the baseboard management controller through a first serial communication bus, the at least one server power supply returns response information to the baseboard management controller through the first serial communication bus, wherein the first serial communication bus includes a first data line and a first clock line, and the at least one server power supply includes a group of first switches and a group of second switches;

[0013] At least one server power supply determines whether the working communication between the server power supply and the baseboard management controller is abnormal according to a polling period set by the user; and

[0014] In response to an abnormality in working communication with the baseboard management controller, at least one server power supply and the baseboard management controller resume communication through one of a first serial communication bus and a second serial communication bus and a group of a first switch and a second switch, wherein the second serial communication bus includes a second data line and a second clock line, the first clock line and the second clock line are connected in parallel; the first data line and the second data line are connected in parallel.

[0015] According to an embodiment of the present application, in a third aspect, a power information communication system is further provided, the system comprising a baseboard management controller, at least one server power supply, a first serial communication bus, and a second serial communication bus;

[0016] Each of the at least one server power supply includes a set of first switches and a set of second switches; the baseboard management controller includes a set of third switches; and

[0017] The baseboard management controller and at least one server power supply perform working communication via a first serial communication bus, a third switch, and a first switch; the baseboard management controller and at least one server power supply perform working communication via a second serial communication bus, a third switch, and a first switch; the baseboard management controller and at least one server power supply perform interchangeable bilateral bidirectional communication via a second serial communication bus, a third switch, and a second switch, wherein the first serial communication bus includes a first data line and a first clock line, the second serial communication bus includes a second data line and a second clock line, the first clock line and the second clock line are connected in parallel; the first data line and the second data line are connected in parallel.

[0018] According to an embodiment of the present application, in a fourth aspect, a computer device is also provided, comprising a memory, a processor, and computer-readable instructions stored in the memory and executable on the processor, wherein when the processor executes the computer-readable instructions, the method of any one of the embodiments of the first and second aspects described above is implemented.

[0019] According to an embodiment of the present application, in a fifth aspect, a non-volatile computer-readable storage medium is further provided, on which computer-readable instructions are stored. When the computer-readable instructions are executed by a processor, the method of any one of the embodiments of the first and second aspects mentioned above is implemented.

[0020] The details of one or more embodiments of the present application are set forth in the accompanying drawings and the description below. Other features and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0022] FIG1 is a topological diagram of a device interaction system of a server system according to one or more embodiments of the present application;

[0023] FIG2 is a schematic diagram illustrating the communication principle of a single PSU to a BMC system during operation of one or more embodiments of the present application;

[0024] FIG3 is a diagram of a conventional communication architecture for interaction between a BMC and a PSU according to one or more embodiments of the present application;

[0025] FIG4 is a schematic diagram of the steps of a device communication method of a server according to one or more embodiments of the present application;

[0026] FIG5 is a topological diagram of a conventional server system according to one or more embodiments of the present application;

[0027] FIG6 is an example diagram of signal waveforms for normal communication on an I2C bus according to one or more embodiments of the present application;

[0028] FIG7 is a communication architecture diagram of a single PSU and a BMC for normal interaction according to one or more embodiments of the present application;

[0029] FIG8 is a communication architecture diagram of normal interaction between multiple PSUs and a BMC according to one or more embodiments of the present application;

[0030] FIG9 is an example diagram of signal waveforms when communication between the BMC and the PSU is down according to one or more embodiments of the present application;

[0031] FIG10 is a communication architecture diagram of an I2C bus including serially connected components according to one or more embodiments of the present application;

[0032] FIG11 is a communication architecture diagram of an I2C bus including multiple I2C devices according to one or more embodiments of the present application;

[0033] FIG12 is a flowchart illustrating a device communication method for a server according to one or more embodiments of the present application;

[0034] FIG13 is an example diagram of signal waveforms for restoring normal communication between a PSU and a BMC according to one or more embodiments of the present application;

[0035] FIG14 is a diagram of a digital Server PSU communication architecture according to one or more embodiments of the present application;

[0036] FIG15 is a schematic diagram illustrating the communication principle of a single PSU to a BMC system during bilateral communication in accordance with one or more embodiments of the present application;

[0037] FIG16 is a diagram illustrating a communication architecture of a single PSU to BMC system for bilateral exchange according to one or more embodiments of the present application;

[0038] FIG17 is a diagram illustrating a communication architecture of a system for exchanging two-way multiple PSUs to a BMC according to one or more embodiments of the present application;

[0039] FIG18 is a diagram illustrating a bilateral, bidirectional communication architecture of multiple PSUs to a BMC system according to one or more embodiments of the present application;

[0040] FIG19 is an example diagram of an instruction set of the PMB1.2 instruction set according to one or more embodiments of the present application;

[0041] FIG20 is a schematic diagram of an instruction set of an I2C bus status instruction set according to one or more embodiments of the present application;

[0042] FIG21 is a diagram showing the internal structure of a computer device according to one or more embodiments of the present application;

[0043] FIG22 is a schematic diagram of the structure of a non-volatile computer-readable storage medium according to one or more embodiments of the present application. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0045] The system topology provided by the present application is shown in FIG1 , wherein the system includes: a BMC, at least one PSU, and an I2C Bus. The communication function of the I2C Bus is mainly realized through four signal lines: SDA (Serial Data Line), SCL (Serial Clock Line), VCC (Voltage To Current Converter), and GND (Ground). (1) VCC: power supply (2) SDA: serial data line for transmitting data, i.e., data line (3) SCL: serial clock line for transmitting clock sequence, i.e., clock line (4) GND: ground, i.e., ground line. Unlike existing technologies, this system includes two SDAs (first and second data lines) and two SCLs (first and second clock lines). The upper SDA in the figure can be considered the first data line, the lower SDA the second data line, the upper SCL the first clock line, and the lower SCL the second clock line. The two SDAs and two SCLs are connected in parallel. Furthermore, the PSU is equipped with Q1SDAout (first data line switch), Q2SCLout (first clock line switch), Q3SCL'out (second clock line switch), and Q4SDA'out (second data line switch). Q1 and Q3 are connected in series with the first data line, which is equivalent to being connected in series with the second data line. Q2 and Q4 are connected in series with the first clock line, which is equivalent to being connected in series with the second clock line. During normal communication between the BMC and the PSU, as shown in Figure 2, I2C communication between the two is accomplished through the switching of the first data line, the first clock line, and Q1 and Q2. Figure 3 shows the communication architecture between the BMC and PSU. Server systems require power supply redundancy, so two or more server PSUs are present. Many components on the I2C Bus are waiting to communicate with the BMC. The BMC uses different addresses to distinguish the components it is trying to access.

[0046] In some embodiments, as shown in FIG4 , the present application provides a method for communicating power information, which is applied to at least one server power supply. The at least one server power supply includes a first switch and a second switch. The first switch includes a first clock line switch and a first data line switch. The second switch includes a second clock line switch and a second data line switch. The method includes:

[0047] S401, in response to receiving an access request sent by a baseboard management controller through a first serial communication bus, returning response information to the baseboard management controller through the first serial communication bus, wherein the first serial communication bus includes a first data line and a first clock line;

[0048] S402, determining whether the working communication with the baseboard management controller is abnormal according to the polling period set by the user;

[0049] S403. If yes, restore communication with the baseboard management controller through one of the first serial communication bus and the second serial communication bus and a group of the first switch and the second switch, wherein the second serial communication bus includes a second data line and a second clock line, the first clock line and the second clock line are connected in parallel; the first data line and the second data line are connected in parallel.

[0050] Specifically, upon receiving a query instruction from an upstream device, the BMC in the communication system sends an access request to one or more PSUs to obtain the power information of the corresponding PSU. If there is no abnormality in the communication system, at least one PSU receives the access request and returns a response message to the BMC via the I2C Bus (first serial communication bus) containing SDA and SCL. As shown in FIG5 , this is an architecture diagram of the conventional communication hardware layer of the I2C Bus. Normally, when there is no instruction transmission, SDA and SCL are both high levels. When communication is required, the signal is pulled to a low level of 0 to transmit the signal. By comparing FIG1 and FIG5 , it can be seen that, compared with conventional technology, this application needs to create an additional SDA and an SCL on the basis of the original I2C bus, and to add a clock line switch, namely Q3, and a data line switch, Q4, to at least one PSU device. Referencing the signal waveforms during I2C Bus communication in Figure 6, you can see that SDA / SCL are continuously high when not communicating, and continuously generate 0 / 1 signals when communication is active. Within the server PSU, the MCU (Microcontroller Unit) controls Q1, which corresponds to SDA, and Q2, which corresponds to SCL, to complete I2C communication. Figure 7 shows a simplified communication architecture for a single PSU communicating with the BMC in a system, and Figure 8 shows a simplified communication architecture for multiple PSUs communicating with the BMC in a system.

[0051] During this period, the PSU will determine whether there is any abnormality in the working communication between it and the BMC in each polling cycle. Figure 9 shows the waveform when the communication between the server power supply and the BMC is down. From the waveform, we can see that the BMC I2C communication signal is sent, and the PSU I2C communication signal continues to maintain a high level without any change or feedback. In this case, we call it a communication downtime between the PSU and BMC, which is an abnormality.

[0052] In some embodiments, determining whether the working communication with the baseboard management controller is abnormal according to the polling period set by the user includes:

[0053] In response to monitoring that the pin level of the first data line and the pin level of the first clock line are both high, determining whether an access request is received within a polling period;

[0054] If yes, returning response information to the baseboard management controller via the first serial communication bus;

[0055] If not, it is determined that the working communication is abnormal.

[0056] Specifically, the judgment of communication failure between the Server PSU and the BMC mainly refers to two aspects: (1) Whether the pin levels corresponding to SDA and SCL are continuously VCC (high voltage); (2) Whether the Server PSU receives the I2C signal from the BMC within the polling period (for example, 10ms-2S). The polling period can be set by the BMC, with a minimum of 10 milliseconds and a maximum of 2 seconds. When it is determined that the pin level corresponding to the I2C Bus is continuously high and the Server PSU does not receive the I2C signal of the access request sent by the BMC within the polling period, it means that the communication between the Server PSU and the BMC has failed, which is an abnormality. When communication failure occurs, there are two possible reasons for the communication failure: (1) The pull-down (sink) capability of the I2C switch is insufficient, and the switch cannot be pulled down, resulting in the inability to switch between high and low levels and thus unable to communicate. The specific reasons may include excessive capacitance of the series components on the I2C bus path (the first serial communication bus); (2) Deadlock caused by multiple I2C devices on the I2C Bus communication route. As shown in Figure 10, the I2C bus path has serial components connected to it. The reason for communication downtime due to the inability to transition between high and low levels may be due to issues with the system's I2C topology and address avoidance. Mux switching chips are often used, as are I2C hot-swap chips to support hot-swap communication. This can easily lead to excessive capacitance in the I2C Bus path. Furthermore, when operating in server systems with high and low temperatures, certain chips experience temperature fluctuations that alter the physical properties of semiconductor devices, increasing internal stray capacitance. This can cause excessive pull-down current required by the I2C switch, preventing the I2C signal from being pulled low. As shown in Figure 11, multiple I2C devices may cause an I2C Bus communication route deadlock. In addition to abnormal resets and deadlocks, multiple I2C devices can also interfere with each other. Generally, identical slave addresses are not placed on the same bus. However, some I2C devices are not designed according to the standard I2C bus protocol. Even with a shared I2C bus, some devices will respond as long as the slave address is present. This can lead to an erroneous slave response—when the BMC issues an access request and multiple devices simultaneously return responses—causing the I2C bus to become abnormal due to the multiple clock and data signals on the serial communication bus, potentially locking the bus and causing it to enter a deadlock state. This can cause communication between the server power supply and the BMC to cease. Because the BMC fails to receive a response, it waits for a response and does not issue further access requests. Furthermore, the inability to read various server PSU parameters generates alarms, preventing the server power supply from being fully informed. If a problem with the server power supply occurs, maintenance personnel cannot be notified immediately, potentially further risking server system downtime.

[0057] In some embodiments, resuming communication with the baseboard management controller via one of the first serial communication bus and the second serial communication bus and a set of the first switch and the second switch comprises:

[0058] attempting to restore working communication via the first serial communication bus, a first data line switch corresponding to the first data line, and a first clock line switch corresponding to the first clock line;

[0059] in response to a failure in attempting to restore operational communications via the first serial communication bus, the first data line switch, and the first clock line switch, attempting to restore operational communications via the second serial communication bus, the first data line switch, and the first clock line switch;

[0060] In response to a failure in attempting to resume working communications via the second serial communication bus, the first data line switch, and the first clock line switch, reciprocating bilateral bidirectional communications with the baseboard management controller via the second serial communication bus, the second data line switch, and the second clock line switch.

[0061] Specifically, as shown in FIG12 , after determining that the communication is down, the PSU can make multiple attempts to restore the working communication with the BMC through the first serial communication bus and internal Q1 and Q2, where the number threshold is set by the user, for example, 3 times; if the communication is still not restored after 3 times, then the second serial communication bus and internal Q1 and Q2 are used to make multiple attempts to restore the working communication with the BMC; if the communication is still not restored after multiple attempts, because the attempts to restore the working communication through the above operations fail, it means that the communication downtime is not caused by reason (1); at this time, it is necessary to realize the interchange of bilateral bidirectional communication through the second serial communication bus and internal Q3 and Q4.

[0062] In some embodiments, attempting to resume operational communications via the first serial communication bus, the first data line switch, and the first clock line switch includes:

[0063] Turning on the first data line switch to continuously pull down the pin level of the first data line to a low level and turning on the first clock line switch to continuously pull down the pin level of the first clock line to a low level according to a time threshold set by the user;

[0064] determining whether an access request sent by a baseboard management controller is received within a polling period via the first serial communication bus;

[0065] If yes, returning response information to the baseboard management controller via the first serial communication bus;

[0066] If not, continue trying to restore working communication according to the number threshold and the first serial communication bus.

[0067] Specifically, because it is impossible to determine what exactly caused the communication downtime at the beginning, the PSU first turns on the two I2C switches (the first clock line switch and the first data line switch) to keep them grounded to achieve the function of the I2C bus maintaining a low level, that is, the levels of the two pins of the first SDA and the first SCL in the hardware layer are simultaneously pulled to a low level (0V) for 100ms (the time threshold can be set by the user); if the working communication is successfully restored, as shown in FIG13 , the signal waveform returned by the Server PSU to the BMC shows that normal communication with the BMC is restored at this time, and it is determined that the reason is that the capacitance of the series element on the first serial communication bus is too large, resulting in insufficient pull-down (sink) capability of the I2C switch, resulting in the inability to pull down the switch and thus the inability to switch between high and low levels, and the abnormality has been restored; if the communication abnormality is caused by reason (1), the capacitance of the first serial communication bus is repaired by continuously pulling down the level to restart the line. If communication is not restored successfully the first time, the above operation can be tried again for a number of times set by the user, such as 3 times. If normal communication is still not restored after trying the same 3 times, multiple attempts are made to restore working communication with the BMC through the second serial communication bus and internal Q1 and Q2.

[0068] In some embodiments, returning response information to the baseboard management controller via the first serial communication bus includes:

[0069] Returning a clock signal corresponding to the response information via the first clock line and the first clock line switch in the first serial communication bus;

[0070] A data signal corresponding to the response information is returned via the first data line and the first data line switch in the first serial communication bus.

[0071] Specifically, after communication is successfully restored through the above operations, the PSU returns the data signal to the BMC through the first SDA and controls the Q1 action, and returns the clock signal to the BMC through the first SCL and controls the Q2 action.

[0072] In some embodiments, attempting to resume working communication again via the second serial communication bus, the first data line switch, and the first clock line switch includes:

[0073] Turning on the first data line switch according to the time threshold to continuously pull down the pin level of the second data line to a low level, and turning on the first clock line switch to continuously pull down the pin level of the second clock line to a low level;

[0074] determining whether an access request sent by the baseboard management controller is received within a polling period via the second serial communication bus;

[0075] If yes, returning a response message to the baseboard management controller via the second serial communication bus;

[0076] If not, the second serial communication bus continues to try to restore working communication according to the number threshold.

[0077] Specifically, the PSU first turns on Q1 and Q2 so that the second SDA and second SCL pins are simultaneously pulled to a low level (0V) for 100ms (this time threshold can be set by the user). Due to the parallel connection, the two SDA pins have the same level, and the two SCL pins have the same level. If the second serial communication bus successfully receives the I2C signal sent by the BMC and returns the corresponding I2C signal to the BMC, it indicates that the communication between the BMC and the PSU is normal, and that the abnormality of the first serial communication bus, such as excessive capacitance, cannot be repaired. Of course, if the communication is not successfully restored the first time, you can continue to try the user-set threshold, such as 3 times. If normal communication is still not restored after trying the same operation 3 times, it is determined that it is not because the capacitance of the series element on the I2C bus path is too large, causing the I2C switch to have insufficient pull-down (sink) capability, resulting in the inability to pull down the switch and thus the inability to switch between high and low levels. At this time, it is determined that the communication downtime is caused by reason (2).

[0078] In some embodiments, returning response information to the baseboard management controller via the second serial communication bus includes:

[0079] Returning a clock signal corresponding to the response information via the second clock line and the first clock line switch in the second serial communication bus;

[0080] The data signal corresponding to the response information is returned via the second data line and the first data line switch in the second serial communication bus.

[0081] Specifically, after communication is successfully restored through the above operations, the PSU returns the data signal to the BMC through the second SDA and controls the Q1 action, and returns the clock signal to the BMC through the second SCL and controls the Q2 action.

[0082] In some embodiments, performing bilateral communication with a baseboard management controller via a second serial communication bus, a second data line switch, and a second clock line switch includes:

[0083] Turning on the second data line switch according to the time threshold to continuously pull down the pin level of the second clock line to a low level, and turning on the second clock line switch to continuously pull down the pin level of the second data line to a low level;

[0084] In response to receiving the access request sent by the baseboard management controller, response information is returned to the baseboard management controller through the second serial communication bus, the second data line switch and the second clock line switch.

[0085] Specifically, as shown in Figure 14, the internal architecture block diagram of the digital Server PSU, the current Server PSU will use the MCU to complete the converter switch control, fan control, LED control, monitoring, protection, communication and other functions in the power supply. ... The division of labor is divided into the primary side MCU and the secondary side MCU. The main external communication functions are all controlled and implemented by the secondary side MCU. As shown in Figure 15, it is a communication principle diagram of a single PSU with a BMC system for bilateral exchange. Due to the communication downtime caused by reason (2), the MCU continuously turns on Q3 and Q4 so that the second SDA and second SCL pin levels are simultaneously pulled to a low level (0V) for 100ms (the time threshold can be set by the user), which plays a role similar to restarting the line. At this time, the PSU can definitely receive the access request sent by the BMC through the second serial communication bus, and then control the I2C hardware switch action (opening and closing) of Q3 and Q4 and the second serial communication bus containing the second SDA and second SCL to achieve bilateral exchange. At this time, the Q1 and Q2 switches are not in action. In scenarios where the first SDA or the first SCL cannot communicate normally, an additional communication path is provided, allowing multiple slaves (Slaver) to perform cross-communication with the master mode (Master), which is called interchangeable bilateral bidirectional communication, thereby avoiding communication downtime caused by I2C bus deadlock. As shown in Figure 16, it is a communication architecture diagram of interchangeable bilateral bidirectional single PSU to BMC system, as shown in Figure 17, it is a communication architecture diagram of interchangeable bilateral bidirectional multiple PSU to BMC system, as shown in Figure 18, it is a communication architecture diagram of interchangeable bilateral bidirectional multiple PSU to BMC system. In the above scheme, if interchangeable bilateral bidirectional communication is performed between BMC and PSU, Q3 and Q4 need to exist in each PSU. However, BMC and PSU can also use bilateral bidirectional communication, that is, BMC and PSU communicate simultaneously through two serial communication buses. In this case, only one of the PSUs needs to have a pair of Q3 and Q4. In response to receiving a bilateral bidirectional communication instruction sent by the user, the BMC conducts bilateral bidirectional communication with at least one PSU, and the remaining PSUs return response information containing power information to the target PSU with a pair of Q3 and Q4 via the first serial communication bus. The target PSU then returns the response information of the remaining PSUs to the BMC via the second serial communication bus and controls the actions of Q3 and Q4.

[0086] In some embodiments, returning response information to the baseboard management controller through the second serial communication bus, the second data line switch, and the second clock line switch includes:

[0087] Returning a data signal corresponding to the response information via a second clock line and a second data line switch in the second serial communication bus;

[0088] The clock signal corresponding to the response information is returned via the second data line and the second clock line switch in the second serial communication bus.

[0089] Specifically, after communication is successfully restored through the above operations, the PSU returns the clock signal to the BMC through the second SDA and controls the Q3 action, and returns the data signal to the BMC through the second SCL and controls the Q4 action. Because I2C signals sent by other devices can interfere with communication between the PSU and BMC, by exchanging bilateral bidirectional communication, the clock signal is returned on SDA and the data signal is returned on SCL, thereby preventing the data signals transmitted by other devices on SDA from interfering with the clock signal returned by the PSU, and preventing the clock signals transmitted by other devices on SCL from interfering with the data signal returned by the PSU.

[0090] In some embodiments, after returning the response information to the baseboard management controller through the second serial communication bus, the second data line switch, and the second clock line switch, the method further includes:

[0091] Generate communication abnormality information and send the communication abnormality information to the baseboard management controller through the second serial communication bus, the second data line switch and the second clock line switch;

[0092] In response to receiving a restart instruction sent by the baseboard management controller, restarting the input power according to the restart instruction to disconnect the second data line switch and the second clock line switch;

[0093] In response to the completion of restarting the input power, operational communication is performed via the first serial communication bus, the first data line switch, and the first clock line switch.

[0094] Specifically, Figure 19 shows an example of the PMB1.2 instruction set. Using the PMBus1.2 specification, we can define the information fed back to the BMC. In the PMBus1.2 instruction set, the D1h–D3h instructions are reserved for functional expansion. Figure 20 shows a schematic diagram of the I2C bus status instruction set. We can use the D3h address to define and expand functionality. The PSU sends a communication anomaly message containing the D3h address to the BMC. Upon receiving the message, the BMC alerts the user, who then checks other devices on the bus. When the BMC sends a restart command, it indicates that the user has checked all other devices on the bus and sent a restore command to the BMC. The server PSU then restarts its input power. After the server PSU successfully restarts, Q3 and Q4 are automatically disconnected, breaking the link between Q3 and the second SDA and the link between Q4 and the second SCL. Communication with the BMC is then restored via Q1 and the corresponding SDA, and Q2 and the corresponding SCL. That is, the bilateral communication mode can be switched by cutting off the input power to the server PSU. The normal communication path can be restored after powering on again.

[0095] In some embodiments, a method for communicating power information is further provided, which is applied to a baseboard management controller. The baseboard management controller includes a third switch, which includes a third clock line switch and a third data line switch. The method includes:

[0096] In response to receiving a query instruction sent by the server system, determining at least one server power supply according to the query instruction and sending an access request to the at least one server power supply via the first serial communication bus and the third switch;

[0097] In response to receiving response information returned by the at least one server power supply via the first serial communication bus, performing working communication with the at least one server power supply via the first serial communication bus and the third switch;

[0098] In response to receiving response information returned by at least one server power supply through the second serial communication bus, performing reciprocal bilateral communication or working communication with the at least one server power supply through the second serial communication bus and the third switch.

[0099] Specifically, based on system requirements, the BMC needs to poll each server PSU for power supply information within the system polling time. The information can be categorized as voltage, current, temperature, power, fan speed, and more. The server uses the BMC to access the server PSU via the I2C Bus (hardware layer) and obtains these readings from the server PSU via the IPMI command set (software layer) using the PMBus 1.2 specification. When the BMC sends an access request to the server PSU, it transmits the access request data signal to the server PSU via its internal SDA out switch and the first SDA line, and transmits the access request clock signal to the server PSU via its internal SCL out switch and the first SCL line. When the BMC receives a response from the server PSU via the first serial communication bus, communication between the two is normal. If the BMC receives a response from the server PSU via the second serial communication bus, it indicates a fault on the first serial communication bus. The BMC then continues operating communication or bilateral communication with the server PSU via the second serial communication bus.

[0100] In some embodiments, determining at least one server power supply according to the query instruction and sending an access request to the at least one server power supply through the first serial communication bus and the third switch includes:

[0101] Sending a clock signal of an access request to at least one server power supply via a first clock line and a third clock line switch in the first serial communication bus;

[0102] A data signal of an access request is sent to at least one server power supply through a first data line and a third data line switch in the first serial communication bus.

[0103] Specifically, as shown in Figure 2, when the BMC communicates normally with the PSU through the first serial communication bus, the BMC sends a data signal corresponding to the access request to the PSU by controlling its own SDA out switch (the third data line switch) and the first SDA; and sends a clock signal corresponding to the access request to the PSU by controlling its own SCL out switch (the third clock line switch) and the first SCL.

[0104] In some embodiments, performing reciprocal bilateral communication or operational communication with at least one server power supply via the second serial communication bus includes:

[0105] In response to receiving a clock signal of response information through a second clock line in the second serial communication bus and receiving a data signal of response information through a second data line in the second serial communication bus, performing operation communication through the second serial communication bus and the third switch;

[0106] In response to receiving a data signal via a second clock line in the second serial communication bus and receiving a clock signal via a second data line in the second serial communication bus, reciprocating bilateral bidirectional communication is performed via the second serial communication bus and the third switch.

[0107] Specifically, as described above, when the BMC receives the data signal of the response information via the second SDA and the clock signal of the response information via the second SCL, if it needs to obtain power information again during a subsequent system polling cycle, the BMC sends the data signal of the access request via the second SDA in the second serial communication bus and sends the clock signal of the access request via the second SCL in the second serial communication bus, thereby establishing working communication between the two. When the BMC receives the clock signal of the response information via the second SDA and the data signal of the response information via the second SCL, if it needs to obtain power information again during a subsequent system polling cycle, the BMC sends the data signal of the access request via the second SDA and sends the clock signal of the access request via the second SCL, thereby establishing bilateral, exchanging communication between the two.

[0108] In some embodiments, performing bilateral bidirectional communication via the second serial communication bus and the third switch includes:

[0109] In response to receiving the query instruction sent by the server system again, determining at least one server power supply according to the query instruction and sending a data signal of an access request through the second clock line and the third data line switch in the second serial communication bus;

[0110] The clock signal of the access request is sent through the second data line and the third clock line switch in the second serial communication bus.

[0111] Specifically, as shown in Figure 15, after the BMC sends an access request to the PSU through the first serial communication bus, the SDA out switch and the SCL out switch for the last time, and the PSU returns a response message to the BMC in an interchangeable bilateral bidirectional communication manner, if the BMC receives a query instruction again within the query period set by the user, the BMC also changes to an interchangeable bilateral bidirectional communication manner to send an access request to the PSU again, wherein the BMC sends a data signal corresponding to the access request to the PSU by controlling its own SDA out switch (third data line switch) action and the second SCL; and sends a clock signal corresponding to the access request to the PSU by controlling its own SCL out switch (third clock line switch) action and the second SDA; accordingly, at this time, the PSU returns the clock signal to the BMC through the second SDA and controls the Q3 action, and returns the data signal to the BMC through the second SCL and controls the Q4 action. In addition, as mentioned above, when the BMC and the PSU communicate with each other through the second serial communication bus, the BMC still sends the data signal corresponding to the access request to the PSU by controlling its own SDA out switch (third data line switch) and the second SCL; and sends the clock signal corresponding to the access request to the PSU by controlling its own SCL out switch (third clock line switch) and the second SDA; the difference is that at this time, the PSU returns the data signal to the BMC through the second SDA and controls the Q1 action, and returns the clock signal to the BMC through the second SCL and controls the Q2 action.

[0112] In some embodiments, the method further comprises:

[0113] In response to receiving communication abnormality information sent by at least one server power supply via the second serial communication bus, alerting a user based on the communication abnormality information;

[0114] In response to receiving a restore normal communication instruction sent by a user, sending a restart instruction to at least one server power supply via the second serial communication bus and the third switch to restart the at least one server power supply;

[0115] In response to completion of the power cycle of at least one server, operational communication is performed via the first serial communication bus and the third switch.

[0116] Specifically, as described above, when communication abnormality information is received through the second serial communication bus, the BMC can send an alarm message to the server, which then alerts the user. After understanding the information, the user checks the remaining devices connected in series on the serial communication bus. After resolving the problem, the server system sends an instruction to restore normal communication to the BMC. After receiving the instruction, the BMC sends a restart instruction to the Server PSU through the second serial communication bus to restart the Server PSU. After the restart is completed, the two communicate with each other through the first serial communication bus. The specific steps are not repeated here.

[0117] In some embodiments, a power information communication method applied to a power information communication system is further provided, the method comprising:

[0118] In response to receiving a query instruction sent by the server system, the baseboard management controller determines at least one server power supply according to the query instruction and sends an access request to the at least one server power supply via the first serial communication bus;

[0119] In response to receiving an access request sent by the baseboard management controller through a first serial communication bus, the at least one server power supply returns response information to the baseboard management controller through the first serial communication bus, wherein the first serial communication bus includes a first data line and a first clock line, and the at least one server power supply includes a group of first switches and a group of second switches;

[0120] At least one server power supply determines whether the working communication between the server power supply and the baseboard management controller is abnormal according to a polling period set by the user;

[0121] If so, at least one server power supply and the baseboard management controller resume communication through one of the first serial communication bus and the second serial communication bus and a group of the first switch and the second switch, wherein the second serial communication bus includes a second data line and a second clock line, the first clock line and the second clock line are connected in parallel; the first data line and the second data line are connected in parallel.

[0122] Specifically, when the BMC sends an access request to the Server PSU, it sends the access request data signal to the Server PSU via its internal SDA out switch and the first SDA, and sends the access request clock signal to the Server PSU via its internal SCL out switch and the first SCL. When the Server PSU successfully returns the response data signal to the BMC via the second SDA and by controlling Q1, and successfully returns the response clock signal to the BMC via the second SCL and by controlling Q2, communication between the two is normal. If the Server PSU does not receive an access request from the BMC within the polling cycle, communication is considered down. The Server PSU then attempts to restore communication via the first serial communication bus, Q1 and Q2, and the second serial communication bus, Q1 and Q2. If all attempts fail, the Server PSU performs bilateral communication with the BMC via the second serial communication bus, Q3 and Q4.

[0123] The solution of this application has the following beneficial effects:

[0124] 1) The server PSU continuously monitors the communication between the BMC and the server PSU. When a communication failure is detected, the system first attempts to restore communication between the BMC and the server PSU by turning on the corresponding switch, thereby continuously pulling down the pin voltage. This proactively restores I2C Bus communication before the BMC issues an alarm, eliminating the need for maintenance personnel to shut down the server PSU's AC power or replace the server PSU to restore communication with the system.

[0125] 2) By connecting another SDA and another SCL in parallel and controlling another SDA switch and another SCL switch, bilateral communication can be achieved to avoid communication downtime caused by I2C bus deadlock.

[0126] It should be understood that although the various steps in the flow chart of Figure 4 are shown in sequence as indicated by the arrows, these steps are not necessarily performed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in Figure 4 may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these sub-steps or stages is not necessarily performed in sequence, but can be performed in turn or alternately with at least a portion of other steps or sub-steps or stages of other steps.

[0127] In some embodiments, a power information communication system is further provided, the system comprising a baseboard management controller, at least one server power supply, a first serial communication bus, and a second serial communication bus;

[0128] Each of the at least one server power supply includes a set of first switches and a set of second switches; the baseboard management control includes a set of third switches;

[0129] The baseboard management controller and at least one server power supply perform working communication via a first serial communication bus, a third switch, and a first switch; the baseboard management controller and at least one server power supply perform working communication via a second serial communication bus, a third switch, and a first switch; the baseboard management controller and at least one server power supply perform interchangeable bilateral bidirectional communication via a second serial communication bus, a third switch, and a second switch, wherein the first serial communication bus includes a first data line and a first clock line, the second serial communication bus includes a second data line and a second clock line, the first clock line and the second clock line are connected in parallel; the first data line and the second data line are connected in parallel.

[0130] In some embodiments, the system further comprises:

[0131] The first switch includes a first data line switch and a first clock line switch, wherein the first data line switch is used to adjust the pin levels of the first data line and the second data line, and the first clock line switch is used to adjust the pin levels of the first clock line and the second clock line; the second switch includes a second data line switch and a second clock line switch, wherein the second data line switch is used to adjust the pin level of the second clock line, and the second clock line switch is used to adjust the pin level of the second data line; the third switch includes a third data line switch and a third clock line switch, wherein the third data line switch is used to adjust the pin levels of the first data line and the second clock line, and the third clock line switch is used to adjust the pin levels of the first clock line and the second data line.

[0132] In some embodiments, a computer device is provided, which may be a terminal, and its internal structure diagram may be as shown in Figure 21. The computer device includes a processor, memory, network interface, display screen, and input device connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and computer-readable instructions. The internal memory provides an environment for the operation of the operating system and computer-readable instructions in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer-readable instructions are executed by the processor, an alarm information processing method is implemented. The display screen of the computer device may be a liquid crystal display or an electronic ink display screen. The input device of the computer device may be a touch layer covering the display screen, or may be a key, trackball, or touchpad provided on the computer device housing, or may be an external keyboard, touchpad, or mouse.

[0133] Those skilled in the art will understand that the structure shown in Figure 21 is merely a block diagram of a portion of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0134] In some embodiments, an electronic device is provided, including a memory, a processor, and computer-readable instructions stored in the memory and executable on the processor, wherein the processor implements the method of any one or more of the above-mentioned embodiments when executing the computer-readable instructions.

[0135] In some embodiments, as shown in FIG. 22 , a non-volatile computer-readable storage medium is provided, on which computer-readable instructions are stored. When the computer-readable instructions are executed by a processor, the method of any one or more of the above-mentioned embodiments is implemented.

[0136] Those skilled in the art will understand that all or part of the processes in the methods for implementing the above embodiments can be completed by instructing related hardware through computer-readable instructions, and the computer-readable instructions can be stored in a non-volatile computer-readable storage medium. When the computer-readable instructions are executed, they may include processes such as the embodiments of the above methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0137] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0138] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A method for communicating power information, applied to at least one server power supply, wherein the at least one server power supply comprises a first switch and a second switch, wherein the first switch comprises a first clock line switch and a first data line switch, and the second switch comprises a second clock line switch and a second data line switch, wherein the method comprises: In response to receiving an access request sent by a baseboard management controller through a first serial communication bus, returning response information to the baseboard management controller through the first serial communication bus, wherein the first serial communication bus includes a first data line and a first clock line; Determine whether the working communication with the baseboard management controller is abnormal according to the polling cycle set by the user; as well as In response to abnormal working communication with the baseboard management controller, communication with the baseboard management controller is restored through one of the first serial communication bus and the second serial communication bus and a group of the first switch and the second switch, wherein the second serial communication bus includes a second data line and a second clock line, the first clock line and the second clock line are connected in parallel; the first data line and the second data line are connected in parallel.

2. The method according to claim 1, characterized in that The determining whether the working communication with the baseboard management controller is abnormal according to the polling period set by the user includes: In response to monitoring that the pin level of the first data line and the pin level of the first clock line are both high, determining whether the access request is received within the polling cycle; In response to receiving the access request within the polling period, returning the response information to the baseboard management controller via the first serial communication bus; and In response to not receiving the access request within the polling period, determining that the working communication is abnormal.

3. The method according to claim 1, characterized in that The method of restoring communication with the baseboard management controller through one of the first serial communication bus and the second serial communication bus and a group of the first switch and the second switch comprises: Attempting to restore the working communication through the first serial communication bus, a first data line switch corresponding to the first data line, and a first clock line switch corresponding to the first clock line; In response to a failure in attempting to restore the operating communication through the first serial communication bus, the first data line switch, and the first clock line switch, attempting to restore the operating communication through the second serial communication bus, the first data line switch, and the first clock line switch; and In response to a failure in attempting to restore the operating communication through the second serial communication bus, the first data line switch, and the first clock line switch, reciprocating bilateral bidirectional communication with the baseboard management controller through the second serial communication bus, the second data line switch, and the second clock line switch.

4. The method according to claim 3, characterized in that The attempting to restore the working communication through the first serial communication bus, the first data line switch and the first clock line switch comprises: Turning on the first data line switch to continuously pull down the pin level of the first data line to a low level and turning on the first clock line switch to continuously pull down the pin level of the first clock line to a low level according to the time threshold set by the user; determining whether an access request sent by the baseboard management controller is received through the first serial communication bus within the polling period; In response to receiving the access request sent by the baseboard management controller, returning the response information to the baseboard management controller through the first serial communication bus; and In response to not receiving the access request sent by the baseboard management controller, continue to try to restore the working communication according to the number threshold and the first serial communication bus.

5. The method according to claim 4, characterized in that The returning the response information to the baseboard management controller through the first serial communication bus includes: Returning a clock signal corresponding to the response information through the first clock line in the first serial communication bus and the first clock line switch; and A data signal corresponding to the response information is returned via the first data line in the first serial communication bus and the first data line switch.

6. The method according to claim 3, characterized in that The step of attempting to restore the working communication again through the second serial communication bus, the first data line switch, and the first clock line switch comprises: Turning on the first data line switch according to the time threshold to continuously pull down the pin level of the second data line to a low level, and turning on the first clock line switch to continuously pull down the pin level of the second clock line to a low level; determining whether an access request sent by the baseboard management controller is received through the second serial communication bus within the polling period; In response to receiving the access request sent by the baseboard management controller, returning the response information to the baseboard management controller through the second serial communication bus; and In response to not receiving the access request sent by the baseboard management controller, continue to try to restore the working communication according to the number threshold and the second serial communication bus.

7. The method according to claim 6, characterized in that The returning the response information to the baseboard management controller through the second serial communication bus comprises: Returning a clock signal corresponding to the response information through a second clock line in the second serial communication bus and the first clock line switch; and A data signal corresponding to the response information is returned via the second data line in the second serial communication bus and the first data line switch.

8. The method according to claim 3, characterized in that The method of performing the bilateral bidirectional communication with the baseboard management controller through the second serial communication bus, the second data line switch and the second clock line switch includes: Turning on the second data line switch according to the time threshold to continuously pull down the pin level of the second clock line to a low level and turning on the second clock line switch to continuously pull down the pin level of the second data line to a low level; and In response to receiving the access request sent by the baseboard management controller, response information is returned to the baseboard management controller through the second serial communication bus, the second data line switch and the second clock line switch.

9. The method according to claim 8, characterized in that The returning response information to the baseboard management controller through the second serial communication bus, the second data line switch and the second clock line switch comprises: Returning the data signal corresponding to the response information through the second clock line and the second data line switch in the second serial communication bus; and The clock signal corresponding to the response information is returned via the second data line and the second clock line switch in the second serial communication bus.

10. The method according to claim 8, characterized in that After returning the response information to the baseboard management controller through the second serial communication bus, the second data line switch and the second clock line switch, the method further includes: Generate communication abnormality information and send the communication abnormality information to the baseboard management controller through the second serial communication bus, the second data line switch and the second clock line switch; In response to receiving a restart instruction sent by the baseboard management controller, restarting the input power according to the restart instruction to disconnect the second data line switch and the second clock line switch; and In response to the completion of restarting the input power, the operation communication is performed through the first serial communication bus, the first data line switch, and the first clock line switch.

11. A method for communicating power information, applied to a baseboard management controller, the baseboard management controller comprising a third switch, the third switch comprising a third clock line switch and a third data line switch, the method comprising: In response to receiving a query instruction sent by the server system, determining at least one server power supply according to the query instruction and sending an access request to the at least one server power supply through the first serial communication bus and the third switch; In response to receiving response information returned by the at least one server power supply through the first serial communication bus, performing working communication with the at least one server power supply through the first serial communication bus and the third switch; as well as In response to receiving the response information returned by the at least one server power supply through the second serial communication bus, the reciprocating bilateral bidirectional communication or the working communication with the at least one server power supply is performed through the second serial communication bus and the third switch.

12. The method according to claim 11, characterized in that The step of determining at least one server power supply according to the query instruction and sending an access request to the at least one server power supply through the first serial communication bus and the third switch comprises: sending a clock signal of the access request to the at least one server power supply through the first clock line and the third clock line switch in the first serial communication bus; and The access request data signal is sent to the at least one server power supply through the first data line in the first serial communication bus and the third data line switch.

13. The method according to claim 11, characterized in that The performing of the interchangeable bilateral bidirectional communication or the working communication with the at least one server power supply through the second serial communication bus includes: In response to receiving a clock signal of the response information through a second clock line in the second serial communication bus and receiving a data signal of the response information through a second data line in the second serial communication bus, performing the working communication through the second serial communication bus and the third switch; and In response to receiving the data signal through the second clock line in the second serial communication bus and receiving the clock signal through the second data line in the second serial communication bus, the interchanged bilateral bidirectional communication is performed through the second serial communication bus and the third switch.

14. The method according to claim 12, characterized in that The performing of the interchange bilateral bidirectional communication through the second serial communication bus and the third switch comprises: In response to receiving the query instruction sent by the server system again, determining at least one server power supply according to the query instruction and sending the data signal of the access request through the second clock line and the third data line switch in the second serial communication bus; and The clock signal of the access request is sent through the second data line and the third clock line switch in the second serial communication bus.

15. The method according to claim 11, characterized in that The method further comprises: In response to receiving communication abnormality information sent by the at least one server power supply through the second serial communication bus, alerting a user according to the communication abnormality information; In response to receiving a normal communication restoration instruction sent by the user, sending a restart instruction to the at least one server power supply through the second serial communication bus and the third switch to restart the at least one server power supply; and In response to completion of the power restart of the at least one server, the operating communication is performed through the first serial communication bus and the third switch.

16. A power information communication method applied to a power information communication system, characterized in that: The method comprises: In response to receiving a query instruction sent by the server system, the baseboard management controller determines at least one server power supply according to the query instruction and sends an access request to the at least one server power supply via a first serial communication bus; In response to receiving an access request sent by a baseboard management controller through a first serial communication bus, at least one server power supply returns response information to the baseboard management controller through the first serial communication bus, wherein the first serial communication bus includes a first data line and a first clock line, and the at least one server power supply includes a group of first switches and a group of second switches; The at least one server power supply determines whether the working communication with the baseboard management controller is abnormal according to a polling period set by a user; and In response to an abnormality in working communication with the baseboard management controller, the at least one server power supply and the baseboard management controller resume communication through one of the first serial communication bus and the second serial communication bus and a group of the first switch and the second switch, wherein the second serial communication bus includes a second data line and a second clock line, the first clock line and the second clock line are connected in parallel; the first data line and the second data line are connected in parallel.

17. A power information communication system, characterized in that: The system includes a baseboard management controller, at least one server power supply, a first serial communication bus, and a second serial communication bus; Each of the at least one server power supply comprises a set of first switches and a set of second switches; the baseboard management control comprises a set of third switches; as well as The baseboard management controller and the at least one server power supply perform working communication via the first serial communication bus, the third switch and the first switch; The baseboard management controller and the at least one server power supply perform working communication via the second serial communication bus, the third switch and the first switch; The baseboard management controller and the at least one server power supply exchange bilateral bidirectional communication through the second serial communication bus, the third switch and the second switch, wherein the first serial communication bus includes a first data line and a first clock line, the second serial communication bus includes a second data line and a second clock line, the first clock line and the second clock line are connected in parallel; the first data line and the second data line are connected in parallel.

18. The system according to claim 17, characterized in that The system further comprises: The first switch includes a first data line switch and a first clock line switch, wherein the first data line switch is used to adjust the pin levels of the first data line and the second data line, and the first clock line switch is used to adjust the pin levels of the first clock line and the second clock line; the second switch includes a second data line switch and a second clock line switch, wherein the second data line switch is used to adjust the pin level of the second clock line, and the second clock line switch is used to adjust the pin level of the second data line; the third switch includes a third data line switch and a third clock line switch, wherein the third data line switch is used to adjust the pin levels of the first data line and the second clock line, and the third clock line switch is used to adjust the pin levels of the first clock line and the second data line.

19. A computer device comprising a memory, a processor, and computer-readable instructions stored in the memory and executable on the processor, characterized in that: When the processor executes the computer-readable instructions, the steps of the method according to any one of claims 1 to 16 are implemented.

20. A non-volatile computer-readable storage medium having computer-readable instructions stored thereon, characterized in that: When the computer readable instructions are executed by a processor, the steps of the method according to any one of claims 1 to 16 are implemented.

21. The method according to claim 1, characterized in that The communication between the server power supply and the baseboard management controller includes working communication or interchange bilateral bidirectional communication.

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