Data power-on and power-off processing method and system, device, and computer storage medium

Abstract

A data power-on and power-off processing method and system, a device, and a computer storage medium. The method comprises: during power loss, obtaining target data not written to TLC and a first LBA address of the target data in the TLC; storing the target data and the first LBA address in SLC; obtaining a second LBA address and a second PBA address of the target data stored in the SLC; establishing a mapping relationship between the second LBA address and the first LBA address and a mapping relationship between the second LBA address and the second PBA address; upon power-on, reading the target data and the first LBA address from the SLC, and sorting the target data on the basis of the first LBA address to obtain target sorting results; and classifying the target sorting results into a first sorting result meeting a minimum data write amount of the TLC and a second sorting result not meeting the minimum data write amount of the TLC, and writing the target data to the TLC on the basis of the first sorting result and the second sorting result. The data storage performance of the SSD during power-on and power-off is improved.

Description

Data power-on and power-off processing method, system, device and computer storage medium

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on November 20, 2023, with application number 202311552830.0 and invention name “A method, system, device and computer storage medium for data power-on and power-off processing”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of storage technology, and more specifically, to a data power-on and power-off processing method, system, device, and computer storage medium. Background Art

[0003] Currently, in the process of using SSD (Solid State Disk) for data storage, data security and integrity are extremely important. Data loss or errors may cause immeasurable losses to customers. Since power outages or disk insertion and removal may occur at any time when the host is writing data, how to ensure data security is the most important issue that the storage industry needs to focus on and solve. Especially in the case of sequential writes such as ZNS, combined with the read and write characteristics of Nand, when the power is turned off, there will be data in the cache that is not fully accumulated by a write command and data that is fully accumulated in the future and cannot be written to Nand in time. In order to cope with this scenario, it is necessary to urgently save the data that will not be written to Nand in time. However, since the SSD is powered off at this time, the working time maintained by the capacitor in the SSD disk is limited, and it is often unable to store user data safely, completely and quickly, resulting in poor data storage performance of the SSD during power on and off.

[0004] In summary, how to improve the ability of an SSD to store user data safely, completely, and quickly during power on and off to improve data storage performance is an urgent problem to be solved by those skilled in the art.

[0005] Summary of the Invention

[0006] The purpose of this application is to provide a data power-on and power-off processing method, which can, to a certain extent, solve the technical problem of how to improve the data storage performance of SSD during power-on and power-off. This application also provides a data power-on and power-off processing system, electronic device and computer-readable storage medium.

[0007] In order to achieve the above objectives, this application provides the following technical solutions:

[0008] A data power-on and power-off processing method, characterized by comprising:

[0009] When power is off, obtaining target data not written to the TLC and its first LBA address in the TLC; storing the target data and the first LBA address in the SLC; obtaining a second LBA address and a second PBA address of the target data stored in the SLC; and establishing a mapping relationship between the second LBA address and the first LBA address and the second PBA address respectively;

[0010] After power-on, the target data and the first LBA address are read from the SLC according to the second LBA address and the second PBA address, and the target data is sorted according to the first LBA address to obtain a target sorting result; the target sorting result is classified into a first sorting result that meets the minimum data write amount of the TLC and a second sorting result that does not meet the minimum data write amount of the TLC, and the target data is written into the TLC based on the first sorting result and the second sorting result.

[0011] Preferably, reading the target data and the first LBA address from the SLC according to the second LBA address and the second PBA address includes:

[0012] The target data and the first LBA address are read from the SLC into a cache.

[0013] Preferably, writing the target data into the TLC based on the first sorting result and the second sorting result includes:

[0014] Writing first data corresponding to the first sorting result into the TLC;

[0015] The second data corresponding to the second sorting result is written back from the cache to the memory, and after the second data reaches the minimum data writing amount of the TLC, the second data is written into the TLC.

[0016] Preferably, writing the target data into the TLC includes:

[0017] Determine a block to be written of the target data in the TLC;

[0018] Determine whether there is a data hole in the block to be written;

[0019] If there is a data hole in the block to be written, the written data in the block to be written and the target data are written into another block in sequence;

[0020] If the block to be written does not have a data hole, the target data is sequentially written into the block to be written.

[0021] Preferably, sorting the target data according to the first LBA address to obtain a target sorting result includes:

[0022] The target data is sorted in ascending order according to the first LBA addresses to obtain the target sorting result.

[0023] Preferably, sorting the target data according to the first LBA address to obtain a target sorting result includes:

[0024] The target data is sorted according to the first LBA address and the zone type in which the target data is stored, to obtain the target sorting result corresponding to the zones one by one.

[0025] Preferably, the process of storing the target data and the first LBA address in the SLC includes:

[0026] If the target data does not meet the minimum data writing amount of the SLC, patchwork data is determined and the target data and the patchwork data are written into the SLC together. The amount of the patchwork data is the difference between the minimum data writing amount of the SLC and the amount of the target data.

[0027] A data power-on and power-off processing system, comprising:

[0028] a power-off processing module configured to, when power is off, obtain target data not written to the TLC and its first LBA address in the TLC; store the target data and the first LBA address in the SLC; obtain a second LBA address and a second PBA address of the target data stored in the SLC; and establish a mapping relationship between the second LBA address and the first LBA address and the second PBA address;

[0029] A power-on processing module is used to, after power-on, read the target data and the first LBA address from the SLC according to the second LBA address and the second PBA address, sort the target data according to the first LBA address to obtain a target sorting result; classify the target sorting result into a first sorting result that meets the minimum data write amount of the TLC and a second sorting result that does not meet the minimum data write amount of the TLC, and write the target data into the TLC based on the first sorting result and the second sorting result.

[0030] An electronic device, comprising:

[0031] Memory for storing computer programs;

[0032] A processor is used to implement the steps of any of the above-mentioned data power-on and power-off processing methods when executing the computer program.

[0033] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of any of the above-mentioned data power-on and power-off processing methods.

[0034] The present application provides a data power-on and power-off processing method, which, when power is off, obtains target data that has not been written to the TLC and its first LBA address in the TLC; stores the target data and the first LBA address in the SLC; obtains the second LBA address and the second PBA address where the target data is stored in the SLC; establishes a mapping relationship between the second LBA address and the first LBA address and the second PBA address respectively; after power is on, reads the target data and the first LBA address from the SLC according to the second LBA address and the second PBA address, sorts the target data according to the first LBA address to obtain a target sorting result; classifies the target sorting result into a first sorting result that meets the minimum data write amount of the TLC and a second sorting result that does not meet the minimum data write amount of the TLC, and writes the target data into the TLC based on the first sorting result and the second sorting result. In this application, when power is off, the first LBA address and target data are stored in the SLC. Since the SLC has the fastest read and write speed, data can be quickly saved after power is off. After power is on, the target data is sorted according to the first LBA address to obtain a sequential target sorting result, and the target sorting result is classified into a first sorting result that meets the minimum data write amount of the TLC and a second sorting result that does not meet the minimum data write amount of the TLC. Finally, based on the first sorting result and the second sorting result, the target data is written to the TLC. This allows the target data to be written to the TLC accurately and systematically, improving the data write rate after power is on, and ultimately improving the data storage performance of the SSD during power on and off. The data power on and off processing system, electronic device, and computer-readable storage medium provided by this application also solve corresponding technical problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0036] FIG1 is a first flow chart of a data power-on and power-off processing method provided in an embodiment of the present application;

[0037] Figure 2 is a diagram showing the mapping principle between LBA and PBA;

[0038] Figure 3 is a schematic diagram of the internal structure of NAND;

[0039] Figure 4 is a schematic diagram of the amount of data written at one time to a TLC NAND;

[0040] Figure 5 is a schematic diagram of the zone division in ZNS;

[0041] Figure 6 is a schematic diagram of data writing to a TLC nand in a ZNS non-power-off scenario;

[0042] FIG7 is a schematic diagram of the generation of TLC voids;

[0043] Figure 8 is a flowchart of power-off data refresh;

[0044] FIG9 is a second flow chart of a data power-on and power-off processing method provided in an embodiment of the present application;

[0045] FIG10 is a schematic diagram showing a mapping relationship between a first LBA address and a second LBA address;

[0046] FIG11 is a schematic diagram of generating target ranking results;

[0047] FIG12 is a schematic diagram of target sorting results;

[0048] Figure 13 is a schematic diagram of a buffer;

[0049] FIG14 is a schematic diagram showing the generation of the first sorting result and the second sorting result;

[0050] FIG15 is a schematic diagram of the first sorting result and the second sorting result;

[0051] FIG16 is a schematic diagram of data integration and recovery;

[0052] FIG17 is a schematic diagram of the structure of a data power-on and power-off processing system provided in an embodiment of the present application;

[0053] FIG18 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0054] FIG19 is another schematic structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0055] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0056] Please refer to FIG1 , which is a first flow chart of a data power-on and power-off processing method provided in an embodiment of the present application.

[0057] The present invention provides a method for processing power on and off of data, which may include the following steps:

[0058] Step S101: When power is off, obtain the target data not written in the TLC and its first LBA address in the TLC; store the target data and the first LBA address in the SLC; obtain the second LBA address and the second PBA address where the target data is stored in the SLC; establish a mapping relationship between the second LBA address and the first LBA address and the second PBA address respectively.

[0059] In actual applications, after the SSD loses power, in order to ensure that data reading and writing can continue after power-on, it is necessary to obtain the target data in the TLC that has not been written to the nand and its first LBA address in the TLC, and in this application, the target data and the first LBA address need to be stored in the SLC of the nand. Since the SLC has the fastest read and write speed, the data address and the first LBA address can be stored quickly. In this process, the target data in the TLC that has not been written to the nand can be data that has not yet started to be written to the TLC, or data that is in the process of being written to the TLC but failed to be written, etc. Its type can be determined according to actual needs, and this application does not make specific restrictions here. In addition, it is also necessary to obtain the second LBA address and the second PBA address of the target data stored in the SLC, and establish a mapping relationship between the second LBA address and the first LBA address and the second PBA address, so that the target data and the first LBA address can be read from the SLC based on the mapping relationship.

[0060] It should be noted that the LBA (Logical Block Address) in this application is a general mechanism for indicating the location of data, which refers to the logical address of a data block. Its size can be determined according to the data format of the SSD. For example, the size of an LBA can be 512Byte or 4Kbyte, etc. On this basis, LBA also needs to use PBA (Physics Block Address) to interact with the SSD, where PBA refers to the real physical address after the LBA data is actually written to the NAND of the SSD. During firmware management, the size of a PBA can be fixed to 4Kbyte, and a PBA can correspond to one or more LBAs, etc. In addition, the storage medium NAND used by the SSD needs to be erased before it can be written again, and the characteristics of reading and writing in pages and erasing in blocks (composed of multiple pages) result in the relationship between LBA and PBA no longer being fixed. Therefore, the SSD's main controller uses a mapping table of LBA and PBA to manage the flash memory. When data that needs to be updated is written, the main controller writes the new data to the blank flash memory space (erased), and then updates the mapping table data to point the LBA to the new PBA, as shown in Figure 2.

[0061] It should also be noted that NAND has restrictions on the data it can write. Taking the plane TLC internal architecture shown in Figure 3 as an example, NAND has two LUNs, where LUN is the smallest independent unit in NAND that can execute commands and report its own status; plane is the smallest unit that NAND can operate according to read, write, erase and other commands. A plane is a storage matrix containing several blocks; block is the smallest unit of erase command, which contains several pages; page is the smallest unit that can be read and written in flash memory. The size of each page can be 16KB, etc. For example, SSD disk takes 4KB format, and 4 LBAs can be written in one page (1 LBA is 4KB). When 4KB of data needs to be written, the entire page must be written at the NAND level, resulting in a total of 16KB of data being written. If multi-plane page programming is used, the write command operates on the same-numbered pages of plane 0 and plane 1. For TLC NAND, three pages need to be written simultaneously. For example, if the data written at one time is pages 0, 1, and 2 of plane 0, and pages 0, 1, and 2 of plane 1, then 16KB * 2 * 3 = 96KB of data needs to be written at one time. The write volume for a TLC programming operation is shown in Figure 4. Furthermore, to meet NAND characteristics, after a write command is issued, the data is first cached in a section of DDR memory (cache). Once the required 96KB of data is accumulated, the data is actually written to the NAND. In other words, a data write to a TLC NAND contains multiple LBAs and is written to multiple PBAs.

[0062] Step S102: After power-on, the target data and the first LBA address are read from the SLC according to the second LBA address and the second PBA address, and the target data is sorted according to the first LBA address to obtain a target sorting result; the target sorting result is classified into a first sorting result that meets the minimum data writing amount of the TLC and a second sorting result that does not meet the minimum data writing amount of the TLC, and the target data is written to the TLC based on the first sorting result and the second sorting result.

[0063] In actual applications, after the SSD is powered on, the target data and the first LBA address need to be read from the SLC according to the second LBA address and the second PBA address. For example, the second LBA addresses storing the first LBA address can be determined according to the mapping relationship first, and then the second PBA address corresponding to the second LBA address can be determined according to the mapping relationship, and finally the required target data and the first LBA address are read from the second PBA address; and considering that the data is written to the TLC in the order of the first LBA address, the target data can be sorted according to the first LBA address first to obtain a sequential target sorting result; and considering that the TLC has a minimum data write amount, data that meets the minimum write amount can be directly written to the TLC, and data that does not meet the minimum data write amount cannot be directly written to the TLC, so in order to accurately write these two types of data into the TLC, the target sorting result can be classified into a first sorting result that meets the minimum data write amount of the TLC and a second sorting result that does not meet the minimum data write amount of the TLC, and finally the target data is written to the TLC based on the first sorting result and the second sorting result.

[0064] It should be noted that when ZNS (Zoned Namespace) technology is applied to the SSD, since ZNS technology divides the entire LBA range of the SSD namespace into several equal-length intervals, the equal-length LBA intervals are called a zone, that is, a zone is a continuous and non-overlapping range of LBAs, as shown in Figure 5. Assume that the number of LBAs in each zone is n, where LBA 0 is the minimum LBA of zone 0 and LBA n-1 is the maximum LBA of zone 0. For zone 1, LBA n is the minimum LBA and LBA 2n-1 is its maximum LBA. Therefore, the minimum LBA of zone m is LBA n*(m-1) and the maximum LBA is LBA nm-1. In addition, the ZNS protocol stipulates that data can be read in any order within each zone, but must be written in a sequential manner, that is, random read and sequential write are supported. Therefore, the host side needs to ensure that the transmitted LBAs are in order and non-repeated. According to the protocol specification, each zone has its own independent status management. Before rewriting, the zone status management information must be reset first, and then writing must start from LBA 0. During the data power-on process, this application first sorts the data addresses according to the first LBA address to obtain the target sorting result; then classifies the target sorting result into a first sorting result that meets the minimum data write amount of TLC and a second sorting result that does not meet the minimum data write amount of TLC. Based on the first sorting result and the second sorting result, the target data is written to the TLC, which can meet the sequential write requirements of the ZNS technology. Therefore, this application solution is also applicable to SSDs processed by the ZNS technology.

[0065] For ease of understanding, assume that the data write process to the TLC NAND in a ZNS non-power-down scenario is shown in Figure 6. Data writes to the NAND occur concurrently. At the same time, multiple data entries are written to the TLC NAND on different data channels. If a power failure occurs, some data may already be written to the TLC NAND, while others may not be processed. This creates holes in the TLC NAND, where some data has been written but others have not, as shown in Figure 7. Zone 0's LBAs 0-23, 24-47, and 48-71 represent three TLC data writes. They were written simultaneously before the power failure, but during the power failure, LBAs 0-23 and 48-71 had already been flushed to the TLC, while LBAs 24-47 had not yet been flushed to the TLC NAND. Zone 1's LBAs 0-23 were written to the TLC before the power failure, but LBAs 24-40 were not fully written and are temporarily stored in the cache, not written to the TLC. At this point, the method of the present application can be applied to process the SSD, and the processing process can be shown in FIG8 , where FE refers to the front end, FTL refers to the flash translation layer, and BE refers to the back end.

[0066] The present application provides a data power-on and power-off processing method, which, when power is off, obtains target data that has not been written to the TLC and its first LBA address in the TLC; stores the target data and the first LBA address in the SLC; obtains the second LBA address and the second PBA address where the target data is stored in the SLC; establishes a mapping relationship between the second LBA address and the first LBA address and the second PBA address respectively; after power is on, reads the target data and the first LBA address from the SLC according to the second LBA address and the second PBA address, sorts the target data according to the first LBA address to obtain a target sorting result; classifies the target sorting result into a first sorting result that meets the minimum data write amount of the TLC and a second sorting result that does not meet the minimum data write amount of the TLC, and writes the target data into the TLC based on the first sorting result and the second sorting result. In the present application, when power is off, the first LBA address and target data are stored in the SLC. Since the read and write speed of the SLC is the fastest, the data can be quickly saved after power is off; after power is on, the target data is sorted according to the first LBA address to obtain a sequential target sorting result, and the target sorting result is classified into a first sorting result that meets the minimum data writing amount of the TLC and a second sorting result that does not meet the minimum data writing amount of the TLC. Finally, the target data is written to the TLC based on the first sorting result and the second sorting result. The target data can be written to the TLC accurately and in an organized manner, thereby improving the data write rate after power is on, and ultimately improving the data storage performance of the SSD during power on and off.

[0067] Please refer to FIG. 9 , which is a second flow chart of a data power-on and power-off processing method provided in an embodiment of the present application.

[0068] The present invention provides a method for processing power on and off of data, which may include the following steps:

[0069] Step S201: When power is off, obtain the target data in the TLC that is not written to the NAND and its first LBA address in the TLC; store the target data and the first LBA address in the SLC; obtain the second LBA address and the second PBA address where the target data is stored in the SLC; establish a mapping relationship between the second LBA address and the first LBA address and the second PBA address respectively.

[0070] Step S202: After power-on, the target data and the first LBA address are read from the SLC into the cache according to the second LBA address and the second PBA address, and the target data is sorted according to the first LBA address to obtain a target sorting result; the target sorting result is classified into a first sorting result that meets the minimum data write amount of the TLC and a second sorting result that does not meet the minimum data write amount of the TLC, and the first data corresponding to the first sorting result is written into the TLC; the second data corresponding to the second sorting result is written back from the cache to the memory, and after the second data reaches the minimum data write amount of the TLC, the second data is written into the TLC.

[0071] In actual applications, in the process of reading target data and the first LBA address from the SLC, the data address and the first LBA address can be read from the SLC into the cache so that the data address and the first LBA address can be processed in the cache.

[0072] In a specific application scenario, in the process of writing the target data into the TLC based on the first sorting result and the second sorting result, the first data corresponding to the first sorting result can be written into the TLC; the second data corresponding to the second sorting result can be written back from the cache to the memory, and after the second data reaches the minimum data write amount of the TLC, the second data can be written into the TLC.

[0073] In specific application scenarios, because the SSD can read data in any order after being processed according to the ZNS technology, but must write in a sequential manner, that is, it supports random read and sequential write. Therefore, in the process of writing the target data to the TLC, it is necessary to determine the block to be written in the TLC where the target data is located; determine whether there is a data hole in the block to be written; if there is a data hole in the block to be written, the written data and the target data in the block to be written are written sequentially to another block, and the block to be written can only be written to again after the reset is completed; if there is no data hole in the block to be written, the target data is written sequentially to the block to be written.

[0074] In actual applications, when sorting the target data according to the first LBA address to obtain the target sorting result, the target data can be sorted in ascending order of the first LBA address to obtain the target sorting result. In specific application scenarios, the target data can be sorted in ascending order of the first LBA address based on the category of the zone to which the target data is to be written, to obtain target sorting results corresponding to each zone, such as a sorting result corresponding to zone 1 and a sorting result corresponding to zone 2. Each sorting result can include the target data and the first LBA address, etc. This application does not make specific limitations here.

[0075] In a specific application scenario, in the process of storing the target data and the first LBA address in the SLC, if the target data does not meet the minimum data write amount of the SLC, the patchwork data can be determined and the target data and the patchwork data can be written into the SLC together. The data amount of the patchwork data is the difference between the minimum data write amount of the SLC and the data amount of the target data.

[0076] In actual applications, in order to quickly find LBA 0 from the PBA in the SLC for data processing, the SLC start PBA character used to record the first physical address PBA (which block, page) of the SLC's LBA 0 can be set in the SLC, and the initial value of the SLC start PBA can be set to an invalid value 0xFFFFFFFF. When data is stored in the SLC, the value of the SLC start PBA is modified accordingly. At this time, the mapping relationship reflecting the storage relationship between the first LBA address and the second LBA address can be shown in Figure 10. Furthermore, the mapping relationship can also store data such as which zone it belongs to, what data format it is, and which LBAs correspond to user data. Accordingly, the target data and the first LBA address are read from the SLC into the cache, and the target data is sorted according to the first LBA address. The process of obtaining the target sorting result can be shown in Figure 11. Considering that the SSD under the ZNS technology processes data according to the zone, a linked list can be used to record the LBA information of the corresponding zone. That is, this process includes the following steps:

[0077] After power-on, the mapping relationship between the SLC's LBA and PBA is read from the NAND;

[0078] Traverse the mapping relationship of the SLC to determine whether the current LBA of the SLC is less than the maximum LBA, which is the maximum number of LBAs stored in a single page of the SLC;

[0079] If the current LBA of the SLC is greater than or equal to the maximum LBA, the data has been read out and sorted according to the zone allocation. For ease of understanding, assume that data is read from pages 0 to 5 of the SLC nand and placed in the buffer. The data in page 1 is not sequential (TLC LBA 32, 33, 34, 41, 42, 43, 44, 45), and the valid data in page 5 is only 1 4KB (TLC LBA 31). After sorting, the SLC nand stores the data of zone 0 and zone 1. After the data is read into the buffer, two linked lists are requested. The linked list of zone 0 is list 0, and the linked list of zone 1 is list 1. After the data is read out in sequence, the list to be linked is selected according to the zone ID, and the insertion position is traversed backward on the list according to the TLC LBA of the data. The final storage order on the list is shown in Figure 12, and the linked list can record the TLC LBA value and the corresponding data address.

[0080] If the current LBA of the SLC is less than the maximum LBA, the mapping relationship corresponding to the current LBA is obtained;

[0081] Determine whether the SLC start PBA of the current LBA is valid;

[0082] If the SLC start PBA of the current LBA is invalid, the value of the current LBA is increased by 1, and the process returns to the step of determining whether the current LBA of the SLC is less than the maximum LBA;

[0083] If the SLC start PBA of the current LBA is valid, then apply for a buffer. The buffer is a continuous DDR memory segment applied in advance and divided into several parts, each of which is consistent with the SLC page size (multi-plane page, 16KB*2plane=32KB), as shown in Figure 13; obtain the nand physical address through the SLC PBA, and read the data on the SLC page into the buffer; LBA_Count starts from zero and traverses the TLC LBA in the mapping relationship[8];

[0084] Determine whether LBA_Count is less than 8. LBA_Count is used to record the number of PBAs corresponding to an LBA. 8 represents the maximum number of PBAs corresponding to a single LBA.

[0085] If LBA_Count is greater than or equal to 8, the value of the current LBA is increased by 1, and the process returns to the step of determining whether the current LBA of the SLC is less than the maximum LBA;

[0086] If LBA_Count is less than 8, determine whether the TLC LBA array element is valid;

[0087] If the TLC LBA array element is invalid, the value of LBA_Count is increased by 1, and the process returns to the step of determining whether the current LBA of the SLC is less than the maximum LBA;

[0088] If the TLC LBA array element is valid, select the data linked list according to the zone id, link it in ascending order according to the LBA size, add 1 to the value of LBA_Count, and return to the step of determining whether the current LBA of the SLC is less than the maximum LBA.

[0089] Furthermore, based on the above embodiment, as shown in FIG14 , in the process of classifying the target sorting result into a first sorting result that satisfies the minimum data writing amount of TLC and a second sorting result that does not satisfy the minimum data writing amount of TLC, the first sorting result and the second sorting result may be recorded using different linked lists. In this case, the following steps may be included:

[0090] Initialize the current list value to 0;

[0091] Determine whether the current list value is less than the maximum value of the list;

[0092] If the current list value is greater than or equal to the maximum value of the list, the data classification is completed and subsequent data sorting is carried out;

[0093] If the value of the current list is less than the maximum value of the list, determine whether there is a data node on the current list;

[0094] If there is no data node in the current list, add 1 to the value of the current list and return to the step of determining whether the value of the current list is less than the maximum value of the list;

[0095] If there is a data node in the current list, it is determined whether management resources have been applied for. Management resources are used to temporarily store information such as LBA data addresses;

[0096] If management resources have not been applied for, apply for management resources;

[0097] If management resources have been requested, the head node is taken out and the data address of the LBA is stored in the management resource;

[0098] Determine whether the LBA address recorded in the management resource has reached the TLC write capacity;

[0099] If the LBA address recorded in the management resource does not reach the TLC write amount, then determine whether there are still data nodes on the current list. If there are still data nodes on the current list, return to execute the step of taking out the head node and storing the LBA data address in the management resource; if there are no more data nodes on the current list, then restore it to the cache and use the management resource to store the linked list Y, and again determine whether there are still data nodes on the current list. If so, return to the step of applying for management resources. If not, add 1 to the value of the current list and return to execute the step of determining whether the value of the current list is less than the maximum value of the list;

[0100] If the LBA address recorded in the management resource reaches the TLC write amount, it is determined whether the linked list X has been applied;

[0101] If linked list X is not requested, zone n requests linked list X;

[0102] If linked list X has been requested, it will be used during data sorting and management resources will be stored in linked list X;

[0103] Determine whether there are still data nodes on the current list. If so, return to the step of applying for management resources. If not, add 1 to the value of the current list and return to the step of determining whether the value of the current list is less than the maximum value of the list. In this way, as shown in Figure 15, after sorting, the SLC data is sorted and hung on the corresponding linked list. The data that meets the TLC write requirement is placed in linked list A, that is, linked list A records the first sorting result. When subsequent data is sorted, it is written to the TLC. The data that does not meet the TLC's one-time write data amount is placed in linked list B, that is, linked list B records the second sorting result. It is then restored back to the cache and receives the host data. When enough data is accumulated, a write command is issued to write the data to the TLC. Accordingly, the process of writing the target data into the TLC based on the first sorting result and the second sorting result can be shown in Figure 16.

[0104] Please refer to FIG. 17 , which is a schematic structural diagram of a data power-on and power-off processing system provided in an embodiment of the present application.

[0105] An embodiment of the present application provides a data power-on and power-off processing system, which may include:

[0106] The power-off processing module 101 is configured to, when power is off, obtain target data not written to the TLC and its first LBA address in the TLC; store the target data and the first LBA address in the SLC; obtain a second LBA address and a second PBA address of the target data stored in the SLC; and establish a mapping relationship between the second LBA address and the first LBA address and the second PBA address, respectively.

[0107] The power-on processing module 102 is used to read the target data and the first LBA address from the SLC according to the second LBA address and the second PBA address after power-on, sort the target data according to the first LBA address, and obtain a target sorting result; classify the target sorting result into a first sorting result that meets the minimum data writing amount of the TLC and a second sorting result that does not meet the minimum data writing amount of the TLC, and write the target data into the TLC based on the first sorting result and the second sorting result.

[0108] An embodiment of the present application provides a data power-on and power-off processing system, wherein the power-on processing module may include:

[0109] The reading unit is used to read the target data and the first LBA address from the SLC into the cache.

[0110] An embodiment of the present application provides a data power-on and power-off processing system, wherein the power-on processing module may include:

[0111] The first writing unit is used to write the first data corresponding to the first sorting result into the TLC; write the second data corresponding to the second sorting result from the cache back to the memory, and write the second data into the TLC after the second data reaches the minimum data writing amount of the TLC.

[0112] An embodiment of the present application provides a data power-on and power-off processing system, wherein the power-on processing module may include:

[0113] The second writing unit is configured to determine the block to be written in the TLC where the target data is located; determine whether the block to be written has a data hole; if the block to be written has a data hole, sequentially write the written data and the target data in the block to be written into another block; if the block to be written does not have a data hole, sequentially write the target data into the block to be written.

[0114] An embodiment of the present application provides a data power-on and power-off processing system, wherein the power-on processing module may include:

[0115] The first sorting unit is used to sort the target data in ascending order of the first LBA address to obtain a target sorting result.

[0116] An embodiment of the present application provides a data power-on and power-off processing system, wherein the power-on processing module may include:

[0117] The second sorting unit is configured to sort the target data according to the first LBA address and the zone type in which the target data is stored, and obtain a target sorting result corresponding to each zone one by one.

[0118] An embodiment of the present application provides a data power-on and power-off processing system, in which a power-off processing module can be used to: during the process of storing target data and a first LBA address in an SLC, if the target data and the first LBA address do not meet the minimum data write amount of the SLC, determine patchwork data, and write the target data and the patchwork data together into the SLC, where the amount of the patchwork data is the difference between the minimum data write amount of the SLC and the amount of the target data.

[0119] The present application also provides an electronic device and a computer-readable storage medium, both of which have the corresponding effects of the data power-on and power-off processing method provided in the embodiment of the present application. Please refer to Figure 18, which is a structural diagram of an electronic device provided in the embodiment of the present application.

[0120] An electronic device provided in an embodiment of the present application includes a memory 201 and a processor 202. The memory 201 stores a computer program. When the processor 202 executes the computer program, the steps of the data power-on and power-off processing method described in any of the above embodiments are implemented.

[0121] Referring to FIG19 , another electronic device provided in an embodiment of the present application may further include: an input port 203 connected to the processor 202 for transmitting commands inputted from the outside to the processor 202; a display unit 204 connected to the processor 202 for displaying the processing results of the processor 202 to the outside; and a communication module 205 connected to the processor 202 for enabling communication between the electronic device and the outside. The display unit 204 may be a display panel, a laser scanning display, etc. The communication method adopted by the communication module 205 includes but is not limited to Mobile High-Definition Link (MHL), Universal Serial Bus (USB), High-Definition Multimedia Interface (HDMI), wireless connection: Wireless Fidelity (WiFi), Bluetooth communication technology, Bluetooth low energy communication technology, and communication technology based on IEEE802.11s.

[0122] An embodiment of the present application provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of the data power-on and power-off processing method described in any of the above embodiments are implemented.

[0123] The computer-readable storage medium involved in this application includes random access memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs (Compact Disc Read-Only Memory), or any other form of storage medium known in the technical field.

[0124] For descriptions of the relevant portions of the data power-on / off processing system, electronic device, and computer-readable storage medium provided in the embodiments of this application, please refer to the detailed description of the corresponding portions of the data power-on / off processing method provided in the embodiments of this application, and will not be repeated here. In addition, portions of the above-mentioned technical solutions provided in the embodiments of this application that are consistent with the implementation principles of corresponding technical solutions in the prior art are not described in detail to avoid excessive elaboration.

[0125] It should also be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0126] The above description of the disclosed embodiments will enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein but is to be construed in the widest possible manner consistent with the principles and novel features disclosed herein.

Claims

1. A data power-on and power-off processing method, characterized in that: include: When power is off, obtaining target data not written into the TLC and its first LBA address in the TLC; Storing the target data and the first LBA address in the SLC; Acquire a second LBA address and a second PBA address where the target data is stored in the SLC; Establishing a mapping relationship between the second LBA address and the first LBA address and the second PBA address respectively; After power-on, the target data and the first LBA address are read from the SLC according to the second LBA address and the second PBA address, and the target data is sorted according to the first LBA address to obtain a target sorting result; The target sorting result is classified into a first sorting result that satisfies the minimum data writing amount of the TLC and a second sorting result that does not satisfy the minimum data writing amount of the TLC, and the target data is written into the TLC based on the first sorting result and the second sorting result.

2. The method according to claim 1, characterized in that The reading the target data and the first LBA address from the SLC according to the second LBA address and the second PBA address includes: The target data and the first LBA address are read from the SLC into a cache.

3. The method according to claim 2, characterized in that The step of writing the target data into the TLC based on the first sorting result and the second sorting result includes: Writing first data corresponding to the first sorting result into the TLC; The second data corresponding to the second sorting result is written back from the cache to the memory, and after the second data reaches the minimum data writing amount of the TLC, the second data is written into the TLC.

4. The method according to claim 3, characterized in that Writing the target data into the TLC includes: Determine a block to be written of the target data in the TLC; Determine whether there is a data hole in the block to be written; If there is a data hole in the block to be written, the written data in the block to be written and the target data are sequentially written into another block; If the block to be written does not have a data hole, the target data is written sequentially into the block. The data to be written into the block.

5. The method according to any one of claims 1 to 4, characterized in that: The step of sorting the target data according to the first LBA address to obtain a target sorting result includes: The target data is sorted in ascending order according to the first LBA addresses to obtain the target sorting result.

6. The method according to claim 5, characterized in that The step of sorting the target data according to the first LBA address to obtain a target sorting result includes: The target data are sorted according to the first LBA address and the zone type in which the target data is stored, to obtain the target sorting result corresponding to the zones one by one.

7. The method according to claim 5, characterized in that The process of storing the target data and the first LBA address in the SLC includes: If the target data does not meet the minimum data write amount of the SLC, patchwork data is determined, and the target data and the patchwork data are written into the SLC together, and the data amount of the patchwork data is the difference between the minimum data write amount of the SLC and the data amount of the target data.

8. A data power-on and power-off processing system, characterized in that: include: A power-off processing module, used for obtaining target data not written into the TLC and its first LBA address in the TLC when power is off; Storing the target data and the first LBA address in the SLC; Acquire a second LBA address and a second PBA address where the target data is stored in the SLC; Establishing a mapping relationship between the second LBA address and the first LBA address and the second PBA address respectively; a power-on processing module, configured to, after power-on, read the target data and the first LBA address from the SLC according to the second LBA address and the second PBA address, and sort the target data according to the first LBA address to obtain a target sorting result; The target sorting result is classified into a first sorting result that satisfies the minimum data writing amount of the TLC and a second sorting result that does not satisfy the minimum data writing amount of the TLC, and the target data is written into the TLC based on the first sorting result and the second sorting result.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor for implementing the method according to any one of claims 1 to 7 when executing the computer program The steps of the data power-on and power-off processing method are described.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the data power-on and power-off processing method according to any one of claims 1 to 7 are implemented.

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