Power converter and three-phase four-leg inverter circuit modulation method

Abstract

A power converter and a three-phase four-leg inverter circuit modulation method. The power converter comprises a three-phase four-leg inverter circuit and a controller. The controller is used for: when the absolute value of the instantaneous value of a modulation signal for an N-leg is greater than a first effective modulus value, injecting the modulation signal into the N-leg in a unipolar manner, or when the absolute value of the instantaneous value of the modulation signal for the N-leg is less than a second effective modulus value, injecting the modulation signal into the N-leg in a bipolar manner. The present application can prevent the modulation signal for the N-leg from being lost, reducing the switching loss of main legs, and improving the quality of electric energy output by the power converter.

Description

Power converter and three-phase four-bridge-arm inverter circuit modulation method

[0001] This application claims priority to the Chinese patent applications filed with the Patent Office of China on November 22, 2023, with application number 202311572905.1 and application name “Inverter and three-phase four-leg inverter circuit modulation method” and filed with the Patent Office of China on February 1, 2024, with application number 202410156981.2 and application name “Inverter and three-phase four-leg inverter circuit modulation method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of power electronics technology, and in particular to a power converter and a modulation method for a three-phase four-bridge-arm inverter circuit. Background Art

[0003] Power converters are used in communications, automotive electronics, power grids, new energy vehicles and other fields. A power converter is a device that can convert one type of current into another type of current.

[0004] For power converters, especially those using three-phase, four-leg inverter circuits, discontinuous pulse width modulation (DPWM) is typically used in the main leg to reduce switching losses and improve system efficiency. However, when DPWM is used in the main leg, when the modulation index is high, the modulus of the injected common-mode signal is small, and the N-leg is prone to modulation signal loss due to the switch dead zone or minimum pulse limit. Preventing modulation signal loss in the N-leg and ensuring stable and effective DPWM control is a pressing issue for three-phase, four-leg inverter circuits.

[0005] Summary of the Invention

[0006] The present application provides a power converter and a three-phase four-bridge-arm inverter circuit modulation method, which can reduce switching losses and prevent modulation signal loss, thereby improving the efficiency and power quality of the power output of the power converter.

[0007] In a first aspect, a power converter is provided, characterized in that it includes a three-phase four-bridge-arm inverter circuit and a controller, wherein the input end of the three-phase four-bridge-arm inverter circuit is used to connect to a DC input, and the output end of the three-phase four-bridge-arm inverter circuit is used to connect to a load; the three-phase four-bridge-arm inverter circuit includes three main bridge arms and one N bridge arm; the controller is used to inject a common-mode signal into the main bridge arm and the N bridge arm, so that the main bridge arm operates in a discontinuous state; wherein the main bridge arm operates in a discontinuous state means that the switch tube of the main bridge arm remains in an on state or an off state during a period of time in the modulation cycle of the main bridge arm, so that the bridge arm output voltage of the main bridge arm is clamped at half of the DC bus voltage during a period of time in the modulation cycle of the main bridge arm; the The controller is also used to inject the modulation signal into the N bridge arm in a unipolar manner when the absolute value of the instantaneous value of the modulation signal of the N bridge arm is greater than the first effective modulus value, or to inject the modulation signal into the N bridge arm in a bipolar manner when the absolute value of the instantaneous value of the modulation signal of the N bridge arm is less than the second effective modulus value, and the first effective modulus value is greater than or equal to the second effective modulus value; or, the controller is also used to inject the modulation signal into the N bridge arm in a bipolar manner when the modulation degree of the three-phase four-bridge-arm inverter circuit is greater than the first switching threshold, or to inject the modulation signal into the N bridge arm in a unipolar manner when the modulation degree of the three-phase four-bridge-arm inverter circuit is less than the second switching threshold, and the first switching threshold is greater than or equal to the second switching threshold.

[0008] The injecting of the modulation signal into the N bridge arm in a unipolar manner means controlling the level of the output of the N bridge arm to change only between the positive level and the zero level within half a modulation cycle, or controlling the level of the output of the N bridge arm to change only between the negative level and the zero level within half a modulation cycle; the injecting of the modulation signal into the N bridge arm in a bipolar manner means controlling the level of the output of the N bridge arm to change between the positive level, the negative level and the zero level within half a modulation cycle.

[0009] By adopting a unipolar modulation mode when the modulation signal of the N bridge arm is large, and adopting a bipolar modulation mode when the modulation signal of the N bridge arm is small, it is possible to effectively avoid modulation failure of the N bridge arm due to the modulation signal, resulting in loss of the N bridge arm modulation signal, and avoid distortion of the output waveform of the power converter due to loss of the modulation signal. In addition, it is possible to effectively make the main bridge arm operate in a discontinuous state, thereby reducing the switching loss of the main bridge arm switch tube.

[0010] In one possible implementation, the controller is used to inject a common-mode signal into the main bridge arm and the N bridge arm so that the main bridge arm operates in a discontinuous state when the absolute value of the instantaneous value of the modulation signal of the main bridge arm is greater than or equal to a first threshold.

[0011] By performing DPWM modulation near the peak, the modulus of the common-mode signal to be injected is smaller, which can effectively reduce common-mode oscillation.

[0012] In one possible implementation, the controller is used to inject a common-mode signal into the main bridge arm and the N bridge arm so that the main bridge arm operates in a discontinuous state when the absolute value of the instantaneous value of the modulated signal of the main bridge arm is less than or equal to a second threshold and greater than or equal to a third threshold, the second threshold is less than the first threshold, and the third threshold is greater than 0 and less than the second threshold.

[0013] By performing DPWM modulation near the half-wave peak, the modulus of the common-mode signal to be injected is larger, and the common-mode signal can be injected more frequently in a unipolar modulation manner.

[0014] In one possible implementation, the controller is used to inject a zero-sequence modulation signal into the N bridge arm when the load is an unbalanced load; the controller is used to inject the common-mode signal into the main bridge arm and the N bridge arm so that the main bridge arm operates in a discontinuous state when the absolute value of the instantaneous value of the modulation signal of the main bridge arm is greater than a first zero-sequence threshold.

[0015] In one possible implementation, the controller is used to inject the common-mode signal into the main bridge arm and the N bridge arm so that the main bridge arm operates in a discontinuous state when the absolute value of the instantaneous value of the modulated signal of the main bridge arm is less than or equal to a second zero-sequence threshold and greater than or equal to a third zero-sequence threshold, the second zero-sequence threshold is less than the first zero-sequence threshold, and the third zero-sequence threshold is greater than 0 and less than the second zero-sequence threshold.

[0016] In one possible implementation, a modulation cycle of the main bridge arm includes moments t1, t3, and t5, where t1 is the starting moment of the modulation cycle of the main bridge arm, t5 is the ending moment of the modulation cycle of the main bridge arm, and t3 is the middle moment of the modulation cycle of the main bridge arm; the period of time is between moment t1 and moment t3 or between moment t3 and moment t5, or is two identical time periods simultaneously located between moment t1 and moment t3 and between moment t3 and moment t5.

[0017] In one possible implementation, a modulation cycle of the main bridge arm includes time t1 and time t2, wherein time t1 is 1 / 4 of the modulation cycle of the main bridge arm, and time t2 is 1 / 2 of the modulation cycle of the main bridge arm. The period starts at time t3 and ends at time t4, wherein t2>t4>t1>t3, and t4 minus t1 is equal to t1 minus t3.

[0018] In one possible implementation, a modulation cycle of the main bridge arm includes moments t1, t2, t3, t4 and t5, wherein t1 is the starting moment of the modulation cycle of the main bridge arm, t2 is the 1 / 4 moment of the modulation cycle of the main bridge arm, t3 is the middle moment of the modulation cycle of the main bridge arm, t4 is the 3 / 4 moment of the modulation cycle of the main bridge arm, and t5 is the end moment of the modulation cycle of the main bridge arm; the period of time is two identical time periods simultaneously located between moment t1 and moment t2 and between moment t2 and moment t3, or four identical time periods simultaneously located between moment t1 and moment t2, between moment t2 and moment t3, between moment t3 and moment t4, and between moment t4 and moment t5.

[0019] In one possible implementation, a modulation cycle of the main bridge arm includes time t1 and time t2, wherein time t1 is 1 / 4 of the modulation cycle of the main bridge arm, and time t2 is 1 / 2 of the modulation cycle of the main bridge arm. The period of time is two periods of the same length, wherein the first period of time starts from time t3 and ends at time t4, and the second period of time starts from time t5 and ends at time t6, wherein t2>t6>t5>t1>t4>t3, and t1 minus t4 is equal to t5 minus t1, and t4 minus t3 is equal to t6 minus t5.

[0020] In one possible implementation, the first effective modulus value is greater than the second effective modulus value; when the modulation signal used by the controller for the N bridge arm is greater than or equal to the first effective modulus value in a first time period and is greater than the second effective modulus value and less than the first effective modulus value in an adjacent second time period, the modulation signal is injected into the N bridge arm in a unipolar manner in the second time period, and the second time period is after the first time period; or, when the modulation signal used by the controller for the N bridge arm is less than the second effective modulus value in a third time period and is greater than the second effective modulus value and less than the first effective modulus value in an adjacent fourth time period, the modulation signal is injected into the N bridge arm in a bipolar manner in the fourth time period, and the fourth time period is after the third time period.

[0021] In one possible implementation, the first switching threshold is greater than the second switching threshold; the controller is used to inject a modulation signal into the N bridge arm in a unipolar manner when the modulation degree of the three-phase four-bridge-arm inverter circuit changes from greater than the first switching threshold to greater than the second switching threshold and less than or equal to the first switching threshold, or to inject a modulation signal into the N bridge arm in a bipolar manner when the modulation degree of the three-phase four-bridge-arm inverter circuit changes from less than the second switching threshold to greater than or equal to the second switching threshold and less than the first switching threshold.

[0022] In a second aspect, a three-phase four-bridge-arm inverter circuit modulation method is provided, characterized in that the method includes:

[0023] A common-mode signal is injected into the main bridge arm of the three-phase four-bridge-arm inverter circuit and the N bridge arm of the three-phase four-bridge-arm inverter circuit so that the main bridge arm operates in a discontinuous state; and when the absolute value of the instantaneous value of the modulation signal of the N bridge arm is greater than the first effective modulus value, the modulation signal is injected into the N bridge arm in a unipolar manner, or when the absolute value of the instantaneous value of the modulation signal of the N bridge arm is less than the second effective modulus value, the modulation signal is injected into the N bridge arm in a bipolar manner; or, when the modulation degree of the three-phase four-bridge-arm inverter circuit is greater than the first switching threshold, the modulation signal is injected into the N bridge arm in a bipolar manner, or, when the modulation degree of the three-phase four-bridge-arm inverter circuit is less than the second switching threshold, the modulation signal is injected into the N bridge arm in a unipolar manner, and the first switching threshold is greater than or equal to the second switching threshold.

[0024] In one possible implementation, the common-mode signal is injected into the main bridge arm and the N bridge arm so that the main bridge arm operates in a discontinuous state when the absolute value of the instantaneous value of the modulation signal of the main bridge arm is greater than or equal to a first threshold.

[0025] In one possible implementation, the common-mode signal is injected into the main bridge arm and the N bridge arm so that the main bridge arm operates in a discontinuous state when the absolute value of the instantaneous value of the modulated signal of the main bridge arm is less than or equal to a second threshold and greater than or equal to a third threshold, the second threshold is less than the first threshold, and the third threshold is greater than 0 and less than the second threshold.

[0026] In one possible implementation, when the load of the three-phase four-bridge-arm inverter circuit is an unbalanced load, a zero-sequence modulation signal is injected into the N bridge arm; and the common-mode signal is injected into the main bridge arm and the N bridge arm, so that the main bridge arm operates in a discontinuous state when the absolute value of the instantaneous value of the modulation signal of the main bridge arm is greater than a first zero-sequence threshold.

[0027] In one possible implementation, the common-mode signal is injected into the main bridge arm and the N bridge arm so that the main bridge arm operates in a discontinuous state when the absolute value of the instantaneous value of the modulation signal of the main bridge arm is less than or equal to the second zero-sequence threshold and greater than or equal to the third zero-sequence threshold, the second zero-sequence threshold is less than the first zero-sequence threshold, the third zero-sequence threshold is greater than 0 and less than the second zero-sequence threshold, and the third zero-sequence threshold is greater than 0 and less than the second zero-sequence threshold.

[0028] In one possible implementation, a modulation cycle of the main bridge arm includes moments t1, t3, and t5, where t1 is the starting moment of the modulation cycle of the main bridge arm, t5 is the ending moment of the modulation cycle of the main bridge arm, and t3 is the middle moment of the modulation cycle of the main bridge arm; the period of time is between moment t1 and moment t3 or between moment t3 and moment t5, or is two identical time periods simultaneously located between moment t1 and moment t3 and between moment t3 and moment t5.

[0029] In one possible implementation, a modulation cycle of the main bridge arm includes time t1 and time t2, wherein time t1 is 1 / 4 of the modulation cycle of the main bridge arm, and time t2 is 1 / 2 of the modulation cycle of the main bridge arm. The period starts at time t3 and ends at time t4, wherein t2>t4>t1>t3, and t4 minus t1 is equal to t1 minus t3.

[0030] In one possible implementation, a modulation cycle of the main bridge arm includes moments t1, t2, t3, t4 and t5, wherein t1 is the starting moment of the modulation cycle of the main bridge arm, t2 is the 1 / 4 moment of the modulation cycle of the main bridge arm, t3 is the middle moment of the modulation cycle of the main bridge arm, t4 is the 3 / 4 moment of the modulation cycle of the main bridge arm, and t5 is the end moment of the modulation cycle of the main bridge arm; the period of time is two identical time periods simultaneously located between moment t1 and moment t2 and between moment t2 and moment t3, or four identical time periods simultaneously located between moment t1 and moment t2, between moment t2 and moment t3, between moment t3 and moment t4, and between moment t4 and moment t5.

[0031] In one possible implementation, a modulation cycle of the main bridge arm includes time t1 and time t2, wherein time t1 is 1 / 4 of the modulation cycle of the main bridge arm, and time t2 is 1 / 2 of the modulation cycle of the main bridge arm. The period of time is two periods of the same length, wherein the first period of time starts from time t3 and ends at time t4, and the second period of time starts from time t5 and ends at time t6, wherein t2>t6>t5>t1>t4>t3, and t1 minus t4 is equal to t5 minus t1, and t4 minus t3 is equal to t6 minus t5.

[0032] In one possible implementation, the first effective modulus value is greater than the second effective modulus value; when the modulation signal of the N bridge arm is greater than or equal to the first effective modulus value in a first time period and greater than the second effective modulus value and less than the first effective modulus value in an adjacent second time period, the modulation signal is injected into the N bridge arm in a unipolar manner in the second time period, and the second time period is after the first time period; or, when the modulation signal of the N bridge arm is less than the second effective modulus value in a third time period and greater than the second effective modulus value and less than the first effective modulus value in an adjacent fourth time period, the modulation signal is injected into the N bridge arm in a bipolar manner in the fourth time period, and the fourth time period is after the third time period.

[0033] In one possible implementation, the first switching threshold is greater than the second switching threshold; when the modulation index of the three-phase four-bridge-arm inverter circuit changes from greater than the first switching threshold to greater than the second switching threshold and less than or equal to the first switching threshold, the modulation signal is injected into the N bridge arm in a unipolar manner, or, when the modulation index of the three-phase four-bridge-arm inverter circuit changes from less than the second switching threshold to greater than or equal to the second switching threshold and less than the first switching threshold, the modulation signal is injected into the N bridge arm in a bipolar manner.

[0034] It should be understood that the implementation and beneficial effects of the above-mentioned aspects of the present application can be referenced to each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figures 1a-1c are schematic diagrams of application scenarios of the inverter provided in an embodiment of the present application;

[0036] Figures 2a-2d are schematic diagrams of the topology of a three-phase four-bridge-leg inverter circuit provided in an embodiment of the present application;

[0037] FIG3 is a schematic diagram of SVPWM modulation signals of a three-phase four-bridge-arm inverter circuit provided in an embodiment of the present application;

[0038] 4a-4c are schematic diagrams of DPWM modulation signals of a three-phase four-bridge-arm inverter circuit provided in an embodiment of the present application;

[0039] 5a-5b are schematic diagrams of unipolar modulation signals and bipolar modulation signals of a three-phase four-bridge-leg inverter circuit provided in an embodiment of the present application;

[0040] 6a-6b are schematic diagrams illustrating the equivalent principles of unipolar modulation and bipolar modulation provided in an embodiment of the present application;

[0041] 7a-7d are schematic diagrams of DPWM modulation signals of a three-phase four-bridge-arm inverter circuit provided in an embodiment of the present application;

[0042] 8a-8c are schematic diagrams of DPWM modulation signals of a three-phase four-bridge-leg inverter circuit with hysteresis control provided by an embodiment of the present application;

[0043] 9a-9c are schematic diagrams of control methods for a three-phase four-bridge-arm inverter circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0044] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0045] The term "one embodiment" or "embodiment" herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present application. The phrase "in one embodiment" appearing in various places throughout this specification does not necessarily refer to the same embodiment, nor does it refer to separate or selective embodiments that are mutually exclusive of other embodiments. Unless otherwise specified, the terms "connected," "connected," and "connected" herein, indicating electrical connection, refer to direct or indirect electrical connection.

[0046] Hereinafter, if used, the terms "first," "second," etc., are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly specifying the quantity of the technical features being referred to. Thus, a feature qualified as "first," "second," etc. may explicitly or implicitly include one or more of the features. Throughout the description of this application, unless otherwise specified, "plurality" means two or more.

[0047] The technical solutions provided in the embodiments of the present application can be applied to devices with a three-phase four-bridge-arm inverter circuit topology, such as inverters and uninterruptible power supplies (UPS), and are applicable to different application scenarios, such as photovoltaic power supply scenarios, energy storage power supply scenarios, and UPS power supply scenarios. To facilitate understanding of the technical solutions provided in the embodiments of the present application, the following selects one scenario to illustrate the specific application of the technical solutions provided in the embodiments of the present application.

[0048] Refer to Figures 1a-1c, which are schematic diagrams of application scenarios of the photovoltaic system provided in the embodiments of the present application. In the photovoltaic system provided in the embodiments of the present application, a photovoltaic string 200 is included. The photovoltaic string 200 can be one or more strings. A photovoltaic string is obtained by connecting one or more photovoltaic panels in series or in parallel. The photovoltaic string 200 is used to convert the received light energy into direct current under lighting conditions and transmit it to the inverter 100. The inverter 100 is used to convert the direct current input by the photovoltaic string 200 into alternating current and output it to the load. It should be understood that the load in a broad sense can be a power grid, or it can be an electrical device, an energy storage device, etc. The inverter 100 provided in the embodiments of the present application can be connected to an electrical device, an energy storage device, etc. separately, or it can be connected to the power grid separately, or it can be connected to the power grid, power devices and energy storage devices, etc. at the same time. In the application scenario of the inverter 100 as shown in Figures 1a-1c, the output end of the inverter 100 is directly connected to the power-consuming equipment, energy storage equipment, etc. (i.e., the load shown in the figure), and is connected to the transformer through the AC bus AC Bus1. After the voltage is stepped up by the transformer, it is connected to the AC bus AC Bus2, and then connected to the main power grid.

[0049] As shown in Figure 1a, in one possible implementation, the inverter circuit 120 in the inverter 100 is directly connected to the PV strings 200 via a DC bus. This represents a single-stage inverter 100. As shown in Figures 1b and 1c, the inverter circuit 120 in the inverter 100 can also be first connected to a DC / DC converter module 130 via a DC bus before being connected to the PV strings 200. This represents a two-stage inverter 100.

[0050] In one possible embodiment, the number of photovoltaic strings 200 connected to the input end of the inverter 100 can be multiple (as shown in Figure 1c); a photovoltaic optimizer can be connected to the photovoltaic panels of the photovoltaic strings 200, and the photovoltaic optimizer is used to improve the overall power generation efficiency of the photovoltaic system (not shown in the figure).

[0051] It should be noted that in the aforementioned application scenario, the load of the inverter 100 may be a single-phase load or an unbalanced load such as a two-phase unbalanced load. In order to enable the inverter 100 to have the ability to cope with unbalanced loads, the inverter circuit 120 of the inverter 100 can adopt a three-phase four-bridge arm circuit topology.

[0052] It should be understood that the three-phase four-bridge-arm inverter circuit includes three main bridge arms and a fourth bridge arm. The fourth bridge arm is also called the N bridge arm because it has the function of a neutral wire. When the inverter 100 is supplying power to a balanced load, the three main bridge arm currents of the three-phase four-bridge-arm inverter circuit are balanced, the N bridge arm current is 0, and the switch tubes of the N bridge arm can all be inactive. At this time, the three-phase four-bridge-arm inverter circuit is equivalent to a three-phase three-bridge-arm inverter circuit; when the inverter 100 is supplying power to an unbalanced load, the three main bridge arm currents of the three-phase four-bridge-arm inverter circuit are unbalanced, and a zero-sequence current is generated on the N bridge arm. The switch tube on the N bridge arm can be continuously turned on and off, thereby controlling the zero-sequence current and optimizing the power quality output by the inverter 100.

[0053] Figures 2a-2d are schematic diagrams of the circuit topology of four three-phase four-bridge arm inverter circuits provided in the embodiments of the present application. The T-type three-level inverter circuit shown in Figure 2a includes a DC bus, three main bridge arms A, B, and C, and an N bridge arm. The output end of each bridge arm is connected to the corresponding LCL filter circuit. Each bridge arm includes a horizontal bridge arm and a vertical bridge arm. Two switches in opposite directions are connected in series on the horizontal bridge arm. One end of the horizontal bridge arm is connected to the midpoint of the DC bus DC Bus, and the other end of the horizontal bridge arm is connected to the midpoint of the vertical bridge arm. Two switches in the same direction are connected in series at both ends of the midpoint of the vertical bridge arm. One end of the vertical bridge arm is connected to the positive end of the DC bus DC Bus, and the other end of the vertical bridge arm is connected to the negative end of the DC bus DC Bus. A line is drawn between the two filter inductors of the LCL filter circuit connected to the output end of each bridge arm and connected to the midpoint O of the DC bus DC Bus.

[0054] It should be understood that the specific topological forms of the three-phase four-bridge-arm inverter circuit are diverse. After reading the technical solutions provided in the embodiments of the present application, those skilled in the art can easily apply the technical solutions provided in the embodiments of the present application to other similar three-phase four-bridge-arm inverter circuits by the same or equivalent means. The embodiments of the present application do not enumerate all types of three-phase four-bridge-arm inverter circuits. The four three-phase four-bridge-arm inverter circuits provided in the embodiments of the present application are only for schematic reference, and do not limit the three-phase four-bridge-arm inverter circuits to which the technical solutions provided in the embodiments of the present application are applicable.

[0055] The following is a detailed introduction to the four three-phase four-bridge-arm inverter circuits provided in the embodiments of the present application.

[0056] The four three-phase four-arm inverter circuits shown in Figures 2a to 2d all include three main arms A, B, and C and one arm N, where the A main arm includes switching tubes Ta1, Ta2, Ta3, and Ta4. The current generated by the alternating conduction of the switching tubes of the A main arm can output a sinusoidal AC voltage on phase A (point a relative to point O) after passing through the LC filtering of the filter inductor and the filter capacitor; the B main arm includes switching tubes Tb1, Tb2, Tb3, and Tb4. The current generated by the alternating conduction of the switching tubes of the B main arm can output a sinusoidal AC voltage on phase B (point b relative to point O) after passing through the LC filtering of the filter inductor and the filter capacitor; the C main arm includes switching tubes Tc1, Tc2, Tc3, and Tc4. The current generated by the alternating conduction of the switching tubes of the C main arm can output a sinusoidal AC voltage on phase C (point c relative to point O) after passing through the LC filtering of the filter inductor and the filter capacitor. The N bridge arm includes switch tubes Tn1, Tn2, Tn3 and Tn4. When the inverter 100 supplies power to an unbalanced load, the currents on the three main bridge arms of the three-phase four-bridge-arm inverter circuit are unbalanced, and a zero-sequence current is generated on the N bridge arm. At this time, the N bridge arm can receive a zero-sequence modulation signal, so that the switch tubes Tn1, Tn2, Tn3 and Tn4 can be continuously turned on and off, so that the currents on the three main bridge arms are balanced.

[0057] In one possible implementation, as shown in FIG2a , the inverter circuit 120 adopts a T-type three-level three-phase four-bridge-arm inverter circuit topology, wherein the connection point of the switch tubes Ta1 and Ta4 is connected to the LCL filter circuit at the output end of the A bridge arm, and the switch tubes Ta2 and Ta3 are connected in reverse series between the connection point of the switch tubes Ta1 and Ta4 and the midpoint of the DC bus DC Bus; the connection point of the switch tubes Tb1 and Tb4 is connected to the LCL filter circuit at the output end of the B bridge arm, and the switch tubes Tb2 and Tb3 are connected in reverse series between the connection point of the switch tubes Tb1 and Tb4 and the midpoint of the DC bus DC Bus; the connection point of the switch tubes Tc1 and Tc4 is connected to the LCL filter circuit at the output end of the C bridge arm, and the switch tubes Tc2 and Tc3 are connected in reverse series between the connection point of the switch tubes Tc1 and Tc4 and the midpoint of the DC bus DC Bus. The connection point between switches Tn1 and Tn4 is connected to the LCL filter circuit at the output of the N-arm. Switches Tn2 and Tn3 are connected in reverse series between the connection point between switches Tn1 and Tn4 and the midpoint of the DC bus (DC Nus). The reverse direction refers to the conduction direction of the parasitic diodes of the switches being opposite.

[0058] In one possible embodiment, as shown in FIG2b , the inverter circuit 120 adopts an I-type three-level three-phase four-bridge-arm inverter circuit topology. The switch tubes Ta1, Ta2, Ta3, and Ta4 of the A bridge arm are connected in series between the positive terminal and the negative terminal of the DC bus DC Bus, wherein the switch tubes Ta1 and Ta2 have the same direction, and the switch tubes Ta3 and Ta4 have opposite directions to the switch tubes Ta1 and Ta2. The output end of the A bridge arm is connected to the LCL filter circuit of the output end of the A bridge arm from between the switch tubes Ta2 and Ta3. Two diodes Da5 and Da6 with opposite conduction directions are connected in series between the connection point of the switch tubes Ta1 and Ta2 and the connection point of the switch tubes Ta3 and Ta4. The connection point of the diodes Da5 and Da6 is connected to the midpoint of the DC bus DC Bus; the switch tubes Ta2 and Ta3 are connected in series in reverse direction between the connection point of the switch tubes Ta1 and Ta4 and the midpoint of the DC bus DC Bus; the switch tubes Tb1, Tb2, Tb3, and Tb4 of the B bridge arm are connected in series to the DC bus DC Bus. Bus, wherein the directions of the switch tubes Tb1 and Tb2 are the same, and the directions of the switch tubes Tb3 and Tb4 are opposite to those of the switch tubes Tb1 and Tb2. The output end of the B bridge arm is led out from between the switch tubes Tb2 and Tb3 and connected to the LCL filter circuit at the output end of the B bridge arm. Two diodes Db5 and Db6 with opposite conduction directions are connected in series between the connection point of the switch tubes Tb1 and Tb2 and the connection point of the switch tubes Tb3 and Tb4. The connection point of the diodes Db5 and Db6 is connected to the midpoint of the DC bus DC Bus; the switch tubes Tb2 and Tb3 are connected in reverse series between the connection point of the switch tubes Tb1 and Tb4 and the midpoint of the DC bus DC Bus; the switch tubes Tc1, Tc2, Tc3 and Tc4 of the C bridge arm are connected in series to the DC bus DC Between the positive and negative terminals of Cus, wherein the switching tubes Tc1 and Tc2 have the same direction, and the switching tubes Tc3 and Tc4 have the opposite direction to the switching tubes Tc1 and Tc2. The output end of the C bridge arm is connected to the LCL filter circuit at the output end of the C bridge arm from between the switching tubes Tc2 and Tc3. Two diodes Dc5 and Dc6 with opposite conduction directions are connected in series between the connection point of the switching tubes Tc1 and Tc2 and the connection point of the switching tubes Tc3 and Tc4. The connection point of the diodes Dc5 and Dc6 is connected to the midpoint of the DC bus DC Cus. The switching tubes Tc2 and Tc3 are connected in reverse series between the connection point of the switching tubes Tc1 and Tc4 and the midpoint of the DC bus DC Cus.The N-arm switches Tn1, Tn2, Tn3, and Tn4 are connected in series between the positive and negative terminals of the DC Bus. Switches Tn1 and Tn2 have the same direction, while switches Tn3 and Tn4 have opposite directions. The output of the N-arm is connected from between switches Tn2 and Tn3 to an LCL filter circuit at the output of the N-arm. Two diodes Dn5 and Dn6 with opposite conduction directions are connected in series between the connection point between switches Tn1 and Tn2 and the connection point between switches Tn3 and Tn4. The connection point between diodes Dn5 and Dn6 is connected to the midpoint of the DC Bus. Switches Tn2 and Tn3 are connected in series in opposite directions between the connection point between switches Tn1 and Tn4 and the midpoint of the DC Bus.

[0059] In one possible embodiment, as shown in FIG2c , the inverter circuit 120 adopts a T-type two-level three-phase four-bridge-arm inverter circuit, wherein the switch tubes Ta1 and Ta2 of the A bridge arm are connected in series in the same direction between the positive terminal and the negative terminal of the DC bus DC Bus, and the connection point of the switch tubes Ta1 and Ta2 leads to the output end of the A bridge arm, and the output end of the A bridge arm is connected to the LCL filter circuit of the A bridge arm; the switch tubes Tb1 and Tb2 of the B bridge arm are connected in series in the same direction between the positive terminal and the negative terminal of the DC bus DC Bus, and the connection point of the switch tubes Tb1 and Tb2 leads to the output end of the B bridge arm, and the output end of the B bridge arm is connected to the LCL filter circuit of the B bridge arm; the switch tubes Tc1 and Tc2 of the C bridge arm are connected in series in the same direction between the positive terminal and the negative terminal of the DC bus DC Bus, and the connection point of the switch tubes Tc1 and Tc2 leads to the output end of the C bridge arm, and the output end of the C bridge arm is connected to the LCL filter circuit of the C bridge arm; the switch tubes Tn1 and Tn4 of the N bridge arm are connected in series in the same direction between the DC bus DC Bus. Between the positive and negative terminals of the Bus, the connection point of the switching tubes Tn1 and Tn4 leads to the output end of the N bridge arm, and the output end of the N bridge arm is connected to the LCL filter circuit of the N bridge arm. The switching tubes Tn2 and Tn3 of the N bridge arm are connected in series between the connection point of the switching tubes Tn1 and Tn4 and the midpoint of the DC bus DC Bus.

[0060] In one possible implementation, as shown in FIG2d , the inverter circuit 120 adopts an I-type two-level three-phase four-bridge-arm inverter circuit. Compared with the I-type three-level three-phase four-bridge-arm inverter circuit shown in FIG2b , two switching tubes are omitted in each of the three main bridge arms A, B, and C, and only four switching tubes are retained in the N bridge arm. Diodes Dn5 and Dn6 are retained, which are reversely connected in series between the connection point of the switching tubes Tn1 and Tn2 and the connection point of the switching tubes Tn3 and Tn4.

[0061] It should be noted that, in addition to processing zero-sequence current, the N bridge arm can also improve the power output quality of the three-phase four-bridge-arm inverter circuit by receiving common-mode signals together with the main bridge arm.

[0062] In one possible implementation, by simultaneously injecting a common-mode signal into the main bridge arm and the N bridge arm, the modulation mode of the main bridge arm can be changed, thereby improving the operating state of the inverter 100. Without changing the characteristics of the output phase voltage of the inverter 100, by injecting the common-mode signal, the bus voltage utilization rate of the inverter circuit 120 can be improved, or discontinuous modulation of the main bridge arm can be achieved, thereby reducing the switching losses of the main bridge arm. The common-mode signal switches between unipolar and bipolar modulation, which can avoid the loss of the modulation signal when the modulation signal of the N bridge arm is small.

[0063] The technical solution provided in the embodiments of the present application will be described in detail below with reference to specific circuit topologies and control methods as examples.

[0064] Taking Figures 1a and 2a as an example, inverter 100 includes an inverter circuit 120, which has the circuit topology shown in Figure 2a. The input of inverter circuit 120 is connected to the DC output of photovoltaic string 200 via a DC bus, and the output of inverter circuit 120 is connected to the power consumption equipment and the power grid. The controller 110 in inverter 100 is used to control the operation of inverter circuit 120, inputting pulse width modulation (PWM) signals to the switching transistors in inverter circuit 120, thereby driving inverter circuit 120 to perform DC-to-AC power conversion.

[0065] It is understood that the PWM modulation signal for each main bridge arm is the AC output phase voltage corresponding to that main bridge arm divided by half the DC input voltage. For example, in Figure 1a, half the DC input voltage is half the DC bus voltage. During normal use of the inverter 100, if the grid voltage or load voltage does not change significantly, its AC output voltage generally remains unchanged. For example, the three-phase AC output voltage of the inverter 100 during normal use has a line voltage RMS value of 380V, or an output industrial standard line voltage RMS value of 690V. Taking 380V line voltage as an example, the effective value of the phase voltage of each phase of the inverter circuit 120 is 220V, then the waveform of the three-phase AC output phase voltage presents a sine wave with a voltage peak of 220*sqrt(2)=311.17V, and the phase difference between the phases of the three-phase AC output voltage is 120°, which corresponds to the voltage of the three main bridge arm output voltages of the three-phase four-bridge arm inverter circuit 120 relative to the midpoint of the DC bus, such as the voltage of point a relative to point O, the voltage of point b relative to point O, and the voltage of point c relative to point O in Figure 2a.

[0066] The DC bus voltage is determined by the DC input voltage of the inverter circuit 120. For example, if the AC output voltage is 220V RMS, when the DC input voltage is 700V, the DC bus voltage is 700V. The modulation signal of the inverter circuit 120 is a sinusoidal modulation signal with a peak value of 311.17 / 350 = 0.889. In this case, the modulus of the modulation signal received by the inverter circuit 120 is always less than 1. In other words, the inverter circuit 120 is never overmodulated and can always operate in sinusoidal pulse width modulation (SPWM) mode. Furthermore, the controller 110 can inject a common-mode signal into the three main bridge arms A, B, C and N of the inverter circuit 120, so that the inverter circuit 120 operates in a space vector pulse width modulation (SVPWM) mode, thereby improving the utilization rate of the bus voltage by the inverter circuit 120 and improving the working efficiency of the inverter 100.

[0067] In addition to using the common-mode signal to improve the utilization rate of the DC input voltage of the inverter circuit 120, the common-mode signal can also be injected to make the switch tube of the main bridge arm work in a discontinuous state, thereby reducing the loss of the switch tube of the main bridge arm.

[0068] Referring to Figure 4a, a waveform diagram of the modulation signal of one of the main bridge arms of the inverter circuit 120 is shown before and after the common-mode signal is injected. The modulation signal waveforms of the other two main bridge arms are identical, differing only by a 120° phase difference. The modulation signals of the other two main bridge arms are not described in detail here. As shown in Figure 4a, the main bridge arm modulation signal, which is a sinusoidal waveform, becomes a quasi-sinusoidal waveform after being superimposed with a common-mode signal. Specifically, the common-mode signal is superimposed on the original modulation signal of the main bridge arm so that the modulation signal of the main bridge arm remains at 1 near the peak of the original modulation signal of the main bridge arm. This controls the switch of the main bridge arm to remain in a long-on state for a period of time. During this period, the switch of the main bridge arm does not perform continuous switching, operating in discontinuous pulse width modulation (DPWM) mode, which can reduce the switching losses of the main bridge arm switch. In this case, the output voltage of the main bridge arm is clamped to half the voltage of the DC bus for a period of time during the main bridge arm modulation cycle. It should be understood that the period of time here can be a continuous period of time or multiple periods of time, and the duration of these multiple periods of time is the same.

[0069] Referring to Figure 4b , the modulation signal of the main bridge arm is larger than the modulation signal in Figure 4a , and the value of the modulation signal of the main bridge arm at its peak is 1. For example, when the effective value of the AC output voltage is 220V, the DC input voltage is 622.34V, and the voltage of the DC bus is 622.34V. Half of the voltage of the DC bus is exactly equal to the peak value of 311.17V of the AC voltage output by the inverter circuit 120. At this time, the absolute value of the common-mode signal in the period near the peak of the modulation signal of the main bridge arm can be correspondingly reduced. After superposition with the modulation signal of the main bridge arm, a quasi-sine wave modulation signal can be obtained. Near the peak of the original modulation signal of the main bridge arm, the value of the modulation signal of the main bridge arm remains 1. The main bridge arm switch remains on, and the main bridge arm switch does not perform continuous switching. Instead, it operates in discontinuous PWM mode, which can reduce the switching loss of the main bridge arm switch.

[0070] Referring to Figure 4c, the modulation signal of the main bridge arm is further increased relative to the modulation signal in Figure 4b, and the absolute value of the modulation signal is greater than 1 within a certain period of time. For example, the effective value of the AC output voltage is 220V, the DC input voltage is 600V, and the voltage of the DC bus DC Bus is 600V. The modulation signal of the three-phase four-bridge arm inverter circuit is a sinusoidal modulation signal with a peak value of 311.17 / 300=1.037. In this case, the inverter circuit 120 has a modulation signal with a modulus greater than 1 within a modulation cycle, that is, the inverter circuit 120 will be in an overmodulation state for a certain period of time within a modulation cycle, resulting in distortion of the output voltage waveform and inability to operate normally in the SPWM mode. At this time, the main bridge arm can also be made to operate in the discontinuous PWM mode by injecting a common-mode signal.

[0071] The following is a mathematical deduction to introduce the specific implementation principle of DPWM modulation. In the conventional PWM modulation process, the main bridge arms A, B, and C receive the modulation signal U respectively. a 、U b 、U c By injecting common-mode signals into the N bridge arm and the three main bridge arms at the same time, a reverse or same-direction common-mode signal is superimposed on the peak of the modulation signal of the main bridge arm, so that the modulation signal of the main bridge arm is maintained at 1 for a certain period of time. At this time, the modulation signal of the A bridge arm is U sa =U a +U Cmv , the modulation signal of the B bridge arm is U sb =U b +U Cmv , the modulation signal of the C bridge arm is U sc =U c +U Cmv, so that the absolute value of the modulation signal at the peak of the output voltage waveform changes from greater than 1 or less than 1 to equal to 1, so that the modulation signal of the main bridge arm is a modulation signal in the form of a sine wave after the peak of the modulation signal is "clipped". The output voltage of the main bridge arm superimposed with the common-mode signal is a superimposed common-mode voltage. Since there is also a common-mode signal in the N bridge arm, the N bridge arm also outputs a common-mode voltage. The final output of each phase voltage of the inverter circuit 120, taking phase A as an example, is the output voltage of the A bridge arm minus the output voltage of the N bridge arm. The common-mode voltage is offset, and the final output A phase voltage is still the voltage waveform controlled by the original modulation signal of the A bridge arm. That is to say, after the common-mode signal is injected, the modulation signal for adjusting the A phase voltage is equivalent to, U an =U sa -U n =U sa -U Cmv =U a .

[0072] Although theoretically the main bridge arm can be made to operate in DPWM mode by injecting a common-mode signal, since the switch tube is limited by the minimum on-time and dead time, when the common-mode signal is small, the modulation signal on the N bridge arm may be too small to effectively control the switch tube on the N bridge arm to perform continuous switching operations, resulting in the loss of the common-mode signal on the N bridge arm, and ultimately causing the voltage waveform output by the inverter circuit 120 to be distorted.

[0073] For example, when the DC input voltage is 600V, the modulation signal of the main bridge arm has a low degree of overmodulation at the peak, and the maximum value of the modulation signal is only 1.037. The maximum value of the modulus of the reverse common-mode signal that needs to be injected is also small, only 0.037. Due to the limitations of the dead time and the minimum on-time of the switch tube, the common-mode signal sent by the controller 110 to the switch tube of the N bridge arm may be lost, resulting in the common-mode signal U received by the N bridge arm. Cmv In fact, it is equal to 0. However, the common-mode signal on the main bridge arm is superimposed on the original modulation signal of the main bridge arm. The total modulation signal of the main bridge arm is larger, and the common-mode signal will not be lost due to the limitation of the dead time and the minimum conduction time of the switch tube. sa Still satisfied with U an =U sa -U n =U sa +U Cmv –0=U a +U Cmv Therefore, the output voltage waveform of the main bridge arm is relative to the output voltage waveform of the N bridge arm, that is, the phase voltage waveform of phase A. Since the common mode voltage part cannot be offset, the final phase voltage waveform presented is a distorted sine wave after "peak clipping".

[0074] The previous embodiment addresses the issue of modulation signal loss caused by injecting a common-mode signal through unipolar modulation. Unipolar modulation means that during the positive or negative half of the modulation cycle, the bridge arm output PWM voltage is either exclusively positive or 0, or exclusively negative or 0. To prevent modulation signal loss when the spikes are small, bipolar modulation can be used to inject the common-mode signal. Bipolar modulation means that within any modulation cycle, the PWM voltage output by the bridge arm can switch back and forth between positive level, negative level and 0 level. By partially offsetting each other between the positive level and the negative level, it can eventually be equivalent to a unipolar modulation signal that is only positive level or only negative level in half a cycle. For example, a positive modulation signal with a magnitude of 0.1 is output through unipolar modulation. When bipolar modulation is used, a superimposed positive modulation signal with an absolute value of 0.3 and a negative modulation signal with an absolute value of 0.2 can be output, resulting in a positive modulation signal with an absolute value of 0.1 equivalent to the output under unipolar modulation. This can increase the absolute value of the common-mode signal, thereby preventing the common-mode signal on the N bridge arm from being lost due to the absolute value of the modulation signal being too small.

[0075] Figure 5a shows a schematic diagram of injecting a common-mode signal into the N-bridge arm using unipolar modulation. Referring to Figure 2a, during half a modulation cycle, only switches Tn1 and Tn3 are turned on, or only switches Tn2 and Tn4 are turned on, so that the output voltage of the N-bridge arm remains at a positive level and zero level, or at a negative level and zero level, throughout the half modulation cycle. Combining the PWM signal of switch Tn1 with the common-mode signal, it can be seen that when the common-mode signal is small, the PWM pulse width of switch Tn1 is small, meaning that the on-time of switch Tn1 is short. This may result in the inability to achieve short-term on / off switching due to the limitations of switch Tn1's dead time and minimum on-time. This ultimately results in the loss of the modulation signal and the failure of common-mode signal injection.

[0076] Continuing to refer to FIG5b, a schematic diagram of injecting a common-mode signal into the N-bridge arm using bipolar modulation is shown. Similarly, in conjunction with FIG2a, within half a modulation cycle, the switch tube Tn1, the switch tube Tn2, the switch tube Tn3, and the switch tube Tn4 will all be turned on or off, so that the output voltage of the N-bridge arm switches between three levels: positive level, zero level, and negative level within half a modulation cycle. It can be understood that the positive and negative levels are switched in a short period of time, and the external output voltage is ultimately expressed as a positive voltage (the positive level PWM pulse width is longer than the negative level PWM pulse width) or a negative voltage (the positive level PWM pulse width is shorter than the negative level PWM pulse width). The bipolar modulation signal can be equivalent to the unipolar modulation signal, and the final output voltage waveform is the same. Because the PWM signal pulse width received by the switch tube of the N bridge arm is large under bipolar modulation, the N bridge arm will not lose the modulation signal, thereby ensuring that the N bridge arm can effectively output the common-mode voltage. Ultimately, the common-mode voltage part of the output voltage of the main bridge arm can offset the output voltage of the N bridge arm, so that the phase voltage of the output three-phase AC power is in the form of a sine wave.

[0077] The principle of using bipolar modulation to equal unipolar modulation can be explained as follows:

[0078] Among them, in the unipolar PWM signal, combined with reference to Figure 2a and Figure 6a, it is assumed that the instantaneous value of the modulation wave is t, the switching frequency is fs, and the modulation period of carrier 1 and carrier 2 is ts. Among them, the waveforms of carrier 1 and carrier 2 are both isosceles right triangles. Carrier 1 is used to control switch tubes Tn1 and switch tube Tn3, and carrier 2 is used to control switch tubes Tn2 and switch tubes Tn4.

[0079] Taking the switch tube Tn1 as an example, it can be seen that the pulse width t of the modulation wave t controlling the switch tube Tn1 to be turned on (and controlling the switch tube Tn3 to be turned off) is on for:

[0080] When t on When the value is less than 10%, the PWM signal will be limited by the dead time and minimum on-time of the switch tube, resulting in the loss of the PWM signal.

[0081] The basic principle of the bipolar PWM modulation method is shown in Figure 6b. The bipolar PWM modulation method uses a bipolar triangular carrier wave and a modulation wave that alternate between positive and negative. The bipolar PWM signal can be directly obtained by comparing the triangular carrier wave and the modulation wave. Therefore, the bipolar modulation involved in this application is characterized by the presence of positive, zero, and negative levels in the positive and negative half-cycles of the bridge arm output voltage modulation, that is, the P, O, and N levels exist in each half modulation cycle. By adjusting the bipolar coefficient, the modulation signal offset compensation can be flexibly performed.

[0082] Among them, the principle of bipolar PWM modulation is:

[0083] To address the narrow pulse problem, the modulation wave t is compensated. k is the compensation value. After compensation, the modulation signal of modulation wave 1 is 0.5t+k, and the modulation signal of modulation wave 2 is 0.5tk. This is equivalent to splitting the modulation wave into modulation wave 1 and modulation wave 2. Modulation wave 1 is used to control switching transistors Tn1 and Tn3, and modulation wave 2 is used to control switching transistors Tn2 and Tn4.

[0084] 1) The time for level 1 is the on-time of switch tube tn1 (off-time of switch tube tn3), which is equivalent to:

[0085] 2) The time for the -1 level is the off time of the switch tube tn4 (the on time of the switch tube tn2), which is equivalent to:

[0086] 3) From 1) and 2), we can know that the equivalent level time is:

[0087] Alternatively, this can be achieved as follows:

[0088] 1) The time for level 1 is the on-time of switch tube tn1 (off-time of switch tube tn3), which is equivalent to:

[0089] 2) The time for the -1 level is the off time of the switch tube tn4 (the on time of the switch tube tn2), which is equivalent to:

[0090] 3) From 1) and 2), we can know that the equivalent level time is:

[0091] From the above analysis, we can see that by adjusting the k value, we can compensate for the switching transistor modulation signal, thereby solving the narrow pulse problem without affecting the actual results. Obviously, under bipolar modulation, by dynamically adjusting the distribution of t and combining k value compensation, the same technical effect as under unipolar modulation can be achieved.

[0092] Based on the above-mentioned equivalence principle of unipolar modulation and bipolar modulation, bipolar modulation can be used when the modulation signal of the N bridge arm is small to avoid the loss of the modulation signal.

[0093] In one possible implementation provided in the present application, taking FIG2a as an example, in conjunction with FIG5a and FIG5b, the controller 110 injects a common-mode signal into the three main bridge arms A, B, and C and the N bridge arm in a unipolar manner as shown in FIG5a when the absolute value of the instantaneous value of the modulation signal of the N bridge arm is greater than the first effective modulus value. Alternatively, when the absolute value of the instantaneous value of the modulation signal of the N bridge arm is less than the second effective modulus value, the controller 110 injects a common-mode signal into the three main bridge arms A, B, and C and the N bridge arm in a bipolar manner as shown in FIG5b, thereby avoiding loss of the modulation signal and preventing distortion of the output waveform of the main bridge arm when the modulation signal of the N bridge arm is small. It should be understood that the first effective modulus value is greater than or equal to the second effective modulus value.

[0094] By switching between unipolar and bipolar modulation modes, the inverter circuit 120 can flexibly perform various DPWM modulations without causing modulation signal loss and reducing switching losses in the main bridge arm. Two DPWM control modes are described below.

[0095] Referring to Figure 7a, a schematic diagram of the modulation signal received by inverter circuit 120 operating in DPWM modulation mode is shown. Because the modulation signal in the main bridge arm is "clipped" at its peak, the modulus of the modulation signal remains constant at 1. Switches T2 and T3 in the main bridge arm can be considered to be in a long-on state. During this period, the switches are inactive, which reduces switching losses. In other words, the switches in the main bridge arm do not continuously switch on and off within a modulation cycle, and can be considered to operate in a discontinuous state. This modulation method, which injects a common-mode signal and thus inactivates the switches in the main bridge arm for a period of time within a modulation cycle, is the DPWM modulation mode. As previously mentioned, DPWM modulation can be achieved by injecting a common-mode signal using either unipolar modulation or bipolar modulation. Since unipolar modulation may risk common-mode signal loss in the N-bridge arm, bipolar modulation can be used to inject the common-mode signal, increasing the PWM pulse width of the common-mode signal, thereby preventing loss of the common-mode signal in the N-bridge arm and ensuring DPWM modulation.

[0096] It is understood that, referring to Figure 7b, DPWM control can also be performed when the modulation signal is small. When the modulation signal of the main bridge arm is small, that is, when the modulation signal of the main bridge arm is less than 1, such as when the modulus value of the modulation signal is 0.2-0.5, DPWM modulation can also be achieved by injecting a common-mode signal in the same direction.

[0097] With reference to Figures 7a and 7b , DPWM modulation can occur at the peak of the original main bridge arm modulation signal. This modulation method of performing DPWM modulation at the peak is referred to as DPWM1 mode below. Of course, DPWM modulation can also occur on both sides of the peak of the original main bridge arm modulation signal. This modulation method of performing DPWM modulation on both sides of the peak is referred to as DPWM2 mode below.

[0098] It should be understood that the modulus of the common-mode signal injected in DPWM1 mode is small, resulting in higher efficiency, but there is a risk of modulation signal loss when the modulation signal is large; the modulus of the common-mode signal injected in DPWM2 mode is large, but lower efficiency, and there is a risk of common-mode oscillation when the modulation signal is small. Therefore, bipolar modulation can be performed in DPWM1 mode to avoid modulation signal loss, while unipolar modulation can be performed in DPWM2 mode. Although the risk of common-mode oscillation may still exist, unipolar modulation is more efficient than bipolar modulation. In this way, the main bridge arm of the inverter circuit 120 can operate in a discontinuous state as much as possible, thereby reducing switching losses and improving efficiency.

[0099] In a possible implementation provided in the present application, for example, in DPWM1 mode, DPWM modulation is performed on the main bridge arm when the absolute value of the instantaneous value of the modulation signal of the main bridge arm is greater than or equal to a first threshold.

[0100] Specifically, referring to (1) in Figure 7a, a modulation cycle of the main bridge arm begins at time t1 and ends at time t5. Time t3 is the middle moment of the modulation cycle of the main bridge arm. Between time t1 and time t3 or between time t3 and time t5, the modulation signal of the main bridge arm before the common mode is injected passes the peak value. After the common mode signal is added, the modulation signal of the main bridge arm remains at 1 for a period of time. At this time, the switch tube of the main bridge arm does not operate and remains in the on state or the off state, thereby reducing the switching loss of the switch tube of the main bridge arm. During these two periods, the output voltage of the main bridge arm is clamped at half the DC bus voltage value. The length of these two periods can be the same and less than the time of 1 / 2 modulation cycle of the main bridge arm.

[0101] Further, referring to (2) in FIG7a, the time when the value of the aforementioned modulation signal is 1 can be symmetrically distributed based on the 1 / 4 cycle moment of the modulation period. Time t1 is the 1 / 4 cycle moment of the modulation period of the main bridge arm, time t2 is the 1 / 2 cycle moment of the modulation period of the main bridge arm, and a period of time starts at time t3 and ends at time t4, wherein t2>t4>t1>t3, and t4 minus t1 is equal to t1 minus t3, that is, time t1 is located in the middle of time t2 and time t3, and this period of time is symmetrically distributed based on the 1 / 4 cycle moment of the modulation period of the main bridge arm. Similarly, the time when the modulation signal is 1 can also be symmetrically distributed based on the 3 / 4 cycle moment of the modulation period, which will not be repeated here.

[0102] In another possible implementation provided in the present application, for example, in DPWM2 mode, DPWM modulation is performed on the main bridge arm when the absolute value of the instantaneous value of the modulation signal of the main bridge arm is less than or equal to the second threshold and greater than or equal to the third threshold. Because the modulation signal at the zero crossing point is often difficult to control accurately, the third threshold here is usually greater than 0.

[0103] Specifically, referring to (1) in FIG7b , a modulation cycle of the main bridge arm starts at time t1 and ends at time t5, t2 is the 1 / 4 cycle of the modulation cycle of the main bridge arm, t3 is the middle of the modulation cycle of the main bridge arm, and t4 is the 3 / 4 cycle of the modulation cycle of the main bridge arm; during the time when the output voltage of the main bridge arm is clamped to half the DC bus voltage value, the modulation signal of the main bridge arm before the corresponding common mode is injected does not pass the peak. The time when the output voltage of the main bridge arm is clamped to half the DC bus voltage value can be between time t1 and time t2 and time t2 and time t3, or simultaneously between time t1 and time t2, time t2 and time t3, time t3 and time t4, and time t4 and time t5. During the time when the output voltage of the main bridge arm is clamped to half the DC bus voltage value, the switch tube of the main bridge arm does not operate and remains in the on state or the off state, thereby reducing the switching loss of the switch tube of the main bridge arm.

[0104] Further, referring to (2) in FIG7b, the time t1 is the 1 / 4 cycle time of the modulation period of the main bridge arm, and the time t2 is the 1 / 2 cycle time of the modulation period of the main bridge arm. The period in which the output voltage of the main bridge arm is clamped at half the DC bus voltage value is two time periods of equal length, wherein the first period starts at the time t3 and ends at the time t4, and the second period starts at the time t5 and ends at the time t6, wherein t2>t6>t5>t1>t4>t3, and t1 minus t4 is equal to t5 minus t1, and t4 minus t3 is equal to t6 minus t5. In other words, the duration of the two time periods is equal and symmetrically distributed based on the 1 / 4 cycle time of the modulation period of the main bridge arm. Similarly, the two time periods in which the modulation signal is 1 can also be symmetrically distributed based on the 3 / 4 cycle time of the modulation period of the main bridge arm, which will not be repeated here.

[0105] It should be noted that since the magnitude of the modulation signal is equal to the ratio of the AC output phase voltage to the half-bus voltage, in actual applications, the AC output phase voltage is usually set according to the needs of the power grid and the load and remains unchanged. In this scenario, the magnitude change of the modulation signal can be directly observed by observing the change in the DC bus voltage. The threshold condition of the modulation signal set in the aforementioned embodiment can also be changed to set a threshold condition for the DC bus voltage as a condition for switching between unipolar modulation and bipolar modulation. For example, when the DC bus voltage is greater than the set voltage threshold, it can be considered that the modulation signal is small and unipolar modulation is adopted. When the DC bus voltage is less than or equal to the set voltage threshold, it can be considered that the modulation signal is large and bipolar modulation is adopted.

[0106] Similarly, the modulation index can be used as a switching condition between single- and bipolar modulation. The modulation index is the peak value of the AC output phase voltage divided by the half-bus voltage. When the modulation index is greater than the set modulation index threshold, the modulation signal is considered large and bipolar modulation is used. When the modulation index is less than or equal to the set modulation index threshold, the modulation signal is considered small and unipolar modulation is used. Regardless of whether the modulation signal size, DC bus voltage, or modulation index are used as the switching condition between single- and bipolar modulation, the choice between bipolar and unipolar modulation is actually based on the modulus of the injected common-mode signal. When the modulus of the injected common-mode signal is large, unipolar modulation is used, while when the modulus of the injected common-mode signal is small, bipolar modulation is used. Under balanced load conditions, the common-mode signal is the modulation signal of the N-bridge arm. If the modulation signal of the N-bridge arm is too small, the modulation signal of the N-bridge arm will be lost, causing distortion of the three-phase AC output phase voltage and preventing the output of a normal sinusoidal AC output phase voltage.

[0107] The above embodiment introduces the method of performing DPWM modulation on the main bridge arm of a three-phase four-bridge-arm inverter circuit under balanced load. Under unbalanced load, DPWM modulation can be performed in a similar manner, except that a zero-sequence modulation signal is added to the N bridge arm under unbalanced load. Under unbalanced load, the magnitude of the zero-sequence voltage is equal to u n =1 / 3(u a +u b +u c ), refer to Figure 2a-2c, u a is the voltage from point a to point n, u b is the voltage from point b to point n, u c is the voltage from point C to point N, and the zero-sequence modulation signal is obtained according to the zero-sequence voltage loop control. When the main bridge arm is modulated by DPWM, the common-mode signal U is injected into the main bridge arm and the N bridge arm at the same time. Cmv , the modulated signal received by the N bridge arm is U sn '=U n '+U Cmv , since the load is unbalanced, so u n =1 / 3(u a +u b +u c )≠0, that is, U n '≠0, even if the modulation signal of the main bridge arm is large, the common mode signal U Cmv When the modulus value is small, U sn '=U n '+U Cmv It may also be sufficient to drive the switch tube of the N bridge arm to perform switching action, and the probability of losing the modulation signal of the N bridge arm is small.

[0108] Referring to Figure 7c and Figure 7a, the modulation signal for the N-arm in Figure 7c superimposes a common-mode signal and a zero-sequence modulation signal, compared to the modulation signal for the N-arm in Figure 7a. This increases the modulus of the N-arm modulation signal and reduces the risk of modulation signal loss. The same applies to Figures 7d and 7b. Therefore, under unbalanced load conditions, the switching conditions for the main-arm discontinuous control can be adjusted accordingly to better adapt to the operating conditions under unbalanced loads.

[0109] In one possible implementation provided herein, for example, under unbalanced load conditions, the conditions for placing the main bridge arm in a discontinuous operating state are changed. That is, the conditions for entering the DPWM1 modulation and DPWM2 modulation states can vary. For example, in DPWM1 mode, DPWM modulation is performed on the main bridge arm when the absolute value of the instantaneous value of the modulation signal of the main bridge arm is greater than or equal to the first zero-sequence threshold.

[0110] In another possible implementation provided in the present application, for example, in DPWM2 mode, DPWM modulation is performed on the main bridge arm when the absolute value of the instantaneous value of the modulation signal of the main bridge arm is less than or equal to the second zero-sequence threshold and greater than or equal to the third zero-sequence threshold. Because the modulation signal at the zero-crossing point is often difficult to accurately control, the third zero-sequence threshold here is usually greater than 0.

[0111] It should be noted that within the same modulation cycle, the absolute value of the instantaneous value of the modulation signal in the N bridge arm may be greater than the first effective modulus value during the first time period. In this case, the common-mode signal will be injected into the N bridge arm using unipolar modulation during the first time period. However, if the first effective modulus value is not equal to the second effective modulus value, after the first time period, the absolute value of the instantaneous value of the modulation signal in the N bridge arm will not immediately fall below the second effective modulus value. In this case, the unipolar common-mode signal injection method can be maintained to inject the common-mode signal into the N bridge arm. Similarly, if the absolute value of the instantaneous value of the modulation signal in the N bridge arm is less than the second effective modulus value during the third time period, the common-mode signal will be injected into the N bridge arm using bipolar modulation during the third time period. However, after the third time period, the absolute value of the instantaneous value of the modulation signal in the N bridge arm will not immediately fall above the first effective modulus value. In this case, the bipolar common-mode signal injection method can be maintained to inject the common-mode signal into the N bridge arm. This reduces the switching between common-mode injection methods, simplifies the control logic, and improves control continuity. This control method can be called "hysteresis control".

[0112] 8a and 8b , which are schematic diagrams of two different hysteresis control methods in the embodiments of the present application.

[0113] In a possible implementation provided in the present application, as shown in Figure 8a, the first effective modulus value and the second effective modulus value are equal. At this time, the switching condition has only one first effective modulus value Mth1. When the absolute value of the instantaneous value of the modulation signal of the N bridge arm is greater than the first effective modulus value Mth1, a unipolar modulation method is adopted; when the absolute value of the instantaneous value of the modulation signal of the N bridge arm is reduced to less than the first effective modulus value Mth1, a bipolar modulation method is directly adopted.

[0114] In another possible embodiment provided by the present application, the first effective modulus value and the second effective modulus value are not equal. Referring to FIG8b , the switching condition at this time has a first effective modulus value Mth1 and a second effective modulus value Mth2, and hysteresis control exists. When the absolute value of the instantaneous value of the modulation signal of the N-bridge arm is greater than the first effective modulus value Mth1, a unipolar modulation mode is directly adopted; when the absolute value of the instantaneous value of the modulation signal of the N-bridge arm decreases to less than the second effective modulus value Mth2, a bipolar modulation mode is directly adopted. When the absolute value of the instantaneous value of the modulation signal of the N-bridge arm decreases from greater than the first effective modulus value Mth1 to less than the first effective modulus value Mth1 and then greater than the second effective modulus value Mth2, the former modulation mode can be maintained at this time to avoid switching back and forth between modulation modes. For example, in the interval t1 and t2, since the unipolar modulation mode is adopted in the previous period, in another adjacent period, the absolute value of the instantaneous value of the modulation signal of the N-bridge arm is less than the first effective modulus value Mth1 and greater than the second effective modulus value Mth2, and the unipolar modulation mode is continued. The same applies to bipolar hysteresis control. For example, in the interval t3 and t4, since the bipolar modulation method is adopted in the previous period, in the adjacent period, the absolute value of the instantaneous value of the modulation signal of the N bridge arm is less than the first effective modulus value Mth1 and greater than the second effective modulus value Mth2, and the bipolar modulation method is continued.

[0115] The embodiment of the present application also provides a control method for a three-phase four-bridge-arm inverter circuit. By adjusting the PWM modulation mode of the N-bridge arm and reasonably adjusting the control mode, it is possible to reduce losses in various scenarios while ensuring that the output voltage of the N-bridge arm is effectively controlled, avoiding the influence of dead zones and narrow pulses under low modulation signals, thereby improving the power quality output by the power converter. The specific control method is similar to the control method performed by the controller in the aforementioned embodiment. Please refer to Figures 9a-9b and will not be repeated here.

[0116] The preferred embodiments of the present application disclosed above are intended only to help illustrate the present application. The preferred embodiments do not exhaustively describe all details, nor do they limit the present application to the specific embodiments described. Obviously, many modifications and variations can be made based on the content of the embodiments of the present application. This application selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can better understand and utilize the present application. The present application is limited only by the claims and their full scope and equivalents.

[0117] In the above embodiments, several modulation methods for the N bridge arm in a three-phase four-bridge-arm inverter circuit using single-polarity and bipolarity modulation switching are introduced. The difference between the several modulation modes lies mainly in the different switching conditions of single-polarity and bipolarity modulation, including: (1) the absolute value of the instantaneous value of the modulation signal of the N bridge arm is used as the modulation condition; (2) the magnitude of the modulation index is used as the switching condition; (3) the magnitude of the DC bus voltage is used as the switching condition.

[0118] A modulation mode that uses the absolute value of the instantaneous modulation signal of the N-bridge arm as the modulation condition can be called unipolar-bipolar mixed modulation, because in this modulation mode, unipolar modulation and bipolar modulation typically coexist within the same modulation cycle. As shown in Figures 8a and 8b, unipolar modulation intervals and bipolar modulation intervals coexist within the same modulation cycle.

[0119] The modulation mode that uses the size of the modulation index or the size of the DC bus voltage as the single-polarity and bipolarity modulation switching conditions can be called single-polarity and bipolarity switching modulation, because in this modulation mode, in the same cycle or multiple consecutive modulation cycles, there will usually only be single-polarity modulation or only bipolar modulation.

[0120] It should be understood that the specific implementation of the modulation mode using the magnitude of the modulation index or the magnitude of the DC bus voltage as the switching condition for single-polarity and bipolarity modulation is introduced again below. In the case of using the magnitude of the modulation index as the switching condition for single-polarity and bipolarity modulation, it is necessary to determine the magnitude of the modulation index. The magnitude of the modulation index is the value of the peak value of the AC output phase voltage divided by half the bus voltage. When the modulation index is greater than the set modulation index threshold, it can be considered that the modulation signal is large. At this time, the common-mode signal to be injected is small, the modulation signal of the N bridge arm is small, and bipolar modulation is adopted. When the modulation index is less than or equal to the set modulation index threshold, it can be considered that the modulation signal is small. At this time, the common-mode signal to be injected is large, the modulation signal of the N bridge arm is large, and unipolar modulation is adopted.

[0121] It's worth noting that the modulation index calculation involves a relatively fixed quantity: the output voltage of the three-phase, four-leg inverter circuit. This output voltage generally remains consistent with the grid voltage, which is generally stable. Therefore, in practice, the modulation index is solely determined by the DC bus voltage. Based on the preceding analysis, switching based on the modulation index and the DC bus voltage are effectively the same modulation mode.

[0122] In a modulation mode where the switching condition is based on the magnitude of the modulation index or the magnitude of the DC bus voltage, since the DC bus voltage is typically determined by the input voltage of a DC input source such as an energy storage battery or photovoltaic module, and the input voltage of these DC sources typically remains relatively stable over a period of time and does not experience significant instantaneous fluctuations, the modulation index of the three-phase four-leg inverter circuit typically remains unchanged over a period of time. Therefore, referring to FIG8 c , in a modulation mode where the switching condition is based on the magnitude of the modulation index or the magnitude of the DC bus voltage, within a relatively large modulation index range, that is, when the modulation index of the three-phase four-leg inverter circuit is greater than a first switching threshold, a modulation signal is injected into the N-leg in a bipolar manner. Within a relatively small modulation index range, that is, when the modulation index of the three-phase four-leg inverter circuit is less than a second switching threshold, a modulation signal is injected into the N-leg in a unipolar manner, where the first switching threshold is greater than or equal to the second switching threshold.

[0123] In one embodiment, in order to avoid slight fluctuations that cause the modulation mode to switch back and forth, the first switching threshold is set to be greater than the second switching threshold. There is an interval between the first switching threshold and the second switching threshold. This interval can be called a hysteresis interval. Hysteresis control can be performed within the hysteresis interval. For example, when the modulation index of the three-phase four-bridge-arm inverter circuit changes from greater than the first switching threshold to greater than the second switching threshold and less than or equal to the first switching threshold, the modulation signal is injected into the N bridge arm in a unipolar manner; when the modulation index of the three-phase four-bridge-arm inverter circuit changes from less than the second switching threshold to greater than or equal to the second switching threshold and less than the first switching threshold, the modulation signal is injected into the N bridge arm in a bipolar manner. For the specific control mode, please refer to Figure 9c.

[0124] It should be understood that regardless of the magnitude of the modulation signal, the DC bus voltage, or the modulation index used as the switching condition between bipolar and bipolar, the choice between bipolar and unipolar modulation is actually determined by the modulus of the injected common-mode signal. Unipolar modulation is used when the modulus of the injected common-mode signal is large, while bipolar modulation is used when the modulus of the injected common-mode signal is small. Under balanced load conditions, the common-mode signal is the modulation signal for the N bridge arms. If the modulation signal for the N bridge arm is too small, the N bridge arm modulation signal will be lost, causing distortion in the three-phase AC output phase voltage and preventing the output of a normal sinusoidal AC output phase voltage.

[0125] The preferred embodiments of the present application disclosed above are intended only to help illustrate the present application. The preferred embodiments do not exhaustively describe all details, nor do they limit the present application to the specific embodiments described. Obviously, many modifications and variations can be made based on the content of the embodiments of the present application. This application selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can better understand and utilize the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A power converter, characterized in that: It comprises a three-phase four-bridge-arm inverter circuit and a controller, wherein the input end of the three-phase four-bridge-arm inverter circuit is used to connect a DC input, and the output end of the three-phase four-bridge-arm inverter circuit is used to connect a load; The three-phase four-bridge-arm inverter circuit comprises three main bridge arms and one N bridge arm; The controller is used to inject a common mode signal into the main bridge arm and the N bridge arm, so that the bridge arm output voltage of the main bridge arm is clamped at half of the DC bus voltage during a period of time in the main bridge arm modulation cycle; The controller is further used to inject the modulation signal into the N bridge arm in a unipolar manner when the absolute value of the instantaneous value of the modulation signal of the N bridge arm is greater than the first effective modulus value, or to inject the modulation signal into the N bridge arm in a bipolar manner when the absolute value of the instantaneous value of the modulation signal of the N bridge arm is less than the second effective modulus value, and the first effective modulus value is greater than or equal to the second effective modulus value; or The controller is also used to inject a modulation signal into the N bridge arm in a bipolar manner when the modulation degree of the three-phase four-bridge arm inverter circuit is greater than a first switching threshold, or to inject a modulation signal into the N bridge arm in a unipolar manner when the modulation degree of the three-phase four-bridge arm inverter circuit is less than a second switching threshold, and the first switching threshold is greater than or equal to the second switching threshold.

2. The power converter according to claim 1, characterized in that: Injecting the modulation signal into the N bridge arm in a unipolar manner means controlling the level of the output of the N bridge arm to change only between a positive level and a zero level within half a modulation period, or controlling the level of the output of the N bridge arm to change only between a negative level and a zero level within half a modulation period; Injecting the modulation signal into the N bridge arm in a bipolar manner means controlling the level of the output of the N bridge arm to change between a positive level, a negative level and a zero level within half a modulation period.

3. The power converter according to claim 1 or 2, characterized in that: The controller is used to inject the common mode signal into the main bridge arm and the N bridge arm, so that the main bridge arm operates in a discontinuous state when the absolute value of the instantaneous value of the modulation signal of the main bridge arm is greater than or equal to a first threshold.

4. The power converter according to any one of claims 1 to 3, characterized in that: The controller is used to inject the common-mode signal into the main bridge arm and the N bridge arm so that the bridge arm output voltage of the main bridge arm is clamped at half of the DC bus voltage for a period of time in the main bridge arm modulation cycle when the absolute value of the instantaneous value of the modulation signal of the main bridge arm is less than or equal to a second threshold and greater than or equal to a third threshold, the second threshold is less than the first threshold, and the third threshold is greater than 0 and less than the second threshold.

5. The power converter according to claim 1 or 2, characterized in that: The controller is used for injecting a zero-sequence modulation signal into the N bridge arm when the load is an unbalanced load; The controller is used to inject the common-mode signal into the main bridge arm and the N bridge arm so that the bridge arm output voltage of the main bridge arm when the absolute value of the instantaneous value of the modulation signal of the main bridge arm is greater than the first zero-sequence threshold is clamped at half of the DC bus voltage for a period of time in the main bridge arm modulation cycle.

6. The power converter according to claim 1, 2 or 5, characterized in that: The controller is used to inject the common-mode signal into the main bridge arm and the N bridge arm so that the bridge arm output voltage of the main bridge arm is clamped at half of the DC bus voltage for a period of time in the main bridge arm modulation cycle when the absolute value of the instantaneous value of the modulation signal of the main bridge arm is less than or equal to the second zero-sequence threshold and greater than or equal to the third zero-sequence threshold, the second zero-sequence threshold is less than the first zero-sequence threshold, and the third zero-sequence threshold is greater than 0 and less than the second zero-sequence threshold.

7. The power converter according to any one of claims 1 to 6, characterized in that: A modulation cycle of the main bridge arm includes time t1, time t3, and time t5, wherein t1 is the starting time of the modulation cycle of the main bridge arm, t5 is the ending time of the modulation cycle of the main bridge arm, and time t3 is the middle time of the modulation cycle of the main bridge arm; The period of time is between the moment t1 and the moment t3 or between the moment t3 and the moment t5, or is two identical time periods that are simultaneously between the moment t1 and the moment t3 and between the moment t3 and the moment t5.

8. The power converter according to any one of claims 1 to 6, characterized in that: A modulation cycle of the main bridge arm includes time t1 and time t2, wherein time t1 is 1 / 4 of the modulation cycle of the main bridge arm, and time t2 is 1 / 2 of the modulation cycle of the main bridge arm. The period starts from time t3 and ends at time t4, wherein t2>t4>t1>t3, and t4 minus t1 is equal to t1 minus t3.

9. The power converter according to any one of claims 1 to 6, characterized in that: A modulation cycle of the main bridge arm includes time t1, time t2, time t3, time t4 and time t5, wherein t1 is the starting time of the modulation cycle of the main bridge arm, t2 is the 1 / 4 cycle time of the modulation cycle of the main bridge arm, t3 is the middle time of the modulation cycle of the main bridge arm, t4 is the 3 / 4 cycle time of the modulation cycle of the main bridge arm, and t5 is the end time of the modulation cycle of the main bridge arm; The period of time is two identical time periods simultaneously located between the moment t1 and the moment t2 and between the moment t2 and the moment t3, or is four identical time periods simultaneously located between the moment t1 and the moment t2, between the moment t2 and the moment t3, between the moment t3 and the moment t4, and between the moment t4 and the moment t5.

10. The power converter according to any one of claims 1 to 6, characterized in that: A modulation cycle of the main bridge arm includes time t1 and time t2, wherein time t1 is 1 / 4 of the modulation cycle of the main bridge arm, and time t2 is 1 / 2 of the modulation cycle of the main bridge arm. The period of time is two periods of equal length, wherein the first period of time starts from time t3 and ends at time t4, and the second period of time starts from time t5 and ends at time t6, wherein t2>t6>t5>t1>t4>t3, and t1 minus t4 is equal to t5 minus t1, and t4 minus t3 is equal to t6 minus t5.

11. The power converter according to any one of claims 1 to 10, characterized in that: The first effective modulus value is greater than the second effective modulus value; The controller injects the modulation signal into the N bridge arm in a unipolar manner in the second time period when the absolute value of the instantaneous value of the modulation signal of the N bridge arm is greater than or equal to the first effective modulus value in a first time period and greater than the second effective modulus value and less than the first effective modulus value in an adjacent second time period, and the second time period is after the first time period; or When the absolute value of the instantaneous value of the modulation signal used by the controller for the N bridge arm is less than the second effective modulus value in a third time period and is greater than the second effective modulus value and less than the first effective modulus value in an adjacent fourth time period, the controller injects the modulation signal into the N bridge arm in a bipolar manner in the fourth time period, and the fourth time period is after the third time period.

12. The power converter according to any one of claims 1 to 11, characterized in that: The first switching threshold is greater than the second switching threshold; the controller is used to inject a modulation signal into the N bridge arm in a unipolar manner when the modulation degree of the three-phase four-bridge-arm inverter circuit changes from greater than the first switching threshold to greater than the second switching threshold and less than or equal to the first switching threshold, or to inject a modulation signal into the N bridge arm in a bipolar manner when the modulation degree of the three-phase four-bridge-arm inverter circuit changes from less than the second switching threshold to greater than or equal to the second switching threshold and less than the first switching threshold.

13. A three-phase four-bridge-arm inverter circuit modulation method, characterized in that: The method includes: Injecting a common mode signal into the main bridge arm of the three-phase four-bridge arm inverter circuit and the N bridge arm of the three-phase four-bridge arm inverter circuit, so that the bridge arm output voltage of the main bridge arm is clamped at half of the DC bus voltage for a period of time in the main bridge arm modulation cycle; and When the absolute value of the instantaneous value of the modulation signal of the N bridge arm is greater than the first effective modulus value, the modulation signal is injected into the N bridge arm in a unipolar manner, or when the absolute value of the instantaneous value of the modulation signal of the N bridge arm is less than the second effective modulus value, the modulation signal is injected into the N bridge arm in a bipolar manner; or When the modulation degree of the three-phase four-bridge-arm inverter circuit is greater than the first switching threshold, the modulation signal is injected into the N bridge arm in a bipolar manner, or, when the modulation degree of the three-phase four-bridge-arm inverter circuit is less than the second switching threshold, the modulation signal is injected into the N bridge arm in a unipolar manner, and the first switching threshold is greater than or equal to the second switching threshold.

14. The three-phase four-bridge-arm inverter circuit modulation method according to claim 13, characterized in that: Injecting the modulation signal into the N bridge arm in a unipolar manner means controlling the level of the output of the N bridge arm to change only between a positive level and a zero level within half a modulation period, or controlling the level of the output of the N bridge arm to change only between a negative level and a zero level within half a modulation period; Injecting the modulation signal into the N bridge arm in a bipolar manner means controlling the level of the output of the N bridge arm to change between a positive level, a negative level and a zero level within half a modulation period.

15. The three-phase four-bridge-arm inverter circuit modulation method according to claim 13 or 14, characterized in that: The common-mode signal is injected into the main bridge arm and the N bridge arm so that the output voltage of the main bridge arm when the absolute value of the instantaneous value of the modulation signal of the main bridge arm is greater than or equal to the first threshold is clamped at half of the DC bus voltage for a period of time in the main bridge arm modulation period.

16. The three-phase four-bridge-arm inverter circuit modulation method according to any one of claims 13 to 15, characterized in that: The common-mode signal is injected into the main bridge arm and the N bridge arm so that the output voltage of the main bridge arm is clamped at half of the DC bus voltage for a period of time in the main bridge arm modulation period when the absolute value of the instantaneous value of the modulation signal of the main bridge arm is less than or equal to the second threshold and greater than or equal to the third threshold, wherein the second threshold is less than the first threshold, and the third threshold is greater than 0 and less than the second threshold.

17. The three-phase four-bridge-arm inverter circuit modulation method according to claim 13 or 14, characterized in that: When the load of the three-phase four-bridge-arm inverter circuit is an unbalanced load, injecting a zero-sequence modulation signal into the N bridge arm; The common-mode signal is injected into the main bridge arm and the N bridge arm so that the output voltage of the main bridge arm when the absolute value of the instantaneous value of the modulation signal of the main bridge arm is greater than the first zero-sequence threshold is clamped at half of the DC bus voltage for a period of time in the main bridge arm modulation cycle.

18. The three-phase four-bridge-arm inverter circuit modulation method according to claim 13, 14 or 17, characterized in that: The common-mode signal is injected into the main bridge arm and the N bridge arm so that the bridge arm output voltage of the main bridge arm is clamped at half of the DC bus voltage for a period of time in the main bridge arm modulation period when the absolute value of the instantaneous value of the modulation signal of the main bridge arm is less than or equal to the second zero-sequence threshold and greater than or equal to the third zero-sequence threshold, the second zero-sequence threshold is less than the first zero-sequence threshold, the third zero-sequence threshold is greater than 0 and less than the second zero-sequence threshold, and the third zero-sequence threshold is greater than 0 and less than the second zero-sequence threshold.

19. The three-phase four-bridge-arm inverter circuit modulation method according to any one of claims 13 to 18, characterized in that: A modulation cycle of the main bridge arm includes time t1, time t3, and time t5, wherein t1 is the starting time of the modulation cycle of the main bridge arm, t5 is the ending time of the modulation cycle of the main bridge arm, and time t3 is the middle time of the modulation cycle of the main bridge arm; The period of time is between the moment t1 and the moment t3 or between the moment t3 and the moment t5, or is two identical time periods that are simultaneously between the moment t1 and the moment t3 and between the moment t3 and the moment t5.

20. The three-phase four-bridge-arm inverter circuit modulation method according to any one of claims 13 to 18, characterized in that: A modulation cycle of the main bridge arm includes time t1 and time t2, wherein time t1 is 1 / 4 of the modulation cycle of the main bridge arm, and time t2 is 1 / 2 of the modulation cycle of the main bridge arm. The period starts from time t3 and ends at time t4, wherein t2>t4>t1>t3, and t4 minus t1 is equal to t1 minus t3.

21. The three-phase four-bridge-arm inverter circuit modulation method according to any one of claims 13 to 18, characterized in that: A modulation cycle of the main bridge arm includes time t1, time t2, time t3, time t4 and time t5, wherein t1 is the starting time of the modulation cycle of the main bridge arm, t2 is the 1 / 4 cycle time of the modulation cycle of the main bridge arm, t3 is the middle time of the modulation cycle of the main bridge arm, t4 is the 3 / 4 cycle time of the modulation cycle of the main bridge arm, and t5 is the end time of the modulation cycle of the main bridge arm; The period of time is two identical time periods simultaneously located between the moment t1 and the moment t2 and between the moment t2 and the moment t3, or is four identical time periods simultaneously located between the moment t1 and the moment t2, between the moment t2 and the moment t3, between the moment t3 and the moment t4, and between the moment t4 and the moment t5.

22. The three-phase four-bridge-arm inverter circuit modulation method according to any one of claims 13 to 18, characterized in that: A modulation cycle of the main bridge arm includes time t1 and time t2, wherein time t1 is 1 / 4 of the modulation cycle of the main bridge arm, and time t2 is 1 / 2 of the modulation cycle of the main bridge arm. The period of time is two periods of equal length, wherein the first period of time starts from time t3 and ends at time t4, and the second period of time starts from time t5 and ends at time t6, wherein t2>t6>t5>t1>t4>t3, and t1 minus t4 is equal to t5 minus t1, and t4 minus t3 is equal to t6 minus t5.

23. The three-phase four-bridge-arm inverter circuit modulation method according to any one of claims 13 to 18, characterized in that: The first effective modulus value is greater than the second effective modulus value; When the absolute value of the instantaneous value of the modulation signal of the N bridge arm is greater than or equal to the first effective modulus value in a first time period and greater than the second effective modulus value and less than the first effective modulus value in an adjacent second time period, the modulation signal is injected into the N bridge arm in a unipolar manner in the second time period, and the second time period is after the first time period; or When the absolute value of the instantaneous value of the modulation signal of the N bridge arm is less than the second effective modulus value in the third time period and is greater than the second effective modulus value and less than the first effective modulus value in the adjacent fourth time period, the modulation signal is injected into the N bridge arm in a bipolar manner in the fourth time period, and the fourth time period is after the third time period.

24. The three-phase four-bridge-arm inverter circuit modulation method according to any one of claims 13 to 23, characterized in that: The first switching threshold is greater than the second switching threshold; when the modulation degree of the three-phase four-bridge-arm inverter circuit changes from greater than the first switching threshold to greater than the second switching threshold and less than or equal to the first switching threshold, a modulation signal is injected into the N bridge arm in a unipolar manner, or, when the modulation degree of the three-phase four-bridge-arm inverter circuit changes from less than the second switching threshold to greater than or equal to the second switching threshold and less than the first switching threshold, a modulation signal is injected into the N bridge arm in a bipolar manner.

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