Chip and preparation method therefor, and electronic device

Abstract

The present application provides a chip (100) and a preparation method therefor, and an electronic device (1000). The chip (100) comprises a substrate layer (110), a piezoelectric layer (120), an electrode layer (130), and a release barrier layer (140). The substrate layer (110) and the piezoelectric layer (120) are laminated and bonded, and processing of a pre-embedded groove (150), manufacturing of the release barrier layer (140) and the electrode layer (130), and manufacturing of a recessed cavity (111) of the substrate layer (110) are performed in an integrated circuit processing factory. The material of the release barrier layer (140) is a polymer, and a liquid polymer is easily filled in the pre-embedded groove (150) of the chip (100). The process is simple and the filling effect is good. The hardness of the polymer after curing is small, the stress strain of the substrate layer (110) is small when a filling side is planarized, and there is little damage. The recessed cavity (111) is formed in the substrate layer (110) by means of a reaction between a released fluid and the substrate layer (110), so that a resonance region (121) provided in the piezoelectric layer (120) and the bottom surface of the recessed cavity (111) are arranged spaced apart from one another. A transverse dimension of the recessed cavity (111) is defined by means of the release barrier layer (140), so that the transverse dimension of the recessed cavity (111) can be made small. The substrate layer (110), the piezoelectric layer (120), the electrode layer (130), and the release barrier layer (140) in the chip (100) are combined and can be used as an air gap-type acoustic wave resonator (100a). Preparation of the chip (100) has a low manufacturing difficulty, low costs, and a high yield.

Description

Chip and preparation method thereof, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on November 20, 2023, with application number 202311550478.7 and application name “A chip, its preparation method, and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a chip and a method for manufacturing the same, and an electronic device. Background Art

[0003] The acoustic wave resonators in related technology chips include bulk acoustic wave (BAW) devices and plate wave (plate wave) devices. Both devices can be structurally divided into three categories: back-etched type, air gap type, and solid-state assembly type. These three types of structures can confine the acoustic waves in the piezoelectric layer as much as possible, thereby improving the quality factor (Q) of the device. The air gap type structure is superior to the back-etched type structure in mechanical strength and superior to the solid-state assembly type structure in acoustic wave confinement capability. Therefore, the air gap type structure is widely used in the industry. The air gap type acoustic wave resonator has a concave cavity, and the resonance region of the piezoelectric layer is arranged corresponding to the concave cavity, and an electrode layer is arranged on the resonance region.

[0004] When manufacturing a chip with an air-gap acoustic wave resonator, a release barrier layer or a release sacrificial layer can be embedded in the substrate or dielectric layer to limit the lateral dimensions of the cavity. However, the fabrication of chips with air-gap acoustic wave resonators in related technologies is difficult and costly.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a chip and a method for manufacturing the same, as well as an electronic device, which solve the problem in the related art that the preparation of a chip with an air gap acoustic wave resonator is difficult and costly.

[0007] The embodiments of this application adopt the following technical solutions:

[0008] In the first aspect, an embodiment of the present application provides a chip, comprising: a substrate layer, a piezoelectric layer, an electrode layer and a release barrier layer. The piezoelectric layer and the substrate layer are stacked and bonded, and the piezoelectric layer has a resonance zone. The chip has a pre-buried groove connecting the piezoelectric layer and the substrate layer along the thickness direction of the substrate layer, the pre-buried groove is arranged around the resonance zone, and the pre-buried groove forms an opening on the piezoelectric layer. The electrode layer is provided on the resonance zone. The substrate layer has a concave cavity arranged opposite to the resonance zone, the resonance zone and the bottom surface of the concave cavity are spaced apart in the thickness direction of the substrate layer, and the pre-buried groove and the concave cavity are connected. The material of the release barrier layer is a polymer, and the release barrier layer is provided in the pre-buried groove to limit the lateral size of the cavity.

[0009] In the chip provided in the embodiment of the present application, the wafer factory stacks and bonds the substrate layer and the piezoelectric layer. After the integrated circuit processing factory receives the wafer with the piezoelectric layer and the substrate layer bonded, it performs pre-buried groove processing, releases the barrier layer and the electrode layer, and makes the cavity of the substrate layer. There is no need to move the wafer back and forth between the integrated circuit processing factory and the wafer factory as in the related art, thereby reducing wafer damage. If the size or position of the electrode layer needs to be changed, the position of the pre-buried groove for releasing the barrier layer can be changed directly on the wafer, without having to spend more than 6 weeks to re-customize the piezoelectric layer in the wafer factory as in the related art. The material for releasing the barrier layer is polymer, and the liquid polymer is easy to fill in the pre-buried groove of the chip, with a simple process and good filling effect. The hardness of the polymer is low after solidification, and the stress and strain of the substrate layer is small when the filling side is flattened, causing little damage to the substrate layer. There is no need to pre-customize a thick substrate and grind and thin the bottom side of the substrate after filling the pre-buried groove as in the related art. During the front-end and back-end processing, the polymer can release the mechanical stress of the electrode layer above the cavity, reducing the difficulty of processing. The release fluid reacts with the substrate layer to form a cavity within the substrate layer, spacing the resonant region of the piezoelectric layer and the bottom surface of the cavity across the thickness of the substrate layer. The release barrier layer and the release fluid barely react, limiting the lateral dimensions of the cavity. This allows for smaller lateral dimensions, enabling the placement of more acoustic resonators on the wafer and improving the device's mechanical strength and power tolerance. The substrate layer, piezoelectric layer, electrode layer, and release barrier layer combined within the chip form an air-gap acoustic resonator. This chip is easy to manufacture, low-cost, and offers high yield.

[0010] In an alternative implementation, the substrate layer, the piezoelectric layer, the electrode layer, and the release barrier layer can be combined to form an air-gap acoustic wave resonator. A chip can have one or more acoustic wave resonators.

[0011] In an optional implementation, the chip has multiple acoustic wave resonators, and the multiple acoustic wave resonators can be cascaded together in a series-parallel manner to form a filter.

[0012] In an optional implementation, multiple acoustic wave resonators may share a substrate layer and a piezoelectric layer, and each acoustic wave resonator may have an independent electrode layer and a release barrier layer. A partition wall, which is a portion of the substrate layer, is formed between the cavities of two adjacent acoustic wave resonators.

[0013] In one optional implementation, the piezoelectric layer has a resonant region and a non-resonant region. An electrode layer is disposed on the resonant region. Applying a high-frequency electrical signal to the electrode layer can excite a high-frequency acoustic wave signal in the resonant region. The non-resonant region is the region of the piezoelectric layer outside the resonant region. The non-resonant region corresponds to the region of the substrate layer outside the cavity.

[0014] In an optional implementation, the electrode layer adopts a structure of a predetermined shape, and the piezoelectric layer and the electrode layer adopt a predetermined combination method to form different types of acoustic wave resonators, such as a thin film bulk acoustic wave resonator, a Lamb wave resonator / a transversely excited bulk acoustic wave resonator.

[0015] In an optional implementation, the bonded piezoelectric layer can be a single crystal structure with better orientation and better performance.

[0016] In one optional implementation, the resonant region is provided with multiple release holes, each of which communicates with the concave cavity. After the release holes are formed, a release fluid is allowed to pass through the release holes and react with the substrate layer, thereby forming a depression within the substrate layer. The release holes can be arranged along the edge of the resonant region.

[0017] In an optional implementation, the resonance region is roughly rectangular, and multiple release holes are arranged roughly in a rectangular shape. A release fluid that can react with the substrate layer is introduced into all the release holes, and a concave cavity that is roughly a rounded rectangular cavity when viewed from above can be formed on the substrate layer.

[0018] In an optional implementation, a conductive portion is provided on the piezoelectric layer, and the conductive portion is connected to the electrode layer, so that the electrode layers of multiple acoustic wave resonators are cascaded together in a series-parallel manner to form a filter circuit.

[0019] In one alternative implementation, a transversely excited bulk acoustic wave resonator (TBAW) is employed. The electrode layer includes an interdigital transducer (IDT) located on the side of the resonant region facing away from the substrate layer. The IDT is located on one side of the piezoelectric layer, with the resonant region of the piezoelectric layer located above the cavity, forming an air-gap TBAW resonator. Applying a high-frequency electrical signal between the first and second busbars excites Lamb waves in the resonant region of the piezoelectric layer.

[0020] In an optional implementation, the interdigital transducer may include a first bus bar, a second bus bar, a plurality of first electrode fingers, and a plurality of second electrode fingers, wherein the first bus bar and the second bus bar are arranged in parallel and spaced apart. The plurality of first electrode fingers are spaced in parallel and connected to the same side of the first bus bar. The plurality of second electrode fingers are spaced in parallel and connected to the same side of the second bus bar. The plurality of first electrode fingers and the plurality of second electrode fingers are located between the first bus bar and the second bus bar, and the plurality of first electrode fingers and the plurality of second electrode fingers are arranged alternately in sequence. The first bus bar and the second bus bar can be conductively connected to different conductive parts on the chip to achieve transmission of electrical signals.

[0021] In an optional implementation, the resonance region of the piezoelectric layer may be roughly rectangular, the first bus bar and the second bus bar may extend along the length direction of the resonance region, the plurality of first electrode fingers and the plurality of second electrode fingers may extend along the width direction of the resonance region, and a large number of first electrode fingers and second electrode fingers may be alternately arranged on the resonance region.

[0022] In one alternative implementation, a transversely excited bulk acoustic wave resonator (TBAW) is employed. The electrode layer includes an interdigital transducer (IDT) located on the side of the resonant region facing the substrate layer. The IDT is located on one side of the piezoelectric layer, with the resonant region of the piezoelectric layer located above the cavity, forming an air-gap TBAW resonator. Applying a high-frequency electrical signal between the first and second busbars excites Lamb waves in the resonant region of the piezoelectric layer.

[0023] In one optional implementation, a thin film bulk acoustic wave resonator (FBAR) is employed. The electrode layer includes a first electrode plate and a second electrode plate. The first electrode plate is disposed on the side of the resonant region facing away from the substrate layer, and the second electrode plate is disposed on the side of the resonant region facing the substrate layer. Applying a high-frequency electrical signal between the first and second electrode plates excites bulk acoustic waves in the resonant region of the piezoelectric layer, which oscillate and propagate between the first and second electrode plates.

[0024] In an optional implementation, the material of the piezoelectric layer includes one or more of lithium niobate, lithium tantalate, aluminum nitride, zinc oxide, and quartz in various tangential directions.

[0025] In an optional implementation, the electrode layer and the conductive portion may be made of one or more of aluminum, copper, platinum, molybdenum, tungsten, tantalum, gold, and silver. The electrode layer and the conductive portion may be fabricated using a physical vapor deposition process, such as vacuum evaporation or sputtering.

[0026] In one optional implementation, the substrate layer includes a stacked substrate and a dielectric layer, the dielectric layer being positioned between the substrate and the piezoelectric layer. The piezoelectric layer and the dielectric layer are stacked and bonded together. A pre-buried groove connects the piezoelectric layer, the dielectric layer, and the substrate along the thickness of the substrate layer, and a cavity is formed in the substrate. The dielectric layer is disposed on the substrate, thereby improving the connection effect when the piezoelectric layer and the dielectric layer are stacked and bonded together. The pre-buried groove connects the piezoelectric layer, the dielectric layer, and the substrate, and a release barrier layer is disposed in the pre-buried groove.

[0027] In one optional implementation, the substrate layer includes a stacked substrate and a dielectric layer, the dielectric layer being positioned between the substrate and the piezoelectric layer. The piezoelectric and dielectric layers are stacked and bonded together. A pre-buried groove connects the piezoelectric and dielectric layers along the thickness of the substrate layer, and a cavity is formed in the dielectric layer. The dielectric layer is disposed on the substrate, providing a better connection when the piezoelectric and dielectric layers are stacked and bonded together. The pre-buried groove connects the piezoelectric and dielectric layers, and a release barrier layer is disposed in the pre-buried groove.

[0028] In one optional implementation, the base material layer includes a substrate, the piezoelectric layer and the substrate are laminated and bonded, the embedded groove is connected to the substrate along the thickness direction of the base material layer, and the cavity is formed on the substrate. The embedded groove is formed on the substrate, and the release barrier layer is provided in the embedded groove.

[0029] In an optional implementation, the material of the substrate includes one or more of silicon, silicon carbide, diamond, sapphire, aluminum nitride, ceramic, lithium tantalate, and lithium niobate.

[0030] In an optional implementation, the material of the dielectric layer includes one or more of silicon dioxide, silicon nitride, silicon oxynitride, or aluminum oxide. By providing the dielectric layer on the substrate, a good connection effect is achieved when the piezoelectric layer and the dielectric layer are stacked and bonded.

[0031] In an optional implementation, the embedded groove and the release barrier layer have the same cross-sectional shape in a top view, and the cross-sectional shapes of the embedded groove and the release barrier layer can be arranged along a circle, an ellipse, or a polygon. The polygon can be a triangle, a quadrilateral, or a multi-sided shape.

[0032] In an optional implementation, the electrode layer is arranged in a substantially rectangular shape, the release barrier layer is arranged in a substantially rectangular ring shape, and the cross-section of the cavity defined by the release barrier layer in a top view is substantially rectangular.

[0033] In one optional implementation, the pre-buried slot includes multiple sub-slots distributed around the resonant region and connected end-to-end. The release barrier layer includes multiple transverse barrier portions, each correspondingly filling the multiple sub-slots. A transverse barrier portion is formed in each sub-slot, and the multiple transverse barrier portions are connected to form a ring-shaped release barrier layer.

[0034] In one optional implementation, the pre-buried slot includes multiple sub-slots distributed around the resonant region and spaced apart in sequence. The release barrier layer includes multiple transverse barrier portions, each correspondingly filling the multiple sub-slots. A transverse barrier portion is formed in each sub-slot, and the multiple transverse barrier portions are spaced apart, unconnected, and generally annularly distributed.

[0035] In an optional implementation, the plurality of transverse barriers in the release barrier layer may be arranged in a circular, elliptical or polygonal shape, wherein the polygon may be a triangle, a quadrilateral or a multi-sided shape.

[0036] In an optional implementation, the electrode layer is arranged in a roughly rectangular shape, the multiple transverse blocking portions in the release barrier layer are arranged in a roughly rectangular ring shape, and the cross-section of the cavity defined by the release barrier layer in a top view is roughly rectangular.

[0037] In an optional implementation, the longitudinal depth of the pre-buried groove or the release barrier layer ranges from 1 μm to 50 μm. The liquid polymer is flowed into the pre-buried groove.

[0038] In an optional implementation, the width of the release barrier layer in a top view is greater than or equal to 10 microns, so that the liquid polymer can easily flow into and fully fill the embedded groove.

[0039] In an optional implementation, the plurality of transverse barrier portions in the release barrier layer are arranged substantially in a rectangular ring shape.

[0040] In an optional implementation, the polymer may include one or more of polyimide, polydimethylsiloxane, polyvinylidene fluoride, benzocyclobutene, polyethylene terephthalate, and photoresist. The photoresist may be polymethyl methacrylate, etc.

[0041] In an optional implementation, the release barrier layer can be formed by spin-coating a polymer to fill the pre-buried trench, curing the polymer, and planarizing the filled side of the polymer. The filled side of the polymer refers to the side of the wafer filled with polymer during the manufacturing process.

[0042] In one optional implementation, the Young's modulus of the polymer after curing is less than 10 gigapascals (GPa). This lower Young's modulus and lower hardness of the cured polymer allow for planarization of one side of the polymer-filled layer, resulting in less stress and minimal damage to the substrate layer caused by the processing force transmitted to the substrate layer. The polymer can also relieve mechanical stress on the electrode layer above the cavity, reducing processing difficulty.

[0043] In an optional implementation, the Young's modulus of the polymer after curing is less than 5 GPa. The smaller the Young's modulus of the polymer after curing, the lower the hardness, and the less damage to the substrate layer when flattening one side of the filled polymer.

[0044] In an optional implementation, the chip has one or more microgrooves connecting the piezoelectric layer and the substrate layer along the thickness direction of the substrate layer, and the one or more microgrooves are connected to the embedded groove. The microgrooves may form openings on the piezoelectric layer.

[0045] Liquid polymer can enter the pre-embedded grooves, but has difficulty entering the microgrooves. When the polymer is heated and cured, bubbles form within the liquid polymer in the pre-embedded grooves. These bubbles can then overflow through the unfilled microgrooves nearby, allowing the polymer to more fully and tightly fill the pre-embedded grooves. The microgrooves provide a certain amount of deformation space for the release barrier layer, which expands due to heat.

[0046] In an optional implementation, the embedded groove may include a plurality of sub-grooves, and each sub-groove may correspond to one or more connected micro-grooves.

[0047] In an optional implementation, a plurality of microgrooves are arranged at intervals along the edge of the resonance region.

[0048] In an optional implementation, the pre-buried groove includes a plurality of sub-grooves distributed around the resonance region and connected end to end in sequence, and each sub-groove can be connected to the micro-groove.

[0049] In an optional implementation, the pre-buried groove includes a plurality of sub-grooves distributed around the resonance region and arranged in sequence and at intervals, and each sub-groove may also be connected to the micro-groove.

[0050] In a kind of optional implementation, the cross-sectional shape of microgroove in top view can be circular, elliptical, polygonal or X-shaped.Polygon can be the shape of triangle, quadrilateral or more sides.One side or part of the polygonal cross section of microgroove is connected with pre-embedded groove, makes liquid polymer be difficult to enter by the opening of microgroove, also be difficult to enter in the microgroove by pre-embedded groove.

[0051] In an optional implementation, the cross-section of the microgroove in a top view is circular, and a portion of the circular cross-section of the microgroove is connected to a long side of the sub-groove in the embedded groove.

[0052] In an optional implementation, the cross-sectional shape of the microgroove in the top view is a triangle, and one side of the microgroove triangular cross section is connected with the long side of the subgroove in the embedded groove. In addition, one end of the microgroove triangular cross section can also be connected with the long side of the subgroove.

[0053] In an optional implementation, the cross-section of the microgroove in a top view is rectangular, and a short side of the rectangular cross-section of the microgroove is connected to a long side of the sub-groove in the embedded groove.

[0054] In an optional implementation, the cross-sectional shape of the microgroove in a top view is X-shaped, and one end of the X-shaped cross-sectional shape of the microgroove is connected to the long side of the sub-groove in the embedded groove.

[0055] In an optional implementation, the length of the microgroove in a top view is less than or equal to 10 micrometers (um). Or, the cross-sectional area of ​​the microgroove in a top view is less than or equal to 100 square micrometers (um). 2 ). This makes it difficult for liquid polymer to enter the microgrooves through the openings.

[0056] In an optional implementation, the cross-sectional shape of the microgroove in the top view is circular, and the length of the microgroove in the top view is the diameter of the circular cross-sectional shape.

[0057] In an optional implementation, the cross-sectional shape of the microgroove in the top view is a triangle, and the length of the microgroove in the top view is the maximum side length of the triangle.

[0058] In an optional implementation, the cross-sectional shape of the microgroove in the top view is a rectangle, and the length of the microgroove in the top view is the length of the long side of the rectangular cross-sectional shape.

[0059] In an optional implementation, the cross-sectional shape of the microgroove in the top view is X-shaped, and the length of the microgroove in the top view is the length of an arm of the X-shaped cross-section.

[0060] In an optional implementation, a communication port is formed between the microgroove and the embedded groove, and the length of the communication port is less than or equal to 10 micrometers (um); or, a communication port is formed between the microgroove and the embedded groove, and the cross-sectional area of ​​the communication port is less than or equal to 100 square micrometers (um). 2 The connecting port has a rectangular cross section, and the length of the connecting port is the long side dimension of the connecting port on the rectangular cross section of the connecting port, so that it is difficult for the liquid polymer to enter the micro groove from the embedded groove through the connecting port.

[0061] In an optional implementation, the substrate layer, the piezoelectric layer, the electrode layer, and the release barrier layer may be combined to form an air-gap acoustic wave resonator, and a plurality of acoustic wave resonators may be cascaded to form a filter.

[0062] In an optional implementation, the filter can be used as a separate component, or the filter can be integrated with components such as a power amplifier into a module, and the filter is coupled to the power amplifier for signal processing and transmission.

[0063] In an optional implementation, the filter includes a plurality of cascaded resonators, which may have different resonant frequencies and are cascaded together in a series-parallel manner. The filter has a signal input terminal Vi, a signal output terminal Vo, and a ground terminal GND.

[0064] In a second aspect, an embodiment of the present application provides an electronic device, including a printed circuit board and the above-mentioned chip, wherein the chip is arranged on the printed circuit board.

[0065] In one optional implementation, the electronic device is a mobile phone, and includes a cover plate, a display screen, a middle frame, and a rear housing. The rear housing and the display screen are located on opposite sides of the middle frame, respectively. The middle frame and the display screen may be disposed within the rear housing. The cover plate is disposed on a side of the display screen away from the middle frame, with the display side of the display screen facing the cover plate.

[0066] In an optional implementation, the display screen may be a liquid crystal display screen, which includes a liquid crystal display panel and a backlight module. The liquid crystal display panel is disposed between the cover plate and the backlight module, and the backlight module is used to provide light source for the liquid crystal display panel.

[0067] In an optional implementation, the display screen may be an organic light emitting diode display screen. A self-luminous display screen does not require a backlight module.

[0068] In an optional implementation, the middle frame may include a carrying plate and a frame arranged around the carrying plate.

[0069] In an optional implementation, the electronic device may further include a system-on-chip (SoC), a radio frequency (RF) chip, etc., disposed on a printed circuit board (PCB). The PCB is used to carry the SoC, the RF chip, etc., and is electrically connected to the SoC, the RF chip, etc. The RF chip may include components such as a filter and a processor. The processor is used to process various signals.

[0070] In a third aspect, an embodiment of the present application provides a method for preparing a chip, comprising:

[0071] Wafers with laminated bonding of piezoelectric layers and substrate layers;

[0072] Etching a pre-buried groove on the wafer, wherein the pre-buried groove connects the piezoelectric layer and the substrate layer along the thickness direction of the substrate layer, the pre-buried groove is arranged around the resonance region of the piezoelectric layer, and the pre-buried groove forms an opening on the piezoelectric layer; when etching the pre-buried groove on the wafer, a photoresist or other material can be used as a mask for etching the pre-buried groove pattern;

[0073] Spin-coating a polymer on the piezoelectric layer so that the polymer fills the embedded groove; during the spin-coating process, the liquid polymer enters the embedded groove through the opening of the embedded groove, forming a good filling;

[0074] Curing the polymer and flattening the filled side of the polymer to form a release barrier layer for the polymer in the embedded groove; the filled side of the polymer refers to the side of the wafer filled with polymer during the manufacturing process;

[0075] forming an electrode layer on the resonance region;

[0076] Making a release hole penetrating the piezoelectric layer; when making the release hole, photoresist or other materials can be used as a mask for making the release hole pattern;

[0077] The release fluid passes through the release hole and reacts with the substrate layer through etching to form a cavity on the substrate layer. The resonance region and the bottom surface of the cavity are spaced apart in the thickness direction of the substrate layer, and the lateral size of the cavity is limited by the release barrier layer.

[0078] In the chip fabrication method provided in the embodiments of the present application, the wafer fab stacks and bonds the substrate layer and the piezoelectric layer. After the wafer with the piezoelectric layer and substrate layer bonded is received by the integrated circuit fabrication plant, a pre-embedded groove is machined on the wafer to form the release barrier layer and the electrode layer, and the cavity of the substrate layer is formed. The release barrier layer is formed without being restricted by the bonding between the piezoelectric layer and the substrate layer. This eliminates the need to shuttle the wafer back and forth between the integrated circuit fabrication plant and the wafer fab, as in related art, thus reducing wafer damage. To change the size or position of the electrode layer, the position of the pre-embedded groove for the release barrier layer can be directly changed on the wafer, eliminating the need to spend more than six weeks re-customizing the piezoelectric layer at the fab, as in related art. The release barrier layer is made of a polymer, and liquid polymers are easily filled into the pre-embedded grooves of the chip, resulting in a simple process and excellent filling effect. The polymer has a low hardness after curing, and the stress and strain in the substrate layer are reduced during flattening of the filled side, causing minimal damage to the substrate layer. This eliminates the need to pre-customize a thick substrate and then grind and thin the bottom side of the substrate after filling the pre-embedded groove, as in related art. During the front-end and back-end processing, the polymer can release the mechanical stress of the electrode layer above the cavity, reducing the difficulty of processing. By releasing the fluid and reacting with the substrate layer, a cavity is formed in the substrate layer, so that the resonance area of ​​the piezoelectric layer provided on the substrate layer and the bottom surface of the cavity are spaced apart in the thickness direction of the substrate layer. The release barrier layer and the release fluid hardly react with each other, and the lateral size of the cavity is limited by the release barrier layer, so that the lateral size of the cavity can be made smaller, and more acoustic resonators can be arranged on the wafer, thereby improving the mechanical strength and power tolerance of the device. The preparation process of the chip with a release barrier layer is optimized, the processing process is more reasonable, the process feasibility is improved, the chip preparation difficulty is small, the cost is low, and the yield is high.

[0079] In one optional implementation, etching a pre-buried groove on a wafer specifically includes: applying photoresist to the surface of the piezoelectric layer; matching the pattern of the photoresist plate to the shape of the pre-buried groove, placing the wafer on a photolithography machine, aligning the wafer and the photoresist plate, and then performing exposure; developing the film to remove the portion of the photoresist corresponding to the pre-buried groove area, thereby transferring the pattern of the photoresist plate to the photoresist; using the photoresist as a mask for etching the pre-buried groove pattern, and etching to transfer the photoresist pattern to the wafer, thereby forming the pre-buried groove on the wafer. The etching process may be plasma reactive etching.

[0080] In one optional implementation, etching a pre-buried groove on a wafer specifically includes etching a pre-buried groove and one or more microgrooves on the wafer, wherein the one or more microgrooves connect the piezoelectric layer and the substrate layer along the thickness of the substrate layer, and the one or more microgrooves are connected to the pre-buried groove. The microgrooves may form openings in the piezoelectric layer. A photoresist or other material may be used as a mask for etching the pre-buried groove pattern and the microgroove pattern, and the interconnected pre-buried groove and microgroove are etched on the wafer.

[0081] In one optional implementation, when forming microgrooves, etching the pre-buried grooves and microgrooves on a wafer specifically includes: applying photoresist to the surface of the piezoelectric layer; matching the pattern of the photoresist plate to the shape of the pre-buried grooves and microgrooves; placing the wafer on a photolithography machine, aligning the wafer and the photoresist plate, and then performing exposure; after development, removing portions of the photoresist corresponding to the pre-buried grooves and microgrooves, thereby transferring the pattern of the photoresist plate to the photoresist; using the photoresist as a mask for etching the pre-buried groove and microgrooves pattern, and etching to transfer the pattern of the photoresist to the wafer, thereby forming the pre-buried grooves and microgrooves on the wafer. The etching can be plasma reactive etching.

[0082] In one optional implementation, one or more microgrooves are provided on the side of the pre-buried groove facing the resonance zone. Alternatively, one or more microgrooves are provided on the side of the pre-buried groove facing away from the resonance zone. Alternatively, one or more microgrooves are provided on the side of the pre-buried groove facing the resonance zone, and one or more microgrooves are provided on the side of the pre-buried groove facing away from the resonance zone. Microgrooves can be provided on one or both sides of the pre-buried groove. When filling the pre-buried groove, liquid polymer easily enters the pre-buried groove but has difficulty entering the microgrooves, and the interior of the microgrooves may be empty.

[0083] In an optional implementation, the polymer is cured and the filled side of the polymer is planarized, specifically including: pre-baking the wafer filled with the polymer; photolithography development to remove the polymer outside the extended space of the embedded groove; dry stripping to remove the polymer outside the embedded groove; planarizing the filled side of the polymer; and completely baking the wafer to cure the polymer.

[0084] In an optional implementation, curing the polymer and planarizing the filled side of the polymer specifically includes: completely baking the wafer filled with the polymer to cure the polymer; and planarizing the filled side of the polymer.

[0085] In one optional implementation, the polymer fill side is planarized, specifically by one or more of photolithography, dry etching, and chemical mechanical polishing. This planarization of the polymer fill side creates a flat surface on the piezoelectric layer, paving the way for subsequent electrode layer formation on the piezoelectric layer.

[0086] In an optional implementation, an electrode layer is made on the resonant region of the piezoelectric layer, and a conductive portion is made on the non-resonant region of the piezoelectric layer. The conductive portion and the electrode layer are connected and conductive, so that the electrode layers of multiple acoustic wave resonators are cascaded together in series and parallel to form a filter circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0087] (a) and (b) in FIG1 are schematic diagrams of the structure of a chip of the related art;

[0088] Figures (a) to (h) in Figure 2 are schematic diagrams of the chip preparation process in the related art;

[0089] Figures (a) to (h) in Figure 3 are schematic diagrams of a chip preparation process according to another related art;

[0090] Figures (a) to (h) in Figure 4 are schematic diagrams of a chip preparation process according to another related art;

[0091] FIG5 is a front view of a chip provided in an embodiment of the present application;

[0092] FIG6 is a partial cross-sectional view of the chip along line AA of FIG5 ;

[0093] Figure 7 (a) to (h) are schematic diagrams of the preparation process of the chip in Figure 6;

[0094] FIG8 is a schematic structural diagram of a chip provided in another embodiment of the present application;

[0095] FIG9 is a schematic structural diagram of a chip provided in another embodiment of the present application;

[0096] FIG10 is a schematic structural diagram of a chip provided in another embodiment of the present application;

[0097] FIG11 is a schematic structural diagram of a chip provided in another embodiment of the present application;

[0098] FIG12 is a front view of a chip provided in another embodiment of the present application;

[0099] FIG13 is a front view of a chip provided in another embodiment of the present application;

[0100] FIG14 is a partial cross-sectional view of the chip along line BB of FIG13;

[0101] Figure 15 (a) to (h) are schematic diagrams of the preparation process of the chip in Figure 14;

[0102] Figures 16 (a) to (d) are schematic structural diagrams of embedded grooves and microgrooves provided in different embodiments of the present application;

[0103] FIG17 is a circuit diagram of a filter provided in an embodiment of the present application;

[0104] FIG18 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0105] FIG19 is a flow chart of a method for preparing a chip according to an embodiment of the present application;

[0106] FIG20 is a schematic diagram of the preparation process of a chip provided in an embodiment of the present application, wherein the polymer is cured and the filled side is planarized;

[0107] FIG21 is a flow chart of a partial method for preparing a chip provided in an embodiment of the present application;

[0108] FIG22 is a schematic diagram of a chip preparation process of curing the polymer and planarizing the filled side according to another embodiment of the present application;

[0109] Figure 23 is a flow chart of part of the chip preparation method provided in the embodiments of the present application.

[0110] Explanation of Reference Numerals: 1-chip; 1a-resonator; 2-substrate; 3-dielectric layer; 4-piezoelectric layer; 5-electrode layer; 6-cavity; 7-release barrier layer; 8-release sacrificial layer; 9-embedded groove; 10-release hole; 11-photoresist; 100-chip; 100a-resonator; 110-substrate layer; 111-cavity; 112-substrate; 113-dielectric layer; 120-piezoelectric layer; 121-resonant region; 122-non-resonant region; 130-electrode layer; 130a-conductive portion; 131-interdigital transducer; 1311-first bus bar; 1312-second bus bar; 1313-first electrode finger; 1314-second electrode finger; 132-first electrode plate; 133-second electrode plate; 140-release barrier layer; 141-lateral barrier; 140a-polymer; 150-embedded groove; 151-opening; 152-sub-groove; 153-extension space; 160-release hole; 170-microgroove; 171-opening; 172-connecting port; 180-photoresist; 200-printed circuit board; 300-cover plate; 400-display screen; 500-middle frame; 510-carrying board; 520-frame; 600-back cover; 1000-electronic device. DETAILED DESCRIPTION

[0111] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application clearer, the application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit this application. Although the description of this application will be introduced in conjunction with some embodiments, this does not mean that the features of this application are limited to this embodiment. On the contrary, the purpose of introducing the application in conjunction with the embodiment is to cover other options or modifications that may be extended based on the claims of this application. In order to provide an in-depth understanding of the application, the following description will contain many specific details. This application can also be implemented without using these details. In addition, in order to avoid confusion or blurring the focus of this application, some specific details will be omitted in the description. It should be noted that the embodiments in this application and the features in the embodiments can be combined with each other unless there is a conflict.

[0112] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0113] It should be understood that in the description of the embodiments of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "installation" and "connection" should be understood in a broad sense. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium. The orientation or positional relationship indicated by the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0114] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0115] In the embodiments of this application, "and / or" is simply a description of the association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this document generally indicates that the related objects are in an "or" relationship.

[0116] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in yet other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0117] Referring to (a) and (b) in FIG1 , a chip 1 having an air gap type acoustic wave resonator 1a in the related art mainly includes a substrate 2, a dielectric layer 3, a piezoelectric layer 4 and an electrode layer 5. The substrate 2 has a cavity 6. The piezoelectric layer 4 and the bottom surface of the cavity 6 are spaced apart, and the electrode layer 5 is provided on the piezoelectric layer 4. A release barrier layer 7 (as shown in FIG2 ) or a release sacrificial layer 8 (as shown in FIG3 ) can be pre-buried in the substrate 2 or the dielectric layer 3 to achieve the limitation of the lateral size of the cavity 6. The lateral size of the cavity 6 refers to the size in any direction on a plane perpendicular to the thickness direction of the substrate 2 (such as the size in the left and right directions in FIG1 ). By limiting the lateral size of the cavity 6, the cavities 6 of adjacent resonators 1a are prevented from being connected, so that there is a larger connection area between the substrate 2 and the piezoelectric layer 4, thereby improving the mechanical strength of the device; and the size of a single resonator 1a can be made smaller, which facilitates the flexible arrangement of multiple acoustic wave resonators 1a on a wafer.

[0118] Referring to Figures 1(a) and (b), when fabricating an air-gap acoustic wave resonator 1a, the piezoelectric layer 4 can be epitaxially grown on a substrate 2. The piezoelectric layer 4 can also be bonded to the substrate 2. Compared to epitaxially grown polycrystalline piezoelectric layers 4, bonded piezoelectric layers 4 are single-crystal structures, offering better orientation and performance. However, pre-embedding a release barrier layer 7 or a release sacrificial layer 8 between the bonded piezoelectric layer 4 and substrate 2 can be difficult and expensive.

[0119] There are various fabrication techniques for the air-gap acoustic wave resonator 1a bonded to the piezoelectric layer 4. For example, a release barrier layer 7 or sacrificial layer 8 can be pre-embedded before the piezoelectric layer 4 is bonded. Alternatively, the piezoelectric layer 4 can be bonded first and then the release barrier layer 7 is pre-embedded. These fabrication techniques are described below.

[0120] Referring to FIG2 , the preparation process of pre-embedding the release barrier layer 7 and then bonding the piezoelectric layer 4 is as follows: First, as shown in (a) and (b) of FIG2 , the wafer substrate 2 is etched by the integrated circuit fabrication factory (fab) to etch a pre-embedded groove 9 corresponding to the release barrier layer 7 on the substrate 2; then, as shown in (c) of FIG2 , a material that does not react with the released gas (such as silicon dioxide) is used as the release barrier layer 7 material, and the release barrier layer 7 material is filled in the pre-embedded groove 9, and the filled side is flattened; then, as shown in (d) of FIG2 , the pre-embedded release barrier layer 7 is formed. The substrate 2 is sent to the wafer factory, which bonds the single crystal piezoelectric layer 4 and the substrate 2; finally, the bonded wafer is sent back to the integrated circuit processing factory for device processing; as shown in (e) in Figure 2, an electrode layer 5 is set on the piezoelectric layer 4; as shown in (f) in Figure 2, a photoresist 11 is used as a mask for the non-release hole area; as shown in (g) in Figure 2, a release hole 10 is etched on the piezoelectric layer 4; as shown in (h) in Figure 2, the released gas is reacted with the substrate 2 through the release hole 10 to complete the release of the substrate 2, forming a cavity 6 on the substrate 2, and the lateral size of the cavity 6 is limited by the release barrier layer 7.

[0121] Referring to FIG3 , the preparation process of pre-embedding the release sacrificial layer 8 and then bonding the piezoelectric layer 4 is as follows: First, as shown in (a) and (b) in FIG3 , the integrated circuit processing plant etches the wafer substrate 2 and etches a pre-embedded groove 9 corresponding to the release sacrificial layer 8 on the substrate 2; then, as shown in (c) in FIG3 , a material that easily reacts with the released gas is selected as the release sacrificial layer 8 material, the release sacrificial layer 8 material is filled in the pre-embedded groove 9, and the filled side is flattened; then, as shown in (d) in FIG3 , the substrate 2 pre-embedded with the release sacrificial layer 8 is sent to the wafer factory, and the wafer factory The single crystal piezoelectric layer 4 and the substrate 2 are bonded; finally, the bonded wafer is sent back to the integrated circuit processing plant for device processing; as shown in (e) in FIG3 , an electrode layer 5 is set on the piezoelectric layer 4; as shown in (f) in FIG3 , a photoresist 11 is used as a mask for the non-release hole area; as shown in (g) in FIG3 , a release hole 10 is etched on the piezoelectric layer 4; as shown in (h) in FIG3 , the released gas is reacted with the release sacrificial layer 8 through the release hole 10 to complete the release of the release sacrificial layer 8, and a cavity 6 is formed on the substrate 2, and the lateral size of the cavity 6 is limited by the release sacrificial layer 8.

[0122] Referring to FIG4 , the preparation process of first bonding the piezoelectric layer 4 and then pre-embedding the release barrier layer 7 is as follows: First, as shown in FIG4 (a), the integrated circuit processing plant obtains the wafer from the wafer factory, and the substrate 2, the dielectric layer 3 and the piezoelectric layer 4 are stacked in sequence, and the piezoelectric layer 4 and the dielectric layer 3 are already bonded; as shown in FIG4 (b), a photoresist 11 or other material is used as an etching mask; as shown in FIG4 (c), a pre-embedded groove 9 and a release hole 10 are etched on the piezoelectric layer 4 and the substrate 2; as shown in FIG4 (d), the release hole 10 is covered with a photoresist 11. 0; then, as shown in (e) in FIG4 , a metal or dielectric material is selected as the material of the release barrier layer 7, and the release barrier layer 7 material is filled in the embedded groove 9; as shown in (f) in FIG4 , the filling side is flattened; then, as shown in (g) in FIG4 , an etching or release process is used to release gas through the release hole 10 to remove a predetermined area of ​​the dielectric layer 3, forming a cavity 6 on the dielectric layer 3, and the lateral size of the cavity 6 is limited by the release barrier layer 7; finally, as shown in (h) in FIG4 , an electrode layer 5 is provided on the piezoelectric layer 4.

[0123] Referring to Figures 2 and 3, the first two preparation processes are to pre-embed the release barrier layer 7 or release sacrificial layer 8 before bonding the piezoelectric layer 4. The wafer needs to travel back and forth between the integrated circuit processing plant and the wafer fab many times, which may cause damage to the wafer. The pre-embedded position of the release barrier layer 7 or the release sacrificial layer 8 is set in a one-to-one correspondence with the position of the electrode layer 5. If the size or position of the electrode layer 5 is to be changed, the pre-embedded position of the release barrier layer 7 or the release sacrificial layer 8 must be changed on the wafer. The piezoelectric layer 4 needs to be re-customized from the wafer fab. The piezoelectric layer 4 is a high-precision device, involving bonding the piezoelectric layer 4 to the substrate 2, plasma thinning of the piezoelectric layer 4, grinding and polishing, and other process steps, which takes more than 6 weeks.

[0124] Referring to FIG4 , the third preparation process is to first bond the piezoelectric layer 4 and then pre-embed the release barrier layer 7. As shown in FIG4 (d), the depth of the pre-embedded groove 9 corresponding to the release barrier layer 7 is the sum of the thickness of the photoresist 11, the thickness of the piezoelectric layer 4, and the thickness of the dielectric layer 3. The pre-embedded groove 9 is relatively deep and narrow, that is, the aspect ratio of the pre-embedded groove 9 is large. The use of traditional deposition techniques such as sputtering and evaporation to fill the pre-embedded groove 9 with metal or dielectric materials is difficult, has poor filling properties, and a complex filling process. As shown in FIG4 (e), after filling, part of the material covers the surface of the photoresist 11, and the filled side needs to be flattened and polished. The hardness of the metal or dielectric material is relatively high, and the processing force is transmitted to the substrate 2, causing the stress of the substrate 2 to be relatively large, which can easily cause damage to the substrate 2. During the front-to-back processing, the metal or dielectric material is not easy to release the stress of the electrode layer 5 above the cavity 6. A substrate 2 with a large thickness can be customized in advance, and after the embedded groove 9 is filled with metal or dielectric material, it is flattened. The bottom side of the substrate 2 with greater stress is ground and thinned to overcome the high stress problem caused by flattening.

[0125] As shown in (g) and (h) in FIG4 , the cavity 6 is first processed on the dielectric layer 3, and then the piezoelectric layer 4 is made on the piezoelectric layer 4. The manufacturing process is very risky and has a low yield. The electrode layer 5 is made on the bottom unsupported area of ​​the piezoelectric layer 4, which can easily cause deformation and damage to the piezoelectric layer 4. As shown in (c) and (d) in FIG4 , after the embedded groove 9 and the release hole 10 are made, the photoresist 11 and the developer in the process will enter the embedded groove 9 and the release hole 10. The openings of the embedded groove 9 and the release hole 10 are very small, making it difficult for the liquid to flow out. The photoresist 11 adheres to the wall of the release hole 10 and solidifies into a film, which is not conducive to the release of gas and the reaction of the dielectric layer 3, and will affect the formation of the cavity 6.

[0126] As can be seen, the preparation of the chip 1 with the air-gap acoustic wave resonator 1a in the related art is difficult and costly. When pre-embedding the release barrier layer 7, the piezoelectric layer 4 and substrate 2 bonded together in the related art are difficult to achieve good filling of the release barrier layer 7 material. Flattening of the filled side after filling can easily damage the substrate 2.

[0127] To facilitate description of the orientation of the chip 100, the two directions on the top surface of the chip 100 are defined as the X and Y directions. The direction perpendicular to the top surface of the chip 100, or the top view direction, is defined as the Z direction. The thickness direction of the chip 100 and the thickness direction of the substrate layer 110 in the chip 100 are both the Z direction. The X, Y, and Z directions are mutually perpendicular.

[0128] 5 and 6 , an embodiment of the present application provides a chip 100 comprising: a substrate layer 110, a piezoelectric layer 120, an electrode layer 130, and a release barrier layer 140. The piezoelectric layer 120 and the substrate layer 110 are stacked and bonded, and the piezoelectric layer 120 has a resonance region 121. The chip 100 has a pre-buried groove 150 connecting the piezoelectric layer 120 and the substrate layer 110 along the thickness direction (Z direction) of the substrate layer 110. The pre-buried groove 150 is arranged around the resonance region 121, and the pre-buried groove 150 forms an opening 151 on the piezoelectric layer 120. The electrode layer 130 is provided on the resonance region 121. The substrate layer 110 has a concave cavity 111 arranged opposite to the resonance region 121. The bottom surfaces of the resonance region 121 and the concave cavity 111 are spaced apart in the thickness direction (Z direction) of the substrate layer 110, and the pre-buried groove 150 and the concave cavity 111 are connected. The release barrier layer 140 is made of a polymer and is disposed in the embedded groove 150 to limit the transverse dimension of the cavity 111 .

[0129] The substrate layer 110, piezoelectric layer 120, electrode layer 130, and release barrier layer 140 combine to form an air-gap acoustic wave resonator 100a. The chip 100 may have one or more acoustic wave resonators 100a. If the chip 100 has multiple acoustic wave resonators 100a, the multiple acoustic wave resonators 100a can be cascaded in series and parallel to form a filter. The filter allows signals of a predetermined frequency to pass while blocking signals of another predetermined frequency. The chip 100 may be a filter chip, a radio frequency chip, or other chip.

[0130] In the acoustic filter, multiple acoustic wave resonators 100a can share a base layer 110 and a piezoelectric layer 120, and each acoustic wave resonator 100a has an independent electrode layer 130 and a release barrier layer 140. A partition wall, i.e., a portion of the base layer 110, is formed between the cavities 111 of two adjacent acoustic wave resonators 100a.

[0131] The substrate layer 110 serves as the bottom layer of the chip 100 and as a carrier of the piezoelectric layer 120, the electrode layer 130, etc. The embedded groove 150 and the cavity 111 are connected only when there is no release barrier layer 140 disposed in the embedded groove 150.

[0132] The piezoelectric layer 120 is made of piezoelectric material, which has both piezoelectric effect and inverse piezoelectric effect. The piezoelectric effect refers to the generation of a potential difference when pressure is applied to a piezoelectric material. The inverse piezoelectric effect refers to the generation of mechanical stress when voltage is applied to a piezoelectric material. Applying high-frequency pressure (mechanical vibration) to a piezoelectric material generates a high-frequency current. Applying a high-frequency electrical signal to a piezoelectric material generates a high-frequency acoustic signal (mechanical vibration), i.e., an ultrasonic signal.

[0133] The piezoelectric layer 120 has a resonant region 121 and a non-resonant region 122. An electrode layer 130 is provided on the resonant region 121. Applying a high-frequency electrical signal to the electrode layer 130 can excite a high-frequency acoustic wave signal in the resonant region 121. In the air gap acoustic wave resonator 100a, the resonant region 121 is provided corresponding to the cavity 111 of the substrate layer 110, and the resonant region 121 and the bottom surface of the cavity 111 are spaced apart in the thickness direction (Z direction) of the substrate layer 110. The non-resonant region 122 is the region of the piezoelectric layer 120 excluding the resonant region 121. The non-resonant region 122 is provided corresponding to the region of the substrate layer 110 excluding the cavity 111.

[0134] The electrode layer 130 is used to convert electrical signals into acoustic signals, and also to convert acoustic signals into electrical signals. The electrode layer 130 has a predetermined shape, and the piezoelectric layer 120 and the electrode layer 130 are combined in a predetermined manner to form various types of acoustic resonators, such as film bulk acoustic resonators (FBARs), Lamb wave resonators / laterally excited bulk acoustic resonators (XBARs), and other specific embodiments. Specific embodiments are described below.

[0135] The bonded piezoelectric layer 120 can be a single crystal structure, which has better orientation and performance. A pre-buried groove 150 is formed on the bonded piezoelectric layer 120 and substrate layer 110 by etching or other methods. The pre-buried groove 150 connects the piezoelectric layer 120 and substrate layer 110 along the thickness direction (Z direction) of the substrate layer 110. That is, the pre-buried groove 150 passes through the piezoelectric layer 120 and extends into the substrate layer 110, thereby forming an opening 151 in the piezoelectric layer 120.

[0136] The material of the release barrier layer 140 is a polymer. The liquid polymer is easily filled in the embedded groove 150 of the chip 100, and the polymer is solidified and the filled side is flattened to form a release barrier layer 140 in the embedded groove 150. The polymer can be solidified within a wide temperature range, has low residual stress and good adhesion, will not produce cracks after reliability testing, and has stable physical and chemical properties. In the process of forming the cavity 111, the release fluid reacts with the substrate layer 110, and the release barrier layer 140 limits the diffusion of the release fluid to the periphery of the cavity 111 (i.e., the non-resonant zone 122), thereby limiting the lateral size of the cavity 111. The lateral size of the cavity 111 refers to the dimension in any direction on the plane perpendicular to the thickness direction of the substrate layer 110 (such as the dimension in the X direction and the Y direction).

[0137] In the chip 100 provided in the embodiment of the present application, as shown in FIG7(a), the substrate layer 110 and the piezoelectric layer 120 are laminated and bonded by the wafer fab. As shown in FIG7(b) and (c), after the integrated circuit fabrication plant receives the wafer with the piezoelectric layer 120 and substrate layer 110 bonded, the embedded groove 150 is processed. As shown in FIG7(d) and (e), the release barrier layer 140 and the electrode layer 130 are fabricated. As shown in FIG7(f) to (h), the cavity 111 of the substrate layer 110 is fabricated. This eliminates the need to shuttle the wafer back and forth between the integrated circuit fabrication plant and the wafer fab, as in the related art, thus reducing wafer damage. If the size or position of the electrode layer 130 needs to be changed, the position of the embedded groove 150 for the release barrier layer 140 can be directly changed on the wafer, eliminating the need to spend more than six weeks re-customizing the piezoelectric layer 120 at the wafer fab, as in the related art. As shown in (c) and (d) of Figure 7, the material of the release barrier layer 140 is a polymer. The liquid polymer is easy to fill in the embedded groove 150 of the chip 100, the process is simple, and the filling effect is good. After the polymer is cured, the hardness is small. When the filling side is flattened, the stress and strain of the substrate layer 110 are small, and the damage to the substrate layer 110 is very small. There is no need to pre-customize a large thickness substrate and grind and thin the bottom side of the substrate after filling the embedded groove as in the related art. During the front-end processing, the polymer can release the mechanical stress of the electrode layer 130 above the cavity 111, reducing the processing difficulty. As shown in (f) and (g) of Figure 7, by reacting the released fluid with the substrate layer 110, a cavity 111 is formed in the substrate layer 110, so that the resonance zone 121 of the piezoelectric layer 120 provided on the substrate layer 110 and the bottom surface of the cavity 111 are spaced apart in the thickness direction (Z direction) of the substrate layer 110. Release barrier layer 140 and the release fluid barely react. By limiting the lateral dimensions of cavity 111, release barrier layer 140 allows for smaller lateral dimensions, enabling more acoustic wave resonators 100a to be arranged on the wafer, improving the device's mechanical strength and power tolerance. The substrate layer 110, piezoelectric layer 120, electrode layer 130, and release barrier layer 140 in chip 100 combine to form an air-gap acoustic wave resonator 100a. This chip 100 is easy to manufacture, low-cost, and has a high yield.

[0138] The release fluid may be a release gas flow or solution that can react with the substrate layer 110 and substantially does not react with the polymer, such as xenon difluoride (XeF 2 ) gas, hydrofluoric acid (HF) solution and its buffer solution.

[0139] To allow the release fluid to react with a predetermined area of ​​the substrate layer 110 to form a cavity 111 in the substrate layer 110, in some embodiments, referring to Figures 5 and 6 , a plurality of release holes 160 are provided in the resonance region 121. The plurality of release holes 160 communicate with the cavity 111. After the release holes 160 are formed, the release fluid is allowed to pass through the release holes 160 and react with the substrate layer 110, thereby forming a depression in the substrate layer 110. The release holes 160 can be provided along the edge of the resonance region 121.

[0140] In some embodiments, referring to FIG5 , the resonance region 121 is generally rectangular, and multiple release holes 160 are arranged in a generally rectangular pattern. A release fluid capable of reacting with the substrate layer 110 is introduced into all release holes 160, forming a cavity 111 on the substrate layer 110 that is generally rectangular in shape with rounded corners when viewed from above. Referring to FIG6 , the release fluid reacts isotropically with the substrate layer 110 through the release holes 160, forming spherical cavities centered on each release hole 160 within the substrate layer 110. These cavities together constitute the cavity 111. A non-reactive raised area may appear in the middle of the bottom surface of the cavity 111, ensuring that the resonance region 121 of the piezoelectric layer 120 and the bottom surface of the cavity 111 are spaced apart in the thickness direction (Z direction) of the substrate layer 110.

[0141] In order to connect the electrode layers 130 of multiple acoustic wave resonators 100a in the filter in series and parallel, in some embodiments, referring to Figures 5 and 6, a conductive portion 130a is provided on the piezoelectric layer 120, and the conductive portion 130a and the electrode layer 130 are connected and conductive, so that the electrode layers 130 of the multiple acoustic wave resonators 100a are cascaded together in series and parallel to form a filter circuit.

[0142] There are multiple optional arrangements for arranging the piezoelectric layer 120 and the electrode layer 130 , and three arrangements are given below as examples.

[0143] The first arrangement of the piezoelectric layer 120 and the electrode layer 130 forms a lateral excited bulk acoustic wave resonator 100a. Referring to Figures 5 and 6 , the electrode layer 130 includes an interdigital transducer (IDT) 131, which is located on the side of the resonant region 121 facing away from the substrate layer 110. IDT 131 is located on one side of the piezoelectric layer 120, with the resonant region 121 of the piezoelectric layer 120 positioned above the cavity 111, forming an air-gap lateral excited bulk acoustic wave resonator 100a.

[0144] Figures 5 and 6 schematically illustrate the structure of the interdigital transducer 131. The number of electrode fingers can be large and the width can be very small. The interdigital transducer 131 can include a first bus bar 1311, a second bus bar 1312, a plurality of first electrode fingers 1313, and a plurality of second electrode fingers 1314. The first bus bar 1311 and the second bus bar 1312 are arranged in parallel and spaced apart. The plurality of first electrode fingers 1313 are spaced in parallel and connected to the same side of the first bus bar 1311. The plurality of second electrode fingers 1314 are spaced in parallel and connected to the same side of the second bus bar 1312. The plurality of first electrode fingers 1313 and the plurality of second electrode fingers 1314 are located between the first bus bar 1311 and the second bus bar 1312, and the plurality of first electrode fingers 1313 and the plurality of second electrode fingers 1314 are arranged alternately and spaced apart in sequence. The first bus bar 1311 and the second bus bar 1312 may be conductively connected to different conductive portions 130 a on the chip 100 to implement transmission of electrical signals.

[0145] During operation, a high-frequency electrical signal is applied between the first bus bar 1311 and the second bus bar 1312 to excite Lamb waves in the resonance region 121 of the piezoelectric layer 120. When the piezoelectric layer 120 and the substrate layer 110 are bonded, the interdigital transducer 131 is fabricated on the side of the piezoelectric layer 120 away from the substrate layer 110 for easier molding.

[0146] Exemplarily, the resonance region 121 of the piezoelectric layer 120 may be roughly rectangular, the first bus bar 1311 and the second bus bar 1312 may extend along the length direction (Y direction) of the resonance region 121, and the plurality of first electrode fingers 1313 and the plurality of second electrode fingers 1314 may extend along the width direction (X direction) of the resonance region 121, so that a large number of first electrode fingers 1313 and second electrode fingers 1314 may be alternately arranged on the resonance region 121.

[0147] The second arrangement of the piezoelectric layer 120 and the electrode layer 130 forms a transversely excited bulk acoustic wave resonator 100a. Referring to FIG8 , the electrode layer 130 includes an interdigital transducer 131, which is located on the side of the resonance region 121 facing the substrate layer 110. IDT 131 is located on a single side of the piezoelectric layer 120, and the resonance region 121 of the piezoelectric layer 120 is located above the cavity 111, forming an air-gap transversely excited bulk acoustic wave resonator 100a.

[0148] The specific structure and connection method of the IDT 131 can be referred to the first arrangement of the piezoelectric layer 120 and the electrode layer 130 and will not be described in detail. During operation, a high-frequency electrical signal is applied between the first bus bar 1311 and the second bus bar 1312 to excite Lamb waves in the resonant region 121 of the piezoelectric layer 120.

[0149] The third arrangement of the piezoelectric layer 120 and the electrode layer 130 is a thin film bulk acoustic resonator 100a: referring to FIG9 , the electrode layer 130 includes a first electrode plate 132 and a second electrode plate 133, the first electrode plate 132 being arranged on the side of the resonance region 121 facing away from the substrate layer 110, and the second electrode plate 133 being arranged on the side of the resonance region 121 facing the substrate layer 110.

[0150] The resonant region 121 of the piezoelectric layer 120 is located above the cavity 111. A first electrode plate 132 is disposed on one side of the resonant region 121 in the thickness direction (Z direction), and a second electrode plate 133 is disposed on the other side. The first electrode plate 132 is disposed outward, while the second electrode plate 133 is disposed toward the cavity 111, thereby forming an air-gap thin film bulk acoustic resonator 100a. During operation, a high-frequency electrical signal is applied between the first electrode plate 132 and the second electrode plate 133, which can excite bulk acoustic waves in the resonant region 121 of the piezoelectric layer 120, oscillating and propagating between the first electrode plate 132 and the second electrode plate 133. The outside of the first electrode plate 132 and the outside of the second electrode plate 133 are both air, and the acoustic impedance of air is much lower than that of the piezoelectric layer 120, causing most of the acoustic waves to be reflected.

[0151] When configuring the piezoelectric layer 120, referring to Figures 6, 8, and 9, the material of the piezoelectric layer 120 includes one or more of lithium niobate (LiNbO3), lithium tantalate (LiTaO3), aluminum nitride (AlN), zinc oxide (ZnO), and quartz in various tangential directions. Since the tangential direction of the single crystal structure of the piezoelectric layer 120 is related to a specific acoustic mode, the tangential direction of the material can be set as needed, such as in the X-tangent direction, the Y-tangent direction, the Z-tangent direction, the rotated Y-tangent direction, or the rotated Z-tangent direction.

[0152] When providing the electrode layer 130 and the conductive portion 130a, referring to Figures 6, 8, and 9, the material of the electrode layer 130 and the conductive portion 130a includes one or more of aluminum (Al), copper (Cu), platinum (Pt), molybdenum (Mo), tungsten (W), tantalum (Ta), gold (Au), and silver (Ag). The electrode layer 130 and the conductive portion 130a can be fabricated using a physical vapor deposition (PVD) process, such as vacuum evaporation or sputtering.

[0153] There are multiple optional implementations for setting the substrate layer 110 , and three implementations are exemplified below.

[0154] The first implementation method of the substrate layer 110: Referring to Figure 6, the substrate layer 110 includes a stacked substrate 112 and a dielectric layer 113, the dielectric layer 113 is located between the substrate 112 and the piezoelectric layer 120, the piezoelectric layer 120 and the dielectric layer 113 are stacked and bonded, the embedded groove 150 connects the piezoelectric layer 120, the dielectric layer 113 and the substrate 112 along the thickness direction (Z direction) of the substrate layer 110, and the cavity 111 is formed on the substrate 112.

[0155] A dielectric layer 113 is disposed on substrate 112, providing a superior connection when piezoelectric layer 120 and dielectric layer 113 are stacked and bonded. A pre-buried groove 150 connects piezoelectric layer 120, dielectric layer 113, and substrate 112, and a release barrier layer 140 is disposed within pre-buried groove 150. A release fluid reacts with substrate 112 to form a cavity 111 on substrate 112. The release barrier layer 140, which is substantially non-reactive with the release fluid, defines the lateral dimensions of cavity 111, ensuring that the resonant region 121 of piezoelectric layer 120 and the bottom surface of cavity 111 are spaced apart in the thickness direction of substrate layer 110.

[0156] The second implementation method of the substrate layer 110: Referring to Figure 10, the substrate layer 110 includes a stacked substrate 112 and a dielectric layer 113, the dielectric layer 113 is located between the substrate 112 and the piezoelectric layer 120, the piezoelectric layer 120 and the dielectric layer 113 are stacked and bonded, the embedded groove 150 connects the piezoelectric layer 120 and the dielectric layer 113 along the thickness direction (Z direction) of the substrate layer 110, and the cavity 111 is formed on the dielectric layer 113.

[0157] A dielectric layer 113 is disposed on substrate 112, providing a superior connection when piezoelectric layer 120 and dielectric layer 113 are stacked and bonded. A pre-buried groove 150 connects piezoelectric layer 120 and dielectric layer 113, and a release barrier layer 140 is disposed within pre-buried groove 150. A release fluid reacts with dielectric layer 113 to form a cavity 111 in dielectric layer 113. The release barrier layer 140, which is substantially non-reactive with the release fluid, defines the lateral dimensions of cavity 111, ensuring that the resonant region 121 of piezoelectric layer 120 and the bottom surface of cavity 111 are spaced apart in the thickness direction of substrate layer 110.

[0158] The third implementation method of the substrate layer 110: Referring to Figure 11, the substrate layer 110 includes a substrate 112, the piezoelectric layer 120 and the substrate 112 are stacked and bonded, the embedded groove 150 is connected to the substrate 112 along the thickness direction (Z direction) of the substrate layer 110, and the cavity 111 is formed on the substrate 112.

[0159] A pre-buried groove 150 is formed on the substrate 112, and a release barrier layer 140 is provided on the pre-buried groove 150. The release fluid reacts with the substrate 112 to form a cavity 111 on the substrate 112, and the lateral dimensions of the cavity 111 are limited by the release barrier layer 140, which is substantially non-reactive with the release fluid. This allows the resonant region 121 of the piezoelectric layer 120 and the bottom surface of the cavity 111 to be spaced apart in the thickness direction of the base material layer 110.

[0160] When providing substrate 112, referring to Figures 6, 8, and 11, the material of substrate 112 includes one or more of silicon (Si), silicon carbide (SiC), diamond, sapphire, aluminum nitride (AlN), ceramics, lithium tantalate (LiTaO3), and lithium niobate (LiNbO3). The specific material of substrate 112 is selected as needed.

[0161] When the dielectric layer 113 is provided, referring to FIG. 6, FIG. 8 to FIG. 11, the material of the dielectric layer 113 includes silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y By providing the dielectric layer 113 on the substrate 112, the piezoelectric layer 120 and the dielectric layer 113 can achieve a good connection effect when they are stacked and bonded.

[0162] When determining the shape of the embedded groove 150 and the release barrier layer 140, referring to FIG5 , the embedded groove 150 and the release barrier layer 140 have the same cross-sectional shape in a top view. The cross-sectional shapes of the embedded groove 150 and the release barrier layer 140 can be arranged in a circular, elliptical, or polygonal shape. The polygon can be a triangular, quadrilateral, or multi-sided shape. The shape of the release barrier layer 140 can be determined based on the arrangement of the electrode layer 130, and the shape of the cavity 111 is defined by the release barrier layer 140.

[0163] For example, referring to FIG5 , the electrode layer 130 is arranged in a substantially rectangular shape, the release barrier layer 140 is arranged in a substantially rectangular ring shape, and the cross section of the cavity 111 defined by the release barrier layer 140 in a top view is substantially rectangular.

[0164] There are multiple optional implementations for setting the shapes of the embedded groove 150 and the release barrier layer 140 , and two implementations are exemplified below.

[0165] The first implementation method of the embedded groove 150 and the release barrier layer 140: Referring to Figures 5 and 6, the embedded groove 150 includes a plurality of sub-grooves 152 distributed around the resonance zone 121 and connected end to end in sequence; the release barrier layer 140 includes a plurality of transverse blocking portions 141, and the plurality of transverse blocking portions 141 are filled in the plurality of sub-grooves 152 in a one-to-one correspondence.

[0166] The embedded groove 150 is configured to be annular and interconnected, i.e., multiple sub-grooves 152 are sequentially connected end to end, as shown in FIG7(d). A liquid polymer is then filled into the multiple sub-grooves 152, for example, by spin coating the liquid polymer onto one side of the embedded groove 150 on the substrate layer 110. The polymer is then solidified and the filled side is flattened, thereby forming a transverse barrier 141 in each sub-groove 152. Multiple transverse barriers 141 are connected to form an annular release barrier layer 140. As shown in FIG7(g) and (h), when a release fluid reacts with the substrate layer 110, the release fluid does not react with the transverse barriers 141, effectively limiting the lateral size of the cavity 111 within the substrate layer 110.

[0167] The second implementation method of the embedded groove 150 and the release barrier layer 140: Referring to Figure 12, the embedded groove 150 includes a plurality of sub-grooves 152 distributed around the resonance zone 121 and arranged in sequence; the release barrier layer 140 includes a plurality of lateral blocking portions 141, and the plurality of lateral blocking portions 141 are filled in the plurality of sub-grooves 152 in a one-to-one correspondence.

[0168] The embedded groove 150 is configured as an annular, non-connected configuration, i.e., multiple sub-grooves 152 are spaced apart in sequence, and liquid polymer is filled into the multiple sub-grooves 152. For example, the liquid polymer is applied by spin coating on one side of the embedded groove 150 of the substrate layer 110, and then the polymer is solidified and the filled side is flattened, thereby forming a transverse barrier 141 in each sub-groove 152. The multiple transverse barriers 141 are spaced apart, non-connected, and roughly annular. When a release fluid is used to react with the substrate layer 110, each release fluid does not react with the transverse barrier 141, thereby limiting the transverse size of the cavity 111 within the substrate layer 110. By setting the sub-grooves 152 to the appropriate width and spacing, the transverse size of the cavity 111 can be limited, so that the wall surface of the cavity 111 substantially surrounds the resonant region 121 of the piezoelectric layer 120.

[0169] The plurality of transverse barriers 141 in the release barrier layer 140 may be arranged in a circular, elliptical, or polygonal shape. The polygonal shape may be a triangular, quadrilateral, or multi-sided shape.

[0170] 12 , the electrode layer 130 is arranged in a generally rectangular shape, the plurality of transverse blocking portions 141 in the release barrier layer 140 are arranged in a generally rectangular ring shape, and the cross section of the cavity 111 defined by the release barrier layer 140 in a top view is generally rectangular.

[0171] Regarding the longitudinal depth of the embedded groove 150 or the release barrier layer 140, referring to FIG6 , the longitudinal depth of the embedded groove 150 or the release barrier layer 140 ranges from 1 micron (μm) to 50 μm. The longitudinal depth of the embedded groove 150 or the release barrier layer 140 is the dimension in the thickness direction (Z direction) of the substrate layer 110. With the embedded groove 150 within this range, after the liquid polymer flows into the embedded groove 150 and solidifies, the release fluid reacts with the substrate layer 110, forming a cavity 111 in the substrate layer 110. This allows the resonant region 121 of the piezoelectric layer 120 to be spaced apart from the bottom surface of the cavity 111.

[0172] To facilitate the flow of liquid polymer into the embedded groove 150, in some embodiments, referring to Figures 5 and 6, the width L1 of the release barrier layer 140 in a top view is greater than or equal to 10 microns. A top view is a view looking down from above toward the chip 100 and its cross-section along the top-view direction (Z direction). The width L1 of the release barrier layer 140 in a top view is the width of the embedded groove 150 in a top view, i.e., the short side dimension of a single transverse barrier portion 141 in the release barrier layer 140 in a top-view cross-section, and also the short side dimension of a single sub-groove 152 in the embedded groove 150 in a top-view cross-section.

[0173] By limiting the minimum short side dimension of a single transverse barrier portion 141 in the release barrier layer 140 (or a single sub-groove 152 in the embedded groove 150) in a top-view cross-section, the liquid polymer can easily flow into and fully fill the embedded groove 150. The liquid polymer is cured to form the release barrier layer 140.

[0174] 5 , the plurality of transverse blocking portions 141 in the release barrier layer 140 are arranged in a generally rectangular ring shape, and the width L1 of the release barrier layer 140 in a top view is the short side dimension of a single transverse blocking portion 141 in a cross section in the top view direction.

[0175] When selecting a polymer for the release barrier layer 140, the polymer may include one or more of polyimide (PI), polydimethylsiloxane (PDMS), polyvinylidene fluoride (PVDF), benzocyclobutene (BCB), polyethylene glycol terephthalate (PET), and photoresist (Pr). The photoresist may be polymethyl methacrylate (PMMA), etc. There are many materials for photoresist, the main component of which is photosensitive rubber, which is a high molecular polymer. The polymer used is a material that is basically non-reactive with the release fluid, and the liquid polymer can be easily filled into the embedded groove 150.

[0176] When forming the release barrier layer 140, referring to FIG7(d), the release barrier layer 140 can be formed by spin-coating a polymer to fill the embedded trench 150, curing the polymer, and planarizing the polymer-filled side. The polymer-filled side refers to the side of the wafer filled with polymer during the manufacturing process.

[0177] After the embedded groove 150 is formed, liquid polymer is applied to the center of the side of the wafer where the embedded groove 150 is located. The wafer is rotated to evenly distribute the liquid polymer across the wafer, ensuring that the embedded groove 150 at each acoustic wave resonator 100a is filled with liquid polymer. The polymer is then heated to solidify, effectively adhering to one side of the piezoelectric layer 120. The polymer-filled side is then flattened, and any excess polymer covering the piezoelectric layer 120 is removed. This ensures that the release barrier layer 140 is securely attached to the embedded groove 150, paving the way for the reaction between the release fluid and the substrate layer 110.

[0178] When setting the polymer, the Young's modulus of the polymer after solidification is less than 10 gigapascals (GPa). Compared with the related art that uses metal or dielectric materials with a Young's modulus greater than 70 GPa to fill the embedded groove, this embodiment solidifies the liquid polymer to form a release barrier layer 140. The Young's modulus of the polymer after solidification is small and the hardness is low. When flattening one side of the filled polymer, the stress of the substrate layer 110 caused by the processing force transmitted to the substrate layer 110 is small, and the damage to the substrate layer 110 is very small. There is no need to pre-customize a large thickness substrate and fill the embedded groove and then grind and thin the bottom side of the substrate as in the related art. During the front-end and back-end processing, the polymer can release the mechanical stress of the electrode layer 130 above the cavity 111, reducing the difficulty of processing. This makes the preparation difficulty of the chip 100 low, the cost low, and the yield high.

[0179] For example, the Young's modulus of the polymer after curing is less than 5 GPa. The smaller the Young's modulus of the polymer after curing, the lower the hardness, and the less damage to the substrate layer 110 when planarizing one side of the filled polymer.

[0180] To ensure that the liquid polymer is tightly packed within the embedded groove 150 and that the polymer can deform under heat after solidification, in some embodiments, referring to Figures 13 and 14 , the chip 100 has one or more microgrooves 170 connecting the piezoelectric layer 120 and the substrate layer 110 along the thickness direction (Z direction) of the substrate layer 110. The one or more microgrooves 170 are connected to the embedded groove 150. The microgrooves 170 may form openings 171 in the piezoelectric layer 120. Figures 13 and 14 schematically illustrate the shape of the microgrooves 170; in practice, the size of the microgrooves 170 is relatively small.

[0181] When making chip 100, as shown in (a) to (c) among Figure 15, first make embedded groove 150 and micro groove 170 on base material layer 110, as shown in (d) among Figure 15, then fill liquid polymer and solidify and planarize, as shown in (g) and (h) among Figure 15, finally form concave cavity 111.Referring to Figure 13, Figure 14, the opening 171 size of micro groove 170 is much smaller than the opening 151 size of embedded groove 150, and the communicating port 172 size of micro groove 170 and embedded groove 150 is also very small.As shown in (d) among Figure 15, when embedded groove 150 and micro groove 170 are filled with liquid polymer, liquid polymer has certain viscosity and surface tension, and liquid polymer can enter embedded groove 150, but is difficult to enter in micro groove 170, and micro groove 170 inside may be empty. When the polymer is heated and cured, bubbles form within the liquid polymer at the embedded groove 150. These bubbles can overflow from the adjacent unfilled microgrooves 170, allowing the polymer to more fully and tightly fill the embedded groove 150. As shown in (g) and (h) of Figure 15 , this facilitates the formation of a strong release barrier layer 140 by the cured polymer. The release barrier layer 140 effectively blocks the released fluid, thereby forming a cavity 111 of predetermined transverse dimensions in the substrate layer 110. After the polymer cures to form the release barrier layer 140, the microgrooves 170 provide sufficient deformation space for the thermally expanded release barrier layer 140, reducing the risk of the release barrier layer 140 being squeezed and ruptured, thereby enhancing device reliability.

[0182] The embedded groove 150 may include a plurality of sub-grooves 152. Each sub-groove 152 may correspond to one or more micro-grooves 170, the specific number of which is related to the size of the sub-groove 152. The longer the sub-groove 152 is in a top view, the more micro-grooves 170 are connected to the sub-groove 152.

[0183] In some embodiments, referring to Figures 13 and 14 , a plurality of microgrooves 170 are spaced apart along the edge of the resonance region 121. The plurality of microgrooves 170 are connected to the embedded grooves 150 so that the liquid polymer is filled in the embedded grooves 150 rather than in the plurality of microgrooves 170. This facilitates venting of the polymer through the microgrooves 170 during heating and curing, facilitating the formation of a reliable release barrier layer 140 during polymer curing. The microgrooves 170 also provide deformation space for the release barrier layer 140, which expands due to heat.

[0184] In the embodiment shown in FIG13 , the embedded groove 150 includes a plurality of sub-grooves 152 distributed around the resonance region 121 and sequentially connected end to end, and each sub-groove 152 can be connected to the microgroove 170. In the embodiment shown in FIG12 , the embedded groove 150 includes a plurality of sub-grooves 152 distributed around the resonance region 121 and sequentially spaced apart, and each sub-groove 152 can also be connected to the microgroove 170.

[0185] When the shape of microflute 170 is set, consult Figure 16, the cross-sectional shape of microflute 170 on the top view can be circle, ellipse, polygon or X-shaped.Polygon can be the shape of triangle, quadrilateral or more edges.When adopting the microflute 170 of polygonal cross section, the polygonal cross section of microflute 170 on one side or a part is connected with embedded groove 150, makes liquid polymer be difficult to enter by the opening 171 of microflute 170, also is difficult to enter in the microflute 170 by embedded groove 150.Show the shape of microflute 170 among Figure 16, the size ratio of actual microflute 170 is little.

[0186] Exemplary, as shown in (a) among Figure 16, the cross-sectional shape of microgrooves 170 on top view is circular, and a part of the circular cross section of microgrooves 170 is communicated with the long side of the subgrooves 152 in the embedded groove 150. A plurality of microgrooves 170 are arranged at intervals along the long side direction of the subgrooves 152 in the embedded groove 150. Make liquid polymer difficult to enter the microgrooves 170, the internal bubble of the liquid polymer in the embedded groove 150 is released from nearby microgrooves 170 when heat-curing, and the liquid polymer is filled and compacted in the embedded groove 150. Microgrooves 170 also provide deformation space for the release barrier layer 140 that is expanded by heat.

[0187] Exemplary, as shown in (b) among Figure 16, the cross-sectional shape of microgrooves 170 on the top view is a triangle, and one side of microgrooves 170 triangular cross sections is communicated with the long side of the subgrooves 152 in the embedded groove 150. A plurality of microgrooves 170 are arranged at intervals along the long side direction of the subgrooves 152 in the embedded groove 150. In addition, one end of microgrooves 170 triangular cross sections also can be communicated with the long side of the subgrooves 152.

[0188] For example, as shown in (c) of FIG16 , the cross-sectional shape of the microgroove 170 in a top view is rectangular, and a short side of the rectangular cross-sectional shape of the microgroove 170 is connected to the long side of the subgroove 152 in the embedded groove 150. The plurality of microgrooves 170 are arranged at intervals along the long side direction of the subgroove 152 in the embedded groove 150.

[0189] For example, as shown in (d) of FIG16 , the cross-sectional shape of the microgroove 170 in a top view is X-shaped, and one end of the X-shaped cross-sectional shape of the microgroove 170 is connected to the long side of the subgroove 152 in the embedded groove 150. The plurality of microgrooves 170 are arranged at intervals along the long side direction of the subgroove 152 in the embedded groove 150.

[0190] In order to make it difficult for the liquid polymer to flow into the embedded groove 150 through the opening 171, in some embodiments, referring to FIG16 , the view shown in FIG16 is a top view of the embedded groove 150 and the micro groove 170, and the length L2 of the micro groove 170 in the top view is less than or equal to 10 microns (um). Alternatively, the cross-sectional area of ​​the micro groove 170 in the top view is less than or equal to 100 square microns (um). 2 The top view is a view of the chip 100 and its cross section from top to bottom along the top-view direction (Z direction). The length L2 of the microgroove 170 in the top view is the long side dimension of the cross section of the microgroove 170 in the top view direction.

[0191] By limiting the maximum length of the long side of the cross section of the microgroove 170 in the top view direction, or limiting the maximum cross-sectional area of ​​the microgroove 170 in the top view direction, it is difficult for liquid polymer to enter the microgroove 170 through the opening 171 .

[0192] For example, as shown in FIG. 16( a ), the cross-sectional shape of the microgroove 170 in a top view is a circle, and the length L2 of the microgroove 170 in a top view is the diameter of the circular cross-sectional shape.

[0193] For example, as shown in FIG16( b ), the cross-sectional shape of the microgroove 170 in the top view is a triangle, and the length L2 of the microgroove 170 in the top view is the maximum side length of the triangle.

[0194] For example, as shown in FIG. 16( c ), the cross-sectional shape of the microgroove 170 in the top view is a rectangle, and the length L2 of the microgroove 170 in the top view is the length of the long side of the rectangular cross-section.

[0195] For example, as shown in FIG. 16( d ), the cross-sectional shape of the microgroove 170 in a top view is X-shaped, and the length L2 of the microgroove 170 in a top view is the arm length of the X-shaped cross-section.

[0196] In order to make it difficult for the liquid polymer to enter the microgroove 170 from the embedded groove 150, in some embodiments, referring to FIG. 14 , a communication port 172 is formed between the microgroove 170 and the embedded groove 150, and the length L3 of the communication port 172 is less than or equal to 10 microns (μm); or, a communication port 172 is formed between the microgroove 170 and the embedded groove 150, and the cross-sectional area of ​​the communication port 172 is less than or equal to 100 square μm (μm). 2 The communication port 172 has a rectangular cross section, and the length L3 of the communication port 172 is the long side dimension of the communication port 172 in the rectangular cross section.

[0197] By limiting the maximum length of the long side of the surface where the communication opening 172 is located, or limiting the maximum cross-sectional area of ​​the communication opening 172 , it is difficult for liquid polymer to enter the microgroove 170 from the embedded groove 150 through the communication opening 172 .

[0198] In some embodiments, referring to Figures 6, 8 to 11, and 14, the substrate layer 110, the piezoelectric layer 120, the electrode layer 130, and the release barrier layer 140 can be combined to form an air gap acoustic wave resonator 100a, and multiple acoustic wave resonators 100a are cascaded to form a filter. The filter can be a low-pass filter, a high-pass filter, a band-pass filter, a band-stop filter, or an active filter. The filter can be a separate component, or the filter can be integrated with a power amplifier or other components into a module (e.g., a radio frequency device, a radio frequency module, a filter module, etc.), and the filter is coupled to the power amplifier for signal processing and transmission.

[0199] Referring to Figure 17, a ladder acoustic filter is a commonly used topology in current acoustic filters. The filter comprises multiple cascaded resonators 100a, each of which can have different resonant frequencies and are connected in series and parallel. The filter has a signal input terminal Vi, a signal output terminal Vo, and a ground terminal GND. The acoustic filter formed by cascading series and parallel resonators 100a with different resonant frequencies has advantages such as low passband insertion loss, high out-of-band steepness, and strong power tolerance.

[0200] The above-mentioned filter can be an acoustic filter for the fifth generation mobile communication technology (5G) frequency band, and can also be used as an acoustic filter for other frequency bands.

[0201] When confirming the chip 100 of the embodiment of the present application, referring to Figures 6, 8 to 11, and 14, the chip 100 can be dissected and sliced, and a focused ion beam (FIB) microscope or a transmission electron microscope (TEM) can be used to observe the stacking structure and thickness of each layer of the chip 100; elemental analysis can be performed on the stacking of the chip 100 to identify the materials of each layer of the chip 100 and determine whether the material of the release barrier layer 140 is a polymer; in the case where the chip 100 has microgrooves 170, the edge position of the release barrier layer 140 can be observed in a top view direction to determine whether there are microgrooves 170.

[0202] 18 , an embodiment of the present application provides an electronic device 1000 , including a printed circuit board 200 and the aforementioned chip 100 , wherein the chip 100 is disposed on the printed circuit board 200 .

[0203] The electronic device 1000 may be a consumer electronic product, a home electronic product, an in-vehicle electronic product, a financial terminal product, a communication electronic product, and the like. Among them, consumer electronic products may be mobile phones, tablet computers, laptop computers, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop displays, smart wearable products (e.g., smart watches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, and the like. Home electronic products may be smart door locks, televisions, remote controls, refrigerators, rechargeable small household appliances (e.g., soybean milk makers, robot vacuums), and the like. In-vehicle electronic products may be in-vehicle navigation systems, in-vehicle high-density digital video discs (DVDs), and the like. Financial terminal products may be automated teller machines (ATMs), self-service terminals, and the like. Communication electronic products may be communication equipment such as servers, storage devices, radars, and base stations.

[0204] For the purpose of illustration, the electronic device 1000 is a mobile phone. The electronic device 1000 includes a cover plate 300, a display screen 400, a middle frame 500, and a rear housing 600. The rear housing 600 and the display screen 400 are located on opposite sides of the middle frame 500. The middle frame 500 and the display screen 400 can be disposed within the rear housing 600. The cover plate 300 is disposed on a side of the display screen 400 that is away from the middle frame 500, with the display side of the display screen 400 facing the cover plate 300.

[0205] There are multiple options for implementing the display screen 400. For example, the display screen 400 can be a liquid crystal display (LCD), which includes a liquid crystal display panel and a backlight module. The LCD panel is disposed between the cover plate 300 and the backlight module, and the backlight module is used to provide light for the LCD panel. Alternatively, the display screen 400 can be an organic light emitting diode (OLED) display screen. OLED displays are self-luminous and do not require a backlight module.

[0206] When the middle frame 500 is provided, the middle frame 500 may include a carrier plate 510 and a frame 520 provided around the carrier plate 510. The electronic device 1000 may also include a printed circuit board (PCB) 200, a battery, a camera, and other electronic components, which may be provided on the carrier plate 510.

[0207] The electronic device 1000 may also include a system-on-chip (SOC), a radio frequency chip, etc., disposed on a printed circuit board 200. The printed circuit board 200 is used to carry the system-on-chip, the radio frequency chip, etc. and is electrically connected to the system-on-chip, the radio frequency chip, etc. Among them, the radio frequency chip may include components such as a filter and a processor. The processor is used to process various signals. The filter is an important part of radio frequency signal processing, which is used to allow signals of a predetermined frequency to pass through and block signals of other predetermined frequencies.

[0208] 7 and 19 , an embodiment of the present application provides a method for preparing a chip 100 , including:

[0209] Step 710: As shown in FIG7 (a), a wafer is formed by laminating and bonding the piezoelectric layer 120 and the substrate layer 110;

[0210] Step 720: As shown in (b) and (c) of FIG7 , a pre-buried groove 150 is etched on the wafer. The pre-buried groove 150 connects the piezoelectric layer 120 and the substrate layer 110 along the thickness direction (Z direction) of the substrate layer 110. The pre-buried groove 150 is arranged around the resonance region 121 of the piezoelectric layer 120. The pre-buried groove 150 forms an opening 151 on the piezoelectric layer 120. When etching the pre-buried groove 150 on the wafer, a photoresist 180 or other material can be used as a mask for etching the pattern of the pre-buried groove 150.

[0211] Step 730: As shown in FIG7( d ), a polymer is spin-coated on the piezoelectric layer 120 so that the polymer fills the embedded groove 150 . During the spin-coating process, the liquid polymer enters the embedded groove 150 through the opening 151 of the embedded groove 150 , thereby forming a good filling.

[0212] Step 740: Curing the polymer and planarizing the filled side of the polymer so that the polymer in the embedded groove 150 forms a release barrier layer 140; the filled side of the polymer refers to the side of the wafer filled with polymer during the manufacturing process;

[0213] Step 750: As shown in FIG7( e ), an electrode layer 130 is formed on the resonance region 121 ;

[0214] Step 760: As shown in (f) and (g) of FIG. 7 , a release hole 160 is formed through the piezoelectric layer 120 . When forming the release hole 160 , a photoresist 180 or other material may be used as a mask for forming the pattern of the release hole 160 .

[0215] Step 770: As shown in (h) in Figure 7, the release fluid passes through the release hole 160 and reacts with the substrate layer 110 through etching to form a cavity 111 on the substrate layer 110, so that the resonance zone 121 and the bottom surface of the cavity 111 are spaced apart in the thickness direction (Z direction) of the substrate layer 110, and the lateral dimension of the cavity 111 is limited by the release barrier layer 140.

[0216] In the method for preparing the chip 100 provided in the embodiment of the present application, the wafer fab stacks and bonds the substrate layer 110 and the piezoelectric layer 120. After the integrated circuit processing plant receives the wafer with the piezoelectric layer 120 and the substrate layer 110 bonded, the wafer is processed with a pre-buried groove 150, the release barrier layer 140 and the electrode layer 130 are produced, and the cavity 111 of the substrate layer 110 is produced. When forming the release barrier layer 140, it is not restricted by the bonding of the piezoelectric layer 120 and the substrate layer 110. There is no need to transport the wafer back and forth between the integrated circuit processing plant and the wafer fab as in the related art to reduce wafer damage. If the size or position of the electrode layer 130 needs to be changed, the position of the pre-buried groove 150 for releasing the barrier layer 140 can be changed directly on the wafer, without having to spend more than 6 weeks to re-customize the piezoelectric layer 120 in the wafer fab as in the related art. The material of the release barrier layer 140 is a polymer. The liquid polymer is easy to fill in the embedded groove 150 of the chip 100. The process is simple and the filling effect is good. The hardness of the polymer is small after solidification. The stress and strain of the substrate layer 110 is small when the filling side is flattened, and the damage to the substrate layer 110 is very small. There is no need to pre-customize a large thickness substrate and grind and thin the bottom side of the substrate after filling the embedded groove as in the related art. During the front-end processing, the polymer can release the mechanical stress of the electrode layer 130 above the cavity 111, reducing the difficulty of processing. By releasing the fluid and reacting with the substrate layer 110, a cavity 111 is formed in the substrate layer 110, so that the resonance zone 121 of the piezoelectric layer 120 provided on the substrate layer 110 and the bottom surface of the cavity 111 are spaced apart in the thickness direction of the substrate layer 110. The release barrier layer 140 and the release fluid barely react. By limiting the lateral dimensions of the cavity 111, the release barrier layer 140 allows for a smaller lateral dimension, enabling more acoustic wave resonators 100a to be arranged on the wafer, thereby improving the device's mechanical strength and power tolerance. The fabrication process for the chip 100 with the release barrier layer 140 is optimized, resulting in a more streamlined process flow and improved process feasibility. The chip 100 is manufactured with minimal difficulty, low cost, and high yield.

[0217] In some embodiments, as shown in FIG. 7 (b) and (c), etching the pre-buried groove 150 on the wafer specifically includes: applying photoresist 180 on the surface of the piezoelectric layer 120; matching the pattern of the photoresist plate with the shape of the pre-buried groove 150, placing the wafer on a photolithography machine, aligning the wafer and the photoresist plate, and then performing exposure; removing the portion of the photoresist 180 corresponding to the pre-buried groove 150 through development, thereby transferring the pattern of the photoresist plate to the photoresist 180; using the photoresist 180 as a mask for etching the pattern of the pre-buried groove 150, and etching to transfer the pattern of the photoresist 180 to the wafer, thereby forming the pre-buried groove 150 on the wafer. The etching may be plasma reactive etching.

[0218] In order to ensure that the liquid polymer is tightly filled in the embedded groove 150 and that the polymer is allowed to deform under heat after solidification, in some embodiments, referring to FIG. 15 , the embedded groove 150 is etched on the wafer, specifically comprising: as shown in FIG. 15 (b) and (c), the embedded groove 150 and one or more microgrooves 170 are etched on the wafer, wherein the one or more microgrooves 170 connect the piezoelectric layer 120 and the substrate layer 110 along the thickness direction (Z direction) of the substrate layer 110, and the one or more microgrooves 170 are connected to the embedded groove 150. The microgrooves 170 may form openings 171 on the piezoelectric layer 120. A photoresist 180 or other material may be used as a mask for etching the embedded groove 150 pattern and the microgrooves 170 pattern, and the interconnected embedded grooves 150 and microgrooves 170 are etched on the wafer.

[0219] The opening 171 of the microgroove 170 is much smaller than the opening 151 of the pre-buried groove 150. The connecting opening 172 between the microgroove 170 and the pre-buried groove 150 is also very small. When the pre-buried groove 150 and microgroove 170 are filled with liquid polymer, the liquid polymer has a certain viscosity and surface tension. This allows the liquid polymer to enter the pre-buried groove 150 but has difficulty entering the microgroove 170, potentially leaving the interior of the microgroove 170 empty. During heat curing of the polymer, bubbles may form within the liquid polymer in the pre-buried groove 150. These bubbles can then overflow from the adjacent unfilled microgroove 170, allowing the polymer to more fully and tightly fill the pre-buried groove 150. After the polymer cures to form the release barrier layer 140, the microgroove 170 provides sufficient space for the thermally expanded release barrier layer 140 to deform, reducing the risk of the release barrier layer 140 being ruptured by heat and enhancing device reliability.

[0220] In the case of forming microgrooves 170, as shown in (b) and (c) of FIG. 15 , etching the pre-buried grooves 150 and microgrooves 170 on a wafer specifically includes: applying photoresist 180 to the surface of the piezoelectric layer 120; matching the pattern of the photoresist plate to the shapes of the pre-buried grooves 150 and microgrooves 170; placing the wafer on a photolithography machine, aligning the wafer and the photoresist plate, and then performing exposure; developing, removing portions of the photoresist 180 corresponding to the pre-buried grooves 150 and microgrooves 170, and transferring the pattern of the photoresist plate to the photoresist 180; using the photoresist 180 as a mask for etching the patterns of the pre-buried grooves 150 and microgrooves 170; and etching to transfer the pattern of the photoresist 180 to the wafer, thereby forming the pre-buried grooves 150 and microgrooves 170 on the wafer. The etching process may be plasma reactive etching.

[0221] There are multiple optional implementations for providing the embedded groove 150. For example, referring to FIG13 , one or more microgrooves 170 are provided on the side of the embedded groove 150 facing the resonance zone 121. Alternatively, one or more microgrooves 170 are provided on the side of the embedded groove 150 facing away from the resonance zone 121. Alternatively, one or more microgrooves 170 are provided on the side of the embedded groove 150 facing the resonance zone 121, and one or more microgrooves 170 are provided on the side of the embedded groove 150 facing away from the resonance zone 121. Microgrooves 170 can be provided on one or both sides of the embedded groove 150. When filling with liquid polymer, it is easy to enter the embedded groove 150, but difficult to enter the microgrooves 170, and the interior of the microgrooves 170 may be empty.

[0222] In the case where multiple microgrooves 170 are provided on the side of the pre-buried groove 150 facing the resonance region 121, as shown in FIG14 , since the release fluid will later react with the substrate layer 110, the microgrooves 170 on the side facing the resonance region 121 will communicate with the concave cavity 111 of the substrate layer 110. Consequently, the microgrooves 170 on the side facing the resonance region 121 will not be visible on the substrate layer 110 of the finished chip 100, while the microgrooves 170 and openings 171 on the side facing the resonance region 121 will be visible on the piezoelectric layer 120. In the case where multiple microgrooves 170 are provided on the side of the pre-buried groove 150 facing away from the resonance region 121, the microgrooves 170 on the side facing away from the resonance region 121 will be visible on both the substrate layer 110 and the piezoelectric layer 120 of the finished chip 100.

[0223] When setting the cross-sectional shape and dimensional characteristics of the embedded groove 150 , reference may be made to the description of the previous embodiment of the chip 100 , which will not be repeated here.

[0224] In some embodiments, referring to FIG. 20 and FIG. 21 , curing the polymer 140 a and planarizing the filled side of the polymer 140 a specifically includes: step 741 , as shown in (a) and (b) of FIG. 20 , pre-baking the wafer filled with the polymer 140 a ;

[0225] Step 742, as shown in (c) of FIG. 20, photolithography and development are performed to remove the polymer 140a outside the extension space 153 of the embedded groove 150;

[0226] Step 743, referring to (d) in FIG. 20 , performing dry stripping to remove the polymer 140a outside the embedded groove 150;

[0227] Step 744: planarizing the filling side of the polymer 140a;

[0228] Step 745 : Completely bake the wafer to solidify the polymer 140 a .

[0229] The extended space 153 of the embedded groove 150 refers to a space formed by the wall surface of the embedded groove 150 extending along the thickness direction (Z direction) of the base material layer 110 .

[0230] As shown in Figure 20 (a), liquid polymer 140a is spin-coated onto one side of the opening 151 of the embedded trench 150 on the wafer, ensuring that the liquid polymer 140a is well filled within the embedded trench 150. As shown in Figure 20 (b), a portion of liquid polymer 140a is present on the wafer surface. A pre-bake is performed to volatilize the solvent in the liquid polymer 140a to a certain extent, enhancing the adhesion between the liquid polymer 140a and the walls of the embedded trench 150. The pattern of the photomask is aligned with the shape of the embedded trench 150. The wafer is placed on a photolithography machine, aligned with the photomask, and then exposed. As shown in Figure 20 (c), the photolithography is then developed to remove the polymer 140a outside the extended space 153 of the embedded trench 150. Excess polymer 140a still remains above the embedded trench 150, as shown in Figure 20 (d). Dry stripping is used to remove the polymer 140a outside the embedded trench 150. The filled side of polymer 140a is flattened to form a flat surface on piezoelectric layer 120. Polymer 140a is present in pre-buried groove 150, preparing for the subsequent formation of electrode layer 130 on piezoelectric layer 120. Fully baking cures polymer 140a, enhancing its adhesion and corrosion resistance, and forming a reliable release barrier layer 140.

[0231] In some embodiments, referring to FIG. 22 and FIG. 23 , curing the polymer 140 a and planarizing the filled side of the polymer 140 a specifically includes: step 741 a , completely baking the wafer filled with the polymer 140 a to cure the polymer 140 a ; and step 742 a , planarizing the filled side of the polymer 140 a .

[0232] As shown in Figures 22 (a) and (b), liquid polymer 140a is spin-coated onto one side of the opening 151 of the embedded trench 150 on the wafer, ensuring that the liquid polymer 140a is well filled within the embedded trench 150, resulting in an excess of liquid polymer 140a on the wafer surface. As shown in Figure 22 (c), the polymer 140a is fully baked to solidify, enhancing its adhesion and corrosion resistance. A chemical mechanical polishing (CMP) process can be used for planarization to form a flat surface on the piezoelectric layer 120, paving the way for the subsequent formation of the electrode layer 130 on the piezoelectric layer 120. The polymer 140a remains within the embedded trench 150, forming a reliable release barrier 140.

[0233] In some embodiments, the filled side of the polymer 140a is planarized by one or more of photolithography, dry etching, and chemical mechanical polishing. This planarization of the filled side of the polymer 140a forms a flat surface on the piezoelectric layer 120, paving the way for subsequent formation of the electrode layer 130 on the piezoelectric layer 120.

[0234] In some embodiments, referring to (d) and (e) in FIG. 7 , an electrode layer 130 is fabricated on the resonant region 121 of the piezoelectric layer 120 , and a conductive portion 130 a is fabricated on the non-resonant region 122 of the piezoelectric layer 120 . The conductive portion 130 a and the electrode layer 130 are connected and conducted, so that the electrode layers 130 of the multiple acoustic wave resonators 100 a are cascaded together in series and parallel to form a filter circuit.

[0235] It should be noted that the above embodiments of the chip 100 are applicable to the method for preparing the chip 100 of the embodiments of the present application and will not be repeated here.

[0236] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A chip, characterized in that: include: a substrate layer, a piezoelectric layer, an electrode layer, and a release barrier layer; The piezoelectric layer and the substrate layer are stacked and bonded, and the piezoelectric layer has a resonance region; The chip has a pre-buried groove connecting the piezoelectric layer and the substrate layer along the thickness direction of the substrate layer, the pre-buried groove is arranged around the resonance area, and the pre-buried groove forms an opening on the piezoelectric layer; The electrode layer is disposed on the resonance region; The substrate layer has a concave cavity arranged opposite to the resonance zone, the resonance zone and the bottom surface of the concave cavity are spaced apart in the thickness direction of the substrate layer, and the embedded groove is connected to the concave cavity; The release barrier layer is made of a polymer and is disposed in the embedded groove to limit the transverse dimension of the cavity.

2. The chip according to claim 1, characterized in that: The electrode layer includes an interdigital transducer, and the interdigital transducer is arranged on a side of the resonance region facing away from the substrate layer; Or, the electrode layer includes an interdigital transducer, and the interdigital transducer is arranged on a side of the resonance region facing the substrate layer; Alternatively, the electrode layer includes a first electrode plate and a second electrode plate, the first electrode plate is disposed on a side of the resonance region facing away from the substrate layer, and the second electrode plate is disposed on a side of the resonance region facing the substrate layer.

3. The chip according to claim 1 or 2, characterized in that: The base material layer includes a substrate and a dielectric layer stacked together, the dielectric layer is located between the substrate and the piezoelectric layer, the piezoelectric layer and the dielectric layer are stacked and bonded, the embedded groove connects the piezoelectric layer, the dielectric layer and the substrate along the thickness direction of the base material layer, and the concave cavity is formed on the substrate; Or, the base material layer includes a substrate and a dielectric layer stacked together, the dielectric layer is located between the substrate and the piezoelectric layer, the piezoelectric layer and the dielectric layer are stacked and bonded, the embedded groove connects the piezoelectric layer and the dielectric layer along the thickness direction of the base material layer, and the cavity is formed on the dielectric layer; Alternatively, the base material layer includes a substrate, the piezoelectric layer and the substrate are stacked and bonded, the embedded groove is connected to the substrate along the thickness direction of the base material layer, and the cavity is formed on the substrate.

4. The chip according to claim 3, characterized in that: The material of the substrate includes one or more of silicon, silicon carbide, diamond, sapphire, aluminum nitride, ceramic, lithium tantalate, and lithium niobate.

5. The chip according to any one of claims 1 to 4, characterized in that: The embedded groove includes a plurality of sub-grooves distributed around the resonance zone and connected end to end in sequence; the release barrier layer includes a plurality of transverse barrier portions, and the plurality of transverse barrier portions are filled in the plurality of sub-grooves in a one-to-one correspondence; Alternatively, the embedded groove includes a plurality of sub-grooves distributed around the resonance zone and arranged in sequence; the release barrier layer includes a plurality of transverse barrier portions, and the plurality of transverse barrier portions are filled in the plurality of sub-grooves in a one-to-one correspondence.

6. The chip according to any one of claims 1 to 5, characterized in that: The release barrier layer is arranged along a circle, an ellipse or a polygon; and / or, the longitudinal depth of the release barrier layer ranges from 1 micron to 50 microns; and / or, the width of the release barrier layer in a top view is greater than or equal to 10 micrometers; and / or, the polymer includes one or more of polyimide, polydimethylsiloxane, polyvinylidene fluoride, benzocyclobutene, polyethylene terephthalate, and photoresist; And / or, the release barrier layer is formed by spin coating the polymer to fill the embedded groove, curing the polymer and planarizing the filled side of the polymer; And / or, the polymer has a Young's modulus of less than 10 GPa after curing.

7. The chip according to any one of claims 1 to 6, characterized in that: The chip has one or more micro grooves connecting the piezoelectric layer and the substrate layer along the thickness direction of the substrate layer, and the one or more micro grooves are connected to the embedded groove.

8. The chip according to claim 7, characterized in that: A plurality of the microgrooves are arranged at intervals along the edge of the resonance region; And / or, the cross-sectional shape of the microgroove in the top view is circular, elliptical, polygonal or X-shaped; And / or, the length of the microgroove in the top view is less than or equal to 10 micrometers; And / or, the cross-sectional area of ​​the microgroove in a top view is less than or equal to 100 square micrometers; And / or, a communication port is formed between the micro groove and the embedded groove, and the length of the communication port is less than or equal to 10 microns; And / or, a communication opening is formed between the micro groove and the embedded groove, and a cross-sectional area of ​​the communication opening is less than or equal to 100 square microns.

9. The chip according to any one of claims 1 to 8, characterized in that: The material of the piezoelectric layer includes one or more of lithium niobate, lithium tantalate, aluminum nitride, zinc oxide, and quartz in each tangential direction; And / or, a plurality of release holes are provided on the resonance zone, and the plurality of release holes are communicated with the concave cavity.

10. An electronic device, characterized in that: The invention comprises a printed circuit board and a chip as claimed in any one of claims 1 to 9, wherein the chip is arranged on the printed circuit board.

11. A method for preparing a chip according to any one of claims 1 to 9, characterized in that: include: Wafers with laminated bonding of piezoelectric layers and substrate layers; Etching a pre-buried groove on the wafer, wherein the pre-buried groove connects the piezoelectric layer and the substrate layer along the thickness direction of the substrate layer, the pre-buried groove is arranged around the resonance region of the piezoelectric layer, and the pre-buried groove forms an opening on the piezoelectric layer; Spin coating a polymer on the piezoelectric layer so that the polymer fills the embedded groove; Curing the polymer and planarizing the filled side of the polymer so that the polymer in the embedded groove forms a release barrier layer; Fabricating an electrode layer on the resonance region; Making a release hole penetrating the piezoelectric layer; The release fluid passes through the release hole and reacts with the substrate layer by etching to form a cavity on the substrate layer, so that the resonance zone and the bottom surface of the cavity are spaced apart in the thickness direction of the substrate layer, and the lateral size of the cavity is limited by the release barrier layer.

12. The method for preparing a chip according to claim 11, characterized in that: The step of curing the polymer and planarizing the filled side of the polymer specifically includes: pre-baking the wafer filled with the polymer; photolithography development to remove the polymer outside the extended space of the embedded groove; dry stripping to remove the polymer outside the embedded groove; planarizing the filled side of the polymer; and completely baking the wafer to cure the polymer; Or, the curing of the polymer and planarizing the filled side of the polymer specifically comprises: completely baking the wafer filled with the polymer to cure the polymer and planarizing the filled side of the polymer; Alternatively, the planarization of the filled side of the polymer may specifically include one or more of photolithography, dry etching, and chemical mechanical polishing.

13. The method for preparing a chip according to claim 11 or 12, characterized in that: The method of etching a pre-buried groove on the wafer specifically includes: etching a pre-buried groove and one or more micro grooves on the wafer, wherein the one or more micro grooves connect the piezoelectric layer and the substrate layer along the thickness direction of the substrate layer, and the one or more micro grooves are connected to the pre-buried groove.

14. The method for preparing a chip according to claim 13, characterized in that: One or more microgrooves are provided on the side of the pre-buried groove facing the resonance zone; And / or, one or more microgrooves are provided on a side of the pre-buried groove facing away from the resonance zone.

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