Perovskite-crystalline silicon tandem solar cell module and manufacturing method therefor

Abstract

Disclosed in the present invention are a perovskite-crystalline silicon tandem solar cell module and a manufacturing method therefor. The module comprises front glass, a perovskite cell layer, an upper-layer adhesive film, a crystalline silicon cell layer, a lower-layer adhesive film, and back glass. The perovskite cell layer consists of a plurality of perovskite sub-cells arranged on the surface of the front glass in a first direction of the front glass, and the perovskite sub-cells are insulated from each other; each perovskite sub-cell comprises a transparent conductive layer, a perovskite layer, and a lower transparent electrode layer which are stacked; continuous and uninterrupted insulating passivation layers are respectively arranged in the second direction of the front glass and fit tightly against the two ends of each perovskite sub-cell; bus bars are respectively arranged along the outer side surfaces of the insulating passivation layers; the lower transparent electrode layer is arranged on the perovskite layer and the bus bars; and positive and negative electrodes of a cell pack in the perovskite cell layer are connected to each other to form positive and negative leads which are arranged in the first direction and located on the same side of the perovskite cell layer, and the positive and negative leads are respectively connected to positive and negative electrodes of the crystalline silicon cell layer and serve as positive and negative electrodes for leading out.

Description

A perovskite-crystalline silicon stacked battery assembly and its preparation method Technical Field

[0001] The present invention relates to the technical field of photovoltaic modules, and in particular to a perovskite-crystalline silicon stacked cell module and a preparation method thereof. Background Art

[0002] Four-terminal perovskite-crystalline silicon cells have become a hot topic in the global photovoltaic research field in recent years due to their simple preparation methods and high efficiency. The two cell circuits can be connected independently, either in series or in parallel. Existing crystalline silicon modules can be directly used to prepare four-terminal tandem cells, requiring only the preparation of an additional semi-transparent perovskite photovoltaic module for stacking and use. However, due to optimal tandem power generation efficiency, the top perovskite cell primarily uses a wide-bandgap cell, resulting in a higher open-circuit voltage per unit area than crystalline silicon cell modules, but lower short-circuit current. To reduce the voltage of the entire perovskite cell module, multiple parallel regions are designed to reduce the voltage of the entire module. This results in an increase in busbars, which increases the area blocked by the underlying crystalline silicon cells, thereby affecting the power generation efficiency of the underlying crystalline silicon cells and reducing the overall power generation efficiency of the perovskite-crystalline silicon tandem module.

[0003] Summary of the Invention

[0004] In order to solve the problem of current mismatch of the crystalline silicon cell layer caused by busbar shading in the low-voltage design of the top perovskite in the perovskite-crystalline silicon tandem solar cell module, the present invention proposes a perovskite-crystalline silicon tandem cell module, which is connected in series and parallel on the short side (second direction) of the perovskite sub-cells, and the busbars are set on the opposite side to reduce the shading of the lower crystalline silicon cells, thereby avoiding a reduction in the overall power generation efficiency of the module.

[0005] The present invention is achieved through the following technical solutions:

[0006] A perovskite-crystalline silicon laminated battery assembly, characterized in that the battery assembly comprises: a front glass, a perovskite battery layer, an upper adhesive film, a crystalline silicon battery layer, a lower adhesive film, and a back glass stacked in sequence from top to bottom;

[0007] Wherein: the perovskite cell layer is composed of a plurality of perovskite sub-cells arranged on the surface of the front glass along the first direction thereof, and the perovskite sub-cells are insulated from each other; the perovskite sub-cells include: a transparent conductive layer arranged on the front glass, and a perovskite layer and a lower transparent electrode layer stacked on the transparent conductive layer; continuous and uninterrupted linear insulating passivation layers are respectively arranged along the second direction of the front glass and close to the two ends of the perovskite sub-cells; bus bars are respectively arranged along the outer surfaces of the insulating passivation layers; the lower transparent electrode layer is arranged on the perovskite layer and the bus bars; the positive and negative electrodes of the perovskite sub-cells in the perovskite cell layer are connected to form positive and negative lead lines arranged along the first direction and located on the same side of the perovskite cell layer, and then they are respectively connected to the positive and negative electrodes of the crystalline silicon cell layer and used as positive and negative lead lines.

[0008] Furthermore, a perovskite-crystalline silicon stacked cell assembly: the first direction is the length direction of the front glass, and the second direction is the width direction (short side direction) of the front glass.

[0009] Furthermore, a perovskite-crystalline silicon stacked battery assembly: several of the perovskite sub-batteries are connected in series first and then in parallel; or are connected in parallel first and then in series.

[0010] Furthermore, a perovskite-crystalline silicon stacked cell assembly: the band gap of the perovskite cell layer is 1.75 to 2.05 eV.

[0011] Furthermore, a perovskite-crystalline silicon stacked cell assembly: the thickness of the insulating passivation layer is not less than that of the perovskite sub-cell.

[0012] Furthermore, a perovskite-crystalline silicon stacked cell assembly: the projected area of ​​the perovskite cell layer is not less than the area of ​​the crystalline silicon cell layer.

[0013] Furthermore, a perovskite-crystalline silicon stacked cell assembly: the edges of the perovskite cell layer and the crystalline silicon cell layer are 10 to 20 mm away from the edge of the front glass.

[0014] A method for preparing a perovskite-crystalline silicon stacked battery assembly, characterized in that the method comprises the following steps:

[0015] S1. Placing a first mask plate on the front glass to prepare a transparent conductive layer;

[0016] S2. Preparing a perovskite layer on the transparent conductive layer; wherein the perovskite layer includes a hole transport layer, a perovskite absorption layer, and an electron transport layer stacked in sequence;

[0017] S3, using laser scribing to scribe the transparent conductive layer and the perovskite layer to form a plurality of perovskite sub-cells spaced apart along the first direction, and filling the laser-scribed lanes with a passivation layer to form insulating channels to separate adjacent perovskite sub-cells from each other;

[0018] S4, removing the first mask plate, and providing a continuous and uninterrupted insulating passivation layer along the second direction and close to both ends of the perovskite sub-cell;

[0019] S5, using a second mask plate to respectively arrange bus bars along the outer surface of the insulating passivation layer;

[0020] S6. Using a third mask plate to prepare a lower transparent electrode layer on the electron transport layer and the bus bar to obtain a perovskite battery layer; wherein: the mask area of ​​the third mask plate includes a laser scribing area; connecting the positive and negative electrodes of the perovskite sub-cells in the perovskite battery layer to form positive and negative lead lines arranged along the first direction and located on the same side of the perovskite battery layer;

[0021] S7. Lay a layer of adhesive film, a crystalline silicon cell layer, a lower layer of adhesive film and back glass on the perovskite cell layer in sequence, connect the positive and negative lead wires to the positive and negative electrodes of the crystalline silicon cell layer respectively and lead them out as the positive and negative electrodes, and then put them into the laminator for lamination to obtain a perovskite-crystalline silicon stacked cell assembly.

[0022] Furthermore, a method for preparing a perovskite-crystalline silicon stacked battery assembly is provided: the height of the passivation layer is not lower than that of the perovskite battery layer.

[0023] Furthermore, a method for preparing a perovskite-crystalline silicon stacked battery assembly is provided: the width of the insulating passivation layer is 20 to 100 μm.

[0024] By adjusting the band gap of the perovskite cell, the upper perovskite cell layer and the lower crystalline silicon cell layer can maximize the use of sunlight per unit area. The perovskite cell layer and the crystalline silicon cell layer are stacked from top to bottom in the order of energy gap from large to small, so that short-wavelength light is absorbed by the upper wide-bandgap perovskite cell layer, and long-wavelength light can penetrate and be absorbed by the narrow-bandgap crystalline silicon cell layer. This can maximize the use of sunlight, improve spectrum utilization, component performance and stability.

[0025] Beneficial effects of the present invention:

[0026] (1) The present invention eliminates the current mismatch problem caused by the bus bar blocking the lower layer of crystalline silicon cells by interconnecting the short sides of the neutron cells in the top perovskite cell layer and arranging the bus bar on the opposite side edges.

[0027] (2) Conventional laser cutting methods for perovskite battery packs (e.g., three cuts to form a series structure) will produce many laser-cut grooves in the battery assembly, which will increase the risk of battery assembly degradation. The present invention reduces the risk of perovskite battery pack degradation through a single laser cutting. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0029] FIG1 is a layer diagram of a perovskite-crystalline silicon tandem battery assembly designed by the present invention;

[0030] FIG2 is a schematic structural diagram of a perovskite cell layer in the present invention;

[0031] FIG3 is an enlarged view of the AA portion in FIG2 ;

[0032] FIG4 is a schematic structural diagram of a first mask;

[0033] FIG5 is a schematic diagram of the structure of a perovskite sub-cell according to the present invention;

[0034] FIG6 is a schematic structural diagram of the third mask.

[0035] Markings in the figure: 1 front glass, 2 perovskite cell layer, 3 upper film, 4 crystalline silicon cell layer, 5 lower film, 6 back glass, 7 insulating passivation layer, 8 bus bar, 1-1 first direction, 1-2 second direction, 2-1 perovskite sub-cell, 2-1-1 transparent conductive layer, 2-1-2 perovskite layer, 2-1-3 lower transparent electrode layer. DETAILED DESCRIPTION

[0036] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is in no way intended to limit the present invention and its application or use. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0037] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "top", "bottom", etc., indicating directions or positional relationships, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific direction, be constructed and operate in a specific direction, and therefore should not be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Moreover, the terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein.

[0038] Example 1

[0039] As shown in Figures 1 to 6, a perovskite-crystalline silicon stacked cell assembly is designed, which includes: a front glass 1, a perovskite cell layer 2, an upper adhesive film 3, a crystalline silicon cell layer 4, a lower adhesive film 5, and a back glass 6 stacked in sequence from top to bottom;

[0040] The perovskite cell layer 2 is composed of a plurality of perovskite sub-cells 2-1 arranged on the surface of the front glass 1 along a first direction 1-1 (length direction), and the perovskite sub-cells 2-1 are insulated from each other. The plurality of perovskite sub-cells 2-1 are connected in parallel and then in series. The perovskite sub-cells 2-1 include a transparent conductive layer 2-1-1 arranged on the front glass 1, and a perovskite layer 2-1-2 and a lower transparent electrode layer 2-1-3 stacked on the transparent conductive layer 2-1-1.

[0041] Along the second direction 1-2 (width direction) of the front glass 1 and in close contact with both ends of the perovskite sub-cell 2-1, a continuous and uninterrupted linear insulating passivation layer 7 with a thickness not less than that of the perovskite sub-cell 2-1 is respectively provided; along the outer surface of the insulating passivation layer 7, bus bars 8 are respectively provided; the lower transparent electrode layer 2-1-3 is provided on the perovskite layer 2-1-2 and the bus bar 8; the positive and negative poles of the perovskite sub-cell 2-1 in the perovskite cell layer 2 are connected to form positive and negative lead lines arranged along the first direction 1-1 and located on the same side of the perovskite cell layer 2, and then connected to the positive and negative poles of the crystalline silicon cell layer 4 respectively and used as positive and negative lead lines.

[0042] The preparation method of Example 1 comprises the following specific steps:

[0043] S1. Place a first mask plate as shown in FIG5 on the front glass 1, and then use a vacuum coating process to prepare a transparent conductive layer 2-1-1 with a thickness of 80 nm;

[0044] S2. Prepare a perovskite layer 2-1-2 on the transparent conductive layer 2-1-1 by a vacuum coating process; wherein the perovskite layer 2-1-2 includes: a hole transport layer, a perovskite absorption layer, and an electron transport layer stacked in sequence;

[0045] S3. Laser scribing is used to scribe the transparent conductive layer 2-1-1 and the perovskite layer 2-1-2 to form 40 perovskite sub-cells 2-1 spaced apart along the first direction 1-1. A passivation layer having a height not less than that of the perovskite cell layer 2 is filled in the laser scribing lanes (the width of the scribing lanes is about 50 μm) to form insulating channels, so that adjacent perovskite sub-cells 2-1 are spaced apart from each other.

[0046] S4. Remove the first mask plate and provide a continuous and uninterrupted insulating passivation layer 7 along the second direction 1-2 and close to both ends of the perovskite sub-cell 2-1. The thickness of the insulating passivation layer 7 is not less than the thickness of the perovskite sub-cell 2-1 and the width is 90 μm.

[0047] S5. Using a second mask plate, bus bars 8 are respectively arranged along the surface of the insulating passivation layer 7;

[0048] S6. Using a third mask plate, prepare a lower transparent electrode layer 2-1-3 on the electron transport layer and the bus bar 8 to obtain a perovskite battery layer; wherein: the mask area of ​​the third mask plate includes a laser scribing area; the positive and negative electrodes of the perovskite sub-battery 2-1 in the perovskite battery layer 2 are connected to form positive and negative lead lines arranged along the first direction 1-1 and located on the same side of the perovskite battery layer 2;

[0049] S7. Layer the adhesive film 3, the crystalline silicon cell layer 4, the lower adhesive film 5 and the back glass 6 on the perovskite cell layer 2 in sequence, connect the positive and negative lead wires to the positive and negative electrodes of the crystalline silicon cell layer 4 respectively and lead them out as the positive and negative electrodes, and then put them into the laminator for lamination to obtain a perovskite-crystalline silicon stacked cell assembly.

[0050] The present invention combines a mask with a vacuum coating process. First, a first mask is placed on the front glass within 13 mm from the edge to sequentially form a transparent conductive layer 2-1-1, a hole transport layer, a perovskite absorption layer, and an electron transport layer. Laser scribing is then used to cut through the transparent conductive layer, the hole transport layer, the perovskite absorption layer, and the electron transport layer, dividing the entire film into 40 perovskite sub-cells 2-1. Secondly, a transparent bus bar 8 shared by the perovskite battery group is prepared in the side area of ​​the short side of the perovskite sub-cell 2-1, and an insulating passivation layer is formed between the bus bar 8 and each functional layer of the perovskite sub-cell. The third mask plate (as shown in FIG6 ) is placed on the electron transport layer to prepare the lower transparent electrode layer 2-1-3. The mask area of ​​the third mask plate includes the location of the scribe groove. The scribe groove is used to separate the lower transparent electrode layer on the electron transport surface into 40 areas where perovskite sub-cells of the same size are located. The electrode layer in the unmasked area is directly prepared on the conductive bus bar, resulting in a battery pack of 5 perovskite sub-cells connected in parallel through a common transparent bus bar 8, and a perovskite battery layer 2 of 8 perovskite battery components connected in series (as shown in FIG2 ). Then, a lower layer of adhesive film 5 is laid on the surface of the back glass 6, and a double-sided power generation crystalline silicon battery layer 4 and an upper layer of adhesive film 3 are laid on the lower layer of adhesive film 5. The front glass 1 with the perovskite battery layer 2 on the inner surface prepared above is then laminated on it, and then placed in a laminator for lamination to obtain a four-terminal parallel perovskite and crystalline silicon stacked battery assembly. Among them, the crystalline silicon cell layer 4 is composed of 12 166mm double-sided HJT cell sheets connected in series, so that the crystalline silicon cell layer 4 and the perovskite cell layer 2 have similar short-circuit currents and matching rated voltages.

[0051] The 40 perovskite sub-cells 2-1 are connected in parallel, with each five adjacent sub-cells then connected in series, resulting in a total voltage of approximately 8.4V and a current of approximately 5.1A for the perovskite cell layer 2. The lower crystalline silicon cell group 4 is composed of 12 166mm double-sided HJT cells connected in series, resulting in a total voltage of approximately 8.4V and a current of approximately 5.5A for the crystalline silicon cell layer 4. The present invention designs a perovskite-crystalline silicon tandem cell assembly having a perovskite cell layer 2 at the top and a crystalline silicon cell layer 4 at the bottom. The circuit loops of the perovskite cell layer 2 and the crystalline silicon cell layer 4 are independent of each other. The positive lead of the perovskite cell layer 2 is connected to the positive electrode of the crystalline silicon cell layer 4 as a positive lead, and the negative lead of the perovskite cell layer 2 is connected to the negative electrode of the crystalline silicon cell layer 4 as a negative lead. These cells are connected in parallel on the same side of the assembly, resulting in a perovskite-crystalline silicon tandem assembly with the upper and lower cell layers connected in parallel, with a total voltage of approximately 8.4V and a total current of 10.5A.

[0052] The present invention eliminates the current mismatch problem caused by the bus bar blocking the lower layer cells and causing power loss by interconnecting the short sides of the neutron cells in the top perovskite cell layer and arranging the opposite side portions of the common bus bar.

[0053] Example 2

[0054] The difference between Example 2 and Example 1 is that the five perovskite sub-cells 2-1 are first connected in series to form a perovskite cell group, and then the eight perovskite cell groups are connected in parallel to form a perovskite cell layer 2; the rest is the same as Example 1.

[0055] The above preferred embodiments of the present invention are only used to explain the present invention and are not used to limit the present invention. Any obvious changes or modifications derived from the technical solution of the present invention are still within the scope of protection of the present invention.

Claims

1. A perovskite-crystalline silicon stacked battery assembly, characterized in that: The battery assembly comprises: front glass (1), a perovskite battery layer (2), an upper adhesive film (3), a crystalline silicon battery layer (4), a lower adhesive film (5) and back glass (6) which are stacked in sequence from top to bottom; Wherein: the perovskite cell layer (2) is composed of a plurality of perovskite sub-cells (2-1) arranged on the surface of the front glass (1) along the first direction (1-1), and the perovskite sub-cells (2-1) are insulated from each other; The perovskite subcell (2-1) comprises: a transparent conductive layer (2-1-1) arranged on the front glass (1), and a perovskite layer (2-1-2) and a lower transparent electrode layer (2-1-3) stacked on the transparent conductive layer (2-1-1); Continuous and uninterrupted linear insulating passivation layers (7) are respectively arranged along the second direction (1-2) of the front glass (1) and in close contact with the two ends of the perovskite sub-cell (2-1); a bus bar (8) is arranged along the outer surface of the insulating passivation layer (7); the lower transparent electrode layer (2-1-3) is arranged on the perovskite layer (2-1-2) and the bus bar (8); The positive and negative electrodes of the perovskite subcell (2-1) in the perovskite cell layer (2) are connected to form positive and negative lead-out lines arranged along the first direction (1-1) and located on the same side of the perovskite cell layer (2), which are then respectively connected to the positive and negative electrodes of the crystalline silicon cell layer (4) and used as positive and negative lead-out lines.

2. A perovskite-crystalline silicon stacked battery assembly according to claim 1, characterized in that: The first direction (1-1) is the length direction of the front glass (1), and the second direction (1-2) is the width direction of the front glass (1).

3. A perovskite-crystalline silicon stacked battery assembly according to claim 1, characterized in that: Some of the perovskite sub-cells (2-1) are connected in series first and then in parallel; or in parallel first and then in series.

4. A perovskite-crystalline silicon stacked battery assembly according to claim 1, characterized in that: The band gap of the perovskite cell layer (2) is 1.75 to 2.05 eV.

5. The perovskite-crystalline silicon stacked battery assembly according to claim 1, characterized in that: The thickness of the insulating passivation layer (7) is not less than that of the perovskite subcell (2-1).

6. A perovskite-crystalline silicon stacked battery assembly according to claim 1, characterized in that: The projected area of ​​the perovskite cell layer (2) is not less than the area of ​​the crystalline silicon cell layer (4).

7. The perovskite-crystalline silicon stacked battery assembly according to claim 1, characterized in that: The edges of the perovskite cell layer (2) and the crystalline silicon cell layer (4) are 10 to 20 mm away from the edge of the front glass (1).

8. A method for preparing a perovskite-crystalline silicon stacked battery assembly according to any one of claims 1 to 7, characterized in that: The method comprises the following steps: S1, placing a first mask plate on the front glass (1) to prepare a transparent conductive layer (2-1-1); S2, preparing a perovskite layer (2-1-2) on the transparent conductive layer (2-1-1); wherein the perovskite layer (2-1-2) comprises a hole transport layer, a perovskite absorption layer and an electron transport layer stacked in sequence; S3, using laser scribing to cut the transparent conductive layer (2-1-1) and the perovskite layer (2-1-2) to form a plurality of perovskite sub-cells (2-1) spaced apart along the first direction (1-1), and filling a passivation layer in the laser scribing path to form an insulating channel so that adjacent perovskite sub-cells (2-1) are spaced apart from each other; S4, removing the first mask plate, and respectively providing a continuous and uninterrupted insulating passivation layer (7) along the second direction (1-2) and in close contact with both ends of the perovskite sub-cell (2-1); S5, using a second mask plate to respectively arrange bus bars (8) along the outer surface of the insulating passivation layer (7); S6. Using a third mask plate, prepare a lower transparent electrode layer (2-1-3) on the electron transport layer and the bus bar (8) to obtain a perovskite battery layer (2); wherein: the mask area of ​​the third mask plate includes a laser scribing area; the positive and negative electrodes of the perovskite sub-battery (2-1) in the perovskite battery layer (2) are connected to form positive and negative lead wires arranged along the first direction (1-1) and located on the same side of the perovskite battery layer (2); S7. Layer the adhesive film (3), the crystalline silicon cell layer (4), the lower adhesive film (5) and the back glass (6) on the perovskite cell layer (2) in sequence, connect the positive and negative lead wires to the positive and negative electrodes of the crystalline silicon cell layer (4) respectively and lead them out as the positive and negative electrodes, and then put them into a laminator for lamination to obtain a perovskite-crystalline silicon stacked cell assembly.

9. The method for preparing a perovskite-crystalline silicon stacked battery assembly according to claim 8, characterized in that: The height of the passivation layer is not lower than that of the perovskite cell layer (2).

10. The method for preparing a perovskite-crystalline silicon stacked battery assembly according to claim 8, characterized in that: The width of the insulating passivation layer (7) is 20-100 μm.

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