Data writing method, system, and apparatus, and quad-level cell NAND

Abstract

The present application relates to the field of data processing, and discloses a data writing method, system, and apparatus, a non-volatile readable storage medium, and a quad-level cell NAND. A second storage module independent of a first storage module is provided. A first check block obtained when writing to a target word line for the first time is stored in a target storage space. When writing for the second time, the first check block is called, and same and a data block written the second time are transmitted to the target word line. According to the present application, data storage is transferred from the first storage module to the second storage module independent of the first storage module, which prevents two write operations from simultaneously occupying resources of the first storage module, can improve the performance and the expansion capability of the system, and ensures the integrity and correctness of data. In addition, in the second write operation, a check block is not computed again; instead, the check block stored in the second storage module by the first write operation is directly used, which also reduces the occupation of a processor and the storage module in the processor.

Description

Data writing method, system, device and quad-level cell flash memory

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on November 22, 2023, with application number 202311559817.8, and application name “A data writing method, system, device, medium and quad-level cell flash memory”, all contents of which are incorporated by reference into this application. Technical Field

[0003] The embodiments of the present application relate to the field of data storage, and in particular, to a data writing method, system, device, non-volatile readable storage medium and quad-level cell flash memory. Background Art

[0004] With the continuous development of NAND technology, QLC NAND (Quad-Level Cell NAND) has lower costs and higher storage capacity than the current mainstream TLC NAND (Triple Level Cell NAND). Each storage cell of QLC NAND can store 4 bits of data.

[0005] However, writing to QLC NAND presents unique requirements and challenges. To ensure data integrity and accuracy, each wordline must be written twice. Furthermore, the write order between wordlines must be strictly adhered to during these two writes. This requires that the first write be performed on each wordline in each level, following the order of the levels. Only after all wordlines in that level have completed the first write can the second write proceed.

[0006] Optionally, when writing data for the first time, it is necessary to call a calculation module, the calculation module includes a processor configured to perform calculations, the processor includes a RAM (random access memory) configured to store data, the processor calculates a check block based on the written data, the RAM is configured to store intermediate data and final data during the calculation process, and after the calculation is completed, the data and the check block are written to the NAND, and then the RAM is released. When writing data for the second time, the calculation module is called again to perform the above calculation steps again. It can be seen that writing data on each word line requires calling the calculation module twice and occupying RAM resources twice, but RAM resources are very limited. Therefore, it is very necessary to provide a data writing method to reduce the occupation of RAM resources. Summary of the Invention

[0007] The purpose of this application is to provide a data writing method, system, device, non-volatile readable storage medium and quad-level cell flash memory, which transfers data storage from a first storage module to a second storage module independent of the first storage module, avoiding the simultaneous occupation of the resources of the first storage module by two write operations, thereby improving the performance and scalability of the system and ensuring the integrity and correctness of the data. In addition, in the second write operation, the check block is no longer calculated, but the check block stored in the second storage module in the first write operation is directly used, saving the occupation of the processor and the storage module in the processor.

[0008] To solve the above technical problems, a first aspect of an embodiment of the present application provides a data writing method, which is applied to a processor, the processor including a first storage module and a second storage module, and the processor is configured to write data to a quad-level cell flash memory, the method comprising:

[0009] When the quad-level unit flash memory is powered on, applying for target storage space from the second storage module, where the second storage module is a storage module independent of the first storage module;

[0010] When writing to the target word line for the first time, calculating a first check block based on the data block written for the first time, transmitting the first check block and the data block to the target word line, and storing the first check block in the target storage space;

[0011] When writing to the target word line for the second time, the first check block in the target storage space is called, and the first check block and the data block written for the second time are transferred to the target word line.

[0012] In one embodiment, when the processor can process N write operations in parallel, where N is an integer greater than 2, the method further includes:

[0013] Divide the computing resources of the processor into N parts, and set a corresponding serial number identifier for each computing resource;

[0014] When the quad-level cell flash memory is powered on, the target storage space is requested from the second storage module, including:

[0015] When the quad-level unit flash memory is powered on, N target storage spaces are requested from the second storage module;

[0016] Bind N target storage spaces to N computing resources in a one-to-one correspondence.

[0017] In one embodiment, it further includes:

[0018] Obtaining a write instruction, and determining whether to write to the target word line for the first time or the second time according to the write instruction;

[0019] If it is the first time to write to the target word line, then entering the step of calculating a first check block based on the data block written for the first time when writing to the target word line, transmitting the first check block and the data block to the target word line, and storing the first check block in the target storage space;

[0020] If the target word line is written for the second time, the process proceeds to the step of calling the first check block in the target storage space when writing to the target word line for the second time, and transferring the first check block and the second written data block to the target word line.

[0021] In one embodiment, when writing to a target word line for the first time, calculating a first check block based on a data block written for the first time, transmitting the first check block and the data block to the target word line, and storing the first check block in a target storage space includes:

[0022] Determine a target serial number identifier and a target storage space corresponding to the target serial number identifier according to a write instruction;

[0023] Apply for the target computing resource corresponding to the target serial number identifier and set the checksum calculation flag to enable state;

[0024] Calculate a first check block based on the first written data block using the target computing resource;

[0025] The first check block is stored in the target storage space corresponding to the target sequence number identifier.

[0026] In one embodiment, when writing to the target word line for the second time, calling the first check block in the target storage space, and transferring the first check block and the second written data block to the target word line includes:

[0027] Determine the target serial number identifier and the target storage space corresponding to the target serial number identifier according to the write instruction, and set the check calculation flag bit to a disabled state;

[0028] Reading a first check block from a target storage space corresponding to the target sequence number identifier;

[0029] The first check block and the second written data block are transferred to the target word line.

[0030] In one embodiment, it further includes:

[0031] When writing to the target word line for the first time, determining whether the process of storing the first check block in the target storage space corresponding to the target serial number identifier is completed;

[0032] If it is determined that the process of storing the first check block in the target storage space corresponding to the target sequence number identifier is completed, the target sequence number identifier is released.

[0033] In one embodiment, releasing the target sequence number identifier includes:

[0034] Mark the target sequence number ID as unassigned.

[0035] In one embodiment, determining a target sequence number identifier and a target storage space corresponding to the target sequence number identifier according to a write instruction includes:

[0036] An unoccupied target serial number identifier and a target address of a target storage space corresponding to the target serial number identifier are determined according to the write instruction.

[0037] In one embodiment, when writing to the target word line for the second time, calling the first check block in the target storage space, and transferring the first check block and the second written data block to the target word line includes:

[0038] Determine a target serial number identifier and a target storage space corresponding to the target serial number identifier according to a write instruction;

[0039] Apply for the target computing resource corresponding to the target serial number identifier and set the checksum calculation flag to the enabled state;

[0040] Calculate a second check block based on the second written data block using the target computing resource;

[0041] Reading a first check block from a target storage space corresponding to the target sequence number identifier;

[0042] The first check block or the second check block and the second written data block are transferred to the target word line.

[0043] In one embodiment, transferring the first parity block or the second parity block and the second written data block to the target word line includes:

[0044] A target parity block is determined in a preset manner according to the first parity block and the second parity block, and the data block and the target parity block written for the second time are transmitted to the target word line.

[0045] In one embodiment, determining a target parity block using a preset method according to the first parity block and the second parity block, and transmitting the second-written data block and the target parity block to the target word line includes:

[0046] A target parity block is determined according to a comparison result between each data bit in the first parity block and each data bit in the second parity block, and the second written data block and the target parity block are transmitted to a target word line.

[0047] In one embodiment, determining a target parity block based on a comparison result of each data bit in the first parity block and each data bit in the second parity block, and transmitting the second-written data block and the target parity block to a target word line includes:

[0048] The check block with a correct calculation result is determined according to each data bit in the first check block and each data bit in the second check block, and the check block with a correct calculation result and the second written data block are transmitted to the target word line.

[0049] In one embodiment, determining a parity block with a correct calculation result based on each data bit in the first parity block and each data bit in the second parity block, and before transmitting the parity block with a correct calculation result and the second written data block to the target word line, the method further includes:

[0050] Determine whether the first check block and the second check block are the same;

[0051] If it is determined that the first check block and the second check block are the same, any one of the first check block and the second check block and the data block written for the second time are transmitted to the target word line;

[0052] If it is determined that the first check block and the second check block are different, the step of determining the check block with the correct calculation result based on each data bit in the first check block and each data bit in the second check block is entered, and the check block with the correct calculation result and the data block written for the second time are transmitted to the target word line.

[0053] In one embodiment, after determining that the calculation result is a correct check block based on each data bit in the first check block and each data bit in the second check block, the method further includes:

[0054] If both the first check block and the second check block are erroneous check blocks, calculation error information is fed back.

[0055] In one embodiment, after feeding back the calculation error information, the method further includes:

[0056] The space of the first check block stored in the target storage space is marked as invalid and cleared.

[0057] In one embodiment, after feeding back the calculation error information, the method further includes:

[0058] When a preset condition is met, the data block is rewritten to the target word line, a third check block is calculated based on the currently written data block, and the third check block and the data block are transmitted to the target word line.

[0059] In one embodiment, when writing to the target word line for the second time, after calling the first check block in the target storage space and transferring the first check block and the second written data block to the target word line, the method further includes:

[0060] Release the space in the target storage space for storing the first check block.

[0061] In one embodiment, releasing space in the target storage space for storing the first check block includes:

[0062] The data in the space for storing the first check block in the target storage space is marked as invalid and cleared.

[0063] In one embodiment, before releasing the space in the target storage space for storing the first check block, the method further includes:

[0064] Determining whether transmission completion information fed back by the target word line is received;

[0065] If the transmission completion information is received, the process proceeds to a step of releasing the space in the target storage space for storing the first check block.

[0066] In one embodiment, calculating a first check block based on a data block written for the first time, transmitting the first check block and the data block to a target word line, and storing the first check block in a target storage space includes:

[0067] According to the write instruction, the check calculation flag is set to the enabled state, the target storage space and target computing resources are applied, the target computing resources are used to calculate the first check block according to the first written data block, and the first check block is stored in the target storage space.

[0068] In one embodiment, calling a first check block in a target storage space and transferring the first check block and a second written data block to a target word line includes:

[0069] The check calculation flag is set to a disabled state according to the write instruction, a first check block is read from the target storage space, and the first check block and the second written data block are transmitted to the target word line.

[0070] To solve the above technical problems, a second aspect of an embodiment of the present application further provides a data writing system, which is applied to a processor, the processor including a first storage module and a second storage module, and the processor is configured to write data to a quad-level cell flash memory, the system comprising:

[0071] a space application unit configured to apply for target storage space from a second storage module when the quad-level unit flash memory is powered on, the second storage module being a storage module independent of the first storage module;

[0072] a first writing unit configured to calculate a first check block according to the data block written for the first time when writing to the target word line for the first time, transfer the first check block and the data block to the target word line, and store the first check block in the target storage space;

[0073] The second writing unit is configured to call the first check block in the target storage space when writing to the target word line for the second time, and transfer the first check block and the second written data block to the target word line.

[0074] To solve the above technical problems, a third aspect of the embodiments of the present application further provides a data writing device, including:

[0075] a memory arranged to store a computer program;

[0076] The processor is configured to implement the steps of the above-mentioned data writing method when executing the computer program.

[0077] To solve the above technical problems, the fourth aspect of the embodiment of the present application further provides a computer non-volatile readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the data writing method as described above are implemented.

[0078] To solve the above technical problems, the fifth aspect of the embodiment of the present application further provides a quad-level cell flash memory, the processor includes a first storage module and a second storage module, and the processor in the data writing device is used to write data to the quad-level cell flash memory.

[0079] The present application provides a data writing method, system, device, non-volatile readable storage medium and quad-level cell flash memory, which relate to the field of data processing and are used to solve the problem of excessive resource occupation. A second storage module independent of the first storage module is set up, and the first check block obtained when writing to the target word line for the first time is stored in the target storage space. When writing for the second time, this first check block is called and it and the data block written for the second time are transferred to the target word line. The present application transfers data storage from the first storage module to a second storage module independent of the first storage module, avoiding the two write operations occupying the resources of the first storage module at the same time, which can improve the performance and scalability of the system and ensure the integrity and correctness of the data. In addition, in the second write operation, the check block is no longer calculated, but the check block stored in the second storage module by the first write operation is directly used, which saves the occupation of the processor and the storage module in the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0081] FIG1 is a storage diagram of a quad-level cell flash memory provided by the present application;

[0082] FIG2 is a flow chart of a data writing method provided by the present application;

[0083] FIG3 is a schematic diagram of an optional embodiment of a data writing method provided by the present application;

[0084] FIG4 is a schematic diagram of an optional data writing architecture according to an embodiment of the present application;

[0085] FIG5 is a schematic diagram of a data writing system provided by the present application;

[0086] FIG6 is a schematic diagram of a data writing device provided by the present application;

[0087] FIG7 is a schematic diagram of a computer non-volatile readable storage medium provided in this application. DETAILED DESCRIPTION

[0088] The core of this application is to provide a data writing method, system, device, non-volatile readable storage medium and quad-level cell flash memory, which transfers data storage to a second storage module independent of the first storage module, avoiding the simultaneous occupation of the resources of the first storage module by two write operations, thereby improving the performance and scalability of the system and ensuring the integrity and correctness of the data. In addition, in the second write operation, the calculation module is no longer called to calculate the check block. Instead, the check block stored in the second storage module during the first write operation is directly used, which also saves the occupation of the calculation module.

[0089] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0090] As shown in FIG1 , FIG1 is a quad-level cell flash memory. The conventional writing process is as follows: First, for level 0, data is first written sequentially to word lines 0 to 3 in level 0. After the first writing is completed on word line 3, data is then written again sequentially from word lines 0 to 3. After the second writing is completed on word line 3, writing is started again on the four word lines in level 1, and the above steps are repeated.

[0091] The present application provides a data writing method, as shown in FIG2 , which is applied to a processor, wherein the processor includes a first storage module and a second storage module, and the processor is configured to write data to a quad-level cell flash memory. The method includes:

[0092] S11: when the quad-level cell flash memory is powered on, applying for target storage space from the second storage module, where the second storage module is a storage module independent of the first storage module;

[0093] In this embodiment of the present application, when the quad-level cell flash memory is powered on, the processor needs to request target storage space from the secondary storage module. The secondary storage module in the processor is an independent storage device that can provide additional storage space. Through the secondary storage module, the system can utilize additional storage resources to store data.

[0094] Alternatively, the processor may send a request to the second storage module to allocate a target storage space. The target storage space is intended for storing the data to be written and the associated check blocks. The second storage module allocates the target storage space based on the request and returns the address or other identifier of the target storage space to the processor.

[0095] Through this step, the system can use the independent storage space of the second storage module to store data, avoiding the simultaneous occupation of the resources of the first storage module and improving the performance and expansion capability of the system.

[0096] S12: When writing to the target word line for the first time, calculating a first check block based on the data block written for the first time, transmitting the first check block and the data block to the target word line, and storing the first check block in the target storage space;

[0097] In an embodiment of the present application, before writing to the target word line for the first time, the processor takes the data block as input and calculates the check block through an algorithm. This algorithm may involve error correction coding, hash functions, etc. The processor uses a first storage module (for example, RAM in the processor) to store the intermediate results in the calculation process and the first check block finally generated. The calculated first check block is transmitted to the target word line together with the data block and stored in the target storage space at the same time. In this way, after the first write is completed, the target word line contains both the data block and the corresponding first check block.

[0098] S13: When writing to the target word line for the second time, calling the first check block in the target storage space, and transferring the first check block and the second written data block to the target word line.

[0099] This step means that when writing data to the target word line for the second time, it is necessary to call the first check block in the target storage space and transfer the first check block and the second written data block to the target word line to ensure the integrity and correctness of the data.

[0100] First, the first check block in the target storage space needs to be called. The check block is calculated by the calculation module based on the first data block written. This check block is stored in a second storage module independent of the first storage module. By calling the first check block in the target storage space, the value of this check block can be obtained. Next, the obtained first check block and the second data block written are transferred to the target word line. The target word line is the specific location where the data is to be written. This process ensures the integrity and correctness of the data. The value of the first check block can be used to verify the correctness of the second data block written, thereby ensuring that the data is correctly written to the target word line.

[0101] The method provided by the embodiments of the present application avoids the need to repeatedly calculate the check block, as the check block has already been calculated and stored during the first write operation. This saves computing module resources. Furthermore, storing data in an independent second storage module prevents two write operations from simultaneously occupying the resources of the first storage module, thereby improving system performance and scalability.

[0102] In one embodiment, when the processor can process N write operations in parallel, where N is an integer greater than 2, the method further includes:

[0103] Divide the computing resources of the processor into N parts, and set a corresponding serial number identifier for each computing resource;

[0104] When the quad-level cell flash memory is powered on, the target storage space is requested from the second storage module, including:

[0105] When the quad-level unit flash memory is powered on, N target storage spaces are requested from the second storage module;

[0106] Bind N target storage spaces to N computing resources in a one-to-one correspondence.

[0107] In this embodiment of the present application, when a processor needs to perform multiple write operations simultaneously, such as processing N write requests, it can distribute the computing tasks to N computing resources and allocate a target storage space for each write request. Each target storage space is bound to a corresponding computing resource to ensure data consistency and correctness during parallel processing.

[0108] By dividing computing resources into N parts and binding them to N target storage spaces, efficient parallel processing capabilities can be achieved. This allows multiple write requests to be processed in separate target storage spaces without interfering with or conflicting with each other. This improves processor efficiency and overall system performance.

[0109] It should be noted that computing resources can be, but are not limited to, used to calculate (for example, encrypt, convert, etc.) data that is not allowed to be written into the quad-level unit flash memory, so that the calculated data can be written into the quad-level unit flash memory. Computing resources can be, but are not limited to, hardware resources and computing power resources provided by the processor. For example, hardware resources can be, but are not limited to, hardware used for performing calculations in the processor. For example, hardware resources can be, but are not limited to, XOR (exclusive OR) calculation units in the processor. Computing power resources can be, but are not limited to, computing performance provided by the processor. For example, if the processor includes a CPU, computing power resources can be, but are not limited to, computing performance provided by the CPU, for example, computing performance provided by the CPU for performing logical operations and bit operations.

[0110] In one embodiment, it further includes:

[0111] Obtaining a write instruction, and determining whether to write to the target word line for the first time or the second time according to the write instruction;

[0112] If it is the first time to write to the target word line, then entering the step of calculating a first check block based on the data block written for the first time when writing to the target word line, transmitting the first check block and the data block to the target word line, and storing the first check block in the target storage space;

[0113] If the target word line is written for the second time, the process proceeds to the step of calling the first check block in the target storage space when writing to the target word line for the second time, and transferring the first check block and the second written data block to the target word line.

[0114] In one embodiment, when writing to a target word line for the first time, calculating a first check block based on a data block written for the first time, transmitting the first check block and the data block to the target word line, and storing the first check block in a target storage space includes:

[0115] Determine a target serial number identifier and a target storage space corresponding to the target serial number identifier according to a write instruction;

[0116] Apply for the target computing resource corresponding to the target serial number identifier and set the verification computing flag to the enabled state;

[0117] Calculate a first check block based on the first written data block using the target computing resource;

[0118] The first check block is stored in the target storage space corresponding to the target sequence number identifier.

[0119] In the embodiment of the present application, before writing data to the target word line, it is necessary to obtain a write instruction and determine whether it is the first time or the second time to write to the target word line based on the write instruction.

[0120] If it is the first time to write to the target word line, then when writing to the target word line for the first time, a first check block is calculated based on the data block written for the first time, the first check block and the data block are transmitted to the target word line, and the first check block is stored in the target storage space. For example, the steps include: determining the target sequence number identifier and the target storage space corresponding to the target sequence number identifier according to the write instruction; applying for the target computing resource corresponding to the target sequence number identifier and setting the check calculation flag bit to an enabled state, which means that the step of calculating the check bit needs to be executed; therefore, using the target computing resource to calculate the first check block based on the data block written for the first time; and storing the first check block in the target storage space corresponding to the target sequence number identifier.

[0121] The above steps ensure that the first parity block is stored in the target storage space during the first write. Thus, during the second write to the target wordline, the first parity block in the target storage space can be called, and the first parity block and the second written data block can be transferred to the target wordline. This design improves the efficiency and reliability of data writes.

[0122] In one embodiment, when writing to the target word line for the second time, calling the first check block in the target storage space, and transferring the first check block and the second written data block to the target word line includes:

[0123] Determine a target serial number identifier and a target storage space corresponding to the target serial number identifier according to a write instruction;

[0124] Set the checksum calculation flag to disabled;

[0125] Reading a first check block from a target storage space corresponding to the target sequence number identifier;

[0126] The first check block and the second written data block are transferred to the target word line.

[0127] In an embodiment of the present application, the target serial number identifier and the target storage space corresponding to the target serial number identifier are determined according to the write instruction: this means that the target storage space to be accessed can be determined according to the target serial number identifier in the write instruction. The check calculation flag is set to a disabled state: this means that there is no need to perform the step of calculating the check bit, and correspondingly, the target computing resource corresponding to the target serial number identifier will be set to an inactivated or unused state so that the target computing resource is not called. Then, data is read directly from the first check block previously written to the target storage space, and the first check block and the second written data block are transferred together to the target word line for subsequent processing or storage operations.

[0128] By performing the above operations, it is possible to call the first check block in the target storage space when writing to the target word line for the second time, no longer call the target computing resources to calculate the check block again when writing for the second time, and transfer the first check block and the data block written for the second time to the target word line. This can achieve efficient data writing operations between the processor and the quad-level cell flash memory, reducing the occupancy of the first storage module and the target computing resources.

[0129] In one embodiment, it further includes:

[0130] When writing to the target word line for the first time, determining whether the process of storing the first check block in the target storage space corresponding to the target serial number identifier is completed;

[0131] If it is determined that the process of storing the first check block in the target storage space corresponding to the target sequence number identifier is completed, the target sequence number identifier is released.

[0132] The present embodiment of the present invention ensures that after a write operation is completed, resources are correctly released and their status is correctly set, allowing for the correct execution of the next write operation. By determining whether the storage process is complete, it can be determined that the data block and check block have been successfully written to the target storage space corresponding to the target sequence number. Only in this case can the target sequence number be safely released for use in the next write operation.

[0133] This control measure ensures correct data writing and proper use of processor resources. By determining whether the storage process is complete, it can prevent the next write operation from occurring if the data has not been correctly written, thereby preventing data loss or errors. Furthermore, by releasing the target sequence number identifier, it ensures that the next write operation can correctly request new target storage space and the corresponding computing resources for the next write operation.

[0134] In one embodiment, releasing the target sequence number identifier includes:

[0135] Mark the target sequence number ID as unassigned.

[0136] In this embodiment, the target sequence number identifier is used to identify the binding relationship with the target storage space and the target computing resource. When a write operation is completed, releasing the target sequence number identifier can ensure that the identifier can be reused in subsequent write operations to improve system efficiency and resource utilization.

[0137] The steps for releasing the target sequence number identifier may include the following aspects:

[0138] Determine whether the storage of the first check block to the target storage space corresponding to the target sequence number identifier is complete. This step ensures that the data is correctly written and stored to prevent data loss or errors before the target sequence number identifier is released. If the data storage process is complete, the target sequence number identifier is released. This means that the identifier is marked as unallocated and can be reused in subsequent write operations. By releasing the target sequence number identifier, the system can continue to use it to bind other target storage spaces and target computing resources.

[0139] In summary, the embodiment of the present application describes a method for releasing a target sequence number identifier, which ensures the reusability of the target sequence number identifier to improve system efficiency and resource utilization.

[0140] In one embodiment, determining a target sequence number identifier and a target storage space corresponding to the target sequence number identifier according to a write instruction includes:

[0141] An unoccupied target serial number identifier and a target address of a target storage space corresponding to the target serial number identifier are determined according to the write instruction.

[0142] In the embodiment of the present application, the target address of the target storage space is determined, and then the first check block is stored at the target address. After the processor receives the write instruction, it first needs to determine an available target sequence number identifier and the corresponding target storage space. This can be accomplished by checking the occupancy status of all target sequence numbers and the corresponding target storage space. If there is an available target sequence number identifier and the corresponding target storage space, it can be allocated to the current write operation.

[0143] The target sequence number is a unique number used to identify the target storage space. It can be an integer, a string, or any other identifier. The target sequence number can be selected based on actual needs, for example, it can be assigned sequentially or generated using an algorithm.

[0144] The target storage space is the storage area used to store data and parity blocks. Each target storage space has a corresponding target address, which identifies the location of the storage space. The target address can be a physical address or a logical address, which can be used to locate the target storage space.

[0145] The purpose of the embodiments of the present application is to allocate an available target sequence number and corresponding target storage space during a write operation. This allocation ensures that each write operation has an independent target storage space, avoiding data confusion and conflicts. This ensures data integrity and reliability of the write operation, improving efficiency and performance during parallel processing on the processor.

[0146] In one embodiment, when writing to the target word line for the second time, calling the first check block in the target storage space, and transferring the first check block and the second written data block to the target word line includes:

[0147] Determine a target serial number identifier and a target storage space corresponding to the target serial number identifier according to a write instruction;

[0148] Apply for the target computing resource corresponding to the target serial number identifier and set the checksum calculation flag to the enabled state;

[0149] Calculate a second check block based on the second written data block using the target computing resource;

[0150] Reading a first check block from a target storage space corresponding to the target sequence number identifier;

[0151] The first check block or the second check block and the second written data block are transferred to the target word line.

[0152] In this embodiment, the step of calculating the check block is performed again when writing data to the target word line for the second time to achieve efficient and reliable operation. First, the target serial number identifier and the target storage space corresponding to the target serial number identifier are determined according to the write instruction; then, the target computing resource corresponding to the target serial number identifier is applied for, and the check calculation flag is set to the enabled state (which means that the step of calculating the check bit needs to be performed) so that the target computing resource can be used to calculate the second check block based on the data block written for the second time; after calculating the second check block, the first check block is read from the target storage space corresponding to the target serial number identifier; the first check block or the second check block and the data block written for the second time are transmitted to the target word line; by calculating the check block twice, the accuracy of the written data can be improved.

[0153] In the embodiment of the present application, the process of calculating the check block is performed during both writes to the target word line. Although this process occupies some computing resources, it improves the processor's writing efficiency and data integrity. In addition, because the calculation results (check blocks) are stored in the second storage module of the processor, the method of this embodiment can also reduce the resource usage of the first storage module of the processor (for example, the RAM in the processor).

[0154] In one embodiment, transferring the first parity block or the second parity block and the second written data block to the target word line includes:

[0155] A target parity block is determined in a preset manner according to the first parity block and the second parity block, and the data block and the target parity block written for the second time are transmitted to the target word line.

[0156] The purpose of the embodiments of the present application is to transfer a first check block or a second check block, and a second written data block, to a target word line, and to determine the target check block using a preset method. This preset method may be a pre-set encryption algorithm, checksum algorithm, or error correction code algorithm. The second written data block and the target check block are transferred together to the target word line to facilitate subsequent write and check operations.

[0157] In one embodiment, determining a target parity block using a preset method according to the first parity block and the second parity block, and transmitting the second-written data block and the target parity block to the target word line includes:

[0158] A target parity block is determined according to a comparison result between each data bit in the first parity block and each data bit in the second parity block, and the second written data block and the target parity block are transmitted to a target word line.

[0159] Optionally, the preset method mentioned in the above embodiment can be: comparing each data bit in the first check block with the corresponding data bit in the second check block to obtain a comparison result. These comparison results will be used to determine the target check block. The preset method can be to use a certain logical operation (such as logical AND, logical OR, logical XOR, etc.) to determine the target check block. Finally, after the target check block is determined, the data block and target check block written for the second time will be transmitted to the target word line, completing the second write operation to the target word line.

[0160] The advantage of this method is that by comparing the first and second check blocks and determining the target check block based on the comparison results, data reliability and integrity can be improved. By using a preset method, the target check block can be determined based on the comparison results more flexibly to adapt to different needs and situations.

[0161] In one embodiment, determining a target parity block based on a comparison result of each data bit in the first parity block and each data bit in the second parity block, and transmitting the second-written data block and the target parity block to a target word line includes:

[0162] The check block with a correct calculation result is determined according to each data bit in the first check block and each data bit in the second check block, and the check block with a correct calculation result and the second written data block are transmitted to the target word line.

[0163] Optionally, in an embodiment of the present application, the data bits of the first check block and the second check block are compared to determine the check block with a correct calculation result, and the check block with a correct calculation result and the data block written for the second time are transmitted to the target word line. For example, if the value of a data bit in the first check block and the second check block is the same, the bit is considered correct.

[0164] This method ensures the correctness of the data block and parity block transmitted in the target wordline, while improving the reliability and stability of data writing. By comparing data bits to determine the correct parity block, it avoids other complex calculations and simplifies the implementation of the data writing method and the design of the processor.

[0165] In one embodiment, determining a parity block with a correct calculation result based on each data bit in the first parity block and each data bit in the second parity block, and before transmitting the parity block with a correct calculation result and the second written data block to the target word line, the method further includes:

[0166] Determine whether the first check block and the second check block are the same;

[0167] If it is determined that the first check block and the second check block are the same, any one of the first check block and the second check block and the data block written for the second time are transmitted to the target word line;

[0168] If it is determined that the first check block and the second check block are different, the step of determining the check block with the correct calculation result based on each data bit in the first check block and each data bit in the second check block is entered, and the check block with the correct calculation result and the data block written for the second time are transmitted to the target word line.

[0169] Optionally, in an embodiment of the present application, it is determined whether the first check block and the second check block are identical. If it is determined that the first check block and the second check block are identical, any one of the first check block and the second check block is transmitted to the target word line together with the data block written for the second time. This is done because if the two check blocks are identical, it means that the first check block or the second check block is already one of the correct check blocks, and therefore it can be directly transmitted to the target word line. If the two check blocks are not identical, it is necessary to determine which check block the calculation result is correct based on the data bits in the first check block and the second check block.

[0170] Optionally, the correct check block is determined based on the comparison results of each data bit in the first check block and each data bit in the second check block. If the value of a data bit in the two check blocks is the same, the bit is considered correct; otherwise, it is considered incorrect. Based on this bit comparison result, the value of the check block that the calculation result is correct can be determined bit by bit. The method in the embodiment of the present application can effectively ensure the correctness and integrity of data and improve the reliability and dependability of data writing.

[0171] In one embodiment, after determining that the calculation result is a correct check block based on each data bit in the first check block and each data bit in the second check block, the method further includes:

[0172] If both the first check block and the second check block are erroneous check blocks, calculation error information is fed back.

[0173] Optionally, in the above embodiment, if both the first check block and the second check block are determined to be erroneous check blocks, this indicates a serious computational error during the data writing process. In this case, a step of providing feedback on the computational error information is provided. This can be achieved by sending the computational error information to the relevant processor or other system components. The computational error information may include relevant information such as the error type and error location to assist other components in fault diagnosis and repair.

[0174] In this way, calculation errors can be identified and processed in a timely manner during the writing process, thereby improving the reliability of data writing.

[0175] In one embodiment, after feeding back the calculation error information, the method further includes:

[0176] The space of the first check block stored in the target storage space is marked as invalid and cleared.

[0177] Optionally, in an embodiment, if both the first check block and the second check block are found to be erroneous during calculation, the system will take action. First, based on the location of the erroneous first check block, the storage space therein is marked as invalid. This means that the system will consider the data in this storage space to be untrustworthy and can no longer be used. Next, the system will perform a zero reset operation on the data in this storage space. The purpose of this step is to completely erase the erroneous data, ensuring that the storage space is clear and can be reused. In this way, the reliability and correctness of the data are ensured.

[0178] In one embodiment, after feeding back the calculation error information, the method further includes:

[0179] When a preset condition is met, data is rewritten to the target word line to calculate a third check block based on the currently written data block, and the third check block and the data block are transmitted to the target word line.

[0180] Optionally, after the system detects a calculation error, it rewrites the data block to the target wordline if a preset condition is met. The system then rewrites the data block to the target wordline to calculate a third parity block based on the currently written data block. This preset condition may be a period of time after the calculation error or after specific processing. By recalculating the third parity block and transferring it along with the data block to the target wordline, the system can correct the previous error and ensure data integrity and accuracy.

[0181] In summary, this method can effectively handle calculation errors and fix errors by recalculating and transmitting data blocks, thereby improving the reliability and accuracy of data writing.

[0182] In one embodiment, when writing to the target word line for the second time, after calling the first check block in the target storage space and transferring the first check block and the second written data block to the target word line, the method further includes:

[0183] Release the space in the target storage space for storing the first check block.

[0184] Optionally, after the second write to the target word line is completed, the storage space used to store the first check block can be released. This can free up more storage space for other data, improve storage space utilization efficiency, and provide a more efficient and flexible data writing method.

[0185] In one embodiment, releasing space in the target storage space for storing the first check block includes:

[0186] The data in the space for storing the first check block in the target storage space is marked as invalid and cleared.

[0187] Optionally, the data in the space for storing the first check block in the target storage space is marked as invalid. This means that the data is no longer considered valid and cannot be accessed or used. The space for storing the first check block in the target storage space is cleared. This means that the data in the space is deleted and set to its initial state. Through this operation, the space in the target storage space for storing the first check block can be effectively freed up. In this way, the space can be reused in subsequent data writing operations, thereby improving the utilization rate of storage resources. In addition, by marking the data in the space as invalid, the risk of misreading or misusing the data can be reduced. The clearing operation ensures that the space does not contain any old data, thereby ensuring the accuracy and reliability of subsequent write operations.

[0188] In one embodiment, before releasing the space in the target storage space for storing the first check block, the method further includes:

[0189] Determining whether transmission completion information fed back by the target word line is received;

[0190] If the transmission completion information is received, the process proceeds to a step of releasing the space in the target storage space for storing the first check block.

[0191] Optionally, before releasing, it is necessary to determine whether a transfer completion message has been received from the target word line. This is to ensure that the previous data write operation has completed. If the transfer completion message is received, proceed to the next step. If the transfer completion message is not received, it is necessary to wait or retry the data write to ensure the integrity of the data write.

[0192] That is, once the transfer completion information is received, the step of releasing the space in the target storage space used to store the first check block can be entered. The purpose of this step is to release the space previously used to store the first check block so that the space can be reused when data is written next time.

[0193] As shown in FIG3 , in an optional embodiment, the data writing method includes the following steps:

[0194] First, N target storage spaces are requested from the second storage module, where N is the number of computing resources in the processor. The serial number identifier of each computing resource is bound to the corresponding target storage space. A write instruction is obtained, and the write instruction is used to determine whether it is the first or second write. If it is the first write, a serial number identifier is requested, and the check calculation flag is set to an enabled state. This allows the processor to use the computing resources to calculate the first check bit based on the first write data based on the enabled check calculation flag. The first check bit is written to the target storage space. Feedback is provided indicating that the first check bit has been written, and the serial number identifier is released. If it is the second write, a serial number identifier is not requested, and the check calculation flag is set to a disabled state. The first check bit is read from the target storage space, and the first check bit and the second write data are written to the target word line.

[0195] This application distinguishes between two writing processes. After performing the check bit calculation for the first time and storing the first check bit in the target storage space, there is no need to apply for computing resources to implement the check bit calculation during the second writing, thereby saving the first storage module in the processor and the resources of the processor, and can release the first storage module faster, thereby improving the write bandwidth, which is also of great help to improve product performance.

[0196] In order to better understand the data writing method in the embodiment of the present application, the data writing method in the embodiment of the present application is explained and illustrated in combination with optional embodiments below, which can be applied to but not limited to the embodiment of the present application.

[0197] FIG4 is a schematic diagram of an optional data writing architecture according to an embodiment of the present application. As shown in FIG4 , the processor may include, but is not limited to, a first storage module and a second storage module. The first storage module and the second storage module may include, but are not limited to, independent storage spaces in the processor. As an optional example, the processor may include, but is not limited to, a CPU (Central Processing Unit). The first storage module may be used to store, but is not limited to, the original data of the word line to be processed and written. The second storage module may be used to store, but is not limited to, the data obtained by the processor after calculating the original data. For example, the first storage module includes a DDR (Double Data Rate) memory, an SRAM (Synchronous Dynamic Random Access Memory), or a RAM, and the second storage module includes a DDR, an SRAM, or a RAM. The data obtained by the processor after calculating the original data may include, but is not limited to, a check block. The check block may be used to verify whether the data obtained after calculating the original data is accurate.

[0198] Quad-Level Cell (QLC) flash memory is a NAND flash memory technology used in storage devices. In NAND flash memory, each memory cell can store different levels of charge. Data is stored by changing the charge state within the memory cell, thereby storing different numbers of bits of information. A characteristic of QLC flash memory is that each memory cell can store 4 bits of information. Compared to SLC (Single-Level Cell) NAND Flash, MLC (Multi-Level Cell) NAND Flash, and TCL NAND Flash, QLC flash memory has a higher storage density. Storage density refers to the number of bits of data that can be stored in each memory cell in a flash memory cell. For example, each memory cell in QLC flash memory stores 4 bits of data (i.e., 00, 01, 10, 11), while each memory cell in SLC NAND Flash stores 1 bit of data, each memory cell in MLC NAND Flash stores 2 bits of data, and each memory cell in TCL NAND Flash stores 3 bits of data.

[0199] A quad-level cell flash memory includes a storage area for storing data. A portion of the storage area in the quad-level cell flash memory is divided into a word line. For example, the storage area in the quad-level cell flash memory is divided into word line 1 to word line n, where n is a positive integer greater than or equal to 1. Each word line may include, but is not limited to, a storage area of ​​the same size in the quad-level cell flash memory. For example, if the quad-level cell flash memory includes a 20MB storage area, each word line may include, but is not limited to, a storage area of ​​48KB within the 20MB. A word line includes one or more memory cells.

[0200] The target word line includes a word line in the quad-level cell flash memory to which the data to be written is to be written. For example, the storage area in the quad-level cell flash memory is divided into word line 1 to word line n, and the target word line is word line 4 among word lines 1 to word line n. The data writing method in the embodiment of the present application can be implemented by, but is not limited to, the following steps:

[0201] Step 1: Obtain a write instruction, wherein the write instruction is used to request to write the original data 1 into the word line 4;

[0202] Step 2: The processor may, but is not limited to, first store the original data 1 into the first storage module;

[0203] Step 3: The processor extracts original data 1 from the first storage module, performs calculations on original data 1, obtains calculated data 2, and stores data 2 in the second storage module. Data 2 may include, but is not limited to, a check block. For example, the processor may encrypt original data 1 according to, but is not limited to, an encryption algorithm to obtain data 2. For example, the encryption algorithm may include, but is not limited to, an XOR algorithm.

[0204] It should be noted that the original data 1 may not be allowed to be written into the quad-level cell flash memory. In this case, the processor can, but is not limited to, calculate (for example, encrypt) the original data 1 so that the data 2 obtained after the calculation is allowed to be written into the quad-level cell flash memory.

[0205] Step 4: Write data 2 into word line 4 for the first time;

[0206] Step 5: After data 1 is written into word line 4, data 2 is written into word line 4 for the second time.

[0207] It should be noted that when data 2 is first written to word line 4, data writing errors may occur. For example, before writing to word line 4, part of data 2 is 1, and after writing to word line 4, the data that should have been 1 becomes 2. In this case, data 2 can be written to word line 4 again, but is not limited to ensuring data accuracy. Furthermore, when writing data 2 to word line 4 for the second time, there is no need to recalculate the original data 1, thereby improving data writing efficiency.

[0208] To solve the above technical problems, the present application further provides a data writing system, as shown in FIG5 , in which a processor includes a first storage module and a second storage module, and the processor is configured to write data to a quad-level cell flash memory. The system includes:

[0209] The space application unit 51 is configured to apply for target storage space from the second storage module when the quad-level unit flash memory is powered on. The second storage module is a storage module independent of the first storage module.

[0210] The first writing unit 52 is configured to calculate a first check block based on the data block written for the first time when writing to the target word line for the first time, transfer the first check block and the data block to the target word line, and store the first check block in the target storage space;

[0211] The second writing unit 53 is configured to call the first check block in the target storage space when writing to the target word line for the second time, and transfer the first check block and the second written data block to the target word line.

[0212] In one embodiment, when the processor can process N write operations in parallel, where N is an integer greater than 2, the method further includes:

[0213] an identification setting unit configured to divide the computing resources of the processor into N parts and set a corresponding serial number identification for each computing resource;

[0214] The space application unit 51 is configured to apply for N target storage spaces from the second storage module when the quad-level unit flash memory is powered on; and bind the N target storage spaces to N computing resources in a one-to-one correspondence.

[0215] In one embodiment, it further includes:

[0216] An instruction acquisition unit is configured to acquire a write instruction and determine whether to write to the target word line for the first time or the second time according to the write instruction;

[0217] If it is the first time to write to the target word line, the signal is transmitted to the first writing unit 52;

[0218] If it is the second time to write to the target word line, the signal is transmitted to the second writing unit 53 .

[0219] In one embodiment, the first writing unit 52 includes:

[0220] a space determining unit configured to determine a target serial number identifier and a target storage space corresponding to the target serial number identifier according to a write instruction;

[0221] An enabling setting unit is configured to apply for a target computing resource corresponding to the target serial number identifier and set the target computing resource to an enabled state;

[0222] A first computing unit is configured to use a target computing resource in an enabled state to calculate a first check block according to a first written data block;

[0223] The first storage unit is configured to store the first check block in a target storage space corresponding to the target sequence number identifier.

[0224] In one embodiment, the second writing unit 53 includes:

[0225] a space determining unit configured to determine a target serial number identifier and a target storage space corresponding to the target serial number identifier according to a write instruction;

[0226] a disabled setting unit configured to set the target computing resource corresponding to the target sequence number identifier to a disabled state;

[0227] a reading unit, configured to read a first check block from a target storage space corresponding to the target sequence number identifier;

[0228] The third writing unit is configured to transfer the first check block and the second written data block to the target word line.

[0229] In one embodiment, it further includes:

[0230] a first judging unit configured to judge whether a process of storing the first check block in a target storage space corresponding to the target sequence number identifier is completed when writing to the target word line for the first time;

[0231] The first execution unit is configured to connect to the disabling setting unit when determining that the process of storing the first check block in the target storage space corresponding to the target sequence number identifier is completed;

[0232] The first releasing unit is configured to release the target sequence number identifier.

[0233] In one embodiment, the first release unit is configured to mark the target sequence number as being in an unallocated state.

[0234] In one embodiment, the space determination unit is configured to determine an unoccupied target sequence number identifier and a target address of a target storage space corresponding to the target sequence number identifier according to the write instruction.

[0235] In one embodiment, the second writing unit 53 includes:

[0236] A space determining unit, wherein the user determines a target serial number identifier and a target storage space corresponding to the target serial number identifier according to a write instruction;

[0237] An enabling setting unit is configured to apply for a target computing resource corresponding to the target serial number identifier and set the target computing resource to an enabled state;

[0238] A second computing unit is configured to use the target computing resource in an enabled state to calculate a second check block according to the second written data block;

[0239] a reading unit, configured to read a first check block from a target storage space corresponding to the target sequence number identifier;

[0240] The fourth writing unit is configured to transfer the first check block or the second check block and the second written data block to the target word line.

[0241] In one embodiment, the fourth writing unit is configured to determine a target parity block using a preset method according to the first parity block and the second parity block, and transmit the second written data block and the target parity block to the target word line.

[0242] In one embodiment, the fourth writing unit is configured to determine the target check block based on the comparison results of each data bit in the first check block and each data bit in the second check block, and transmit the second written data block and the target check block to the target word line.

[0243] In one embodiment, the fourth write unit is configured to determine a check block with a correct calculation result based on each data bit in the first check block and each data bit in the second check block, and transmit the check block with a correct calculation result and the data block written for the second time to the target word line.

[0244] In one embodiment, it further includes:

[0245] A second judgment unit is configured to judge whether the first check block and the second check block are identical;

[0246] The second execution unit is configured to transmit any one of the first and second check blocks and the second written data block to a target word line when it is determined that the first check block and the second check block are identical;

[0247] The third execution unit is configured to connect to the fourth writing unit when it is determined that the first check block and the second check block are different.

[0248] In one embodiment, it further includes:

[0249] The error feedback unit is configured to feed back calculation error information when it is determined that both the first check block and the second check block are erroneous check blocks.

[0250] In one embodiment, it further includes:

[0251] The space clearing unit is configured to mark the space of the first check block stored in the target storage space as invalid and clear it.

[0252] In one embodiment, it further includes:

[0253] The rewriting unit is configured to rewrite data to the target word line when a preset condition is met, calculate a third check block based on the currently written data block, and transmit the third check block and the data block to the target word line.

[0254] In one embodiment, it further includes:

[0255] The space releasing unit is configured to release the space in the target storage space for storing the first check block.

[0256] In one embodiment, the space releasing unit is configured to mark the data in the space for storing the first check block in the target storage space as invalid and clear it to zero.

[0257] In one embodiment, it further includes:

[0258] a third judging unit, configured to judge whether transmission completion information fed back by the target word line is received;

[0259] The fourth execution unit is configured to connect to the space release unit upon receiving the transmission completion information.

[0260] For an introduction to the data writing system, please refer to the above embodiments, which will not be described in detail in this application.

[0261] To solve the above technical problems, the present application further provides a data writing device, as shown in FIG6 , comprising:

[0262] Memory 61, configured to store computer programs;

[0263] The processor 62 is configured to implement the steps of the above-mentioned data writing method when executing the computer program.

[0264] For the introduction of the data writing device, please refer to the above embodiments, and this application will not go into details here.

[0265] To solve the above technical problems, the present application also provides a computer non-volatile readable storage medium 71. As shown in FIG7 , the computer non-volatile readable storage medium 71 stores a computer program 72. When the computer program 72 is executed by the processor, the steps of the data writing method described above are implemented.

[0266] For an introduction to the computer non-volatile readable storage medium, please refer to the above embodiments, and this application will not go into details here.

[0267] To solve the above technical problems, the present application further provides a quad-level cell flash memory, wherein the processor includes a first storage module and a second storage module, such as the processor in the above-mentioned data writing device, and is used to write data to the quad-level cell flash memory. For an introduction to the quad-level cell flash memory, please refer to the above-mentioned embodiment, and this application will not repeat it here.

[0268] It should also be noted that, in this specification, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0269] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A data writing method, characterized in that: Applied to a processor, the processor includes a first storage module and a second storage module, the processor is configured to write data to a quad-level cell flash memory, the method includes: When the quad-level cell flash memory is powered on, applying for a target storage space from the second storage module, the second storage module being a storage module independent of the first storage module; When writing to the target word line for the first time, calculating a first check block according to the data block written for the first time, transmitting the first check block and the data block to the target word line, and storing the first check block in the target storage space; When writing to the target word line for the second time, the first check block in the target storage space is called, and the first check block and the data block written for the second time are transmitted to the target word line.

2. The data writing method according to claim 1, characterized in that: When the processor can process N write operations in parallel, N is an integer greater than 2, the method further includes: Divide the computing resources of the processor into N parts, and set a corresponding serial number identifier for each computing resource; When the quad-level cell flash memory is powered on, applying for a target storage space from the second storage module includes: When the quad-level unit flash memory is powered on, applying for N target storage spaces from the second storage module; The N target storage spaces are bound to the N computing resources in a one-to-one correspondence.

3. The data writing method according to claim 2, characterized in that: Also includes: Obtaining a write instruction, and determining whether to write to the target word line for the first time or for the second time according to the write instruction; If it is the first time to write to the target word line, then entering the step of calculating a first check block according to the data block written for the first time when writing to the target word line for the first time, transmitting the first check block and the data block to the target word line, and storing the first check block in the target storage space; If the target word line is written for the second time, the step of calling the first check block in the target storage space when writing to the target word line for the second time and transferring the first check block and the second written data block to the target word line is entered.

4. The data writing method according to claim 3, characterized in that: When writing to a target word line for the first time, calculating a first check block according to a data block written for the first time, transmitting the first check block and the data block to the target word line, and storing the first check block in the target storage space, comprises: Determine a target serial number identifier and a target storage space corresponding to the target serial number identifier according to the write instruction; Apply for the target computing resource corresponding to the target serial number identifier, and set the verification computing flag bit to an enabled state; Calculate the first check block according to the data block written for the first time using the target computing resource; The first check block is stored in a target storage space corresponding to the target sequence number identifier.

5. The data writing method according to claim 3, characterized in that: When writing to the target word line for the second time, calling the first check block in the target storage space, and transmitting the first check block and the second written data block to the target word line, comprises: Determine a target serial number identifier and a target storage space corresponding to the target serial number identifier according to the write instruction, and set a checksum calculation flag bit to a disabled state; Reading the first check block from the target storage space corresponding to the target sequence number identifier; The first check block and the second written data block are transmitted to the target word line.

6. The data writing method according to claim 5, characterized in that: Also includes: When writing to the target word line for the first time, determining whether a process of storing the first check block in a target storage space corresponding to the target serial number identifier is completed; If it is determined that the process of storing the first check block in the target storage space corresponding to the target sequence number identifier is completed, the target sequence number identifier is released.

7. The data writing method according to claim 6, characterized in that: Releasing the target sequence number identifier includes: The target sequence number identifier is marked as unassigned.

8. The data writing method according to claim 4, characterized in that: Determining a target serial number identifier and a target storage space corresponding to the target serial number identifier according to the write instruction includes: An unoccupied target serial number identifier and a target address of a target storage space corresponding to the target serial number identifier are determined according to the write instruction.

9. The data writing method according to claim 3, characterized in that: When writing to the target word line for the second time, calling the first check block in the target storage space, and transmitting the first check block and the second written data block to the target word line, comprises: Determine a target serial number identifier and a target storage space corresponding to the target serial number identifier according to the write instruction; Apply for the target computing resource corresponding to the target serial number identifier, and set the verification computing flag bit to an enabled state; Calculate a second check block according to the second written data block using the target computing resource; Reading the first check block from the target storage space corresponding to the target sequence number identifier; The first check block or the second check block and the second written data block are transmitted to the target word line.

10. The data writing method according to claim 9, characterized in that: The first check block or the second check block and the second written data block are transmitted to the target word line, comprising: A target check block is determined in a preset manner according to the first check block and the second check block, and the data block written for the second time and the target check block are transmitted to the target word line.

11. The data writing method according to claim 10, characterized in that: Determining a target check block in a preset manner according to the first check block and the second check block, and transmitting the second written data block and the target check block to the target word line, comprising: The target check block is determined according to the comparison result of each data bit in the first check block and each data bit in the second check block, and the second written data block and the target check block are transmitted to the target word line.

12. The data writing method according to claim 11, characterized in that: Determining the target check block according to the comparison result of each data bit in the first check block and each data bit in the second check block, and transmitting the second written data block and the target check block to the target word line, including: A check block with a correct calculation result is determined according to each data bit in the first check block and each data bit in the second check block, and the check block with a correct calculation result and the second written data block are transmitted to the target word line.

13. The data writing method according to claim 12, characterized in that: The method further includes: determining a check block with a correct calculation result according to each data bit in the first check block and each data bit in the second check block, and transmitting the check block with a correct calculation result and the second written data block to the target word line. Determining whether the first check block and the second check block are the same; If it is determined that the first check block and the second check block are the same, transmitting any one of the first check block and the second check block and the second written data block to the target word line; If it is determined that the first check block and the second check block are not the same, the step of determining the check block with the correct calculation result according to each data bit in the first check block and each data bit in the second check block is entered, and the check block with the correct calculation result and the data block written for the second time are transmitted to the target word line.

14. The data writing method according to claim 12, characterized in that: After determining that the calculation result is a correct check block according to each data bit in the first check block and each data bit in the second check block, the method further includes: If both the first check block and the second check block are erroneous check blocks, calculation error information is fed back.

15. The data writing method according to claim 14, characterized in that: After the calculation error information is fed back, it also includes: The space of the first check block stored in the target storage space is marked as invalid and cleared.

16. The data writing method according to claim 14, characterized in that: After the calculation error information is fed back, it also includes: When a preset condition is met, the data block is rewritten to the target word line to calculate a third check block according to the currently written data block, and the third check block and the data block are transmitted to the target word line.

17. The data writing method according to any one of claims 1 to 16, characterized in that: When writing to the target word line for the second time, after calling the first check block in the target storage space and transferring the first check block and the second written data block to the target word line, the method further includes: Release the space in the target storage space used to store the first check block.

18. The data writing method according to claim 17, characterized in that: Releasing space in the target storage space for storing the first check block includes: The data in the space in the target storage space used to store the first check block is marked as invalid and cleared.

19. The data writing method according to claim 18, characterized in that: Before releasing the space in the target storage space for storing the first check block, the method further includes: Determining whether transmission completion information fed back by the target word line is received; If the transmission completion information is received, the process proceeds to a step of releasing the space in the target storage space for storing the first check block.

20. The data writing method according to claim 3, characterized in that: Calculating a first check block according to a data block written for the first time, transmitting the first check block and the data block to the target word line, and storing the first check block in the target storage space, comprises: According to the write instruction, the check calculation flag is set to an enabled state, a target storage space and a target computing resource are applied for, the target computing resource is used to calculate the first check block according to the data block written for the first time, and the first check block is stored in the target storage space.

21. The data writing method according to claim 3, characterized in that: Calling the first check block in the target storage space, and transmitting the first check block and the second written data block to the target word line, comprises: The check calculation flag is set to a disabled state according to the write instruction, the first check block is read from the target storage space, and the first check block and the second written data block are transmitted to the target word line.

22. A data writing system, characterized in that: Applied to a processor, the processor includes a first storage module and a second storage module, the processor is configured to write data to a quad-level cell flash memory, and the system includes: a space application unit, configured to apply for a target storage space from the second storage module when the quad-level unit flash memory is powered on, the second storage module being a storage module independent of the first storage module; A first writing unit is configured to calculate a first check block according to a data block written for the first time when writing to a target word line for the first time, transmit the first check block and the data block to the target word line, and store the first check block in the target storage space; The second writing unit is configured to call the first check block in the target storage space when writing to the target word line for the second time, and transfer the first check block and the second written data block to the target word line.

23. A data writing device, characterized in that: include: a memory arranged to store a computer program; A processor is configured to implement the steps of the data writing method as described in any one of claims 1 to 18 when executing a computer program.

24. A computer non-volatile readable storage medium, characterized in that: The computer non-volatile readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the data writing method according to any one of claims 1 to 21 are implemented.

25. A quad-level cell flash memory, characterized in that: The processor includes a first storage module and a second storage module, and the processor in the data writing device as described in claim 23 is used to write data to the quad-level cell flash memory.

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