Semiconductor device

Abstract

The present invention is provided with a field effect transistor on an insulating surface and an interlayer insulating film covering the field effect transistor. The field effect transistor includes a source region of a first conductivity type, a body region of a second conductivity type, a drift region of the first conductivity type, a drain region of the first conductivity type, and a gate electrode. A field plate connected to the source region is disposed on the interlayer insulating film. The source region and the drift region are disposed at positions sandwiching the body region in a second direction, and the drain region is disposed at a position farther than the drift region when viewed from the body region. The field effect transistor further includes a body contact region of the second conductivity type protruding to the source region side from a body contact connection section, which is a part of the edge of the body region on the source region side. In a plan view, the field plate extends from the source region to at least the drift region, and does not overlap a half line extending in the second direction from the midpoint of the body contact connection section toward the drain region.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] Field-effect transistors (FETs) formed on silicon-on-insulator substrates (SOI substrates) are used in power amplifiers and high-frequency switches for communication devices such as smartphones. When using FETs in high-frequency power amplifiers, the breakdown voltage becomes an issue. To increase the breakdown voltage of FETs, a structure is known in which a drift region is provided to alleviate electric field concentration between the gate and drain (see Patent Document 1). MOSFETs with such a structure are called, for example, extended-drain MOS (EDMOS).

[0003] On the other hand, another known structure for reducing the electric field concentration between the gate and drain is a structure in which a conductive overhang called a field plate is provided above the gate electrode (see Patent Document 1). This structure is also widely known in FETs that use substrates other than SOI substrates, such as GaAs and GaN. A typical field plate is connected to a region at ground potential, such as the source region.

[0004] US Patent Application Publication No. 2022 / 0059665

[0005] A field plate is a technology that improves breakdown voltage by reducing the electric field concentration between the gate and drain. However, when a field plate connected to the source region is placed above the gate electrode, the parasitic capacitance between the gate and source increases. This increase in parasitic capacitance between the gate and source poses a new challenge for FETs used in high-frequency applications.

[0006] An object of the present invention is to provide a semiconductor device that is provided with a field plate and is capable of suppressing an increase in parasitic capacitance between the gate and the source.

[0007] According to one aspect of the present invention, there is provided a field effect transistor disposed on an insulating surface, an interlayer insulating film covering the field effect transistor, and a conductive field plate disposed on the interlayer insulating film, wherein the field effect transistor includes a source region of a first conductivity type, a body region of a second conductivity type, a drift region of the first conductivity type, a drain region of the first conductivity type, and a gate electrode, wherein, in a plan view of the insulating surface, the gate electrode has a shape elongated in a first direction, and the body region is disposed below the gate electrode so as to overlap with the gate electrode, the source region and the drift region are disposed at positions sandwiching the body region in a second direction perpendicular to the first direction, and the drain region is disposed at a position farther from the body region than the drift region, and the field effect transistor further includes a body contact region of the second conductivity type protruding from a body contact connection portion which is a part of the body region on the source region side toward a side on which the source region is disposed, and the field plate is electrically connected to the source region, A semiconductor device is provided in which, when the insulating surface is viewed in a plane, the field plate has a shape that extends from the source region, intersects the gate electrode, and extends at least to the drift region, and does not overlap a first ray that extends in the second direction from the midpoint of the body contact connection point toward the drain region.

[0008] By forming the field plate in a shape that does not overlap with the first ray mentioned above, it is possible to suppress an increase in parasitic capacitance between the gate and the source.

[0009] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. FIGS. 2A and 2B are cross-sectional views taken along dashed dotted lines 2A-2A and 2B-2B in FIG. 1, respectively. FIG. 3 is a diagram showing the positional relationships in a plan view of a body contact region, gate electrode, field plate, and the like of an FET. FIGS. 4A and 4B are cross-sectional views of a semiconductor device according to a first embodiment at an intermediate stage in its manufacture. FIGS. 5A and 5B are cross-sectional views of a semiconductor device according to a first embodiment at an intermediate stage in its manufacture. FIG. 6 is a cross-sectional view of a semiconductor device according to a first embodiment at an intermediate stage in its manufacture. FIGS. 7A and 7B are cross-sectional views of a semiconductor device according to a modification of the first embodiment. FIG. 8 is a plan view of a semiconductor device according to another modification of the first embodiment. FIG. 9 is a plan view of a semiconductor device according to yet another modification of the first embodiment. FIG. 10 is a plan view of a semiconductor device according to yet another modification of the first embodiment. FIG. 11 is a plan view of a semiconductor device according to a second embodiment. FIG. 12 is a cross-sectional view taken along dashed dotted line 12-12 in FIG. 11. FIG. 13 is a plan view of a semiconductor device according to a third embodiment. FIG. 14 is a diagram showing the positional relationship in plan view of one of the gate electrode protrusions of the semiconductor device according to the third embodiment, and the gate electrode, field plate, etc. in the vicinity thereof.

[0010] First Embodiment A semiconductor device according to a first embodiment will be described with reference to FIGS. 1 to 6. FIG. 1 is a plan view of the semiconductor device according to the first embodiment. An N-type source region 20S, a P-type body region 20B, an N-type drift region 20DR, an N-type drain region 20D, and P-type body contact regions 20BC1 and 20BC2 constituting an FET 20 are formed in an active region 10CA of a device layer 10C (FIGS. 2A and 2B) of an SOI substrate 10 (described later). The donor concentration of the drift region 20DR is lower than the donor concentration of the drain region 20D. The acceptor concentration of the body contact region 20BC1 is equal to the acceptor concentration of the body region 20B. The acceptor concentration of the body contact region 20BC2 is higher than the acceptor concentration of the body contact region 20BC1.

[0011] The gate electrode 20G is disposed so as to substantially overlap the body region 20B in plan view, and the gate electrode protrusion 20GP is disposed so as to substantially overlap the body contact region 20BC1. The width (dimension in the gate length direction) of the body region 20B may be narrower than the width (dimension in the gate length direction) of the gate electrode 20G.

[0012] The gate electrode 20G has a shape that is elongated in one direction in a plan view, extending from one side of the rectangular active region 10CA to the opposite side. An xyz Cartesian coordinate system is defined within the surface of the device layer, with the longitudinal direction of the gate electrode 20G being the y direction and the direction perpendicular to it being the x direction. The body region 20B, like the gate electrode 20G, has a shape that is elongated in the y direction. The source region 20S and the drift region 20DR are positioned on either side of the body region 20B in the x direction. The drain region 20D is positioned farther from the body region 20B than the drift region 20DR and is in contact with the drift region 20DR.

[0013] The body contact region 20BC1 protrudes from a body contact connection point 24, which is a part of the edge of the body region 20B on the source region 20S side, in parallel to the x-axis toward the side where the source region 20S is arranged.

[0014] In a plan view, a conductive field plate 40 extends from a position overlapping with the source region 20S, intersecting the gate electrode 20G and the drift region 20DR, to a position overlapping with the drain region 20D. The field plate 40 is hatched in Figure 1. The field plate 40 is separated into two parts by a line that passes through the body contact connection point 24 and is parallel to the x-axis.

[0015] In a plan view, the body contact region 20BC2 is disposed in the source region 20S. The body contact region 20BC2 is in contact with the body contact region 20BC1 and is electrically connected to the body region 20B only via the P-type region.

[0016] A plurality of vias 41 are arranged in the region where the source region 20S and the field plate 40 overlap. The field plate 40 is electrically connected to the source region 20S through the plurality of vias 41. The source region 20S is usually supplied with a ground potential. Therefore, the field plate 40 is also supplied with a ground potential.

[0017] 2A and 2B are cross-sectional views taken along dashed dotted lines 2A-2A and 2B-2B in FIG. 1, respectively. The SOI substrate 10 includes a support substrate 10A, a buried oxide film 10B, and a device layer 10C. The upper surface of the buried oxide film 10B is referred to as the insulating surface. The FET 20 is disposed on the insulating surface. As an example, the support substrate 10A is formed of high-resistivity Si, and the buried oxide film 10B is formed of silicon oxide. The device layer 10C is formed of Si and has a thickness of, for example, 75 nm.

[0018] The FET 20 includes an N-type source region 20S, a P-type body region 20B, an N-type drift region 20DR, an N-type drain region 20D, and P-type body contact regions 20BC1 and 20BC2, which are arranged in a device layer 10C, and further includes a gate insulating film 20GI, a gate electrode 20G, a gate electrode protrusion 20GP, a gate upper insulating film 20T, a gate side insulating film 20I, and a sidewall spacer 20SW, which are arranged on the device layer.

[0019] The source region 20S, drift region 20DR, and drain region 20D extend from the upper surface of the device layer 10C to the interface between the device layer 10C and the buried oxide film 10B. The body region 20B is disposed directly below the gate electrode 20G. The source region 20S and drift region 20DR sandwich the body region 20B in the x-direction. An N-type source extension region 20SE is disposed between the source region 20S and the body region 20B in the surface layer portion of the device layer 10C.

[0020] A silicide film 25 is disposed on a portion of the upper surface of the gate electrode 20G, and the remaining portion is covered by a gate upper insulating film 20T. A gate side insulating film 20I covers the side surfaces of the structure including the gate electrode 20G, gate electrode protrusion 20GP, gate insulating film 20GI, gate upper insulating film 20T, and silicide film 25 on the gate electrode 20G, and sidewall spacers 20SW cover the side surfaces of the gate side insulating film 20I. The gate electrode 20G and gate electrode protrusion 20GP are formed of, for example, polysilicon. The gate insulating film 20GI is formed of, for example, silicon oxide and has a thickness of approximately 6 nm. The gate side insulating film 20I and gate upper insulating film 20T are formed of, for example, silicon oxide, and the sidewall spacers 20SW are formed of, for example, silicon nitride.

[0021] The drift region 20DR extends from a region outside the sidewall spacers 20SW, passes below the sidewall spacers 20SW, and reaches the side surface of the gate electrode 20G. In the cross section shown in Figure 2A, the source region 20S is disposed outside the sidewall spacers 20SW, and the source extension region 20SE is disposed below the sidewall spacers 20SW. The drift region 20DR may be formed beyond the side surface of the gate electrode 20G and reach directly below the gate electrode 20G.

[0022] 2B , the body contact region 20BC2 extends from a region outside the sidewall spacer 20SW, passes below the sidewall spacer 20SW, and reaches the tip of the gate electrode protrusion 20GP. The body contact region 20BC2 is in contact with the body contact region 20BC1 immediately below the gate electrode protrusion 20GP, and is electrically connected to the body region 20B via the body contact region 20BC1.

[0023] A silicide film 25 is disposed on the upper surfaces of the source region 20S, the body contact region 20BC2, and the drain region 20D. A first-layer interlayer insulating film 31 is disposed on the device layer 10C so as to cover the FET 20. A first-layer of vias 41 connected to the silicide film 25 on the source region 20S are disposed in the interlayer insulating film 31. A field plate 40 is disposed on the interlayer insulating film 31. The field plate 40 is connected to the source region 20S and the body contact region 20BC2 via the plurality of vias 41 and the silicide film 25. The field plate 40 extends from above the source region 20S, passing above the gate electrode 20G and the drift region 20DR, to above the drain region 20D.

[0024] 2A, the silicide film 25 provided on the upper surface of the drain region 20D extends from an inner region of the upper surface of the drain region 20D to the boundary line between the drift region 20DR and the drain region 20D, but the silicide film 25 does not have to extend to the boundary line between the drift region DR and the drain region 20D. In other words, the silicide film 25 may be formed in a partial region of the upper surface of the drain region 20D.

[0025] A second interlayer insulating film 32 is disposed on the interlayer insulating film 31 and the field plate 40. A plurality of second-layer vias 46 are disposed in the interlayer insulating film 32. A source wiring 45 is disposed on the interlayer insulating film 32. The source wiring 45 is connected to the source region 20S via the plurality of vias 46, the field plate 40, the plurality of vias 41, and the silicide film 25.

[0026] The interlayer insulating films 31 and 32 are made of an insulating inorganic material, such as silicon oxide or silicon nitride. The vias 41 and 46 are made of a metal, such as tungsten or copper, or an alloy containing these metals as a main component. The field plate 40 and the source wiring 45 are made of a metal, such as tungsten, copper, or aluminum, or an alloy containing these metals as a main component.

[0027] Next, with reference to FIG. 3, the positional relationship between the body contact region 20BC1 and the field plate 40 in a plan view will be described.

[0028] 3 is a diagram showing the positional relationship in a plan view of the body contact region 20BC1, gate electrode 20G, field plate 40, etc. of the FET 20. In Fig. 3, the field plate 40 is hatched. The source region 20S, body region 20B, drift region 20DR, and drain region 20D are arranged in this order in the x direction.

[0029] A gate electrode protrusion 20GP extends from a portion of the edge of the gate electrode 20G parallel to the y-direction on the source region 20S side toward the region where the source region 20S is disposed. The body region 20B is disposed so as to substantially overlap with the gate electrode 20G, and the body contact region 20BC1 is disposed so as to substantially overlap with the gate electrode protrusion 20GP. That is, the body contact region 20BC1 extends from a body contact connection point 24, which is a portion of the edge of the body region 20B elongated in the y-direction on the source region 20S side, toward the side where the source region 20S is disposed. The body contact region 20BC1 is a region of the same conductivity type as the body region 20B, and the dimension of the body contact region 20BC1 in the y-direction is smaller than the dimension of the body region 20B in the y-direction.

[0030] 3, the body contact connection point 24 is represented by a thick solid line. Although the body contact connection point 24 is represented by a thick line segment in FIG. 3, the body contact connection point 24 is not directly observed as a line segment. For example, the body contact connection point 24 can be considered to be a virtual boundary line between the body region 20B and the body contact region 20BC1. For example, the x-direction position of the body contact connection point 24 can be considered to coincide with the x-direction position where the y-direction dimension of the p-type region that constitutes the body region 20B and the body contact region 20BC1 changes. The body contact connection point 24 substantially coincides with a virtual boundary line between the gate electrode 20G and the gate electrode protrusion 20GP.

[0031] The field plate 40 is arranged so as not to overlap with an imaginary half line HL that extends in a direction parallel to the x direction from the midpoint C of the body contact connection point 24 toward the drain region 20D. For example, the field plate 40 is composed of two parts that are separated in the y direction at the position of the half line HL. The distance in the y direction from the half line HL to the field plate 40 is denoted as W.

[0032] When the FET 20 is operated, electrons e － travels from the source region 20S through the body region 20B and the drift region 20DR to the drain region 20D. In the range of the body contact connection point 24 in the y direction, the source region 20S is not in contact with the body region 20B, so electrons e － is not injected.

[0033] Next, a method for manufacturing a semiconductor device according to the first embodiment will be described with reference to Figures 4A to 6. Figures 4A to 6 are cross-sectional views of the semiconductor device according to the first embodiment at intermediate stages in its manufacture.

[0034] 4A, an SOI substrate 10 is prepared, which includes a support substrate 10A, a buried oxide film 10B, and a device layer 10C. After an element isolation region (not shown) is formed in the device layer 10C, a P-type dopant such as boron is implanted into the device layer 10C to form a body region 20B and a body contact region 20BC1.

[0035] Then, an oxidation process is performed to form a silicon oxide film that will become the gate insulating film 20GI over the entire surface of the device layer 10C. Furthermore, a polysilicon film that will become the gate electrode 20G and the gate electrode protrusion 20GP is deposited, and an N-type dopant is implanted into the polysilicon film. Then, a silicon oxide film that will become the gate upper insulating film 20T is deposited by CVD or the like. The three layers of the silicon oxide film, polysilicon film, and silicon oxide film are patterned. Through these steps, the gate insulating film 20GI, the gate electrode 20G, the gate electrode protrusion 20GP, and the gate upper insulating film 20T are obtained. Then, an oxidation process is performed to form a through oxide film 21 on the upper surface of the device layer 10C. At this time, a gate side insulating film 20I is formed on the side surface of the gate electrode 20G.

[0036] Using the gate electrode 20G as a mask, a P-type dopant is implanted to form a halo region (not shown), and an N-type dopant is implanted to form a source extension region 20SE and a drain extension region 20DE.

[0037] Next, as shown in Fig. 4B, a P-type dopant is implanted to form the body contact region 20BC2 using the resist pattern 50 and the gate electrode protrusion 20GP as a mask. Furthermore, as shown in Fig. 5A, an N-type dopant is implanted to form the drift region 20DR using the resist pattern 51 and the gate electrode 20G as a mask.

[0038] As shown in FIG. 5B, using resist pattern 52 as a mask, N-type dopants are implanted to form source region 20S and drain region 20D. At this time, in the cross section shown in FIG. 2A, the sidewall spacers 20SW act as a mask, so the source region 20S is formed outside the sidewall spacers 20SW. Directly below the sidewall spacers 20SW on the source region 20S side, a source extension region 20SE is formed using the N-type dopant implanted in the process shown in FIG. 4A. The drain extension region 20DE (FIG. 4B) formed directly below the sidewall spacers 20SW above the drain region 20D is absorbed into the drift region 20DR formed in the process shown in FIG. 5A.

[0039] The activation annealing of the dopants implanted into the device layer 10C may be performed after each dopant implantation, or may be performed collectively after all the dopant implantation steps.

[0040] 6, the through oxide film 21 (FIG. 5B) on the upper surfaces of the source region 20S, the body contact region 20BC2, and the drain region 20D is removed, and the gate upper insulating film 20T on a portion of the upper surface of the gate electrode 20G that is closer to the source region 20S is removed. Thereafter, a silicide film 25 is formed on the exposed upper surfaces of the source region 20S, the body contact region 20BC2, the drain region 20D, the gate electrode 20G, and the gate electrode protrusion 20GP. The silicide film 25 can be formed by forming a metal film such as cobalt or titanium, and then reacting it with silicon.

[0041] Thereafter, as shown in FIGS. 2A and 2B, an interlayer insulating film 31, a via 41, a field plate 40, an interlayer insulating film 32, a via 46, a source wiring 45, and the like are formed.

[0042] Next, the advantageous effects of the first embodiment will be described. In the first embodiment, the drift region 20DR and the field plate 40 are provided, which can alleviate the electric field concentration between the gate and the drain. Furthermore, of the electron-hole pairs generated near the boundary between the body region 20B and the drift region 20DR by impact ionization, the holes are transported to the ground via the body region 20B and the body contact regions 20BC1 and 20BC2. This can suppress the accumulation of holes in the body region 20B.

[0043] Furthermore, in the y direction, the field plate 40 is not disposed in at least a portion of the body contact connection portion 24 (FIGS. 1 and 3). That is, in plan view, a portion of the gate electrode 20G does not overlap with the field plate 40. Therefore, compared to a configuration in which the entire gate electrode 20G overlaps with the field plate 40, the parasitic capacitance between the gate and source is smaller.

[0044] The current gain cutoff frequency ft is an index that represents the high frequency performance of an FET. The current gain cutoff frequency ft is expressed by the following equation: ft=gm / (2π(Cgs+Cgd)) (1) where gm is the transfer conductance, Cgs is the parasitic capacitance between the gate and source, and Cgd is the parasitic capacitance between the gate and drain. In the first embodiment, by reducing the parasitic capacitance Cgs between the gate and source, a decrease in the current gain cutoff frequency ft is suppressed, as shown in equation (1).

[0045] In the range where the field plate 40 is not disposed in the y direction, the effect of alleviating the electric field concentration between the gate and the drain is reduced. However, as described with reference to FIG. 3, in the range of the body contact connection portion 24 in the y direction, the electrons e －Since the current does not substantially travel, impact ionization does not occur. Therefore, even if a region where the field plate 40 is not disposed occurs within the range of the body contact connection portion 24, the effect of suppressing impact ionization is not weakened. In this way, in the first embodiment, it is possible to reduce the parasitic capacitance Cgs between the gate and source without weakening the effect of suppressing impact ionization, which is the purpose of disposing the field plate 40.

[0046] Furthermore, in the first embodiment, the field plate 40 is separated into two parts even in the region where the field plate 40 and the drain region 20D overlap in a plan view. This reduces the parasitic capacitance Cds between the source and drain. When the FET 20 is used in an application where the parasitic capacitance Cds between the source and drain adversely affects the electrical characteristics, the reduction in the parasitic capacitance Cds can suppress degradation of the electrical characteristics. For example, when the FET 20 is used as a high-voltage switch, it is possible to reduce the output capacitance.

[0047] Next, a preferred range for arranging the field plate 40 will be described. In order to suppress impact ionization, as shown in FIG. － It is preferable to arrange the field plate 40 in a range where the current flows. That is, it is preferable to arrange the field plate 40 at least in a range where the junction interface between the P-type body region 20B and the N-type source region 20S is arranged. In reality, as shown in FIG. 2A , the source extension region 20SE is arranged between the source region 20S and the body region 20B in the surface layer portion of the device layer 10C. Here, it can be considered that the junction interface between the P-type body region 20B and the N-type source region 20S includes the junction interface between the source extension region 20SE and the body region 20B.

[0048] Note that, in the y direction, if the effect of generating electron-hole pairs due to impact ionization in the areas near both ends of the body contact connection point 24 is small, a configuration may be adopted in which the field plate 40 is not disposed in the area of ​​the junction interface between the source region 20S and the body region 20B near the body contact connection point 24. In other words, the edge of the field plate 40 may be moved in a direction that increases the distance W ( FIG. 3 ) from the half line HL to the field plate 40. By adopting this configuration, the parasitic capacitance Cgs between the gate and source can be further reduced.

[0049] If the distance W ( FIG. 3 ) from the half line HL to the field plate 40 becomes too short, the effect of reducing the parasitic capacitance Cgs between the gate and source becomes small. As an example, in order to obtain a sufficient effect of reducing the parasitic capacitance Cgs, it is preferable that the minimum value of the distance W in the y direction from the half line HL to the field plate 40 be equal to or greater than ¼ of the dimension of the body contact connection point 24 in the y direction.

[0050] Next, a semiconductor device according to a modification of the first embodiment will be described with reference to Figures 7A and 7B. Figures 7A and 7B are cross-sectional views of the semiconductor device according to the modification of the first embodiment. In the first embodiment (Figure 2A), a silicide film 25 is disposed in a partial region on the source region 20S side of the upper surface of the gate electrode 20G, and a gate upper insulating film 20T is disposed in the remaining region.

[0051] 7A, the silicide film 25 is disposed over the entire upper surface of the gate electrode 20G. Although not shown in the cross section shown in FIG. 7A, the silicide film 25 is also disposed over the entire upper surface of the gate electrode protrusion 20GP (FIG. 1).

[0052] In the modified example shown in FIG. 7B, similarly to the modified example shown in FIG. 7A, a silicide film 25 is disposed over the entire upper surface of the gate electrode 20G, and further, a gate upper insulating film 20T is disposed over the entire upper surface of the silicide film 25.

[0053] As shown in FIGS. 7A and 7B, by disposing the silicide film 25 over the entire upper surface of the gate electrode 20G, the resistance of the gate electrode 20G can be further reduced.

[0054] Next, a semiconductor device according to another modification of the first embodiment will be described with reference to FIG. 8 . FIG. 8 is a plan view of the semiconductor device according to the modification of the first embodiment. In FIG. 8 , the field plate 40 is hatched. In the first embodiment ( FIG. 1 ), the field plate 40 has a rectangular shape in plan view. That is, the y-direction dimension of each field plate 40 is constant regardless of the position in the x-direction. In contrast, in the modification shown in FIG. 8 , the y-direction dimension of at least a portion of the portion of the field plate 40 overlapping with the source region 20S is smaller than the y-direction dimension of the portion overlapping with the gate electrode 20G. For example, the field plate 40 includes a field plate protrusion 40P that protrudes from the portion overlapping with the gate electrode 20G toward the side where the source region 20S is located.

[0055] Some of the multiple vias 41 are arranged in positions that overlap with the field plate protrusion 40P in a plan view, and the remaining vias 41 are arranged in regions that do not overlap with the field plate 40. The vias 41 that are arranged in positions that do not overlap with the field plate 40 are connected to vias 46 in the second interlayer insulating film 32 via inner-layer lands that are arranged in the same layer as the field plate 40 in the cross section shown in FIG.

[0056] In the modified example shown in FIG. 8, as in the first embodiment, it is possible to reduce the parasitic capacitance Cgs between the gate and source without weakening the effect of suppressing impact ionization.

[0057] Next, a semiconductor device according to yet another modification of the first embodiment will be described with reference to FIG. 9 . FIG. 9 is a plan view of the semiconductor device according to this modification of the first embodiment. In FIG. 9 , the field plate 40 is hatched. In the first embodiment ( FIG. 1 ), the field plate 40 extends from the source region 20S through the body region 20B and the drift region 20DR to the drain region 20D in plan view. In contrast, in the modification shown in FIG. 9 , the field plate 40 extends partway through the drift region 20DR and does not reach the drain region 20D.

[0058] The configuration according to this modification also makes it possible to reduce the electric field concentration between the gate electrode 20G and the drift region 20DR.

[0059] Next, a semiconductor device according to yet another modification of the first embodiment will be described with reference to Fig. 10. Fig. 10 is a plan view of the semiconductor device according to this modification of the first embodiment. In Fig. 10, field plate 40 is hatched. In the first embodiment (Fig. 1), in plan view, the dimension in the y direction of the portion of field plate 40 that overlaps drift region 20DR is the same as the dimension in the y direction of the portion that overlaps gate electrode 20G.

[0060] 10 , in plan view, the y-direction dimension of the portion of field plate 40 that overlaps gate electrode 20G is smaller than the y-direction dimension of the portion that overlaps drift region 20DR. When there are multiple "overlapping portions," the "y-direction dimension of the overlapping portions" refers to the sum of the y-direction dimensions of the overlapping portions.

[0061] For example, in Fig. 10, one field plate 40 (upper side in Fig. 10) has an opening 40W that overlaps with a portion of the gate electrode 20G. This field plate 40 overlaps with the gate electrode 20G at two locations. The y-direction dimensions of these overlapping portions are labeled Lg1 and Lg2. The y-direction dimension of the portion where this field plate 40 overlaps with the drift region DR is labeled Ld1.

[0062] The other field plate 40 (lower in FIG. 10) overlaps with the gate electrode 20G at one location. The dimension of this overlapping portion in the y direction is denoted as Lg3. The dimension of the overlapping portion between this field plate 40 and the drift region DR in the y direction is denoted as Ld2. In this case, the following magnitude relationships hold: Lg1 + Lg2 < Ld1 Lg3 < Ld2 Lg1 + Lg2 + Lg3 < Ld1 + Ld2 ... (2)

[0063] As in the modified example shown in Figure 10, by configuring the y-direction dimension of the portion of the field plate 40 that overlaps with the gate electrode 20G in a plan view to be smaller than the y-direction dimension of the portion that overlaps with the drift region 20DR, the effect of reducing the parasitic capacitance Cgs between the gate and source can be enhanced.

[0064] The semiconductor device according to the first embodiment includes an N-channel FET 20, but may also include a P-channel FET, or may include both an N-channel FET and a P-channel FET.

[0065] 2B , the position of the boundary between the body contact region 20BC1 and the body contact region 20BC2 in the x direction substantially coincides with the position of the tip (the left end in FIG. 2B ) of the gate electrode protrusion 20GP, but the two positions may not coincide. For example, if ion implantation to form the body contact region 20BC2 is performed before forming the gate electrode 20G and the gate electrode protrusion 20GP, a configuration is obtained in which the boundary between the body contact region 20BC2 and the body contact region 20BC1 is located at the midpoint of the gate electrode protrusion 20GP in the x direction, as shown in FIG.

[0066] Second Embodiment Next, a semiconductor device according to a second embodiment will be described with reference to Figures 11 and 12. Hereinafter, a description of the configuration common to the semiconductor device according to the first embodiment described with reference to Figures 1 to 6 will be omitted.

[0067] 11 is a plan view of a semiconductor device according to the second embodiment. In FIG. 11, field plate 40 is hatched. In the first embodiment (FIG. 1), gate electrode protrusion 20GP is provided, protruding from gate electrode 20G toward source region 20S. In contrast, in the second embodiment, gate electrode protrusion 20GP is not provided.

[0068] The body contact region 20BC is provided so as to contact the edge of the gate electrode 20G on the source region 20S side in plan view. For example, the acceptor concentration of the body contact region 20BC is the same as the acceptor concentration of the body contact region 20BC2 ( FIG. 1 ) of the semiconductor device according to the first embodiment. The implantation of P-type dopants to form the body contact region 20BC is performed instead of the implantation of P-type dopants to form the body contact region 20BC2 ( FIG. 4B ) of the semiconductor device according to the first embodiment.

[0069] In the second embodiment, the boundary line between the body region 20B and the body contact region 20BC in a plan view forms the body contact connection point 24.

[0070] 12 is a cross-sectional view taken along dashed line 12-12 in FIG. 11. The body contact region 20BC extends to just below the sidewall spacer 20SW and contacts the body region 20B. Note that in the step shown in FIG. 4A, N-type dopants are implanted just below the sidewall spacer 20SW to form the source extension region 20SE, but because the doping concentration of the P-type dopant is sufficiently higher than the doping concentration of the N-type dopant, the region just below the sidewall spacer 20SW becomes a P-type region.

[0071] In the first embodiment (FIG. 2B), the body contact region 20BC2, which has a higher acceptor concentration than the body region 20B, is connected to the body region 20B via the body contact region 20BC1, which has the same acceptor concentration as the body region 20B. In contrast, in the second embodiment, the body contact region 20BC, which has a higher acceptor concentration than the body region 20B, is in direct contact with the body region 20B.

[0072] Next, the advantageous effects of the second embodiment will be described. As in the first embodiment, the second embodiment also makes it possible to reduce the parasitic capacitance Cgs between the gate and source without weakening the effect of suppressing impact ionization. The preferred positional relationship between the body contact connection point 24 and the field plate 40 in plan view is the same as in the first embodiment.

[0073] [Third Embodiment] Next, a semiconductor device according to a third embodiment will be described with reference to Figures 13 and 14. Hereinafter, a description of the configuration common to the semiconductor device according to the first embodiment described with reference to Figures 1 to 6 will be omitted.

[0074] 13 is a plan view of a semiconductor device according to the third embodiment. In FIG. 13, the field plate 40 is hatched. In the first embodiment (FIG. 1), one gate electrode protrusion 20GP is provided at approximately the center of the gate electrode 20G in the y direction. In contrast, in the third embodiment, a gate electrode protrusion 20GP is provided near each end of the gate electrode 20G in the y direction. Each of the two gate electrode protrusions 20GP is positioned so as to overlap the edge of the active region 10CA.

[0075] 14 is a diagram showing the positional relationship in a plan view of one gate electrode protrusion 20GP, the gate electrode 20G in the vicinity thereof, the field plate 40, etc. In FIG. 14, the field plate 40 is hatched. In the first embodiment (FIG. 3), the body contact region 20BC1 is arranged over almost the entire area of ​​the gate electrode protrusion 20GP in a plan view. In contrast, in the third embodiment, the body contact region 20BC1 is arranged over almost the entire area of ​​the portion of the active region 10CA in which the gate electrode protrusion 20GP is arranged in a plan view.

[0076] Therefore, the y-direction dimension of the body contact connection point 24 is smaller than the y-direction dimension of the gate electrode protrusion 20GP. One end of the body contact connection point 24 is connected to the edge of the active region 10CA. As in the first embodiment ( FIG. 3 ), the field plate 40 does not overlap with the half line HL extending parallel to the x-direction from the midpoint C of the body contact connection point 24 toward the drain region 20D. Note that the field plate 40 is disposed only on one side of the half line HL (the side of the center of the active region 10CA). While the field plate 40 is separated into two parts in the first embodiment ( FIG. 1 ), in the third embodiment, the field plate 40 is configured as a single continuous part.

[0077] As in the first embodiment (FIG. 3), the distance W in the y direction from the half line HL to the field plate 40 is preferably at least ¼ of the dimension of the body contact connection point 24 in the y direction.

[0078] Next, a description will be given of the excellent effects of Example 3. In Example 3, as in Example 1, it is possible to reduce the parasitic capacitance Cgs between the gate and source without weakening the effect of suppressing impact ionization.

[0079] The above-described embodiments are merely examples, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible. Similar effects resulting from similar configurations of multiple embodiments will not be mentioned sequentially for each embodiment. Furthermore, the present invention is not limited to the above-described embodiments. For example, it will be obvious to those skilled in the art that various modifications, improvements, combinations, etc. are possible.

[0080] Based on the above-described embodiments described in this specification, the following invention is disclosed. <1> A field effect transistor is provided on an insulating surface, an interlayer insulating film covering the field effect transistor, and a conductive field plate provided on the interlayer insulating film, wherein the field effect transistor includes a source region of a first conductivity type, a body region of a second conductivity type, a drift region of the first conductivity type, a drain region of the first conductivity type, and a gate electrode, wherein, in a plan view of the insulating surface, the gate electrode has a shape elongated in a first direction, and the body region is disposed below and overlaps with the gate electrode, the source region and the drift region are disposed at positions sandwiching the body region in a second direction perpendicular to the first direction, and the drain region is disposed at a position farther from the body region than the drift region, and the field effect transistor further includes a body contact region of the second conductivity type protruding from a body contact connection point that is a part of an edge of the body region on the source region side toward a side on which the source region is disposed, and the field plate is electrically connected to the source region, When the insulating surface is viewed in a plane, the field plate has a shape that extends from the source region, intersects the gate electrode, and reaches at least the drift region, and does not overlap a first ray that extends in the second direction from a midpoint of the body contact connection point toward the drain region.

[0081] <2> The semiconductor device according to <1>, wherein, when the insulating surface is viewed from above, the field plate reaches at least to a boundary line between the drift region and the drain region.

[0082] <3> The semiconductor device according to <1> or <2>, wherein the field plate is arranged in a range in which a junction interface between the body region and the source region is arranged in the first direction.

[0083] <4> The semiconductor device according to any one of <1> to <3>, wherein a distance in the first direction from the first ray to the field plate is equal to or greater than ¼ of a dimension in the first direction of the body contact connection point.

[0084] <5> The semiconductor device according to any one of <1> to <4>, wherein the body contact connection point is disposed between both ends of the body region in the first direction, and the field plate is composed of at least two parts separated in the first direction at the position of the first half-line.

[0085] <6> The semiconductor device according to any one of <1> to <4>, wherein the body contact regions are disposed on both ends of the body region in the first direction, and the field plate is configured as a single continuous pattern.

[0086] <7> The semiconductor device according to any one of <1> to <6>, wherein, in a plan view of the insulating surface, a dimension in the first direction of an overlapping portion between the field plate and the gate electrode is smaller than a dimension in the first direction of an overlapping portion between the field plate and the drift region.

[0087] 10 Substrate 10A Support substrate 10B Buried insulating layer 10C Device layer 10CA Active region 20 Field effect transistor (FET) 20B Body region 20BC, 20BC1, 20BC2 Body contact region 20D Drain region 20DE Drain extension region 20DR Drift region 20G Gate electrode 20GI Gate insulating film 20GP Gate electrode protrusion 20I Gate side insulating film 20S Source region 20SE Source extension region 20SW Sidewall spacer 20T Gate upper insulating film 21 Through oxide film 24 Body contact connection portion 25 Silicide film 31, 32 Insulating film 40 Field plate 40P Field plate protrusion 40W Field plate opening 41 Via 45 Source wiring 46 Via 50, 51, 52 Resist pattern

Claims

1. A field effect transistor comprising: an insulating surface; an interlayer insulating film covering the field effect transistor; and a conductive field plate disposed on the interlayer insulating film, wherein the field effect transistor comprises: a source region of a first conductivity type, a body region of a second conductivity type, a drift region of the first conductivity type, a drain region of the first conductivity type, and a gate electrode, wherein, when the insulating surface is viewed in a plan view, the gate electrode has a shape elongated in a first direction, and the body region is disposed below the gate electrode so as to overlap with the gate electrode, the source region and the drift region are disposed at positions sandwiching the body region in a second direction perpendicular to the first direction, and the drain region is disposed at a position farther from the body region than the drift region, wherein the field effect transistor further comprises: a body contact region of the second conductivity type protruding from a body contact connection point which is a part of the edge of the body region on the source region side towards the side where the source region is disposed, and the field plate is electrically connected to the source region, a field plate having a shape that, when the insulating surface is viewed in a planar view, extends from the source region, intersects the gate electrode, and reaches at least the drift region, and does not overlap a first half line extending in the second direction from a midpoint of the body contact connection point toward the drain region.

2. The semiconductor device according to claim 1, wherein, when the insulating surface is viewed in plan, the field plate reaches at least as far as the boundary line between the drift region and the drain region.

3. The semiconductor device according to claim 1 or 2, wherein the field plate is disposed in at least an area in the first direction where a junction interface between the body region and the source region is disposed.

4. A semiconductor device according to any one of claims 1 to 3, wherein the distance in the first direction from the first ray to the field plate is equal to or greater than 1 / 4 of the dimension in the first direction of the body contact connection point.

5. A semiconductor device according to any one of claims 1 to 4, wherein the body contact connection point is disposed between both ends of the body region in the first direction, and the field plate is composed of at least two portions separated in the first direction at the position of the first half line.

6. A semiconductor device according to any one of claims 1 to 4, wherein the body contact regions are disposed on both ends of the body region in the first direction, and the field plate is configured as a single continuous pattern.

7. A semiconductor device according to any one of claims 1 to 6, wherein, when the insulating surface is viewed in a plan view, the dimension in the first direction of an overlapping portion between the field plate and the gate electrode is smaller than the dimension in the first direction of an overlapping portion between the field plate and the drift region.

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