Multilayer ceramic capacitor

Abstract

An element body part according to the present invention includes: a first outer layer part (X1) that is further to a first principal surface side than an internal electrode layer of a plurality of internal electrode layers that is furthest to the first principal surface side in the layering direction; and a second outer layer part that is further to a second principal surface side than an internal electrode layer of the plurality of internal electrode layers that is furthest to the second principal surface side in the layering direction. Both the first outer layer part (X1) and the second outer layer part include an outermost layer part (Xa) that is furthest to the outside and an inside outer layer part (Xb) that is inside the outermost layer part (Xa). The maximum height (Ha) of the unevenness of the outer surface of the outermost layer part (Xa) is smaller than the maximum height (Hb) of the unevenness of the outer surface of the inside outer layer part (Xb).

Description

Multilayer ceramic capacitors

[0001] The present disclosure relates to multilayer ceramic capacitors.

[0002] Japanese Patent Laid-Open Publication No. 2021-2645 (Patent Document 1) is a prior art document that discloses the configuration of a multilayer ceramic capacitor. The multilayer ceramic capacitor described in Patent Document 1 includes a ceramic body, a plurality of internal electrodes, and a side margin portion. The side margin portion is divided into a first region adjacent to the outer surface and a second region adjacent to the internal electrodes. The dielectric grain size included in the second region is larger than the dielectric grain size included in the first region.

[0003] Japanese Patent Application Laid-Open No. 2021-2645

[0004] When the outer surface of a ceramic body is formed by sintering dielectric particles, the outer surface has many fine irregularities. If these fine irregularities are subjected to an impact, cracks will form on the outer surface, reducing the moisture resistance of the multilayer ceramic capacitor.

[0005] The present disclosure has been made in view of the above-mentioned problems, and has an object to provide a multilayer ceramic capacitor capable of suppressing a decrease in moisture resistance.

[0006] A multilayer ceramic capacitor according to the present disclosure includes an element body and external electrodes. The element body includes a plurality of dielectric layers and a plurality of internal electrode layers stacked in a stacking direction, and has first and second main surfaces facing each other in the stacking direction, first and second side surfaces facing each other in a width direction perpendicular to the stacking direction, and first and second end surfaces facing each other in a length direction perpendicular to the stacking direction and the width direction. External electrodes are provided on each of the first end surfaces and second end surfaces and are electrically connected to the plurality of internal electrode layers. The element body includes a first outer layer portion located closer to the first main surface than an internal electrode layer of the plurality of internal electrode layers that is closest to the first main surface in the stacking direction, and a second outer layer portion located closer to the second main surface than an internal electrode layer of the plurality of internal electrode layers that is closest to the second main surface in the stacking direction. Each of the first outer layer portion and the second outer layer portion includes an outermost outer layer portion disposed on the outside and an inner outer layer portion located inside the outermost outer layer portion. The maximum height of the irregularities on the outer surface of the outermost layer portion is smaller than the maximum height of the irregularities on the outer surface of the inner outer layer portion.

[0007] According to the present disclosure, it is possible to suppress a decrease in the moisture resistance of a multilayer ceramic capacitor.

[0008] 1 is a perspective view schematically illustrating the appearance of a multilayer ceramic capacitor according to an embodiment; FIG. 2 is a perspective view schematically illustrating an element portion of a multilayer ceramic capacitor according to an embodiment; FIG. 3 is a schematic cross-sectional view of the multilayer ceramic capacitor shown in FIG. 1 , viewed from the direction of the arrows III-III; FIG. 4 is a schematic cross-sectional view of the multilayer ceramic capacitor shown in FIG. 1 , viewed from the direction of the arrows IV-IV; FIG. 5 is a schematic cross-sectional view of the multilayer ceramic capacitor shown in FIG. 3 , viewed from the direction of the arrows V-V; FIG. 6 is a schematic cross-sectional view of the multilayer ceramic capacitor shown in FIG. 3 , viewed from the direction of the arrows VI-VI; FIG. 7 is a schematic cross-sectional view for explaining details of a side margin portion of a multilayer ceramic capacitor according to an embodiment; FIG. 8 is a schematic cross-sectional view for explaining details of an outer layer portion of a multilayer ceramic capacitor according to an embodiment; FIG. 9 is a schematic cross-sectional view for explaining details of an end margin portion and an external electrode of a multilayer ceramic capacitor according to an embodiment; FIG. 10 is a schematic cross-sectional view showing a detailed configuration of an external electrode of a multilayer ceramic capacitor according to an embodiment; FIG. 11 is a schematic cross-sectional view for explaining misalignment in the width direction of extension portions of internal electrode layers in a multilayer ceramic capacitor according to an embodiment; FIG. 12 is a flow diagram showing a method for manufacturing a multilayer ceramic capacitor according to an embodiment; FIG. 13 is a schematic cross-sectional view for explaining details of an end margin portion and an external electrode of a multilayer ceramic capacitor according to a modified example. FIG. 10 is a flowchart showing a method for manufacturing a multilayer ceramic capacitor according to a modified example.

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the embodiments described below, identical or common parts are designated by the same reference numerals in the drawings, and their description will not be repeated. In the drawings, the length direction of an element body portion (described later) is indicated by L, the width direction of the element body portion by W, and the stacking direction of the element body portion by T.

[0010] FIG. 1 is a perspective view schematically showing the appearance of a multilayer ceramic capacitor according to an embodiment. FIG. 2 is a perspective view schematically showing an element part of a multilayer ceramic capacitor according to an embodiment. FIG. 3 is a schematic cross-sectional view of the multilayer ceramic capacitor shown in FIG. 1, as viewed from the direction of the arrows along line III-III. FIG. 4 is a schematic cross-sectional view of the multilayer ceramic capacitor shown in FIG. 1, as viewed from the direction of the arrows along line IV-IV. FIG. 5 is a schematic cross-sectional view of the multilayer ceramic capacitor shown in FIG. 3, as viewed from the direction of the arrows along line V-V. FIG. 6 is a schematic cross-sectional view of the multilayer ceramic capacitor shown in FIG. 3, as viewed from the direction of the arrows along line VI-VI.

[0011] 1 to 6, the multilayer ceramic capacitor 100 according to the embodiment includes an element body 110 and external electrodes. The external electrodes of the multilayer ceramic capacitor 100 include a first external electrode 120 and a second external electrode 130.

[0012] 1 , the element body 110 has a substantially rectangular parallelepiped shape. The element body 110 has a first main surface 111 and a second main surface 112 that face each other in the stacking direction T, a first side surface 113 and a second side surface 114 that face each other in a width direction W that is perpendicular to the stacking direction T, and a first end surface 115 and a second end surface 116 that face each other in a length direction L that is perpendicular to the stacking direction T and the width direction W.

[0013] It is preferable that the corners and ridges of the element body 110 are rounded. Here, a corner is a portion where three faces of the element body 110 intersect, and a ridge is a portion where two faces of the element body 110 intersect.

[0014] 1 and 3 to 6 , the first external electrode 120 is provided on the first end surface 115. Specifically, the first external electrode 120 is formed over the entire first end surface 115, and is formed so as to extend from the first end surface 115 around the first main surface 111, the second main surface 112, the first side surface 113, and the second side surface 114. As shown in FIGS. 5 and 6 , the first external electrode 120 includes an extending portion 120E that extends from the first end surface 115 to each of the first side surface 113 and the second side surface 114.

[0015] 1 and 3 to 6 , the second external electrode 130 is provided on the second end surface 116. Specifically, the second external electrode 130 is formed over the entire second end surface 116, and is formed so as to extend from the second end surface 116 around the first main surface 111, the second main surface 112, the first side surface 113, and the second side surface 114. As shown in FIGS. 5 and 6 , the second external electrode 130 includes an extending portion 130E that extends from the second end surface 116 to each of the first side surface 113 and the second side surface 114.

[0016] The detailed configurations of the first external electrode 120 and the second external electrode 130 will be described later.

[0017] 2 to 6, the element body 110 includes a laminate 101 and a covering layer 160. The covering layer 160 contains Si and K.

[0018] The laminate 101 has a pair of principal surfaces 101a, 101b facing each other in the stacking direction T, a pair of side surfaces 101c, 101d facing each other in the width direction, and a pair of end surfaces 101e, 101f facing each other in the length direction. The pair of principal surfaces 101a, 101b, the pair of side surfaces 101c, 101d, and the pair of end surfaces 101e, 101f are covered with a coating layer 160. The coating layer 160 is located on the first side surface 113, the second side surface 114, the first principal surface 111, and the second principal surface 112. At the first end surface 115 and the second end surface 116, the multiple dielectric layers 140 are covered with the coating layer 160.

[0019] As shown in FIGS. 2 to 4, the laminate 101 has a plurality of dielectric layers 140 and a plurality of internal electrode layers 150 alternately stacked along a stacking direction T.

[0020] The plurality of internal electrode layers 150 includes a plurality of first internal electrode layers 151 and a plurality of second internal electrode layers 152. The plurality of first internal electrode layers 151 and the plurality of second internal electrode layers 152 are alternately stacked in the stacking direction T.

[0021] The plurality of first internal electrode layers 151 are extended to the end face 101 e. The plurality of first internal electrode layers 151 are electrically connected to the first external electrode 120. The plurality of second internal electrode layers 152 are extended to the end face 101 f. The plurality of second internal electrode layers 152 are electrically connected to the second external electrode 130. Both end portions in the width direction W of the plurality of first internal electrode layers 151 and the plurality of second internal electrode layers 152 are exposed to the side faces 101 c, 101 d.

[0022] 2 to 4 show an example in which seven first internal electrode layers 151 and seven second internal electrode layers 152 are provided, but the number of each of the first internal electrode layers 151 and the second internal electrode layers 152 is not limited to seven. The number of the multiple internal electrode layers 150 is preferably 1 to 1000. The thickness of the internal electrode layer 150 is preferably 0.3 μm to 0.8 μm.

[0023] 5, the first internal electrode layer 151 includes a first opposing portion 151C and a first lead portion 151X. The first opposing portion 151C faces the adjacent second internal electrode layer 152 in the stacking direction T. The first lead portion 151X connects the first opposing portion 151C and the first external electrode 120. The first lead portion 151X is led out to the first end face 115 side. The first opposing portion 151C and the first lead portion 151X are integrally configured.

[0024] The first internal electrode layer 151 has a first narrow portion 151N, on the side opposite to the side connected to the first external electrode 120 in the longitudinal direction L, which has a width in the width direction W narrower than that of a central portion in the longitudinal direction L. In the width direction W, the width W2 of the first narrow portion 151N is smaller than the width W1 of the first opposing portion 151C.

[0025] As shown in Figure 5, the region on the second end face 116 side of the element body 110 where adjacent internal electrode layers 150 do not overlap in the stacking direction T, i.e., the region from the end on the second end face 116 side of the region where adjacent internal electrode layers 150 overlap in the stacking direction T to the second end face 116, is defined as Lgap.

[0026] The first narrow portion 151N does not necessarily have to be formed, and the width of the portion where the first narrow portion 151N is formed may be W1. In this case, it is preferable that the length in the longitudinal direction L of the extending portion 120E of the first external electrode 120 is shorter than the length Lgap along the longitudinal direction L, or that the extending portion 120E is not formed.

[0027] 6 , the second internal electrode layer 152 includes a second opposing portion 152C and a second lead portion 152X. The second opposing portion 152C faces the adjacent first internal electrode layer 151 in the stacking direction T. The second lead portion 152X connects the second opposing portion 152C and the second external electrode 130. The second lead portion 152X is led out to the second end face 116 side. The second opposing portion 152C and the second lead portion 152X are integrally configured.

[0028] The second internal electrode layer 152 has a second narrow portion 152N, which is located on the side opposite to the side connected to the second external electrode 130 in the longitudinal direction L and has a width in the width direction W that is narrower than that of the central portion in the longitudinal direction L. In the width direction W, the width W4 of the second narrow portion 152N is smaller than the width W3 of the second opposing portion 152C.

[0029] As shown in Figure 6, the region on the first end face 115 side of the element body 110 where adjacent internal electrode layers 150 do not overlap in the stacking direction T, i.e., the region from the end on the first end face 115 side of the region where adjacent internal electrode layers 150 overlap in the stacking direction T to the first end face 115, is defined as Lgap.

[0030] The second narrow portion 152N does not necessarily have to be formed, and the width of the portion where the second narrow portion 152N is formed may be W3. In this case, it is preferable that the length in the longitudinal direction L of the extending portion 130E of the second external electrode 130 is shorter than the length Lgap along the longitudinal direction L, or that the extending portion 130E is not formed.

[0031] Each of the first internal electrode layer 151 and the second internal electrode layer 152 contains one kind of metal selected from the group consisting of Ni, Cu, Ag, Pd, and Au, or an alloy containing the metal. In this embodiment, each of the first internal electrode layer 151 and the second internal electrode layer 152 contains Ni as a main component. Each of the first internal electrode layer 151 and the second internal electrode layer 152 may further contain dielectric particles having the same composition as the ceramic contained in the dielectric layer 140. Furthermore, each of the first internal electrode layer 151 and the second internal electrode layer 152 may contain Sn at the interface with the dielectric layer 140.

[0032] The plurality of dielectric layers 140 are composed of outer dielectric layers located between the internal electrode layer 150 located closest to the first main surface 111 in the stacking direction T and the first main surface 111, and between the internal electrode layer 150 located closest to the second main surface 112 in the stacking direction T and the second main surface 112, and inner dielectric layers located between the internal electrode layers 150 adjacent to each other in the stacking direction T. The number of the plurality of dielectric layers 140 is preferably 100 to 1000. The thickness of the dielectric layers 140 is preferably 0.4 μm to 0.8 μm.

[0033] Each of the plurality of dielectric layers 140 may be made of a ceramic material such as a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. Alternatively, a material containing these main components plus a secondary component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound may be used.

[0034] 3 and 4 , the element body 110 is partitioned into an inner layer portion C, a first outer layer portion X1 and a second outer layer portion X2, a first side margin portion S1 and a second side margin portion S2, and a first end margin portion E1 and a second end margin portion E2. The inner layer portion C has a capacitance due to a first opposing portion 151C (described later) of the first internal electrode layer 151 and a second opposing portion 152C (described later) of the second internal electrode layer 152 being stacked in the stacking direction T.

[0035] The first outer layer portion X1 and the second outer layer portion X2 sandwich the inner layer portion C in the stacking direction T. The first outer layer portion X1 is located outside the inner layer portion C in the stacking direction T, and is located on the first main surface 111 side. That is, the first outer layer portion X1 is located closer to the first main surface 111 than the internal electrode layer 150 located closest to the first main surface 111 in the stacking direction T. The second outer layer portion X2 is located outside the inner layer portion C in the stacking direction T, and is located closer to the second main surface 112. That is, the second outer layer portion X2 is located closer to the second main surface 112 than the internal electrode layer 150 located closest to the second main surface 112 in the stacking direction T.

[0036] Each of the first outer layer portion X1 and the second outer layer portion X2 extends in the length direction L and the width direction W so as to include the ridge portions of the element body portion 110. The thickness of each of the first outer layer portion X1 and the second outer layer portion X2 is preferably not less than 10 μm and not more than 30 μm.

[0037] Each of the first outer layer portion X1 and the second outer layer portion X2 includes an outermost layer portion disposed on the outermost side and an inner outer layer portion located inside the outermost layer portion. The outermost layer portion is made of a coating layer 160. The inner outer layer portion is made of an outer dielectric layer.

[0038] 3, the first end margin E1 and the second end margin E2 sandwich the inner layer portion C in the longitudinal direction L. The first end margin E1 is located outside the inner layer portion C in the longitudinal direction L, on the side of the first end face 115. The second end margin E2 is located outside the inner layer portion C in the longitudinal direction L, on the side of the second end face 116.

[0039] 4 to 6 , the side margins are located in the element body 110, in the width direction W, between the first side surface 113 and the multiple internal electrode layers 150, and between the second side surface 114 and the multiple internal electrode layers 150. The side margins are made up of a covering layer 160. The covering layer 160 covers both end portions of the multiple internal electrode layers 150 in the width direction W.

[0040] Specifically, the first side margin S1 is provided on the side surface 101c of the laminate. The first side margin S1 is provided so as to cover the entire side surface 101c. The first side margin S1 exists in the element body 110 from one end of the internal electrode layer 150 located on one side in the width direction W to the first side surface 113. That is, the covering layer 160 is formed on one end in the width direction W of each of the multiple internal electrode layers 150 at the center in the length direction L.

[0041] The second side margin S2 is provided on the side surface 101d of the laminate. The second side margin S2 is provided so as to cover the entire side surface 101d. The second side margin S2 exists in the element body 110 from the other end of the internal electrode layer 150 located on the other side in the width direction W to the second side surface 114. That is, the covering layer 160 is formed on the other end in the width direction W of the center portion in the length direction L of each of the multiple internal electrode layers 150.

[0042] The size of the multilayer ceramic capacitor 100 including the element body 110, the first external electrode 120 and the second external electrode 130 is not particularly limited, but may be within the following ranges, for example.

[0043] As shown in Fig. 3, the dimension of the multilayer ceramic capacitor 100 in the length direction L (length dimension L0) is, for example, 0.1 mm or more and 3.2 mm or less. The dimension of the multilayer ceramic capacitor 100 in the stacking direction T (thickness dimension T0) is, for example, 0.05 mm or more and 1.6 mm or less. As shown in Fig. 4, the dimension of the multilayer ceramic capacitor 100 in the width direction W (width dimension W0) is, for example, 0.05 mm or more and 1.6 mm or less.

[0044] The multilayer ceramic capacitor 100 has, for example, a length L of 0.1 mm, a width W of 0.05 mm, and a thickness T of 0.05 mm, or a length L of 0.6 mm, a width W of 0.3 mm, and a thickness T of 0.3 mm, or a length L of 1.0 mm, a width W of 0.5 mm, and a thickness T of 0.5 mm, or a length L of 1.6 mm, a width W of 0.8 mm, and a thickness T of 0.8 mm, or a length L of 3.2 mm, a width W of 1.6 mm, and a thickness T of 1.6 mm. Note that tolerances are taken into account in the above sizes.

[0045] 7 is a schematic cross-sectional view illustrating the details of the side margins of the multilayer ceramic capacitor according to the embodiment. Fig. 7 shows a cross section of the element body 110 on the second side surface 114 side, which is parallel to the stacking direction T and the width direction W. The following description focuses on the second side margin S2 side, but the same applies to the first side margin S1 side.

[0046] As shown in Figure 7, the second side margin portion S2 is composed of a coating layer 160 containing Si and K. The composition of the coating layer 160 can be confirmed by EDX (Energy Dispersive X-ray spectroscopy). The coating layer 160 is amorphous, and the fact that the coating layer 160 is amorphous can be confirmed by Raman spectroscopy. The fact that the coating layer 160 is amorphous can also be confirmed by the fact that no specific crystal pattern can be detected by X-ray diffraction of the coating layer 160.

[0047] The second side margin portion S2 protrudes so as to contact the ends of the multiple internal electrode layers 150 in the width direction W. As a result, a part 161 of the covering layer 160 covering both ends of the multiple internal electrode layers 150 in the width direction W is sandwiched between adjacent dielectric layers 140 in the stacking direction T among the multiple dielectric layers 140. The reason for this shape is that the shrinkage rate of the internal electrode layers 150 is greater than the shrinkage rate of the dielectric layers 140 during firing. This shape of the side margin portion can increase the adhesive strength of the side margin portion to the side surfaces 101c, 101d of the laminate 101. Consequently, peeling of the side margin portion can be suppressed.

[0048] The minimum thickness TS of the covering layer 160 located on the ends of the multiple internal electrode layers 150 in the width direction W is 0.01 μm or more and 10 μm or less. From the viewpoint of moisture resistance, it is more preferable that the minimum thickness TS is 0.1 μm or more, and even more preferable that it is 0.3 μm or more. The shortest distance TP between the multiple internal electrode layers 150 and the first side surface S1 and the shortest distance TP between the multiple internal electrode layers 150 and the second side surface S2 are 0.01 μm or more and 10 μm or less. From the viewpoint of moisture resistance, it is more preferable that the shortest distance TP is 0.1 μm or more, and even more preferable that it is 0.3 μm or more. Note that the numerical ranges of the minimum thickness TS and the shortest distance TP are not limited to those described above.

[0049] The relationship between the shape and thickness described with reference to Fig. 7 can be confirmed by polishing the element body part 110 from the first external electrode 120 side to the center in the length direction L, and observing a cross section of the element body part 110 parallel to the stacking direction T and the width direction W using an electron microscope or the like. The minimum thickness TS is the thickness of the thinnest covering layer 160 measured in an image taken with a SEM (Scanning Electron Microscope) in an area where about 10 first internal electrode layers 151 or second internal electrode layers 152 are included in the field of view at the center in the stacking direction T of the cross section. Similarly, the shortest distance TP is the distance measured between the internal electrode layer 150 and the first side surface S1 or the second side surface S2 in the image.

[0050] 8 is a schematic cross-sectional view for explaining details of the outer layer portions of the multilayer ceramic capacitor according to the embodiment. Fig. 8 shows a cross section of the element body portion 110 on the first outer layer portion X1 side, parallel to the stacking direction T and the width direction W. While the following description focuses on the first outer layer portion X1 side, the same applies to the second outer layer portion X2 side.

[0051] 8, the first outer layer portion X1 includes an outermost layer portion Xa disposed on the outermost side and an inner outer layer portion Xb located inside the outermost layer portion Xa. The outermost layer portion Xa is composed of a coating layer 160. The inner outer layer portion Xb is composed of an outer dielectric layer 140.

[0052] The outer surface of the inner outer layer portion Xb has fine irregularities due to the dielectric grains of the outer dielectric layer 140. The coating layer 160 is amorphous and covers the inner outer layer portion Xb so as to fill in the irregularities on the outer surface of the inner outer layer portion Xb, so that the outer surface of the outermost layer portion Xa is almost free of irregularities. Therefore, the maximum height Ha of the irregularities on the outer surface of the outermost layer portion Xa is smaller than the maximum height Hb of the irregularities on the outer surface of the inner outer layer portion Xb. This improves the impact resistance of the outermost layer portion Xa and prevents a decrease in the moisture resistance of the multilayer ceramic capacitor 100.

[0053] The minimum thickness TM of the coating layer 160 in the stacking direction T in each of the first outer layer portion X1 and the second outer layer portion X2 is 0.01 μm or more and 0.5 μm or less. Note that the numerical range of the minimum thickness TM is not limited to the above.

[0054] The relationship between the shape and thickness described with reference to Figure 8 can be confirmed by polishing the element body part 110 from the first external electrode 120 side to the center in the length direction L, and observing a cross section of the element body part 110 parallel to the stacking direction T and the width direction W using an electron microscope or the like. The smallest thickness of the covering layer 160 in the stacking direction T measured in an image taken with a SEM (Scanning Electron Microscope) in a range where the first outer layer part X1 or the second outer layer part X2 is visible at the end of the stacking direction T of the cross section is defined as the minimum thickness TM.

[0055] 9 is a schematic cross-sectional view for explaining details of the end margins and external electrodes of the multilayer ceramic capacitor according to the embodiment. Fig. 9 shows a cross section of the element body 110 on the second end margin E2 side, parallel to the stacking direction T and the length direction L. While the following description focuses on the second end margin E2 side, the same applies to the first end margin E1 side.

[0056] As shown in FIG. 9 , the external electrode includes a Cu layer 10 containing a Cu component 11 as a main component and a glass component 12. The composition of the Cu layer 10 can be confirmed by EDX. A coating layer 160 is disposed on the second end surface 116, and a portion 13 of the Cu layer 10 penetrates the coating layer 160 and is electrically connected to the second internal electrode layer 152. The coating layer 160 is located between the multiple dielectric layers 140 and the external electrode. Specifically, the coating layer 160 is located between the multiple dielectric layers 140 and the Cu layer 10. The thickness of the Cu layer 10 is 30 μm or more and 100 μm or less at the center in the stacking direction T and the width direction W. Note that the numerical range of the thickness of the Cu layer 10 is not limited to the above. The Cu layer 10 may be a resin layer containing a Cu component and a glass component. In this case, a base metal layer is formed between the resin layer and the coating layer 160.

[0057] The minimum thickness TS of the covering layer 160 located on the end of the multiple internal electrode layers 150 in the width direction W shown in Figure 7 is thicker than the minimum thickness TE of the covering layer 160 located between the multiple dielectric layers 140 and the Cu layer 10, which is the external electrode, shown in Figure 9.

[0058] 9 can be confirmed by polishing the element body part 110 from the first side surface 113 side to the center in the width direction W, and observing a cross section of the element body part 110 parallel to the stacking direction T and the length direction L using an electron microscope or the like. The minimum thickness TE is the thickness of the thinnest covering layer 160 measured in an image taken by an SEM in a range that includes about 10 first internal electrode layers 151 or second internal electrode layers 152 in the field of view at the center in the stacking direction T and the end in the length direction L of the cross section.

[0059] 9 is formed because the coating layer 160 contains K, which lowers the melting point of Si contained in the coating layer 160 to a temperature lower than the firing temperature of the Cu layer 10. Therefore, when the Cu layer 10 is fired, the coating layer 160 melts and the contraction force of the Cu layer 10 acts on the molten coating layer 160, causing a part 13 of the Cu layer 10 to penetrate the coating layer 160 and connect to the second internal electrode layer 152.

[0060] The K contained in the coating layer 160 flows and diffuses into the glass component 12 in the Cu layer 10. That is, the glass component 12 contains K. The closer to the second end face 116, the higher the concentration of K contained in the glass component 12. Furthermore, some of the Si contained in the coating layer 160 penetrates into the Cu layer 10 so as to bond with the glass component 12 in the Cu layer 10. Cu diffuses from the Cu layer 10 into the Ni of the internal electrode layer 150. This increases the adhesive strength between the Cu layer 10 and the internal electrode layer 150. Consequently, peeling of the first external electrode 120 and the second external electrode 130 can be suppressed.

[0061] The Si concentration of the covering layer 160 located on the end of the multiple internal electrode layers 150 in the width direction W shown in Figure 7 is higher than the Si concentration of the covering layer 160 located between the multiple dielectric layers 140 and the external electrode shown in Figure 9.

[0062] The K concentration of the covering layer 160 located on the end of the multiple internal electrode layers 150 in the width direction W shown in Figure 7 is higher than the K concentration of the covering layer 160 located between the multiple dielectric layers 140 and the external electrode shown in Figure 9.

[0063] The concentration distribution of Si and K may be observed from an image captured by a TEM (Transmission Electron Microscope) or EDX. For example, in an image captured by a TEM in a range in which approximately one first internal electrode layer 151 or one second internal electrode layer 152 is included in the field of view, the concentration gradients of Si and K are measured by the TEM as a molar ratio relative to 100 mol of Ti contained in the dielectric layer 140.

[0064] The above-described configuration of the covering layer 160 and the external electrodes ensures moisture resistance by the thin side margins, while ensuring electrical connection between the internal electrode layer 150 and the external electrodes without removing the covering layer 160 by sandblasting or the like on the first end face 115 and the second end face 116. This in turn expands the area in which the internal electrode layer 150 can be arranged, thereby enabling the multilayer ceramic capacitor 100 to be made smaller and have a larger capacitance.

[0065] Fig. 10 is a schematic cross-sectional view showing a detailed configuration of the external electrodes of the multilayer ceramic capacitor according to the embodiment. Fig. 10 shows a cross section of the element body 110 parallel to the stacking direction T and the length direction L on the second external electrode 130 side. In the following explanation, the second external electrode 130 side will be described, but the same applies to the first external electrode 120 side.

[0066] As shown in FIG. 10 , the first external electrode 120 and the second external electrode 130 include a Cu layer 10 provided on the base body 110, a Ni plating layer 20 provided on the Cu layer 10, and a Sn plating layer 30 provided on the Ni plating layer 20.

[0067] The material constituting the plating layer may be one metal selected from the group consisting of Ni, Cu, Ag, Pd, and Au, or an alloy containing such a metal. The total thickness of the Ni plating layer 20 and the Sn plating layer 30 is, for example, 3 μm or more and 20 μm or less.

[0068] 6, in the width direction W, the extending portion 120E overlaps only at the narrow width portion 152N with the second internal electrode layer 152, which is not electrically connected to the first external electrode 120 including the extending portion 120E, among the plurality of internal electrode layers 150. As shown in Fig. 5 and 10, the extending portion 130E overlaps only at the narrow width portion 151N with the first internal electrode layer 151, which is not electrically connected to the second external electrode 130 including the extending portion 130E, among the plurality of internal electrode layers 150.

[0069] This makes it possible to prevent a short circuit caused by an electrical connection between the extension portion 120E and the end portion of the second internal electrode layer 152 in the width direction W. Similarly, it is possible to prevent a short circuit caused by an electrical connection between the extension portion 130E and the end portion of the first internal electrode layer 151 in the width direction W.

[0070] 11 is a schematic cross-sectional view illustrating the widthwise displacement of the extension portions of the internal electrode layers in the multilayer ceramic capacitor according to the embodiment. Note that Fig. 11 is illustrated for convenience in order to explain the amount of displacement of the extension portions, and the positions of the extension portions are not limited to the embodiment shown in Fig. 11.

[0071] 11 , the amount of misalignment D1 in the width direction W between the extending portion 130E located closest to the first side surface 113 and the extending portion 130E located closest to the second side surface 114 is 3 μm or more. The amount of misalignment described above is also the same for the extending portions 120E as for the extending portions 130E. In this way, the ends of the extending portions 120E and the extending portions 130E in the width direction W are not aligned in the stacking direction T but are misaligned in the width direction W.

[0072] On the other hand, as shown in Figure 4, in a cross section of the element body 110 parallel to the stacking direction T and the width direction W at the center of the element body 110 in the length direction L, the amount of misalignment in the width direction W between internal electrode layers 150 adjacent to each other in the stacking direction T is less than 3 μm.

[0073] That is, the amount of misalignment in the width direction W of the first narrow width portion 151N and the second narrow width portion 152N is greater than the amount of misalignment in the width direction W of the central portion of the plurality of internal electrode layers 150 in the length direction L.

[0074] Therefore, it is preferable that the widths of the first narrow width portion 151N and the second narrow width portion 152N are equal to or greater than the maximum expected positional deviation in the width direction W of the first narrow width portion 151N and the second narrow width portion 152N, and narrower than the width of the central portion in the length direction L of the plurality of internal electrode layers 150. This makes it possible to stably prevent the extending portion 120E and the end portion in the width direction W of the second internal electrode layer 152 from being electrically connected to each other and causing a short circuit. Similarly, it is possible to stably prevent the extending portion 130E and the end portion in the width direction W of the first internal electrode layer 151 from being electrically connected to each other and causing a short circuit.

[0075] A method for manufacturing the multilayer ceramic capacitor 100 according to this embodiment will now be described. Fig. 12 is a flow chart showing a method for manufacturing the multilayer ceramic capacitor according to this embodiment.

[0076] As shown in FIG. 12, a ceramic dielectric slurry is prepared (step S1). Specifically, ceramic dielectric powder, additive powder, binder resin, and solvent are dispersed and mixed to prepare the ceramic dielectric slurry. The ceramic dielectric powder is, for example, perovskite-structured dielectric particles such as BaTiO3, CaTiO3, SrTiO3, CaZrO3, or CaHfO3. The additive powder is, for example, composed of at least one of Si compounds, Mg compounds, Mn compounds, Fe compounds, Cr compounds, Ni compounds, and Co compounds. Examples of binder resins that can be used include polyurethane resins, urea resins, melamine resins, epoxy resins, vinyl acetate resins, acrylic resins, and aqueous polymers such as polyvinyl alcohol (PVA) and polyvinyl butyral (PVB). These may be used alone or in combination. The ceramic dielectric slurry may be either solvent-based or water-based. When the ceramic dielectric slurry is a water-based paint, the ceramic dielectric slurry is prepared by mixing a water-soluble binder, a dispersant, etc. with a dielectric raw material dissolved in water.

[0077] Next, a ceramic dielectric sheet is formed (step S2). Specifically, the ceramic dielectric slurry is formed into a sheet on a carrier film using a die coater, gravure coater, microgravure coater, or the like, and then dried to form the ceramic dielectric sheet. From the viewpoint of miniaturization and high capacitance of the multilayer ceramic capacitor, the thickness of the ceramic dielectric sheet is preferably 0.4 μm or more and 0.8 μm or less.

[0078] Next, a mother sheet is formed (step S3). Specifically, a conductive paste is applied to a ceramic dielectric sheet in a predetermined pattern, thereby forming a mother sheet having a predetermined internal electrode pattern on the ceramic dielectric sheet. The conductive paste contains Ni powder, a solvent, a dispersant, a binder, and the like, and is prepared to have a constant viscosity. Examples of binders include polyvinyl butyral (PVB) and polyvinyl alcohol (PVA). The conductive paste can be applied by screen printing, inkjet printing, gravure printing, or the like. The thickness of the internal electrode pattern is preferably 0.3 μm or more and 0.8 μm or less, from the viewpoint of miniaturization and high capacity of the multilayer ceramic capacitor. In addition to mother sheets having internal electrode patterns, ceramic dielectric sheets that have not undergone step S3 can also be prepared.

[0079] Next, a plurality of mother sheets are stacked (step S4). Specifically, a predetermined number of mother sheets, each consisting of only ceramic dielectric sheets and having no internal electrode pattern formed thereon, are stacked to a thickness of, for example, 10 μm or more and 30 μm or less. A predetermined number of mother sheets, each having an internal electrode pattern formed thereon, are stacked thereon. The number of stacked mother sheets, each having an internal electrode pattern formed thereon, is, for example, 1 sheet or more and 1000 sheets or less. A predetermined number of mother sheets, each consisting of only ceramic dielectric sheets and having no internal electrode pattern formed thereon, are stacked thereon to a thickness of, for example, 10 μm or more and 30 μm or less. This forms a mother sheet group.

[0080] Next, the group of mother sheets is pressed together to form a dielectric block (step S5). Specifically, the group of mother sheets is pressed together in the stacking direction using an isostatic press or a rigid press, thereby forming the dielectric block. At this time, the ceramic dielectric sheets are pressed at a predetermined temperature, so that the ceramic dielectric sheets adhere to each other. Furthermore, by placing and pressing a ceramic dielectric sheet of a certain thickness as the outermost layer in the stacking direction, it is possible to protect the dielectric sheet on which the internal electrode pattern is formed.

[0081] Next, the dielectric block is divided into chips (step S6). Specifically, the dielectric block is divided into a matrix shape by press-cutting, dicing, or laser cutting, and is separated into a plurality of chips. When dividing the dielectric block, the dielectric block may be divided in a softened state by heating.

[0082] Next, the chip is fired (step S7). Specifically, the chip is heated, which fires the dielectric material and conductive material contained in the chip, forming the laminate 101. The firing temperature is set appropriately depending on the dielectric material and conductive material.

[0083] Next, a coating layer 160 is formed on the fired chip (step S8). Specifically, the fired stack 101 is immersed in a solution containing Si and K, and then dried. The solution is, for example, water glass containing K.

[0084] Next, a paste that will become the Cu layer 10 is applied to the chip (step S9). Specifically, a paste containing Cu particles and a glass component is applied to each of the first end face 115 and the second end face 116 of the dried element body 110, and then dried.

[0085] Next, the chip coated with the paste that will become the Cu layer 10 is fired (step S10). Specifically, the element body 110 coated with the paste that will become the Cu layer 10 is fired at a temperature of 600° C. to 800° C. As a result, the metal components contained in the paste that will become the Cu layer 10 are sintered, and the coating layer 160 is melted, so that the first internal electrode layer 151 and the Cu layer 10 are electrically connected at the first end surface 115, and the second internal electrode layer 152 and the Cu layer 10 are electrically connected at the second end surface 116.

[0086] Next, the external electrodes are formed (step S11). The Cu layer 10 is plated with Ni and Sn in this order to form the Ni plated layer 20 and the Sn plated layer 30, thereby forming the first external electrode 120 and the second external electrode 130.

[0087] By going through the above-described series of steps, the multilayer ceramic capacitor 100 according to the embodiment can be manufactured.

[0088] A multilayer ceramic capacitor according to a modified example of this embodiment will be described below. The multilayer ceramic capacitor according to the modified example differs from multilayer ceramic capacitor 100 according to this embodiment mainly in that a base electrode layer containing Ni as a main component is formed on first end face 115 and second end face 116 of element body 110. Therefore, description of the same configuration as multilayer ceramic capacitor 100 according to this embodiment will not be repeated.

[0089] 13 is a schematic cross-sectional view illustrating the details of the end margins and external electrodes of a multilayer ceramic capacitor according to a modified example. Fig. 13 shows a cross section of the element body 110 on the second end margin E2 side, parallel to the stacking direction T and the length direction L. While the following description focuses on the second end margin E2 side, the same applies to the first end margin E1 side.

[0090] 13 , the external electrode includes a base electrode layer 40 containing Ni as a main component, and a Cu layer 10 containing a Cu component 11 as a main component and also containing a glass component 12. The base electrode layer 40 may further include dielectric particles having the same composition as the ceramic contained in the dielectric layer 140.

[0091] A base electrode layer 40 is formed on the second end face 116, a covering layer 160 is formed on the base electrode layer 40, and a Cu layer 10 is formed on the covering layer 160. The base electrode layer 40 is covered with the Cu layer 10.

[0092] The minimum thickness TS of the covering layer 160 located on the end of the multiple internal electrode layers 150 in the width direction W shown in Figure 7 is thicker than the minimum thickness TF of the covering layer 160 located between the base electrode layer 40 and the Cu layer 10 shown in Figure 13.

[0093] 13 , a portion 13 of the Cu layer 10 penetrates the coating layer 160 and is electrically connected to the base electrode layer 40. The Cu layer 10 is electrically connected to the second internal electrode layer 152 via the base electrode layer 40.

[0094] In this modification, the base electrode layer 40 is formed so as to wrap around from the second end face 116 to the first main surface 111, the second main surface 112, the first side surface 113, and the second side surface 114. Similarly, the base electrode layer 40 is formed so as to wrap around from the first end face 115 to the first main surface 111, the second main surface 112, the first side surface 113, and the second side surface 114.

[0095] In the multilayer ceramic capacitor according to the modified example, the Cu layer 10 and the second internal electrode layer 152 are electrically connected via the base electrode layer 40 that covers the entire second end face 116, thereby enabling a stable electrical connection between the second internal electrode layer 152 and the second external electrode 130. Similarly, the Cu layer 10 and the first internal electrode layer 151 are electrically connected via the base electrode layer 40 that covers the entire first end face 115, thereby enabling a stable electrical connection between the first internal electrode layer 151 and the first external electrode 120.

[0096] The K contained in the coating layer 160 flows and diffuses into the glass component 12 in the Cu layer 10. Some of the Si contained in the coating layer 160 penetrates into the Cu layer 10 so as to bond with the glass component 12 in the Cu layer 10. Cu from the Cu layer 10 diffuses into the Ni of the base electrode layer 40. This increases the adhesive strength between the Cu layer 10 and the base electrode layer 40. Consequently, peeling of the first external electrode 120 and the second external electrode 130 can be suppressed.

[0097] A method for manufacturing a multilayer ceramic capacitor according to this modification will now be described with reference to Fig. 14, which is a flow chart showing a method for manufacturing a multilayer ceramic capacitor according to this modification.

[0098] As shown in FIG. 14, the method for manufacturing the multilayer ceramic capacitor according to the modified example is similar to the method for manufacturing the multilayer ceramic capacitor 100 from step S1 to step S6.

[0099] After step S6, a paste that will become a base electrode layer is applied to the chip (step S17). Specifically, a paste containing Ni particles is applied to each of end faces 101e and 101f of laminate 101, and then dried.

[0100] Next, the chip coated with the paste that will become the base electrode layer 40 is fired (step S18). Specifically, the chip is heated, which causes the dielectric material and conductive material contained in the chip as well as the paste containing Ni particles to be fired, forming the laminate 101 and the base electrode layer 40.

[0101] Next, a covering layer 160 is formed on the chip on which the base electrode layer 40 has been formed (step S19). Specifically, the stack 101 on which the base electrode layer 40 has been formed is immersed in a solution containing Si and K, and then dried. The solution is, for example, water glass containing K.

[0102] Next, a paste that will become the Cu layer 10 is applied to the chip (step S20). Specifically, a paste containing Cu particles and a glass component is applied so as to cover the base electrode layer 40 on each of the first end face 115 and the second end face 116 via the coating layer 160, and then dried.

[0103] Next, the chip coated with the paste that will become the Cu layer 10 is fired (step S21). Specifically, the chip coated with the paste that will become the Cu layer 10 is fired at a temperature of 600° C. to 800° C. As a result, the metal components contained in the paste that will become the Cu layer 10 are sintered, the coating layer 160 is melted, and the base electrode layer 40 and the Cu layer 10 are electrically connected.

[0104] Next, the external electrodes are formed (step S22). The Cu layer 10 is plated with Ni and Sn in this order to form the Ni plated layer 20 and the Sn plated layer 30, thereby forming the first external electrode 120 and the second external electrode 130.

[0105] By going through the above-described series of steps, the multilayer ceramic capacitor according to the modified example can be manufactured.

[0106] In the above-described embodiments, configurations that can be combined may be combined with each other.

[0107] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims, not by the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0108] 10 Cu layer, 11 Cu component, 12 Glass component, 20 Ni plating layer, 30 Sn plating layer, 40 Base electrode layer, 100 Multilayer ceramic capacitor, 101 Laminate, 101a, 101b Main surface, 101c, 101d Side surface, 101e, 101f End surface, 110 Body portion, 111 First main surface, 112 Second main surface, 113, S1 First side surface, 114, S2 Second side surface, 115 First end surface, 116 Second end surface, 120 First external electrode, 120E, 130E Extension portion, 130 Second external electrode, 140 Dielectric layer, 150 Internal electrode layer, 151 First internal electrode layer, 151C First opposing portion, 151N, 152N Narrow width portion, 151X First lead portion, 152 second internal electrode layer, 152C second opposing portion, 152X second lead portion, 160 coating layer, C inner layer portion, E1 first end margin portion, E2 second end margin portion, S1 first side margin portion, S2 second side margin portion, X1 first outer layer portion, X2 second outer layer portion, Xa outermost layer portion, Xb inner outer layer portion.

Claims

1. An element body including a plurality of dielectric layers and a plurality of internal electrode layers stacked in a stacking direction, and having first and second main surfaces opposing each other in the stacking direction, first and second side surfaces opposing each other in a width direction perpendicular to the stacking direction, and first and second end surfaces opposing each other in a length direction perpendicular to the stacking direction and the width direction; and external electrodes provided on each of the first end surfaces and the second end surfaces and electrically connected to the plurality of internal electrode layers, wherein the element body includes a first outer layer portion located on the first main surface side of an internal electrode layer that is located furthest to the first main surface in the stacking direction among the plurality of internal electrode layers, and a second outer layer portion located on the second main surface side of an internal electrode layer that is located furthest to the second main surface in the stacking direction among the plurality of internal electrode layers, each of the first outer layer portion and the second outer layer portion includes an outermost layer portion arranged on the outside, and an inner outer layer portion located inside the outermost layer portion, a maximum height of the irregularities on the outer surface of the outermost layer portion is smaller than a maximum height of the irregularities on the outer surface of the inner outer layer portion.

2. The multilayer ceramic capacitor according to claim 1, wherein the outermost layer is composed of a coating layer containing Si and K.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the inner outer layer portion is formed of a portion of the plurality of dielectric layers.

4. The multilayer ceramic capacitor according to claim 2, wherein the covering layer covers both ends of the plurality of internal electrode layers in the width direction.

5. The multilayer ceramic capacitor according to claim 4, wherein a portion of the covering layer covering both ends of the plurality of internal electrode layers in the width direction is sandwiched between adjacent dielectric layers of the plurality of dielectric layers in the stacking direction.

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