Photodetector and method for manufacturing photodetector

Abstract

Provided are a photodetector with which it is possible to suppress any deterioration in performance, and a method for manufacturing the photodetector. This photodetector comprises: a semiconductor substrate that has a first surface and a second surface positioned on the opposite side from the first surface; a plurality of pixels that are provided to the semiconductor substrate and have photoelectric conversion elements; and an inter-pixel separation part that is provided to the semiconductor substrate and separates one pixel from another adjacent pixel, among the plurality of pixels. The inter-pixel separation part has a trench that opens to the first-surface side of the semiconductor substrate, and an embedded film that is embedded in the trench. The embedded film includes a first portion, a second portion that is positioned between the first portion and the first surface and is such that the line width in a first direction parallel to the first surface is greater than that in the first portion, and a third portion that is positioned between the second portion and the first surface and is such that the line width in the first direction is greater than that in the second portion.

Description

Photodetector and method for manufacturing the same

[0001] The present disclosure relates to a light detection device and a method for manufacturing a light detection device.

[0002] An imaging device is known that includes a plurality of pixels provided on a semiconductor substrate and an inter-pixel isolation portion provided on the semiconductor substrate to isolate the pixels, the inter-pixel isolation portion penetrating the semiconductor substrate in the depth direction (see, for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2018-148116

[0004] When a high-concentration layer containing a high concentration of impurities is formed along the sidewall of the inter-pixel isolation portion, a strong electric field is likely to be generated between the high-concentration layer and the gate electrode of the transfer transistor (hereinafter also referred to as the transfer gate). This strong electric field generates a large number of electrons, and if the generated electrons unintentionally flow into the floating diffusion, there is a possibility that the performance of the imaging device will be degraded, for example, by the occurrence of white spots.

[0005] The present disclosure has been made in view of the above circumstances, and aims to provide a photodetector capable of suppressing degradation in performance and a method for manufacturing a photodetector.

[0006] According to one aspect of the present disclosure, there is provided a photodetector device including a semiconductor substrate having a first surface and a second surface opposite to the first surface, a plurality of pixels provided on the semiconductor substrate, each having a photoelectric conversion element, and an inter-pixel isolation portion provided on the semiconductor substrate to separate adjacent pixels from each other among the plurality of pixels. The inter-pixel isolation portion includes a trench opening toward the first surface of the semiconductor substrate and a buried film buried in the trench. The buried film includes a first portion, a second portion located between the first portion and the first surface, the second portion having a line width in a first direction parallel to the first surface that is wider than that of the first portion, and a third portion located between the second portion and the first surface, the second portion having a line width in the first direction that is wider than that of the second portion.

[0007] According to this, the inter-pixel isolation portion can be formed by removing a high-concentration impurity layer formed in the trench and then filling the trench with a buried film after the high-concentration layer has been removed. Because the high-concentration layer is removed during the process of forming the inter-pixel isolation portion, the generation of a strong electric field caused by the high-concentration layer can be suppressed. For example, the generation of white spots due to a strong electric field can be suppressed. From the above, it is possible to provide a photodetector device capable of suppressing performance degradation.

[0008] A method for manufacturing a photodetector according to one aspect of the present disclosure includes the steps of forming a plurality of pixels, each having a photoelectric conversion element, on a semiconductor substrate having a first surface and a second surface opposite the first surface, and forming an inter-pixel separation portion on the semiconductor substrate that separates adjacent pixels from each other among the plurality of pixels.

[0009] the step of forming the inter-pixel isolation portion includes the steps of: etching the first surface side of the semiconductor substrate to form a first trench; forming sidewalls on side surfaces of the first trench; etching a bottom surface of the first trench with the sidewalls formed thereon to form a second trench from the bottom surface toward the second surface; epitaxially growing a semiconductor layer on the side surfaces of the second trench; ion-implanting a first impurity of a first conductivity type from the first surface side toward the semiconductor layer; etching the semiconductor layer into which the first impurity has been ion-implanted from the first surface side to remove a portion of the semiconductor layer; removing the sidewalls from the side surfaces of the first trench after removing the portion of the semiconductor layer;

[0010] This allows the above-mentioned inter-pixel isolation portion to be formed. In the process of forming the inter-pixel isolation portion, the layer containing the first impurity at a high concentration (i.e., the high-concentration layer) can be removed by etching (e.g., etch-back) from the first surface side. This makes it possible to suppress the generation of a strong electric field caused by the high-concentration layer, and for example, to suppress the generation of white spots caused by the strong electric field. From the above, it is possible to manufacture a photodetector device capable of suppressing performance degradation.

[0011] FIG. 1 is a block diagram showing an example of the overall configuration of an imaging device according to a first embodiment of the present disclosure. FIG. 2 is a horizontal cross-sectional view showing an example of the configuration of one pixel (i.e., one pixel) of the imaging device according to the first embodiment of the present disclosure. FIG. 3 is a vertical cross-sectional view showing an example of the configuration of one pixel of the imaging device according to the first embodiment of the present disclosure. FIG. 4 is a cross-sectional view showing an example of the configuration of an inter-pixel isolation section and its periphery according to the first embodiment of the present disclosure. FIG. 5 is a cross-sectional view showing, in process order, a method for manufacturing an inter-pixel isolation section and its periphery according to the first embodiment of the present disclosure. FIG. 6 is a cross-sectional view showing, in process order, a method for manufacturing an inter-pixel isolation section and its periphery according to the first embodiment of the present disclosure. FIG. 7 is a cross-sectional view showing, in process order, a method for manufacturing an inter-pixel isolation section and its periphery according to the first embodiment of the present disclosure. FIG. 8 is a cross-sectional view schematically showing the flow of charge (e−) in the periphery of the inter-pixel isolation section according to the first embodiment of the present disclosure. FIG. 9 is a cross-sectional view showing an example of the configuration of an inter-pixel isolation section according to a first comparative example of the present disclosure. FIG. 10 is a cross-sectional view showing an example of the configuration of an inter-pixel isolation section according to a second comparative example of the present disclosure. FIG. 11 is a plan view schematically showing a first modification of the imaging device according to the first embodiment of the present disclosure. FIG. 12 is a plan view schematically illustrating a second modified example of the imaging device according to the first embodiment of the present disclosure. FIG. 13 is a cross-sectional view illustrating a method for manufacturing an inter-pixel isolation portion and its periphery according to the second embodiment of the present disclosure. FIG. 14 is a cross-sectional view illustrating an example configuration of an inter-pixel isolation portion and its periphery according to the third embodiment of the present disclosure. FIG. 15 is a cross-sectional view illustrating a modified example of an inter-pixel isolation portion and its periphery according to the third embodiment of the present disclosure. FIG. 16 is a cross-sectional view illustrating an example configuration of an inter-pixel isolation portion according to the fourth embodiment of the present disclosure. FIG. 17 is a cross-sectional view illustrating a method for manufacturing an inter-pixel isolation portion according to the fifth embodiment of the present disclosure. FIG. 18 is a cross-sectional view illustrating an example configuration of an inter-pixel isolation portion and its periphery according to the sixth embodiment of the present disclosure. FIG. 19 is a cross-sectional view illustrating, in the order of steps, a method for manufacturing an inter-pixel isolation portion and its periphery according to the seventh embodiment of the present disclosure. FIG. 20 is a cross-sectional view illustrating a method for manufacturing an inter-pixel isolation portion and its periphery according to the eighth embodiment of the present disclosure.

[0012] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the drawings referred to in the following description, identical or similar parts are designated by identical or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Furthermore, it goes without saying that the drawings may include parts with different dimensional relationships and ratios.

[0013] Furthermore, the definitions of directions such as up and down in the following explanation are merely for the convenience of explanation and do not limit the technical idea of ​​the present disclosure. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if an object is rotated 180 degrees and observed, up and down are obviously read as reversed.

[0014] In the following description, directions may be described using the terms X-axis, Y-axis, and Z-axis. For example, the X-axis and Y-axis directions are directions parallel to the surface 10a of the semiconductor substrate 10, which will be described later. The Z-axis direction is a direction perpendicular to the surface 10a of the semiconductor substrate 10, and is also the thickness direction of the semiconductor substrate 10. The X-axis, Y-axis, and Z-axis directions are perpendicular to each other.

[0015] In the following description, + and - may be added to P and N, which indicate the conductivity type of a semiconductor region. A semiconductor region with + and - added means that it has a relatively higher or lower impurity concentration, respectively, compared to a semiconductor region without + and - added. However, even if semiconductor regions are added with the same P and P (or the same N and N), this does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

[0016] <First Embodiment> (Example of Overall Configuration of Imaging Device) Fig. 1 is a block diagram showing an example of the overall configuration of an imaging device 1 according to a first embodiment of the present disclosure. The imaging device 1 is an example of the "photodetection device" of the present disclosure, and is, for example, a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor used in electronic devices such as digital still cameras and digital video cameras. The imaging device 1 captures incident light (image light) from a subject via an optical lens system (not shown), converts the amount of incident light imaged on an imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs the electrical signal as a pixel signal.

[0017] As shown in FIG. 1, the imaging device 1 includes a plurality of pixels 12 , a vertical drive circuit 13 , a column signal processing circuit 14 , a horizontal drive circuit 15 , an output circuit 16 , and a control circuit 17 .

[0018] Each pixel 12 is a light-receiving region that receives light collected by an optical system (not shown). The pixels 12 are arranged in a matrix in a pixel region 11 of a semiconductor substrate 10. The pixels 12 are connected row by row to a vertical drive circuit 13 via horizontal signal lines 22, and are connected column by column to a column signal processing circuit 14 via vertical signal lines 23. Each pixel 12 outputs a pixel signal at a level corresponding to the amount of light received. An image of the subject is constructed from these pixel signals.

[0019] The vertical drive circuit 13 sequentially supplies drive signals for driving (transferring, selecting, resetting, etc.) each of the pixels 12 to the pixels 12 for each row of the pixels 12 via horizontal signal lines 22. The column signal processing circuit 14 performs CDS (Correlated Double Sampling) processing on pixel signals output from the pixels 12 via vertical signal lines 23, thereby performing AD conversion of the pixel signals and removing reset noise.

[0020] The horizontal drive circuit 15 supplies drive signals to the column signal processing circuit 14 for causing the column signal processing circuit 14 to output pixel signals to data output signal lines 24, sequentially for each column of the pixels 12. The output circuit 16 amplifies the pixel signals supplied from the column signal processing circuit 14 via the data output signal lines 24 at timings according to the drive signals from the horizontal drive circuit 15, and outputs the amplified signals to a downstream signal processing circuit. The control circuit 17 controls the driving of each block within the imaging device 1. For example, the control circuit 17 generates clock signals according to the drive cycles of each block and supplies them to each block.

[0021] The pixel 12 includes a photodiode 31, a transfer transistor 32, a floating diffusion 33, an amplification transistor 34, a selection transistor 35, and a reset transistor 36. The transfer transistor 32, the floating diffusion 33, the amplification transistor 34, the selection transistor 35, and the reset transistor 36 configure a readout circuit 30 that reads out the charge (pixel signal) photoelectrically converted by the photodiode 31.

[0022] The photodiode 31 is a photoelectric conversion element that converts incident light into electric charges through photoelectric conversion and stores the electric charges, and has an anode terminal grounded and a cathode terminal connected to the transfer transistor 32. The transfer transistor 32 is driven in accordance with a transfer signal TRG supplied from the vertical drive circuit 13, and when the transfer transistor 32 is turned on, the electric charges stored in the photodiode 31 are transferred to the floating diffusion 33. The floating diffusion 33 is a floating diffusion region having a predetermined storage capacitance connected to the gate electrode of the amplification transistor 34, and temporarily stores the electric charges transferred from the photodiode 31.

[0023] The amplification transistor 34 outputs a pixel signal at a level corresponding to the charge accumulated in the floating diffusion 33 (i.e., the potential of the floating diffusion 33) to the vertical signal line 23 via the selection transistor 35. In other words, with the configuration in which the floating diffusion 33 is connected to the gate electrode of the amplification transistor 34, the floating diffusion 33 and the amplification transistor 34 function as a conversion unit that amplifies the charge generated in the photodiode 31 and converts it into a pixel signal at a level corresponding to the charge.

[0024] The selection transistor 35 is driven in accordance with a selection signal SEL supplied from the vertical drive circuit 13, and when the selection transistor 35 is turned on, the pixel signal output from the amplification transistor 34 is ready to be output to the vertical signal line 23. The reset transistor 36 is driven in accordance with a reset signal RST supplied from the vertical drive circuit 13, and when the reset transistor 36 is turned on, the charge accumulated in the floating diffusion 33 is discharged to the drain power supply Vdd, and the floating diffusion 33 is reset.

[0025] (Pixel Configuration Example) FIG. 2 is a horizontal cross-sectional view showing a configuration example of one pixel 12 (i.e., one pixel) of the imaging device 1 according to the first embodiment of the present disclosure. The horizontal direction is a direction parallel to the surface 10a of the semiconductor substrate 10, for example, directions parallel to the X-axis direction and the Y-axis direction. FIG. 3 is a vertical cross-sectional view showing a configuration example of one pixel of the imaging device 1 according to the first embodiment of the present disclosure. The vertical direction is a direction perpendicular to the surface 10a of the semiconductor substrate 10 (the top surface in FIG. 3), for example, a direction parallel to the Z-axis direction. The cross-section of FIG. 3 taken at the position of line X1-X1' corresponds to FIG. 2.

[0026] 2 and 3 , the imaging device 1 includes a photodiode (PD) 31 provided inside a semiconductor substrate 10, and an inter-pixel isolation portion 50 provided to surround the photodiode 31. The semiconductor substrate 10 is, for example, a single-crystal silicon (Si) substrate. The inter-pixel isolation portion 50 includes, for example, a trench H penetrating the semiconductor substrate 10 in the thickness direction (i.e., the depth direction; Z-axis direction), a polysilicon film 51 (an example of the “buried film” of the present disclosure) buried in the trench H, and a silicon oxide film (SiO film) 53 provided in the trench H and covering the polysilicon film 51 from the surface 10 a side.

[0027] Between the photodiode 31 and the inter-pixel isolation section 50, a P-type layer 43 (an example of the "first impurity layer" in the present disclosure) and an N-type layer 41 (an example of the "second impurity layer" in the present disclosure) are provided in this order from the inter-pixel isolation section 50 side toward the photodiode 31. The P-type layer 43 and the N-type layer 41 are provided along the inter-pixel isolation section 50. As a result, a PN junction portion between the P-type layer 43 and the N-type layer 41 forms a strong electric field region and holds the charge generated in the photodiode 31.

[0028] A light-shielding film 47 that prevents light from leaking to adjacent pixels is formed on the back surface 10b (the bottom surface in FIG. 3 ) side of the inter-pixel isolation portion 50. The light-shielding film 47 is made of a metal material such as W (tungsten). An OCL (on-chip lens) 49 that focuses incident light onto the photodiode 31 is formed on the back surface 10b side of the semiconductor substrate 10.

[0029] A transfer transistor 32 and a floating diffusion (FD) 33 are provided on the surface 10a side of the semiconductor substrate 10. Charges (e.g., electrons) generated in the photodiode 31 are transferred to the floating diffusion 33 by the transfer transistor 32. Furthermore, pixel transistors Tr such as an amplifier transistor 34 (see FIG. 1), a selection transistor 35 (see FIG. 1), and a reset transistor 36 (see FIG. 1) are provided on the surface 10a side of the semiconductor substrate 10.

[0030] An inter-element isolation portion 39 is provided in an active region (e.g., Pwell) 37 on the front surface 10a side of the semiconductor substrate 10. The inter-element isolation portion 39 is configured by, for example, STI (Shallow Trench Isolation). The inter-element isolation portion 39 electrically isolates the pixel transistor Tr from surrounding elements.

[0031] 4 is a cross-sectional view showing a configuration example of the inter-pixel isolation portion 50 and its surrounding area according to the first embodiment of the present disclosure. As shown in Fig. 4, the inter-pixel isolation portion 50 has, for example, a trench H penetrating the semiconductor substrate 10 in the thickness direction (i.e., the depth direction; Z-axis direction), a polysilicon film 51 embedded in the trench H, and a SiO film 53 provided in the trench H and covering the polysilicon film 51 from the front surface 10a side. Although not shown, an insulating film such as a SiO film is interposed between the polysilicon film 51 and the side surface of the trench H.

[0032] The polysilicon film 51 has a first portion 511, a second portion 512, and a third portion 513, arranged in this order from the back surface 10b side toward the front surface 10a side of the semiconductor substrate 10. The first portion 511 is located on the back surface 10b side of the semiconductor substrate 10. An end portion of the first portion 511 on the back surface 10b side of the semiconductor substrate 10 (the lower end portion in FIG. 4 ) is exposed from the back surface 10b while being flush or nearly flush with the back surface 10b. The first portion 511 and the second portion 512, and the second portion 512 and the third portion 513 are connected to each other in the Z-axis direction, which is perpendicular to the front surface 10a of the semiconductor substrate 10.

[0033] The second portion 512 is located between the first portion 511 and the surface 10a of the semiconductor substrate 10. In a direction parallel to the surface 10a of the semiconductor substrate 10 (the X-axis direction in FIG. 4 ), the line width of the second portion 512 is wider than the line width of the first portion 511. The third portion 513 is located between the second portion 512 and the surface 10a of the semiconductor substrate 10. In a direction parallel to the surface 10a of the semiconductor substrate 10 (the X-axis direction in FIG. 4 ), the line width of the third portion 513 is wider than the line width of the second portion 512. In this way, the line widths of the polysilicon film 51 become wider in the order of the first portion 511, the second portion 512, and the third portion 513.

[0034] The cross-sectional shape of the polysilicon film 51 cut along the XZ plane parallel to the X-axis direction and the Z-axis direction is symmetrical with respect to a straight line CL parallel to the Z-axis direction.

[0035] 4, the P-type layer 43 is adjacent to the first portion 511. Furthermore, the N-type layer 41 is adjacent to the first portion 511 with the P-type layer 43 interposed therebetween.

[0036] The semiconductor substrate 10 also has a P-type layer 55 (an example of a "third impurity layer" in the present disclosure) adjacent to the third portion 513. The P-type layer 55 has a lower P-type impurity concentration than the P-type layer 43. The P-type layer 55 is provided, for example, continuously from the bottom surface of the third portion 513 to the side surface of the second portion 512. Although not shown in FIG. 4 , the P-type layer 55 may also be provided on the side surface of the third portion 513. The P-type layer 55 may also be provided continuously from the side surface of the third portion 513, passing through the bottom surface of the third portion 513, to the side surface of the second portion 512.

[0037] 4 , a gate electrode (i.e., transfer gate) 321 of the transfer transistor 32 is disposed between the floating diffusion 33 and the inter-pixel isolation portion 50. The transfer gate 321 has, for example, a vertical electrode 321V buried from the surface 10a of the semiconductor substrate 10 to the interior of the semiconductor substrate 10, and a horizontal electrode 321H provided on the surface 10a of the semiconductor substrate 10. The vertical electrode 321V and the horizontal electrode 321H are connected to each other. Although not shown, a gate insulating film such as a SiO film is interposed between the transfer gate 321 and the semiconductor substrate 10.

[0038] (Manufacturing Method) Next, a method for manufacturing the inter-pixel isolation portion 50 and its peripheral portion shown in Fig. 4 will be described. Note that the imaging device 1 including the inter-pixel isolation portion 50 is manufactured using various types of equipment, such as a film formation apparatus (including a CVD (Chemical Vapor Deposition) apparatus, a thermal oxidation furnace, a sputtering apparatus, a resist coating apparatus, etc.), an exposure apparatus, an ion implantation apparatus, an annealing apparatus, an etching apparatus, a CMP (Chemical Mechanical Polishing) apparatus, etc. Hereinafter, these apparatuses will be collectively referred to as manufacturing apparatuses.

[0039] 5 to 7 are cross-sectional views illustrating a manufacturing method of the inter-pixel isolation portion 50 and its surrounding area according to the first embodiment of the present disclosure in a process order. In step ST1 of FIG. 5 , a silicon oxide film (SiO film) 61, a silicon nitride film (SiN film) 63, and a SiO film 66 are stacked in this order on the surface 10a of the semiconductor substrate 10. The manufacturing equipment partially removes a stacked film 67 consisting of the SiO film 61, the SiN film 63, and the SiO film 65 using photolithography and dry etching techniques to form an opening h having a bottom surface on the surface 10a of the semiconductor substrate 10. The opening h is formed between adjacent pixels 12 among a plurality of pixels 12 (see FIG. 4 ).

[0040] 5 , the manufacturing equipment uses the stacked film 67 as a mask to dry-etch the semiconductor substrate 10 to form a first trench H1. Next, the manufacturing equipment thermally oxidizes the front surface 10a side of the semiconductor substrate 10 to form a SiO film 69 on the bottom and side surfaces of the first trench H1 that are exposed from the stacked film 67.

[0041] 5, the manufacturing equipment forms a SiN film 71 on the bottom and side surfaces of the first trench H1 on which the SiO film 69 is formed. The SiN film 71 is formed by, for example, a CVD method.

[0042] 5 , the manufacturing equipment etches back the front surface 10a of the semiconductor substrate 10 to leave the SiN film 71 on the side surface of the first trench H1 and remove the SiN film 71 from other regions (for example, on the stacked film 67 and on the bottom surface of the first trench H1). As a result, the stacked film of the SiO film 69 and the SiN film 71 remains as sidewalls 73 on the side surface of the first trench H1.

[0043] Next, as shown in step ST5 of FIG. 6, the manufacturing equipment uses the stacked film 67 and the sidewall 73 as a mask to dry-etch the bottom surface of the first trench T1, thereby forming a second trench T2 from the bottom surface of the first trench T1 toward the back surface 10b.

[0044] Next, as shown in step ST6 of FIG. 6 , the manufacturing equipment epitaxially grows a semiconductor layer 75 on the side and bottom surfaces of the second trench H2. For example, the semiconductor substrate 10 is a single-crystal Si substrate, and the semiconductor layer 75 is a single-crystal Si layer. Here, phosphorus (P), which is an N-type impurity, may be introduced into the semiconductor layer 75 during the epitaxial growth process (i.e., in-situ). As a result, an N-type layer 41 (see FIGS. 3 and 4 ) is formed over the entire semiconductor layer 75.

[0045] Next, as shown in step ST7 of FIG. 6 , the manufacturing equipment ions-implants boron (B), a P-type impurity, from the surface 10a of the semiconductor substrate 10 toward the semiconductor layer 75. This boron (B) is an example of the "first impurity of the first conductivity type" of the present disclosure. Unlike the oblique ion implantation described below, this ion implantation is performed at a normal angle. The normal angle is an angle that is approximately perpendicular to the surface 10a of the semiconductor substrate 10. As a result, boron (B) is introduced at a higher concentration into the top and bottom surfaces of the semiconductor layer 75 (i.e., flat surfaces parallel to the surface 10a) than into the side surfaces of the semiconductor layer 75.

[0046] For example, the top surface of the semiconductor layer 75 becomes a high-concentration layer 431T containing boron (B) at a high concentration, and the bottom surface of the semiconductor layer 75 becomes a high-concentration layer 431B containing boron (B) at a high concentration. In addition, the side surface of the semiconductor layer 75 becomes a low-concentration layer 431S having a lower concentration of boron (B) than the high-concentration layers 431T and 431B.

[0047] Next, as shown in step ST8 of FIG. 6, the manufacturing equipment etches back the semiconductor layer 75 from the front surface 10a side to remove the portions of the semiconductor layer 75 into which boron (B) has been introduced at a high concentration (i.e., the top surface and the bottom surface).

[0048] Next, the manufacturing equipment applies heat treatment to the entire substrate including the semiconductor layer 75 to activate the boron (B) ions implanted into the semiconductor layer 75. As a result, a P-type layer 43 is formed on the side surface of the semiconductor layer 75. Furthermore, the portion of the semiconductor layer 75 where the P-type layer 43 is not formed becomes an N-type layer 41. Because the portion of the semiconductor layer 75 where boron (B) was introduced at a high concentration was removed before the heat treatment, it is possible to prevent a P-type high concentration layer from being formed in the semiconductor layer 75.

[0049] 7, the manufacturing equipment removes the sidewalls 73 covering the side surfaces of the first trenches H1 by, for example, wet etching.

[0050] 7, the manufacturing equipment thermally oxidizes the semiconductor substrate 10 to form a SiO film 77 in the first trench H1 and the second trench H2. Next, the manufacturing equipment obliquely ions-implants boron (B), which is a P-type impurity, toward the side surface of the first trench H1, an exposed region 79 that is part of the side surface of the second trench H2 and is exposed from the semiconductor layer 75, and the upper surface of the semiconductor layer 75. This boron (B) is an example of the "third impurity of the first conductivity type" of the present disclosure. The dose of boron (B) is, for example, 1×10 １１ cm －２ 1x10 or more １４ cm －２ That is, the dose of boron (B) is less than 10 １１ cm －２ 10 from the table １３ cm －２ The dose of boron (B) in the oblique ion implantation shown in step ST10 is lower than the dose of boron (B) in the ion implantation shown in step ST7.

[0051] Next, the manufacturing equipment applies a heat treatment to the entire substrate including the semiconductor layer 75 to activate the boron (B) ions implanted into the exposed region 79 of the second trench H2, etc. As a result, a P-type layer 55 is formed in the exposed region 79 of the second trench H2, etc.

[0052] Next, the manufacturing equipment forms a polysilicon film 51 on the front surface 10a of the semiconductor substrate 10. The polysilicon film 51 is formed by, for example, a CVD method. Next, as shown in step ST11 of FIG. 7 , the manufacturing equipment performs a CMP process on the polysilicon film 51 to remove the polysilicon film 51 from the front surface 10a of the semiconductor substrate 10, while leaving the polysilicon film 51 in the first trench H1 and the second trench H2.

[0053] Next, as shown in step ST12 of FIG. 7 , the manufacturing equipment partially removes the upper portion of the polysilicon film 51 to form a third trench H3. The third trench H3 may be formed at a position overlapping the upper portion of the first trench H1. Next, the manufacturing equipment forms a SiO film 53 on the surface 10a of the semiconductor substrate 10 by, for example, a CVD method, and fills the third trench H3 with the SiO film 53. Next, the manufacturing equipment performs a CMP process on the SiO film 53 to remove the SiO film 53 from the surface 10a of the semiconductor substrate 10, leaving the SiO film 53 in the third trench H3. The process of forming the third trench H3, the process of forming the SiO film 53, and the subsequent CMP process may be performed in conjunction with the process of forming the element isolation portion 39 shown in FIG. 2 , or may be performed separately from the process of forming the element isolation portion 39.

[0054] Thereafter, the manufacturing equipment grinds the back surface 10b of the semiconductor substrate 10 to expose the polysilicon film 51 on the back surface 10b. Through the above steps, the inter-pixel isolation portion 50 that penetrates between the front surface 10a and the back surface 10b of the semiconductor substrate 10 and its peripheral portion are completed.

[0055] Effect of First Embodiment As described above, the imaging device 1 according to the first embodiment of the present disclosure includes a semiconductor substrate 10 having a front surface 10a and a back surface 10b located on the opposite side of the front surface 10a, a plurality of pixels 12 provided on the semiconductor substrate 10 and each having a photodiode 31, and an inter-pixel isolation portion 50 provided on the semiconductor substrate 10 and isolating adjacent pixels 12 from each other among the plurality of pixels 12. The inter-pixel isolation portion 50 includes a trench H that opens toward the front surface 10a of the semiconductor substrate 10, and a polysilicon film 51 embedded in the trench H. The polysilicon film 51 has a first portion 511, a second portion 512 located between the first portion 511 and the surface 10a and having a line width in a first direction parallel to the surface 10a (e.g., the X-axis direction or the Y-axis direction) wider than that of the first portion 511, and a third portion 513 located between the second portion 512 and the surface 10a and having a line width in the first direction wider than that of the second portion 512.

[0056] The inter-pixel isolation portion 50 can be formed by removing a layer containing a high concentration of P-type impurities (for example, the high-concentration layer 431T) formed in the trench H, and filling the trench H from which the high-concentration layer 431T has been removed with a polysilicon film 51. Because the high-concentration layer 431T is removed in the process of forming the inter-pixel isolation portion 50, it is possible to suppress the generation of a strong electric field caused by the high-concentration layer 431T.

[0057] For example, it is possible to suppress the generation of a strong electric field between the high-concentration layer 431T and the N-type floating diffusion 33. If a strong electric field is generated between the high-concentration layer 431T and the N-type floating diffusion 33, electrons may be accelerated and enter the depletion layer between the high-concentration layer 431T and the floating diffusion 33, generating a large number of electron-hole pairs. If the large number of generated electrons flow into the floating diffusion 33, white spots may occur. In the imaging device 1, the high-concentration layer 431T is removed in the process of forming the inter-pixel isolation portion 50, so the generation of white spots can be suppressed. From the above, it is possible to provide an imaging device 1 that can suppress performance degradation.

[0058] A manufacturing method of an imaging device 1 according to a first embodiment of the present disclosure includes the steps of forming a plurality of pixels 12, each having a photodiode 31, on a semiconductor substrate 10 having a front surface 10a and a back surface 10b opposite to the front surface 10a, and forming an inter-pixel isolation portion 50 in the semiconductor substrate 10, which isolates adjacent pixels 12 from one of the plurality of pixels 12. The step of forming the inter-pixel isolation portion 50 includes the steps of etching the front surface 10a side of the semiconductor substrate 10 to form a first trench H1, forming sidewalls 73 on the side surfaces of the first trench H1, etching the bottom surface of the first trench H1 with the sidewalls 73 formed thereon to form a second trench H2 from the bottom surface of the first trench H1 toward the back surface 10b, epitaxially growing a semiconductor layer 75 on the side surface of the second trench H2, and growing a first conductive layer 76 from the front surface 10a side of the semiconductor substrate 10 toward the semiconductor layer 75. the step of ion-implanting a first impurity (e.g., boron (B)) of the type; the step of etching (e.g., etch-back) the semiconductor layer 75 into which the first impurity has been ion-implanted from the surface 10a side to remove a part of the semiconductor layer 75 (e.g., high-concentration layers 431T, 431B); the step of removing the sidewalls 73 from the side surfaces of the first trench H1 after removing the part of the semiconductor layer 75; and the step of forming a polysilicon film 51 in the first trench H1 and the second trench H2 after removing the sidewalls 73.

[0059] This allows the above-described inter-pixel isolation portion 50 to be formed. In the process of forming the inter-pixel isolation portion 50, layers containing a high concentration of the first impurity (e.g., high-concentration layers 431T, 431B) can be removed by etching (e.g., etch-back) from the surface 10a side of the semiconductor substrate 10. This makes it possible to suppress the generation of a strong electric field caused by the high-concentration layer 431T, and, for example, to suppress the generation of white spots caused by the strong electric field. From the above, it is possible to manufacture an imaging device 1 capable of suppressing performance degradation.

[0060] Furthermore, with the imaging device 1, it is possible to expect improved transfer of charges (e-) from a deep portion of the semiconductor substrate 10 (i.e., the back surface 10b side) to a shallow portion (i.e., the front surface 10a side). FIG. 8 is a cross-sectional view schematically showing the flow of charges (e-) in the peripheral portion of the inter-pixel isolation portion 50 according to the first embodiment of the present disclosure. As shown in FIG. 8, the inter-pixel isolation portion 50 has multiple steps in the trench H compared to the inter-pixel isolation portions 1050 and 1150 of Comparative Examples 1 and 2 shown in FIGS. 9 and 10 described below. As a result, the side surfaces of the polysilicon film 51 embedded in the trench H also have multiple steps.

[0061] For example, a first step G1 exists between the first portion 511 and the second portion 512 of the polysilicon film 51, and a second step G2 exists between the second portion 512 and the third portion 513 of the polysilicon film 51. As a result, as shown by the arrows in Figure 8, the charge transfer path from the deep portion to the shallow portion along the inter-pixel isolation portion 50 becomes smoother and the transfer path becomes shorter, which can be expected to improve transfer.

[0062] 9 is a cross-sectional view showing a configuration example of an inter-pixel isolation portion 1050 according to Comparative Example 1 of the present disclosure. Unlike the inter-pixel isolation portion 50 according to Embodiment 1 of the present disclosure, the inter-pixel isolation portion 1050 shown in Fig. 9 is formed without performing the step of removing a portion of the semiconductor layer 75 shown in step ST8 of Fig. 6 (i.e., the step of removing a high-concentration layer containing a high concentration of boron (B)). As a result, in Comparative Example 1, a high-concentration layer is present on the sidewall of the inter-pixel isolation portion 1050.

[0063] The high-concentration layer of Comparative Example 1 is close to the transfer gate and the floating diffusion 33, and therefore a strong electric field is likely to be formed between the high-concentration layer and the floating diffusion 33. This strong electric field causes electrons to accelerate into the depletion layer between the high-concentration layer and the floating diffusion 33, and a large number of electron-hole pairs are likely to be generated. If a large number of generated electrons flow into the floating diffusion 33, the possibility of white spots occurring increases.

[0064] 10 is a cross-sectional view showing an example configuration of an inter-pixel isolation portion 1150 according to Comparative Example 2 of the present disclosure. In the inter-pixel isolation portion 1150 shown in FIG. 10, the high-concentration layer is spaced further away from the floating diffusion 33 than in the inter-pixel isolation portion 1050 shown in FIG. 9. This structure can be achieved by forming the first trench H1 (see, for example, step ST2 in FIG. 5) deeper when forming the inter-pixel isolation portion 1050 of Comparative Example 1. In Comparative Example 2, the high-concentration layer and the floating diffusion 33 are spaced apart in the depth direction, which makes it possible to suppress the occurrence of white spots due to a strong electric field.

[0065] On the other hand, in the region R1 separated in the depth direction, the P-type impurity concentration on the sidewall of the inter-pixel isolation portion is lowered and the PN junction is reduced, which may result in a substantial reduction in the volume of the photodiode 31 and a decrease in the saturated charge amount (Qs).

[0066] 9 and 10 , the step of removing a portion of the semiconductor layer 75 shown in step ST8 in Fig. 6 is not performed, and therefore the steps of the trench H are not multi-stepped and are not smooth compared to the inter-pixel isolation portion 50 according to the first embodiment of the present disclosure. As a result, in comparative examples 1 and 2, the transfer path of the electric field from the deep portion to the shallow portion of the semiconductor substrate 10 takes a shape that largely detours around the trench H, and the transfer path is likely to be long.

[0067] (Modification of First Embodiment) In the first embodiment described above, for example, as shown in Fig. 3, a mode has been described in which the transfer transistor 32 and other pixel transistors Tr (e.g., the amplification transistor 34, the selection transistor 35, the reset transistor 36, etc.) are provided on the semiconductor substrate 10 on which the pixels 12 and the inter-pixel isolation portions 50 are formed. In other words, a mode has been described in which the imaging device 1 is made up of a single semiconductor substrate.

[0068] However, embodiments of the present disclosure are not limited to this. In embodiments of the present disclosure, the semiconductor substrate constituting the imaging device 1 may be a laminated substrate in which two or more semiconductor substrates are stacked. For example, a first semiconductor substrate may be provided with the pixels 12, the inter-pixel isolation portion 50, and the transfer transistor 32, and a second semiconductor substrate may be provided with pixel transistors Tr other than the transfer transistor 32 (e.g., the amplification transistor 34, the selection transistor 35, and the reset transistor 36), and the second semiconductor substrate may be stacked on the opposite side of the light-receiving surface of the first semiconductor substrate.

[0069] 11 is a plan view schematically illustrating a first variation of the imaging device 1 according to the first embodiment of the present disclosure. Variation 1 illustrated in FIG. 11 illustrates a configuration example of a first semiconductor substrate 10 when the semiconductor substrates constituting the imaging device 1 are laminated substrates. A cross section of the plan view of FIG. 11 taken along line A-A' corresponds to the cross section illustrated in FIG. 4. As illustrated in FIG. 11, the semiconductor substrate 10 is provided with a plurality of pixels 12, inter-pixel isolation sections 50 that isolate the pixels 12, and transfer transistors 32 that transfer charge from the photodiode 31 to the floating diffusion 33 in each pixel 12.

[0070] The pixel transistors Tr other than the transfer transistor 32 (for example, the amplification transistor 34, the selection transistor 35, and the reset transistor 36) are provided on a second semiconductor substrate (not shown) stacked on the opposite side of the light-receiving surface of the semiconductor substrate 10.

[0071] The pixel 12 shown in Fig. 11 may be divided into a plurality of pixels. Fig. 12 is a plan view schematically illustrating a second modification of the imaging device 1 according to the first embodiment of the present disclosure. Similar to the first modification shown in Fig. 11, the second modification shown in Fig. 12 illustrates a configuration example of the first semiconductor substrate 10 when the semiconductor substrates constituting the imaging device 1 are laminated substrates.

[0072] 12 , the pixel 12 includes a first pixel 12R, a second pixel 12L disposed adjacent to the first pixel 12R, and a connecting portion 121 connecting the first pixel 12R and the second pixel 12L. The first pixel 12R includes a first photodiode PD1 and a first transfer gate (not shown). The second pixel 12L includes a second photodiode PD2 and a second transfer gate (not shown). The connecting portion 121 is made of the same material (e.g., Si) as the semiconductor substrate 10.

[0073] The first photodiode PD1 and the second photodiode PD2 each correspond to the photodiode 31 shown in Fig. 1. The first photodiode PD1 and the second photodiode PD2 each function as an imaging pixel during normal imaging, and function as a pair of phase difference detection pixels during phase difference detection.

[0074] During phase difference detection, each of the plurality of pixels 12 detects the phase difference by detecting the difference (or the ratio of pixel signals) between pixel signals based on the charges generated by a pair of first photodiode PD1 and second photodiode PD2. This phase difference is detected as a differential signal by, for example, the output circuit 16 shown in FIG. 1 , and the amount of defocus is calculated based on the detected phase difference, and an imaging lens (not shown) is adjusted (moved), thereby realizing autofocus.

[0075] The connecting portion 121 electrically isolates the pair of first and second photodiodes PD1 and PD2 during phase difference detection and functions as an overflow path during normal image capture. During normal image capture, if charge in one of the first and second photodiodes PD1 and PD2 approaches saturation, the overflow path allows charge to move from one of the first and second photodiodes PD1 and PD2 to the other, thereby preventing charge saturation. This ensures linearity of the pixel signal output from the pixel 12 and prevents degradation of the captured image. The inter-pixel isolation portion 50 surrounds the first and second photodiodes PD1 and PD2 and physically isolates adjacent pixels 12 from each other.

[0076] 11 and 12, similarly to the first embodiment, the high-concentration layer 431T (see step ST7 in FIG. 6) is removed, so that the occurrence of white spots caused by a strong electric field can be suppressed. Furthermore, because the trench H is multi-staged, the charge transfer path along the inter-pixel isolation portion 50 becomes smoother and shorter. This can be expected to improve charge transfer.

[0077] 7 , the P-type layer 55 is formed by obliquely implanting boron (B), a P-type impurity, into the side surface of the first trench H1 and the exposed region 79, which is a part of the side surface of the second trench H2 and is exposed from the semiconductor layer 75. However, in the embodiments of the present disclosure, the method for forming the P-type layer 55 is not limited to obliquely implanting ions. For example, the P-type impurity boron (B) may be implanted at a normal angle.

[0078] 13 is a cross-sectional view showing a manufacturing method of the inter-pixel isolation portion 50 and its surrounding area according to the second embodiment of the present disclosure. In the manufacturing method shown in FIG. 13, the oblique ion implantation of boron (B) shown in step ST10 of FIG. 7 is not performed. Instead, after forming the SiO film 53 on the surface 10a of the semiconductor substrate 10 in step ST12 of FIG. 7, the manufacturing equipment forms a mask M1 on the SiO film 53, as shown in FIG. 13. The mask M1 is made of, for example, resist, and has a shape that opens above the inter-pixel isolation portion 50 and above the region where the P-type layer 55 is to be formed, and covers the other regions.

[0079] Next, the manufacturing equipment ion-implants boron (B), a P-type impurity, at a normal angle into the region that is open from under the mask M1. This introduces boron into the region where the P-type layer 55 is to be formed. The manufacturing equipment then removes the mask M1 from the surface 10a of the semiconductor substrate 10. Next, the manufacturing equipment applies heat treatment to the entire substrate including the semiconductor layer 75 to activate the boron (B) ion-implanted at the normal angle. This forms the P-type layer 55.

[0080] The manufacturing method according to the second embodiment also makes it possible to form the inter-pixel isolation portion 50 and its surrounding area, similar to the first embodiment. In the second embodiment, the high-concentration layer 431T (see step ST7 in FIG. 6 ) is removed, similar to the first embodiment, so that the occurrence of white spots caused by a strong electric field can be suppressed. Furthermore, since the trench H is multi-staged, the charge transfer path along the inter-pixel isolation portion 50 becomes smooth and the transfer path is shortened. This can be expected to improve the charge transfer. The modified example of the first embodiment can also be applied to the second embodiment.

[0081] Third Embodiment In the first embodiment described above, the transfer gate 321 is disposed between the inter-pixel isolation portion 50 and the floating diffusion 33. However, the embodiments of the present disclosure are not limited to this.

[0082] 14 is a cross-sectional view showing a configuration example of an inter-pixel isolation section 50 and its surrounding area according to a third embodiment of the present disclosure. In an embodiment of the present disclosure, as shown in FIG. 14, a floating diffusion 33 may be present between the inter-pixel isolation section 50 and the transfer gate 321. Even in this configuration, as in the first embodiment, the high-concentration layer 431T (see step ST7 in FIG. 6) is removed, thereby making it possible to suppress the occurrence of white spots caused by a strong electric field. Note that the modified example of the first embodiment can also be applied to the third embodiment.

[0083] (Modification of Embodiment 3) FIG. 15 is a cross-sectional view showing a modification of the inter-pixel isolation portion 50 and its surrounding area according to Embodiment 3 of the present disclosure. As shown in FIG. 15, the transfer gate 321 may be composed of only a horizontal electrode 321H provided on the surface 10a of the semiconductor substrate 10. In other words, the transfer gate 321 may not have a vertical electrode 321V. Even in this embodiment, the high-concentration layer 431T (see step ST7 in FIG. 6) is removed, thereby suppressing the occurrence of white spots caused by a strong electric field. This modification is also applicable to the above-described Embodiment 1 and its modifications, as well as Embodiment 2.

[0084] Fourth Embodiment In the first embodiment described above, the polysilicon film 51 is used as an example of the "buried film" of the present disclosure. However, in the embodiments of the present disclosure, the "buried film" is not limited to the polysilicon film.

[0085] FIG. 16 is a cross-sectional view showing an example configuration of an inter-pixel isolation portion 50 according to a fourth embodiment of the present disclosure. In the inter-pixel isolation portion shown in FIG. 16, an insulating film having a negative fixed charge may be used as an example of the "buried film" of the present disclosure. The fixed charge film 51A shown in FIG. 16 is an example of an insulating film having a negative fixed charge. Even in this configuration, as in the first embodiment, the high-concentration layer 431T (see step ST7 in FIG. 6 ) is removed, thereby suppressing the occurrence of white spots caused by a strong electric field.

[0086] Furthermore, the fixed charge film 51A can pin the charges (holes) in the P-type layer 43, which can further strengthen the electric field at the PN junction between the P-type layer 43 and the N-type layer 41. This makes it easier to retain the charges generated in the photodiode 31, potentially further increasing the saturation charge quantity (Qs) of the photodiode 31.

[0087] 7, the back surface 10b of the semiconductor substrate 10 is ground to expose the polysilicon film 51 from the back surface 10b, and then the polysilicon film 51 is etched from the back surface 10b side to remove it from the trench H. Thereafter, the fixed charge film 51A may be formed in the trench from the back surface 10b side.

[0088] Embodiment 5 In the above-described embodiment 1, for example, as shown in step ST8 of FIG. 6 , the semiconductor layer 75 is etched back from the front surface 10 a side to remove the portions of the semiconductor layer 75 into which boron (B) is introduced at a high concentration (i.e., the high-concentration layers 431T and 431B). Step ST8 of FIG. 6 illustrates an aspect in which the upper surface of the semiconductor layer 75 after the etch-back is parallel to the front surface 10 a of the semiconductor substrate 10. However, in embodiments of the present disclosure, the upper surface of the semiconductor layer 75 after the etch-back does not have to be parallel to the front surface 10 a of the semiconductor substrate 10.

[0089] 17 is a cross-sectional view showing a manufacturing method of the inter-pixel isolation portion 50 according to the fifth embodiment of the present disclosure. As shown in Fig. 17, the upper surface of the semiconductor layer 75 after the etch-back in step ST8 of Fig. 6 may be inclined with respect to the surface 10a of the semiconductor substrate 10 (i.e., may have a tapered shape). Even in this case, as in the first embodiment, the high-concentration layer 431T (see step ST7 of Fig. 6) is removed, so that the occurrence of white spots caused by a strong electric field can be suppressed.

[0090] 17 and subsequent steps in the method for manufacturing the inter-pixel isolation portion 50 according to the fifth embodiment are the same as steps ST10 to ST12 in FIG. 7 described in the first embodiment. Through these steps, the inter-pixel isolation portion 50 according to the fifth embodiment is completed.

[0091] Sixth Embodiment In an embodiment of the present disclosure, the buried film constituting the inter-pixel isolation portion may be a conductive film, such as a polysilicon film doped with impurities. In addition, when the buried film is a conductive film, a bias may be applied to the buried film.

[0092] 18 is a cross-sectional view showing a configuration example of an inter-pixel isolation portion 50 and its surrounding area according to a sixth embodiment of the present disclosure. The polysilicon film 51 shown in FIG. 18 is doped with an N-type impurity such as phosphorus (P), and is therefore conductive. In the inter-pixel isolation portion 50 according to the sixth embodiment, a negative bias is applied to the conductive polysilicon film 51. This allows for stronger pinning of charges (holes) in the P-type layer 55, thereby further strengthening the electric field at the PN junction between the P-type layer 43 and the N-type layer 41.

[0093] In the sixth embodiment, as in the first embodiment, the high-concentration layer 431T (see step ST7 in FIG. 6) is removed, so that the occurrence of white spots caused by a strong electric field can be suppressed.

[0094] Furthermore, by applying a negative bias to the polysilicon film 51, a positive charge can be induced on the side surface of the trench H adjacent to the inter-pixel isolation portion 50, and therefore, for example, as in region R2 in Fig. 18, the P-type layer 55 (see, for example, Fig. 4) provided on the side surface of the shallow portion of the trench H may be omitted. The P-type layer 55 is formed, for example, by oblique ion implantation of boron (B) shown in step ST10 in Fig. 7, but omitting the P-type layer 55 eliminates the need for this oblique ion implantation step, which contributes to shortening the manufacturing process.

[0095] Seventh Embodiment In the first embodiment described above, the semiconductor layer 75 is epitaxially grown on the side surface of the second trench H2, as shown in step ST6 of Fig. 6. However, for example, if the opening end of the second trench H2 narrows relative to the depth thereof (i.e., bows), the step of forming the semiconductor layer 75 by epitaxial growth may be omitted.

[0096] FIG. 19 is a cross-sectional view showing a manufacturing method for the pixel isolation portion 50 and its surrounding area according to a seventh embodiment of the present disclosure in the order of steps. Step ST21 in FIG. 19 corresponds to a modification of step ST5 shown in FIG. 6. Step ST21 illustrates a case where the second trench H2 has a narrow line width and is formed so that its opening end is narrower relative to its depth (i.e., bowed). In the seventh embodiment, after the second trench H2 is formed, a semiconductor layer is not epitaxially grown on the side surface of the second trench H2. As shown in step ST22 in FIG. 19, the manufacturing equipment ions implants boron (B), a P-type impurity, into the second trench H2 at a normal angle without epitaxially growing a semiconductor layer.

[0097] As a result, boron (B) is introduced at a high concentration into a bowing portion (hereinafter referred to as a bowing portion) 91 on the side surface of the second trench H2 and into the bottom surface of the second trench H2. In the seventh embodiment, the upper layer portion of the bowing portion 91 becomes a high-concentration layer 431T, and the bottom surface of the trench H having the bowing portion 91 becomes a high-concentration layer 431B.

[0098] Next, as shown in step ST23 of FIG. 19, the manufacturing equipment etches back the semiconductor layer 75 from the front surface 10a side to remove the high concentration layers 431T and 431B into which boron (B) has been introduced at a high concentration.

[0099] Next, the manufacturing equipment applies a heat treatment to the entire substrate including the semiconductor layer 75 to activate the boron (B) ions implanted into the semiconductor layer 75. As a result, a P-type layer 43 is formed on the side surface of the second trench H2. Furthermore, the portion of the side surface of the second trench H2 where the P-type layer 43 is not formed becomes an N-type layer 41. Because the portions of the bowing portion 91 and bottom surface of the second trench H2 where boron (B) was introduced at a high concentration were removed before the heat treatment, it is possible to prevent a P-type high concentration layer from being formed on the bowing portion 91 and bottom surface of the second trench H2.

[0100] 19, the manufacturing equipment removes the sidewalls 73 covering the side surfaces of the first trenches H1. The sidewalls are removed by, for example, wet etching. The subsequent steps are the same as those from step ST10 onward in FIG. 7 described in the first embodiment.

[0101] According to the manufacturing method of the seventh embodiment, similarly to the first embodiment, the high-concentration layer 431T is removed, so that the occurrence of white spots caused by a strong electric field can be suppressed.

[0102] Furthermore, the manufacturing method according to the seventh embodiment does not require the step of forming the semiconductor layer 75 by epitaxial growth, which contributes to shortening the manufacturing process.

[0103] 6, the stacked film 67 and the sidewall 73 are used as a mask to implant boron (B), a P-type impurity, from the surface 10a of the semiconductor substrate 10 toward the semiconductor layer 75. However, the embodiments of the present disclosure are not limited to this. In step ST7 of FIG. 6, an N-type impurity such as phosphorus (P) or arsenic (As) may be implanted instead of the P-type impurity, or both the P-type impurity and the N-type impurity may be implanted sequentially.

[0104] FIG. 20 is a cross-sectional view showing a manufacturing method of the inter-pixel isolation portion 50 and its surrounding area according to the eighth embodiment of the present disclosure. FIG. 20 corresponds to a modification of step ST7 shown in FIG. 20. In FIG. 20, using the stacked film 67 and the sidewall 73 as a mask, phosphorus (P), an N-type impurity, is ion-implanted from the surface 10a of the semiconductor substrate 10 toward the semiconductor layer 75. In the eighth embodiment, this phosphorus (P) is an example of the "first impurity of the first conductivity type" of the present disclosure. This ion implantation is performed at a normal angle. As a result, phosphorus (P) is introduced at a higher concentration into the top and bottom surfaces of the semiconductor layer 75 than into the side surfaces of the semiconductor layer 75.

[0105] For example, the top surface of the semiconductor layer 75 becomes a high-concentration layer 411T, and the bottom surface of the semiconductor layer 75 becomes a high-concentration layer 411B. The side surface of the semiconductor layer 75 becomes a low-concentration layer 411S having a lower concentration of phosphorus (P) than the high-concentration layers 411T and 411B.

[0106] Next, the manufacturing equipment etches back the semiconductor layer 75 from the front surface 10a side to remove the portions of the semiconductor layer 75 into which phosphorus (P) has been introduced at a high concentration (i.e., the high-concentration layers 411T, 411B). Next, the manufacturing equipment applies a heat treatment to the entire substrate including the semiconductor layer 75 to activate the phosphorus (P) ions implanted into the semiconductor layer 75. As a result, an N-type layer 41 is formed in the semiconductor layer 75. Because the portions of the semiconductor layer 75 into which phosphorus (P) has been introduced at a high concentration are removed before the heat treatment, it is possible to prevent the formation of an N-type high-concentration layer in the semiconductor layer 75.

[0107] In the eighth embodiment of the present disclosure, after forming the N-type layer 41 as described above, boron (B), a P-type impurity, may be ion-implanted from the surface 10a of the semiconductor substrate 10 toward the semiconductor layer 75 using the stacked film 67 and the sidewalls 73 as a mask. In this case, after the boron (B) ion implantation, the semiconductor layer 75 is etched back again from the surface 10a to remove the portions of the semiconductor layer 75 where boron (B) is highly doped (e.g., the high-concentration layers 431T and 431B shown in step ST7 of FIG. 6 ). The manufacturing equipment then performs a heat treatment on the entire substrate including the semiconductor layer 75 again to activate the boron (B) ion-implanted into the semiconductor layer 75. This forms a P-type layer 43 (see step ST8 of FIG. 6 ) in the semiconductor layer 75, which is bonded to the N-type layer 41. The subsequent steps are the same as steps ST9 to ST12 of FIG. 7 described in the first embodiment. Through these steps, the inter-pixel isolation portion 50 is completed.

[0108] According to the manufacturing method of the eighth embodiment, the high-concentration layers 411T and 431T are removed, so that the occurrence of white spots caused by a strong electric field can be suppressed.

[0109] Furthermore, according to the manufacturing method of the eighth embodiment, a structure can be formed in which the P-type layer 43 and the N-type layer 41 are stacked in this order from the inside to the outside of the second trench H2. The P-type impurity concentration in the P-type layer 43 and the N-type impurity concentration in the N-type layer 41 can be adjusted by the dose amount in ion implantation, etc. Therefore, for example, it is easy to form a steep high electric field at the PN junction interface between the P-type layer 43 and the N-type layer 41. This may further increase the saturation charge (Qs) of the photodiode 31.

[0110] (Other Embodiments) As described above, the present disclosure has been described with reference to embodiments and modifications. However, the descriptions and drawings that form part of this disclosure should not be understood to limit the present disclosure. Various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure. It goes without saying that the present technology includes various embodiments not described herein. Various omissions, substitutions, and / or modifications of components may be made without departing from the spirit of the above-described embodiments and modifications. Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0111] The present disclosure may also be configured as follows: (1) A photodetector comprising: a semiconductor substrate having a first surface and a second surface located opposite to the first surface, a plurality of pixels provided on the semiconductor substrate and each having a photoelectric conversion element, and an inter-pixel isolation portion provided on the semiconductor substrate and isolating one of the plurality of pixels from the other adjacent pixel, the inter-pixel isolation portion having: a trench opening toward the first surface of the semiconductor substrate; and a buried film buried in the trench, the buried film having: a first portion, a second portion located between the first portion and the first surface, the second portion having a line width in a first direction parallel to the first surface that is wider than that of the first portion, and a third portion located between the second portion and the first surface, the third portion having a line width in the first direction that is wider than that of the second portion. (2) The photodetector according to (1), wherein a cross-sectional shape of the buried film cut by a plane parallel to the first direction and a second direction orthogonal to the first surface is symmetrical about a line parallel to the second direction. (3) The photodetector according to (1) or (2), wherein the first portion and the second portion, and the second portion and the third portion are connected in the second direction orthogonal to the first surface. (4) The photodetector according to any one of (1) to (3), wherein the buried film has a first step between the first portion and the second portion, and a second step between the second portion and the third portion. (5) The photodetector according to any one of (1) to (4), further comprising a first impurity layer of a first conductivity type provided in the semiconductor substrate and adjacent to the first portion. (6) The photodetector according to (5), further comprising: a second impurity layer of a second conductivity type provided in the semiconductor substrate and adjacent to the first portion via the first impurity layer. (7) The photodetector according to any one of (1) to (6), further comprising: a third impurity layer of the first conductivity type provided in the semiconductor substrate and adjacent to the second portion. (8) The photodetector according to any one of (1) to (7), wherein the inter-pixel isolation portion penetrates between the first surface and the second surface of the semiconductor substrate. (9) The photodetector according to any one of (1) to (8), wherein the buried film is a polysilicon film.(10) The photodetector according to any one of (1) to (8), wherein the buried film is an insulating film having a negative fixed charge. (11) The photodetector according to any one of (1) to (10), further comprising: a floating diffusion provided on the first surface side of the semiconductor substrate; and a transfer transistor provided on the first surface side of the semiconductor substrate, the transfer transistor transferring charges generated in the photoelectric conversion element to the floating diffusion. (12) The photodetector according to (11), wherein a gate electrode of the transfer transistor is disposed between the floating diffusion and the inter-pixel isolation portion. (13) A method for manufacturing a semiconductor device, comprising: forming a plurality of pixels, each having a photoelectric conversion element, on a semiconductor substrate having a first surface and a second surface opposite to the first surface; and forming an inter-pixel isolation portion in the semiconductor substrate that isolates one adjacent pixel from the other adjacent pixel of the plurality of pixels, wherein the step of forming the inter-pixel isolation portion includes the steps of: etching the first surface side of the semiconductor substrate to form a first trench; forming sidewalls on side surfaces of the first trench; etching a bottom surface of the first trench with the sidewalls formed thereon to form a second trench from the bottom surface toward the second surface; epitaxially growing a semiconductor layer on side surfaces of the second trench; ion-implanting a first impurity of a first conductivity type from the first surface side toward the semiconductor layer; etching the semiconductor layer into which the first impurity has been ion-implanted from the first surface side to remove a portion of the semiconductor layer; and removing the sidewalls from the side surfaces of the first trench after removing the portion of the semiconductor layer. (14) The method for manufacturing a photodetector according to (13), wherein the step of forming the inter-pixel isolation portion further includes the step of, after removing the part of the semiconductor layer, performing a heat treatment on the semiconductor layer to form a first impurity layer of a first conductivity type on a side surface of the semiconductor layer, and the step of removing the sidewall is performed after the step of forming the first impurity layer.(15) The method for manufacturing a photodetector according to (13) or (14), wherein the step of forming the inter-pixel isolation portion further includes the step of: forming a second impurity layer of a second conductivity type in the semiconductor layer before ion-implanting the first impurity. (16) The method for manufacturing a photodetector according to any one of (13) to (15), further including the steps of: obliquely ion-implanting a third impurity of the first conductivity type into an exposed region that is part of a side surface of the second trench and is exposed from the semiconductor layer after removing the sidewall; and performing a heat treatment on the semiconductor substrate after oblique ion-implanting the third impurity, thereby forming a third impurity layer of the first conductivity type in the exposed region of the second trench, wherein a dose of the third impurity in the oblique ion-implanting of the third impurity is lower than a dose of the first impurity in the ion-implanting of the first impurity, and the step of forming the buried film is performed after the step of forming the third impurity layer. (17) The method for manufacturing a photodetector described in any one of (13) to (16), wherein the step of forming the inter-pixel isolation portion further includes a step of grinding the second surface of the semiconductor substrate after forming the buried film to expose the buried film on the second surface.

[0112] 1 Imaging device 10 Semiconductor substrate 10a Front surface 10b Back surface 11 Pixel region 12 Pixel 12L Second pixel 12R First pixel 13 Vertical drive circuit 14 Column signal processing circuit 15 Horizontal drive circuit 16 Output circuit 17 Control circuit 22 Horizontal signal line 23 Vertical signal line 24 Data output signal line 30 Readout circuit 31 Photodiode (PD) 32 Transfer transistor 33 Floating diffusion (FD) 34 Amplification transistor 35 Selection transistor 36 Reset transistor 37 Active region 39 Inter-element isolation section 41 N-type layer 43 P-type layer 47 Light-shielding film 50, 1050, 1150 Inter-pixel isolation section 51 Polysilicon film 51A Fixed charge film 53, 61, 56, 66, 69, 77 Silicon oxide film (SiO film) 55 P-type layer 63, 71 Silicon nitride film (SiN film) 67 Stacked film 73 Sidewall 75 Semiconductor layer 79 Exposed region 91 Bowing portion 121 Connecting portion 321 Transfer gate 321H Horizontal electrode 321V Vertical electrode 411B, 411T, 431B, 431T Highly-doped layer 411S, 431S Low-doped layer 511 First portion 512 Second portion 513 Third portion G1 First step G2 Second step h Opening H Trench H1 First trench H2 Second trench H3 Third trench M1 Mask PD1 First photodiode PD2 Second photodiode Qs Saturation charge amount R1, R2 Region Tr Pixel transistor

Claims

1. A photodetector comprising: a semiconductor substrate having a first surface and a second surface located opposite the first surface; a plurality of pixels provided on the semiconductor substrate, each having a photoelectric conversion element; and an inter-pixel isolation portion provided on the semiconductor substrate and isolating one of the plurality of pixels from the other adjacent pixel, the inter-pixel isolation portion having a trench opening to the first surface side of the semiconductor substrate, and a buried film buried in the trench, the buried film having a first portion, a second portion located between the first portion and the first surface, the second portion having a line width in the first direction parallel to the first surface wider than that of the first portion, and a third portion located between the second portion and the first surface, the third portion having a line width in the first direction wider than that of the second portion.

2. The optical detection device described in claim 1, wherein the cross-sectional shape of the embedded film cut by a plane parallel to the first direction and a second direction perpendicular to the first surface is symmetrical with respect to a straight line parallel to the second direction.

3. The optical detection device of claim 1, wherein the first portion and the second portion, and the second portion and the third portion are each connected in a second direction perpendicular to the first surface.

4. The optical detection device as described in claim 1, wherein the buried film has a first step between the first portion and the second portion, and a second step between the second portion and the third portion.

5. The photodetector according to claim 1, further comprising a first impurity layer of a first conductivity type provided on said semiconductor substrate and adjacent to said first portion.

6. The photodetector according to claim 5, further comprising a second impurity layer of a second conductivity type provided on said semiconductor substrate and adjacent to said first portion with said first impurity layer interposed therebetween.

7. The photodetector according to claim 1, further comprising a third impurity layer of the first conductivity type provided on said semiconductor substrate and adjacent to said second portion.

8. The photodetector according to claim 1, wherein the inter-pixel isolation portion penetrates between the first surface and the second surface of the semiconductor substrate.

9. The photodetection device of claim 1, wherein the buried film is a polysilicon film.

10. The photodetector according to claim 1, wherein the buried film is an insulating film having a negative fixed charge.

11. The photodetector device according to claim 1, further comprising: a floating diffusion provided on the first surface side of the semiconductor substrate; and a transfer transistor provided on the first surface side of the semiconductor substrate, which transfers charges generated by the photoelectric conversion element to the floating diffusion.

12. The photodetection device according to claim 11, wherein a gate electrode of the transfer transistor is disposed between the floating diffusion and the inter-pixel isolation portion.

13. A method for manufacturing a semiconductor device, comprising: forming a plurality of pixels, each having a photoelectric conversion element, on a semiconductor substrate having a first surface and a second surface opposite to the first surface; and forming an inter-pixel isolation portion in the semiconductor substrate that isolates one pixel from the other pixel, the plurality of pixels being adjacent to each other. The step of forming the inter-pixel isolation portion includes the steps of: etching the first surface side of the semiconductor substrate to form a first trench; forming a sidewall on a side surface of the first trench; etching a bottom surface of the first trench with the sidewall formed therein to form a second trench from the bottom surface toward the second surface; epitaxially growing a semiconductor layer on a side surface of the second trench; ion-implanting a first impurity of a first conductivity type from the first surface side toward the semiconductor layer; etching the semiconductor layer into which the first impurity has been ion-implanted from the first surface side to remove a portion of the semiconductor layer; and removing the sidewall from the side surface of the first trench after removing the portion of the semiconductor layer. and forming a buried film in the first trench and the second trench after removing the sidewalls.

14. The method for manufacturing a photodetector described in claim 13, wherein the step of forming the inter-pixel isolation portion further comprises the step of performing a heat treatment on the semiconductor layer after removing the portion of the semiconductor layer to form a first impurity layer of a first conductivity type on a side surface of the semiconductor layer, and the step of removing the sidewall is performed after the step of forming the first impurity layer.

15. The method for manufacturing a photodetector according to claim 13, wherein the step of forming the inter-pixel isolation portion further comprises the step of forming a second impurity layer of a second conductivity type in the semiconductor layer before ion-implanting the first impurity.

16. A method for manufacturing a photodetector as described in claim 13, further comprising the steps of: after removing the sidewall, obliquely ion-implanting a third impurity of the first conductivity type into an exposed region which is a part of the side surface of the second trench and is exposed from the semiconductor layer; and after the oblique ion-implantation of the third impurity, subjecting the semiconductor substrate to a heat treatment to form a third impurity layer of the first conductivity type in the exposed region of the second trench, wherein a dose of the third impurity in the oblique ion-implantation of the third impurity is lower than a dose of the first impurity in the ion-implantation of the first impurity, and the step of forming the buried film is performed after the step of forming the third impurity layer.

17. The method for manufacturing a photodetector as described in claim 13, wherein the step of forming the inter-pixel isolation portion further comprises the step of grinding the second surface of the semiconductor substrate after forming the buried film to expose the buried film on the second surface.

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