Semiconductor device, electronic apparatus, and vehicle

Abstract

A semiconductor device (200) is provided with, for example, at least one voltage drive circuit (DRV1H) that voltage-drives a switch control signal (Vg), and a current drive circuit (DRV2H) that current-drives the switch control signal (Vg). The at least one voltage drive circuit (DRV1H) is turned on in some periods (T1, T2, T4) among a plurality of periods (T1 to T4) included in a logic level transition period (Ton_tr) of the switch control signal (Vg), and is turned off in the remaining period (T3). The current drive circuit (DRV2H) is turned on in all of the plurality of periods (T1 to T4).

Description

Semiconductor devices, electronic devices, vehicles

[0001] The present disclosure relates to a semiconductor device, an electronic device, and a vehicle.

[0002] BACKGROUND ART Signal transmission devices that transmit signals between a primary circuit system and a secondary circuit system while electrically insulating the primary circuit system from the secondary circuit system have been used in various applications (such as power supply devices or motor drive devices).

[0003] An example of the related prior art is Patent Document 1 by the applicant of the present application.

[0004] International Publication No. 2022 / 070944

[0005] [Summary] In conventional signal transmission devices, there is room for further consideration regarding optimization of the slew rate.

[0006] For example, a semiconductor device according to the present disclosure includes at least one voltage drive circuit configured to voltage-drive a switch control signal, and a current drive circuit configured to current-drive the switch control signal, wherein the at least one voltage drive circuit is turned on during a portion of a plurality of periods included in a logic level transition period of the switch control signal and turned off during the remaining periods, and the current drive circuit is turned on during all of the plurality of periods.

[0007] FIG. 1 is a diagram showing the basic configuration of a signal transmission device. FIG. 2 is a diagram showing the basic structure of a transformer chip. FIG. 3 is a perspective view of a semiconductor device used as a two-channel transformer chip. FIG. 4 is a plan view of the semiconductor device shown in FIG. 3. FIG. 5 is a plan view showing a layer in which a low-potential coil is formed in the semiconductor device of FIG. 3. FIG. 6 is a plan view showing a layer in which a high-potential coil is formed in the semiconductor device of FIG. 3. FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. 6. FIG. 8 is an enlarged view (separation structure) of region XIII shown in FIG. 7. FIG. 9 is a diagram schematically showing an example layout of a transformer chip. FIG. 10 is a diagram showing a first comparative example of an electronic device. FIG. 11 is a diagram showing a second comparative example of an electronic device. FIG. 12 is a diagram showing a first embodiment of the electronic device. FIG. 13 is a diagram showing turn-on control of the first embodiment. FIG. 14 is a diagram showing turn-on control (modification) of the first embodiment. FIG. 15 is a diagram showing turn-off control of the first embodiment. FIG. 16 is a diagram showing a second embodiment of the electronic device. FIG. 17 is a diagram showing turn-on control of the second embodiment. Fig. 18 is a diagram showing the turn-off control of the second embodiment. Fig. 19 is a diagram showing the external appearance of the vehicle.

[0008] [Detailed Description] <Signal Transmission Device (Basic Configuration)> Figure 1 shows the basic configuration of a signal transmission device. The signal transmission device 200 of this configuration example is a semiconductor integrated circuit device (a so-called insulated gate driver IC) that transmits a pulse signal from the primary circuit system 200p to the secondary circuit system 200s while isolating the primary circuit system 200p (VCC1-GND1 system) from the secondary circuit system 200s (VCC2-GND2 system) and drives the gate of a switch element (not shown) provided in the secondary circuit system 200s. For example, the signal transmission device 200 is formed by sealing a controller chip 210, a driver chip 220, and a transformer chip 230 in a single package.

[0009] The controller chip 210 is a semiconductor chip that operates by receiving a power supply voltage VCC1 (for example, a maximum of 7 V with respect to GND1). The controller chip 210 has integrated therein, for example, a pulse transmission circuit 211 and buffers 212 and 213.

[0010] The pulse transmitting circuit 211 is a pulse generator that generates transmission pulse signals S11 and S21 in response to the input pulse signal IN. More specifically, when the pulse transmitting circuit 211 notifies that the input pulse signal IN is at a high level, it pulse-drives the transmission pulse signal S11 (outputting a single or multiple transmission pulses), and when it notifies that the input pulse signal IN is at a low level, it pulse-drives the transmission pulse signal S21. In other words, the pulse transmitting circuit 211 pulse-drives either the transmission pulse signal S11 or S21 in response to the logic level of the input pulse signal IN.

[0011] The buffer 212 receives the transmission pulse signal S11 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 231).

[0012] The buffer 213 receives the transmission pulse signal S21 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 232).

[0013] The driver chip 220 is a semiconductor chip that operates by receiving a power supply voltage VCC2 (for example, a maximum of 30 V relative to GND2). The driver chip 220 integrates, for example, buffers 221 and 222, a pulse receiving circuit 223, and a driver 224.

[0014] The buffer 221 shapes the waveform of the received pulse signal S12 induced in the transformer chip 230 (specifically, the transformer 231) and outputs the result to the pulse receiving circuit 223.

[0015] The buffer 222 shapes the waveform of the received pulse signal S22 induced in the transformer chip 230 (specifically, the transformer 232) and outputs the result to the pulse receiving circuit 223.

[0016] The pulse receiving circuit 223 generates the output pulse signal OUT by driving the driver 224 in response to the received pulse signals S12 and S22 input via the buffers 221 and 222. More specifically, the pulse receiving circuit 223 drives the driver 224 so that the output pulse signal OUT rises to a high level in response to the pulse driving of the received pulse signal S12, and the output pulse signal OUT falls to a low level in response to the pulse driving of the received pulse signal S22. In other words, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT in response to the logic level of the input pulse signal IN. Note that an RS flip-flop, for example, can be suitably used as the pulse receiving circuit 223.

[0017] The driver 224 generates an output pulse signal OUT based on the drive control of the pulse receiving circuit 223 .

[0018] The transformer chip 230 provides DC insulation between the controller chip 210 and the driver chip 220 using transformers 231 and 232, and outputs transmission pulse signals S11 and S21 input from the pulse transmission circuit 211 as reception pulse signals S12 and S22, respectively, to the pulse reception circuit 223. In this specification, "DC-insulated" means that the objects to be insulated are not connected by a conductor.

[0019] More specifically, the transformer 231 outputs a received pulse signal S12 from the secondary coil 231s in response to a transmitted pulse signal S11 input to the primary coil 231p, while the transformer 232 outputs a received pulse signal S22 from the secondary coil 232s in response to a transmitted pulse signal S21 input to the primary coil 232p.

[0020] As described above, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (corresponding to a rise signal and a fall signal), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0021] In addition, the signal transmission device 200 of this configuration example has an independent transformer chip 230 equipped with only transformers 231 and 232, separate from the controller chip 210 and driver chip 220, and these three chips are sealed in a single package.

[0022] With this configuration, the controller chip 210 and the driver chip 220 can both be formed using a general low to medium voltage withstand process (withstand voltage of several volts to several tens of volts), eliminating the need to use a dedicated high voltage withstand process (withstand voltage of several kV), thereby making it possible to reduce manufacturing costs.

[0023] The signal transmission device 200 can be suitably used, for example, in a power supply device or a motor drive device for on-board equipment mounted in a vehicle. The above-mentioned vehicles include not only engine vehicles but also electric vehicles (BEVs [battery electric vehicles], HEVs [hybrid electric vehicles], PHEVs / PHVs (plug-in hybrid electric vehicles / plug-in hybrid vehicles), or xEVs such as FCEVs / FCVs (fuel cell electric vehicles / fuel cell vehicles)).

[0024] <Transformer Chip (Basic Structure)> Next, the basic structure of the transformer chip 230 will be described. Fig. 2 is a diagram showing the basic structure of the transformer chip 230. In the transformer chip 230 shown in this figure, the transformer 231 includes a primary coil 231p and a secondary coil 231s that face each other in the vertical direction. The transformer 232 includes a primary coil 232p and a secondary coil 232s that face each other in the vertical direction.

[0025] The primary coils 231p and 232p are both formed on a first wiring layer (lower layer) 230a of the transformer chip 230. The secondary coils 231s and 232s are both formed on a second wiring layer (upper layer in this figure) 230b of the transformer chip 230. The secondary coil 231s is disposed directly above the primary coil 231p and faces the primary coil 231p. The secondary coil 232s is disposed directly above the primary coil 232p and faces the primary coil 232p.

[0026] The primary coil 231p is laid in a spiral shape starting from a first end connected to the internal terminal X21, surrounding the periphery of the internal terminal X21 in a clockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. On the other hand, the primary coil 232p is laid in a spiral shape starting from a first end connected to the internal terminal X23, surrounding the periphery of the internal terminal X23 in a counterclockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. The internal terminals X21, X22, and X23 are linearly arranged in the order shown in the figure.

[0027] The internal terminal X21 is connected to the external terminal T21 on the second layer 230b via the conductive wiring Y21 and the via Z21. The internal terminal X22 is connected to the external terminal T22 on the second layer 230b via the conductive wiring Y22 and the via Z22. The internal terminal X23 is connected to the external terminal T23 on the second layer 230b via the conductive wiring Y23 and the via Z23. The external terminals T21 to T23 are arranged in a straight line and are used for wire bonding with the controller chip 210.

[0028] The secondary coil 231s is laid in a spiral shape starting from a first end connected to the external terminal T24, surrounding the periphery of the external terminal T24 in a counterclockwise direction, and its second end corresponding to its end point is connected to the external terminal T25. Meanwhile, the secondary coil 232s is laid in a spiral shape starting from a first end connected to the external terminal T26, surrounding the periphery of the external terminal T26 in a clockwise direction, and its second end corresponding to its end point is connected to the external terminal T25. The external terminals T24, T25, and T26 are arranged linearly in the order shown in the figure, and are used for wire bonding with the driver chip 220.

[0029] The secondary coils 231s and 232s are AC-connected to the primary coils 231p and 232p by magnetic coupling, and are DC-insulated from the primary coils 231p and 232p, respectively. That is, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230, and is DC-insulated from the controller chip 210 by the transformer chip 230.

[0030] <Transformer Chip (Two-Channel Type)> FIG. 3 is a perspective view showing a semiconductor device 5 used as a two-channel transformer chip. FIG. 4 is a plan view of the semiconductor device 5 shown in FIG. 3. FIG. 5 is a plan view showing a layer in which the low-potential coil 22 (corresponding to the primary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 6 is a plan view showing a layer in which the high-potential coil 23 (corresponding to the secondary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. 6. FIG. 8 is an enlarged view of region XIII shown in FIG. 7, showing an isolation structure 130.

[0031] 3 to 7, the semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. The semiconductor chip 41 includes at least one of silicon, a wide bandgap semiconductor, and a compound semiconductor.

[0032] The wide bandgap semiconductor is a semiconductor with a bandgap exceeding that of silicon (approximately 1.12 eV). The bandgap of the wide bandgap semiconductor is preferably 2.0 eV or greater. The wide bandgap semiconductor may be silicon carbide (SiC). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0033] In this embodiment, the semiconductor chip 41 includes a silicon semiconductor substrate. The semiconductor chip 41 may be an epitaxial substrate having a layered structure including a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0034] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0035] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long sides of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along the first direction X and face the second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short sides of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in the second direction Y and face the first direction X. The chip sidewalls 44A to 44D are made of ground surfaces.

[0036] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating sidewalls 53A to 53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first main surface 42 in a plan view. The insulating main surface 52 extends parallel to the first main surface 42.

[0037] The insulating sidewalls 53A to 53D include a first insulating sidewall 53A, a second insulating sidewall 53B, a third insulating sidewall 53C, and a fourth insulating sidewall 53D. The insulating sidewalls 53A to 53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are continuous with the chip sidewalls 44A to 44D. Specifically, the insulating sidewalls 53A to 53D are formed flush with the chip sidewalls 44A to 44D. The insulating sidewalls 53A to 53D form ground surfaces that are flush with the chip sidewalls 44A to 44D.

[0038] The insulating layer 51 has a multilayer insulating laminate structure including a bottom insulating layer 55, a top insulating layer 56, and multiple (11 in this embodiment) interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 42. The top insulating layer 56 is an insulating layer that forms the insulating main surface 52. The multiple interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the top insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the top insulating layer 56 also has a single-layer structure containing silicon oxide. The thickness of the bottom insulating layer 55 and the top insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, approximately 2 μm).

[0039] Each of the multiple interlayer insulating layers 57 has a stacked structure including a first insulating layer 58 on the side of the bottom insulating layer 55 and a second insulating layer 59 on the side of the top insulating layer 56. The first insulating layer 58 may contain silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, approximately 0.3 μm).

[0040] The second insulating layer 59 is formed on the first insulating layer 58. The second insulating layer 59 contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, approximately 2 μm). The thickness of the second insulating layer 59 is preferably greater than the thickness of the first insulating layer 58.

[0041] The total thickness DT of the insulating layers 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layers 51 and the number of stacked interlayer insulating layers 57 are arbitrary and are adjusted according to the dielectric strength voltage (dielectric breakdown resistance) to be achieved. Furthermore, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layers 57 are arbitrary and are not limited to a specific insulating material.

[0042] The semiconductor device 5 includes a first functional device 45 formed in an insulating layer 51. The first functional device 45 includes one or more (in this embodiment, multiple) transformers 21 (corresponding to the aforementioned transformers). In other words, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed inward of the insulating layer 51 and spaced apart from the insulating side walls 53A to 53D. The multiple transformers 21 are formed at intervals in the first direction X.

[0043] Specifically, the multiple transformers 21 include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed in this order from the insulating side wall 53C side toward the insulating side wall 53D side in a plan view. The multiple transformers 21A to 21D each have a similar structure. The following description will be given using the structure of the first transformer 21A as an example. The description of the structure of the first transformer 21A applies mutatis mutandis to the description of the structures of the second transformer 21B, third transformer 21C, and fourth transformer 21D, and will be omitted.

[0044] 5 to 7 , the first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed in an insulating layer 51. The high-potential coil 23 is formed in the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. In this embodiment, the low-potential coil 22 and the high-potential coil 23 are formed in a region sandwiched between a lowermost insulating layer 55 and an uppermost insulating layer 56 (i.e., multiple interlayer insulating layers 57).

[0045] The low-potential coil 22 is formed on the side of the lowest insulating layer 55 (semiconductor chip 41) within the insulating layer 51, and the high-potential coil 23 is formed on the side of the highest insulating layer 56 (insulating main surface 52) relative to the low-potential coil 22 within the insulating layer 51. In other words, the high-potential coil 23 faces the semiconductor chip 41 with the low-potential coil 22 sandwiched between them. The low-potential coil 22 and the high-potential coil 23 may be disposed in any desired locations. Furthermore, it is sufficient that the high-potential coil 23 faces the low-potential coil 22 with one or more interlayer insulating layers 57 sandwiched between them.

[0046] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of layers of the interlayer insulating layers 57) is adjusted appropriately depending on the dielectric strength and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this embodiment, the low-potential coil 22 is formed on the third interlayer insulating layer 57 counting from the bottom insulating layer 55 side. In this embodiment, the high-potential coil 23 is formed on the first interlayer insulating layer 57 counting from the top insulating layer 56 side.

[0047] The low-potential coil 22 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first spiral portion 26 that is wound in a spiral shape between the first inner end 24 and the first outer end 25. The first spiral portion 26 is wound in a spiral shape that extends in an elliptical shape (oval shape) in a plan view. The portion that forms the innermost periphery of the first spiral portion 26 defines a first inner region 66 that is elliptical in a plan view.

[0048] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The width of the first helical portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in a direction perpendicular to the helical direction. The first winding pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions of the first helical portion 26 in a direction perpendicular to the helical direction.

[0049] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the form shown in Fig. 5 etc. The first spiral portion 26 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The first inner region 66 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the first spiral portion 26.

[0050] The low-potential coil 22 may include at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may have a layered structure including a barrier layer and a body layer. The barrier layer defines a recess space in the interlayer insulating layer 57. The barrier layer may include at least one of titanium and titanium nitride. The body layer may include at least one of copper, aluminum, and tungsten.

[0051] The high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 wound in a spiral shape between the second inner end 27 and the second outer end 28. The second spiral portion 29 is wound in a spiral shape that extends in an elliptical (oval) shape in a plan view. In this embodiment, the portion forming the innermost periphery of the second spiral portion 29 defines a second inner region 67 that is elliptical in a plan view. The second inner region 67 of the second spiral portion 29 faces the first inner region 66 of the first spiral portion 26 in the normal direction Z.

[0052] The number of turns of the second helical portion 29 may be 5 or more and 30 or less. The number of turns of the second helical portion 29 relative to the number of turns of the first helical portion 26 is adjusted according to the voltage value to be boosted. The number of turns of the second helical portion 29 preferably exceeds the number of turns of the first helical portion 26. Of course, the number of turns of the second helical portion 29 may be less than the number of turns of the first helical portion 26 or may be equal to the number of turns of the first helical portion 26.

[0053] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The width of the second helical portion 29 is preferably 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in a direction perpendicular to the helical direction. The width of the second helical portion 29 is preferably equal to the width of the first helical portion 26.

[0054] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The second winding pitch is preferably 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction perpendicular to the helical direction. The second winding pitch is preferably equal to the first winding pitch of the first helical portion 26.

[0055] The winding shape of the second spiral portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the form shown in Fig. 6 etc. The second spiral portion 29 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The second inner region 67 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the second spiral portion 29.

[0056] The high-potential coil 23 is preferably formed from the same conductive material as the low-potential coil 22. That is, like the low-potential coil 22, the high-potential coil 23 preferably includes a barrier layer and a main body layer.

[0057] 4, the semiconductor device 5 includes a plurality of (12 in this figure) low potential terminals 11 and a plurality of (12 in this figure) high potential terminals 12. The plurality of low potential terminals 11 are electrically connected to the low potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high potential terminals 12 are electrically connected to the high potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0058] The plurality of low potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the plurality of low potential terminals 11 are formed in an area on the insulating sidewall 53B side at intervals in the second direction Y from the plurality of transformers 21A to 21D, and are arranged at intervals in the first direction X.

[0059] The plurality of low potential terminals 11 include a first low potential terminal 11A, a second low potential terminal 11B, a third low potential terminal 11C, a fourth low potential terminal 11D, a fifth low potential terminal 11E, and a sixth low potential terminal 11F. In this embodiment, two of each of the plurality of low potential terminals 11A to 11F are formed. The number of the plurality of low potential terminals 11A to 11F is arbitrary.

[0060] The first low potential terminal 11A faces the first transformer 21A in the second direction Y in a plan view. The second low potential terminal 11B faces the second transformer 21B in the second direction Y in a plan view. The third low potential terminal 11C faces the third transformer 21C in the second direction Y in a plan view. The fourth low potential terminal 11D faces the fourth transformer 21D in the second direction Y in a plan view. The fifth low potential terminal 11E is formed in a region between the first low potential terminal 11A and the second low potential terminal 11B in a plan view. The sixth low potential terminal 11F is formed in a region between the third low potential terminal 11C and the fourth low potential terminal 11D in a plan view.

[0061] The first low potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low potential coil 22). The second low potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low potential coil 22). The third low potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low potential coil 22). The fourth low potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low potential coil 22).

[0062] The fifth low potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low potential coil 22) and the first outer end 25 of the second transformer 21B (low potential coil 22). The sixth low potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low potential coil 22) and the first outer end 25 of the fourth transformer 21D (low potential coil 22).

[0063] The plurality of high potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51 at intervals from the plurality of low potential terminals 11. Specifically, the plurality of high potential terminals 12 are formed in an area on the insulating sidewall 53A side at intervals from the plurality of low potential terminals 11 in the second direction Y, and are arranged at intervals in the first direction X.

[0064] The multiple high potential terminals 12 are each formed in a region close to the corresponding transformer 21A to 21D in a plan view. The closeness of the high potential terminal 12 to the transformer 21A to 21D means that the distance between the high potential terminal 12 and the transformer 21 in a plan view is less than the distance between the low potential terminal 11 and the high potential terminal 12.

[0065] Specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to face the multiple transformers 21A to 21D along the first direction X in a plan view. More specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high potential coil 23 and in a region between adjacent high potential coils 23 in a plan view. As a result, the multiple high potential terminals 12 are arranged in a line with the multiple transformers 21A to 21D in the first direction X in a plan view.

[0066] The plurality of high potential terminals 12 include a first high potential terminal 12A, a second high potential terminal 12B, a third high potential terminal 12C, a fourth high potential terminal 12D, a fifth high potential terminal 12E, and a sixth high potential terminal 12F. In this embodiment, two of each of the plurality of high potential terminals 12A to 12F are formed. The number of the plurality of high potential terminals 12A to 12F is arbitrary.

[0067] The first high potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high potential coil 23) in a plan view. The second high potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high potential coil 23) in a plan view. The third high potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high potential coil 23) in a plan view. The fourth high potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high potential coil 23) in a plan view. The fifth high potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0068] The first high potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high potential coil 23). The second high potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high potential coil 23). The third high potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high potential coil 23). The fourth high potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high potential coil 23).

[0069] The fifth high potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high potential coil 23) and the second outer end 28 of the second transformer 21B (high potential coil 23). The sixth high potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high potential coil 23) and the second outer end 28 of the fourth transformer 21D (high potential coil 23).

[0070] 5 to 7, the semiconductor device 5 includes a first low potential wiring 31, a second low potential wiring 32, a first high potential wiring 33, and a second high potential wiring 34, each formed in an insulating layer 51. In this embodiment, a plurality of the first low potential wirings 31, a plurality of the second low potential wirings 32, a plurality of the first high potential wirings 33, and a plurality of the second high potential wirings 34 are formed.

[0071] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the first transformer 21A and the low-potential coil 22 of the second transformer 21B to the same potential. The first low-potential wiring 31 and the second low-potential wiring 32 also fix the low-potential coil 22 of the third transformer 21C and the low-potential coil 22 of the fourth transformer 21D to the same potential. In this embodiment, the first low-potential wiring 31 and the second low-potential wiring 32 fix all of the low-potential coils 22 of the transformers 21A to 21D to the same potential.

[0072] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. The first high-potential wiring 33 and the second high-potential wiring 34 also fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. In this embodiment, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of the transformers 21A to 21D to the same potential.

[0073] The plurality of first low-potential wirings 31 are electrically connected to the corresponding low-potential terminals 11A to 11D and the first inner ends 24 of the corresponding transformers 21A to 21D (low-potential coils 22), respectively. The plurality of first low-potential wirings 31 have the same structure. In the following, the structure of the first low-potential wiring 31 connected to the first low-potential terminal 11A and the first transformer 21A will be described as an example. The description of the structure of the first low-potential wiring 31 connected to the first transformer 21A applies mutatis mutandis to the description of the structure of the other first low-potential wirings 31, and will be omitted.

[0074] The first low-potential wiring 31 includes a through wiring 71, a low-potential connection wiring 72, a lead-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (multiple in this embodiment) pad plug electrodes 76, and one or more (multiple in this embodiment) substrate plug electrodes 77.

[0075] The through wiring 71, the low-potential connecting wiring 72, the lead-out wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the through wiring 71, the low-potential connecting wiring 72, the lead-out wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0076] The through wiring 71 penetrates the multiple interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape along the normal direction Z. In this embodiment, the through wiring 71 is formed in the region of the insulating layer 51 between the lowermost insulating layer 55 and the uppermost insulating layer 56. The through wiring 71 has an upper end on the uppermost insulating layer 56 side and a lower end on the lowermost insulating layer 55 side. The upper end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the high-potential coil 23 and is covered by the uppermost insulating layer 56. The lower end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the low-potential coil 22.

[0077] In this embodiment, the through wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed from the same conductive material as the low-potential coil 22, etc. In other words, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0078] The first electrode layer 78 forms the upper end of the through wiring 71. The second electrode layer 79 forms the lower end of the through wiring 71. The first electrode layer 78 is formed in an island shape and faces the low potential terminal 11 (first low potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0079] The plurality of wiring plug electrodes 80 are embedded in the plurality of interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 are stacked from the lowermost insulating layer 55 toward the uppermost insulating layer 56 so as to be electrically connected to one another, and electrically connect the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 each have a planar area that is less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0080] The number of stacked wiring plug electrodes 80 corresponds to the number of stacked interlayer insulating layers 57. In this embodiment, six wiring plug electrodes 80 are embedded in each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded in each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 may be formed penetrating the interlayer insulating layers 57.

[0081] The low-potential connecting wiring 72 is formed in the first inner region 66 of the first transformer 21A (low-potential coil 22) in the same interlayer insulating layer 57 as the low-potential coil 22. The low-potential connecting wiring 72 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The low-potential connecting wiring 72 preferably has a planar area that exceeds the planar area of ​​the wiring plug electrode 80. The low-potential connecting wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0082] The lead-out wiring 73 is formed in the interlayer insulating layer 57 in a region between the semiconductor chip 41 and the through wiring 71. In this embodiment, the lead-out wiring 73 is formed in the first interlayer insulating layer 57 counting from the bottom insulating layer 55. The lead-out wiring 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. The first end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the lower end of the through wiring 71. The second end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the low-potential connecting wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip shape in the region between the first end and the second end.

[0083] The first connection plug electrode 74 is formed in the interlayer insulating layer 57 in a region between the through wiring 71 and the lead-out wiring 73, and is electrically connected to first ends of the through wiring 71 and the lead-out wiring 73. The second connection plug electrode 75 is formed in the interlayer insulating layer 57 in a region between the low potential connection wiring 72 and the lead-out wiring 73, and is electrically connected to second ends of the low potential connection wiring 72 and the lead-out wiring 73.

[0084] The plurality of pad plug electrodes 76 are formed in the uppermost insulating layer 56 in a region between the low potential terminal 11 (first low potential terminal 11A) and the through wiring 71, and are electrically connected to the upper ends of the low potential terminal 11 and the through wiring 71, respectively. The plurality of substrate plug electrodes 77 are formed in the lowermost insulating layer 55 in a region between the semiconductor chip 41 and the lead-out wiring 73. In this embodiment, the substrate plug electrodes 77 are formed in a region between the semiconductor chip 41 and the first ends of the lead-out wiring 73, and are electrically connected to the semiconductor chip 41 and the first ends of the lead-out wiring 73, respectively.

[0085] 6 and 7 , the plurality of first high-potential wirings 33 are electrically connected to the corresponding high-potential terminals 12A to 12D and the second inner ends 27 of the corresponding transformers 21A to 21D (high-potential coils 23). The plurality of first high-potential wirings 33 each have a similar structure. The following description will be given taking the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A as an example. The description of the structure of the first high-potential wiring 33 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first high-potential wirings 33, and will not be repeated here.

[0086] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (in this embodiment, multiple) pad plug electrodes 82. The high-potential connection wiring 81 and the pad plug electrode 82 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the high-potential connection wiring 81 and the pad plug electrode 82 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0087] The high-potential connecting wiring 81 is formed in the second inner region 67 of the high-potential coil 23 within the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connecting wiring 81 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The high-potential connecting wiring 81 is electrically connected to the second inner end 27 of the high-potential coil 23. The high-potential connecting wiring 81 is formed spaced apart from the low-potential connecting wiring 72 in a plan view and does not face the low-potential connecting wiring 72 in the normal direction Z. This increases the insulation distance between the low-potential connecting wiring 72 and the high-potential connecting wiring 81, thereby increasing the dielectric strength voltage of the insulating layer 51.

[0088] The plurality of pad plug electrodes 82 are formed in the uppermost insulating layer 56 in a region between the high potential terminal 12 (first high potential terminal 12A) and the high potential connecting wiring 81, and are electrically connected to the high potential terminal 12 and the high potential connecting wiring 81. Each of the plurality of pad plug electrodes 82 has a planar area that is smaller than the planar area of ​​the high potential connecting wiring 81 in a plan view.

[0089] 7, the distance D1 between the low potential terminal 11 and the high potential terminal 12 preferably exceeds the distance D2 between the low potential coil 22 and the high potential coil 23 (D2<D1). The distance D1 preferably exceeds the total thickness DT of the multiple interlayer insulating layers 57 (DT<D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. The distance D1 is preferably 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. The distance D2 is preferably 5 μm or more and 25 μm or less. The values ​​of the distance D1 and the distance D2 are arbitrary and are adjusted appropriately depending on the dielectric strength voltage to be achieved.

[0090] 6 and 7, semiconductor device 5 includes dummy patterns 85 embedded in insulating layer 51 so as to be located around transformers 21A to 21D in a plan view.

[0091] The dummy pattern 85 is formed in a pattern (discontinuous pattern) different from the high-potential coil 23 and the low-potential coil 22, and is independent of the transformers 21A to 21D. In other words, the dummy pattern 85 does not function as a part of the transformers 21A to 21D. The dummy pattern 85 is formed as a shielding conductor layer that shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A to 21D and suppresses electric field concentration on the high-potential coil 23. In this form, the dummy pattern 85 is routed with a line density per unit area equal to that of the high-potential coil 23. Having the line density of the dummy pattern 85 equal to that of the high-potential coil 23 means that the line density of the dummy pattern 85 falls within a range of ±20% of the line density of the high-potential coil 23.

[0092] The depth position of the dummy pattern 85 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The dummy pattern 85 is preferably formed in a region closer to the high-potential coil 23 than to the low-potential coil 22 in the normal direction Z. Note that the dummy pattern 85 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z is less than the distance between the dummy pattern 85 and the low-potential coil 22.

[0093] In this case, electric field concentration on the high-potential coil 23 can be appropriately suppressed. The smaller the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z, the more electric field concentration on the high-potential coil 23 can be suppressed. The dummy pattern 85 is preferably formed in the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration on the high-potential coil 23 can be further appropriately suppressed. The dummy pattern 85 includes multiple dummy patterns with different electrical states. The dummy pattern 85 may include a high-potential dummy pattern.

[0094] The depth position of the high-potential dummy pattern 86 within the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be relaxed. The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than to the low-potential coil 22 in the normal direction Z. The high-potential dummy pattern 86 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22.

[0095] The dummy patterns 85 include floating dummy patterns formed in an electrically floating state within the insulating layer 51 so as to be positioned around the transformers 21A to 21D.

[0096] In this embodiment, the floating dummy pattern is routed in a dense line shape so as to partially cover and partially expose the area around the high-potential coil 23 in a plan view. The floating dummy pattern may be formed to have ends or to have no ends.

[0097] The depth position of the floating dummy pattern inside the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed.

[0098] The number of floating lines is arbitrary and can be adjusted depending on the electric field to be relaxed. The floating dummy pattern may be made up of a plurality of floating lines.

[0099] 7, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in a device region 62. The second functional device 60 is formed using a surface layer portion of the first main surface 42 of the semiconductor chip 41 and / or a region above the first main surface 42 of the semiconductor chip 41, and is covered with an insulating layer 51 (lowermost insulating layer 55). In FIG. 7, the second functional device 60 is simply shown by a dashed line drawn on the surface layer portion of the first main surface 42.

[0100] The second functional device 60 is electrically connected to the low-potential terminal 11 via a low-potential wiring, and is electrically connected to the high-potential terminal 12 via a high-potential wiring. The low-potential wiring has a structure similar to that of the first low-potential wiring 31 (second low-potential wiring 32), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. The high-potential wiring has a structure similar to that of the first high-potential wiring 33 (second high-potential wiring 34), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. A detailed description of the low-potential wiring and high-potential wiring related to the second functional device 60 will be omitted.

[0101] The second functional device 60 may include at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device. The second functional device 60 may include a circuit network in which any two or more of the passive devices, the semiconductor rectifying device, and the semiconductor switching device are selectively combined. The circuit network may form part or all of an integrated circuit.

[0102] The passive device may include a semiconductor passive device. The passive device may include either or both of a resistor and a capacitor. The semiconductor rectifying device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor switching device may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0103] 5 to 7 , the semiconductor device 5 further includes a seal conductor 61 embedded in the insulating layer 51. The seal conductor 61 is embedded in the insulating layer 51 in a wall shape spaced apart from the insulating side walls 53A to 53D in a plan view, and divides the insulating layer 51 into a device region 62 and an outer region 63. The seal conductor 61 prevents moisture and cracks from entering the device region 62 from the outer region 63.

[0104] The device region 62 is a region that includes the first functional device 45 (plurality of transformers 21), the second functional device 60, the plurality of low potential terminals 11, the plurality of high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. The outer region 63 is a region outside the device region 62.

[0105] The seal conductor 61 is electrically isolated from the device region 62. Specifically, the seal conductor 61 is electrically isolated from the first functional device 45 (plurality of transformers 21), the second functional device 60, the plurality of low potential terminals 11, the plurality of high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. More specifically, the seal conductor 61 is fixed in an electrically floating state. The seal conductor 61 does not form a current path leading to the device region 62.

[0106] The seal conductor 61 is formed in a strip shape along the insulating side walls 53 to 53D in plan view. In this embodiment, the seal conductor 61 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. As a result, the seal conductor 61 defines a quadrangular (specifically, rectangular) device region 62 in plan view. The seal conductor 61 also defines a quadrangular (specifically, rectangular) outer region 63 that surrounds the device region 62 in plan view.

[0107] Specifically, the seal conductor 61 has an upper end on the insulating principal surface 52 side, a lower end on the semiconductor chip 41 side, and a wall extending in a wall shape between the upper and lower ends. In this embodiment, the upper end of the seal conductor 61 is formed at a distance from the insulating principal surface 52 toward the semiconductor chip 41 and is located within the insulating layer 51. In this embodiment, the upper end of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 61 is formed at a distance from the semiconductor chip 41 toward the upper end.

[0108] Thus, in this embodiment, the seal conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side with respect to the plurality of low-potential terminals 11 and the plurality of high-potential terminals 12. Furthermore, within the insulating layer 51, the seal conductor 61 faces the first functional device 45 (plurality of transformers 21), the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85 in a direction parallel to the insulating principal surface 52. Within the insulating layer 51, the seal conductor 61 may face a part of the second functional device 60 in a direction parallel to the insulating principal surface 52.

[0109] The seal conductor 61 includes a plurality of seal plug conductors 64 and one or more (a plurality in this embodiment) seal via conductors 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 among the plurality of seal plug conductors 64 forms the upper end of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end of the seal conductor 61. The seal plug conductor 64 and the seal via conductor 65 are preferably formed from the same conductive material as the low-potential coil 22. In other words, the seal plug conductor 64 and the seal via conductor 65 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0110] The multiple seal plug conductors 64 are embedded in the multiple interlayer insulating layers 57, respectively, and are each formed in a quadrangular ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in a plan view. The multiple seal plug conductors 64 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be connected to each other. The number of stacked multiple seal plug conductors 64 matches the number of stacked multiple interlayer insulating layers 57. Of course, one or more seal plug conductors 64 may be formed penetrating the multiple interlayer insulating layers 57.

[0111] As long as a single annular seal conductor 61 is formed by an assembly of a plurality of seal plug conductors 64, it is not necessary for all of the plurality of seal plug conductors 64 to be formed in an annular shape. For example, at least one of the plurality of seal plug conductors 64 may be formed in an end-shaped form. Also, at least one of the plurality of seal plug conductors 64 may be divided into a plurality of strip-shaped portions with ends. However, in consideration of the risk of moisture and cracks penetrating into the device region 62, it is preferable that the plurality of seal plug conductors 64 be formed in an endless (annular) form.

[0112] The plurality of seal via conductors 65 are respectively formed in the region between the semiconductor chip 41 and the seal plug conductor 64 in the lowermost insulating layer 55. The plurality of seal via conductors 65 are formed spaced apart from the semiconductor chip 41 and connected to the seal plug conductor 64. The plurality of seal via conductors 65 have a planar area smaller than the planar area of ​​the seal plug conductor 64. When a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area equal to or larger than the planar area of ​​the seal plug conductor 64.

[0113] The width of the shield conductor 61 may be 0.1 μm or more and 10 μm or less. The width of the shield conductor 61 is preferably 1 μm or more and 5 μm or less. The width of the shield conductor 61 is defined by the width in a direction perpendicular to the direction in which the shield conductor 61 extends.

[0114] 7 and 8 , the semiconductor device 5 further includes an isolation structure 130 interposed between the semiconductor chip 41 and the seal conductor 61 to electrically isolate the seal conductor 61 from the semiconductor chip 41. The isolation structure 130 preferably includes an insulator. In this embodiment, the isolation structure 130 is made of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0115] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). The field insulating film 131 is preferably made of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidizing the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0116] The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41 and extends in a band shape along the seal conductor 61 in a plan view. In this embodiment, the isolation structure 130 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in a plan view. The isolation structure 130 has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion where the lower end portion (seal via conductor 65) of the seal conductor 61 is embedded toward the semiconductor chip 41. Of course, the connection portion 132 may be formed flush with the main surface of the isolation structure 130.

[0117] The isolation structure 130 includes an inner end 130A on the device region 62 side, an outer end 130B on the outer region 63 side, and a main body 130C between the inner end 130A and the outer end 130B. The inner end 130A defines the region in which the second functional device 60 is formed (i.e., the device region 62) in a plan view. The inner end 130A may be formed integrally with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0118] The outer end 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is continuous with the chip sidewalls 44A to 44D of the semiconductor chip 41. More specifically, the outer end 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end 130B forms a flush ground surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end 130B may be formed within the first main surface 42 at a distance from the chip sidewalls 44A to 44D.

[0119] The main body 130C has a flat surface extending substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body 130C has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in a portion of the main body 130C spaced apart from the inner end portion 130A and the outer end portion 130B. The isolation structure 130 can take various forms in addition to the field insulating film 131.

[0120] 7 , the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating principal surface 52 of the insulating layer 51 so as to cover the seal conductor 61. The inorganic insulating layer 140 may also be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating principal surface 52.

[0121] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may contain silicon oxide. The first inorganic insulating layer 141 preferably contains USG (undoped silicate glass), which is silicon oxide without added impurities. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may contain silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. Increasing the total thickness of the inorganic insulating layer 140 can increase the dielectric strength voltage on the high-potential coil 23.

[0122] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the breakdown voltage (V / cm) of USG exceeds the breakdown voltage (V / cm) of silicon nitride. Therefore, when the inorganic insulating layer 140 is thickened, it is preferable that the first inorganic insulating layer 141 be thicker than the second inorganic insulating layer 142.

[0123] The first inorganic insulating layer 141 may contain at least one of BPSG (boron-doped phosphor silicate glass) and PSG (phosphorus silicate glass), which are examples of silicon oxide. However, in this case, since impurities (boron or phosphorus) are contained in the silicon oxide, it is particularly preferable to form the first inorganic insulating layer 141 made of USG in order to increase the dielectric strength voltage on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure made of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0124] The inorganic insulating layer 140 covers the entire seal conductor 61, and has a plurality of low potential pad openings 143 and a plurality of high potential pad openings 144 formed in an area outside the seal conductor 61. The plurality of low potential pad openings 143 expose the plurality of low potential terminals 11, respectively. The plurality of high potential pad openings 144 expose the plurality of high potential terminals 12, respectively. The inorganic insulating layer 140 may have an overlapping portion that rides up onto the peripheral edge of the low potential terminal 11. The inorganic insulating layer 140 may have an overlapping portion that rides up onto the peripheral edge of the high potential terminal 12.

[0125] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140. The organic insulating layer 145 may include a photosensitive resin. The organic insulating layer 145 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 includes polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0126] The thickness of the organic insulating layer 145 preferably exceeds the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably equal to or greater than the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably 2 μm or more and 10 μm or less. Furthermore, the thickness of the organic insulating layer 145 is preferably 5 μm or more and 50 μm or less. These structures can prevent the inorganic insulating layer 140 and the organic insulating layer 145 from becoming thicker, and at the same time, the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145 can appropriately increase the dielectric strength voltage on the high-potential coil 23.

[0127] The organic insulating layer 145 includes a first portion 146 covering the low-potential side region and a second portion 147 covering the high-potential side region. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 sandwiched therebetween. The first portion 146 has a plurality of low-potential terminal openings 148 that expose a plurality of low-potential terminals 11 (low-potential pad openings 143) in a region outside the seal conductor 61. The first portion 146 may have an overlapping portion that rises onto the periphery (overlapping portion) of the low-potential pad opening 143.

[0128] The second portion 147 is formed at a distance from the first portion 146, exposing the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high-potential terminal openings 149 that expose the plurality of high-potential terminals 12 (high-potential pad openings 144), respectively. The second portion 147 may have an overlapping portion that rises onto the periphery (overlapping portion) of the high-potential pad opening 144.

[0129] The second portion 147 collectively covers the transformers 21A to 21D and the dummy pattern 85. Specifically, the second portion 147 collectively covers the plurality of high-potential coils 23, the plurality of high-potential terminals 12, the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121.

[0130] The embodiments of the present disclosure can be implemented in other forms. In the above-described embodiment, an example in which the first functional device 45 and the second functional device 60 are formed has been described. However, a form in which only the second functional device 60 is provided without the first functional device 45 may also be adopted. In this case, the dummy pattern 85 may be removed. According to this structure, the second functional device 60 can achieve the same effects as those described in the first embodiment (excluding the effects related to the dummy pattern 85).

[0131] That is, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the high potential terminal 12 and the seal conductor 61. Furthermore, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the low potential terminal 11 and the seal conductor 61.

[0132] In the above embodiment, an example has been described in which the second functional device 60 is formed. However, the second functional device 60 is not necessarily required and may be removed.

[0133] In the above embodiment, the dummy pattern 85 is formed. However, the dummy pattern 85 is not necessarily required and may be removed.

[0134] In the above-described embodiment, an example has been described in which the first functional device 45 is a multi-channel type that includes a plurality of transformers 21. However, a first functional device 45 that is a single-channel type that includes a single transformer 21 may also be employed.

[0135] 9 is a plan view (top view) schematically showing an example of a transformer arrangement in a two-channel transformer chip 300 (corresponding to the aforementioned semiconductor device 5). The transformer chip 300 in this figure has a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 to b8, pads c1 to c4, and pads d1 to d4.

[0136] In the transformer chip 300, pads a1 and b1 are connected to one end of a secondary coil L1s forming a first transformer 301, and pads c1 and d1 are connected to the other end of the secondary coil L1s. Pads a2 and b2 are connected to one end of a secondary coil L2s forming a second transformer 302, and pads c1 and d1 are connected to the other end of the secondary coil L2s.

[0137] Furthermore, pads a3 and b3 are connected to one end of a secondary coil L3s that forms the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of a secondary coil L4s that forms the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0138] Note that the primary coils forming the first transformer 301, the primary coils forming the second transformer 302, the primary coils forming the third transformer 303, and the primary coils forming the fourth transformer 304 are not shown in this figure. However, the primary coils basically have the same configuration as the secondary coils L1s to L4s, and are arranged directly below the secondary coils L1s to L4s, respectively, so as to face the secondary coils L1s to L4s.

[0139] That is, pads a5 and b5 are connected to one end of the primary coil forming the first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil. Also, pads a6 and b6 are connected to one end of the primary coil forming the second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

[0140] Pads a7 and b7 are connected to one end of the primary coil forming the third transformer 303, and pads c4 and d4 are connected to the other end of the primary coil. Pads a8 and b8 are connected to one end of the primary coil forming the fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary coil.

[0141] However, the pads a5 to a8, pads b5 to b8, pads c3 and c4, and pads d3 and d4 are drawn out from the inside of the transformer chip 300 to the surface through vias (not shown).

[0142] Of the multiple pads, pads a1 to a8 correspond to first current supply pads, pads b1 to b8 correspond to first voltage measurement pads, pads c1 to c4 correspond to second current supply pads, and pads d1 to d4 correspond to second voltage measurement pads.

[0143] Therefore, with the transformer chip 300 of this configuration example, the series resistance component of each coil can be accurately measured during the defective product inspection. Therefore, it is possible to not only reject defective products in which a break has occurred in each coil, but also to appropriately reject defective products in which an abnormal resistance value has occurred in each coil (for example, a short circuit between coils), thereby making it possible to prevent defective products from being released onto the market.

[0144] For the transformer chip 300 that has passed the above-mentioned defective product inspection, the above-mentioned plurality of pads may be used as a means for connecting the primary chip and the secondary chip (for example, the above-mentioned controller chip 210 and driver chip 220).

[0145] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 may be connected to the signal input or output terminals of the secondary chip, respectively, and pads c1 and d1, and pads c2 and d2 may be connected to the common voltage application terminal (GND2) of the secondary chip, respectively.

[0146] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 may be connected to the signal input or output terminals of the primary chip, respectively, and pads c3 and d3, and pads c4 and d4 may be connected to the common voltage application terminal (GND1) of the primary chip, respectively.

[0147] 9, the first transformer 301 to the fourth transformer 304 are arranged in a coupled arrangement according to the respective signal transmission directions. Referring to this figure, for example, the first transformer 301 and the second transformer 302, which transmit signals from the primary chip to the secondary chip, are formed into a first pair by a first guard ring 305. Furthermore, for example, the third transformer 303 and the fourth transformer 304, which transmit signals from the secondary chip to the primary chip, are formed into a second pair by a second guard ring 306.

[0148] The reason for such coupling is to ensure a withstand voltage between the primary coil and the secondary coil when the primary coil and the secondary coil that respectively form the first transformer 301 to the fourth transformer 304 are stacked in the vertical direction of the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0149] The first guard ring 305 and the second guard ring 306 may be connected to a low impedance wiring such as a ground terminal via pads e1 and e2, respectively.

[0150] In the transformer chip 300, pads c1 and d1 are shared between the secondary coil L1s and secondary coil L2s. Pads c2 and d2 are shared between the secondary coil L3s and secondary coil L4s. Pads c3 and d3 are shared between the primary coil L1p and primary coil L2p. Pads c4 and d4 are shared between the corresponding primary coils. This configuration reduces the number of pads, making it possible to miniaturize the transformer chip 300.

[0151] 9, it is desirable that the primary coil and secondary coil forming each of the first transformer 301 to the fourth transformer 304 are wound so as to form a rectangular shape (or a track shape with rounded corners) in a plan view of the transformer chip 300. By using such a configuration, the area where the primary coil and the secondary coil overlap each other becomes larger, which makes it possible to improve the transmission efficiency of the transformer.

[0152] Of course, the transformer arrangement in this figure is merely an example, and the number, shape, and arrangement of the coils, as well as the arrangement of the pads, are arbitrary. Furthermore, the chip structure and transformer arrangement described so far can be applied to all semiconductor devices in which coils are integrated on a semiconductor chip.

[0153] 10 is a diagram showing a first comparative example of an electronic device (i.e., an example of a general circuit configuration to be compared with the embodiments described later). The electronic device A of this comparative example includes a switch element SW1, resistors R1H and R1L, a DC power supply E, and a signal transmission device 200.

[0154] As described above, the signal transmission device 200 may be a semiconductor device (a so-called insulated gate driver IC) that transmits the switch control signal Vg from the primary circuit system 200p to the secondary circuit system 200s while insulating the primary circuit system 200p from the secondary circuit system 200s. In this case, the switch control signal Vg corresponds to the output pulse signal OUT described above.

[0155] The signal transmission device 200 also includes a plurality of external terminals (external terminals T11, T12, T13H, and T13L in this figure) as means for establishing connections with the outside of the device.

[0156] The switch element SW1 may be a power device such as an IGBT (insulated gate bipolar transistor). The gate of the switch element SW1 is connected to a terminal to which a switch control signal Vg is applied. The emitter of the switch element SW1 is connected to a terminal to which a ground voltage GND2 is applied in the secondary circuit system 200s. The switch element SW1 is driven by the switch control signal Vg applied to its gate from the signal transmission device 200. For example, the switch element SW1 is turned on when the switch control signal Vg is at a high level. On the other hand, the switch element SW1 is turned off when the switch control signal Vg is at a low level.

[0157] The DC power supply E generates a power supply voltage VCC2 in the secondary circuit system 200s. The positive terminal of the DC power supply E (= the terminal to which the power supply voltage VCC2 is applied) is connected to the external terminal T11 of the signal transmission device 200. The negative terminal of the DC power supply E is connected to the external terminal T12 of the signal transmission device 200 and the terminal to which the ground voltage GND2 is applied.

[0158] A first end of the resistor R1H is connected to an external terminal T13H of the signal transmission device 200. A first end of the resistor R1L is connected to an external terminal T13L of the signal transmission device 200. Second ends of the resistors R1H and R1L are both connected to the gate of the switch element SW1 (=the application terminal of the switch control signal Vg).

[0159] In this comparative example, the driver 224 integrated in the signal transmission device 200 can be understood as a voltage drive circuit configured to voltage-drive the switch control signal Vg. Referring to this figure, the driver 224 includes a transistor M1H (e.g., a P-channel MOSFET [metal oxide semiconductor field effect transistor]) and a transistor M1L (e.g., an N-channel MOSFET).

[0160] In this specification, a MOSFET refers to a transistor whose gate structure is made up of at least three layers: a layer made of a conductor or a semiconductor such as polysilicon with a low resistance value, an insulating layer, and a P-type, N-type, or intrinsic semiconductor layer. In other words, the gate structure of a MOSFET is not limited to a three-layer structure of a metal, an oxide, and a semiconductor.

[0161] The source and back gate of the transistor M1H are both connected to the external terminal T11 (=the application terminal of the power supply voltage VCC2). The drain of the transistor M1H is connected to the external terminal T13H. The source and back gate of the transistor M1L are both connected to the external terminal T12 (=the application terminal of the ground voltage GND2). The drain of the transistor M1L is connected to the external terminal T13L.

[0162] When the transistor M1H is turned on and the transistor M1L is turned off, a gate current IgH (=source current) flows from the application terminal of the power supply voltage VCC2 to the gate of the switch element SW1 via the transistor M1H and the resistor R1H. Therefore, the gate capacitance (not shown) is charged, and the switch control signal Vg rises from low to high. As a result, the switch element SW1 is turned on.

[0163] On the other hand, when the transistor M1H is turned off and the transistor M1L is turned on, a gate current IgL (=sink current) flows from the gate of the switch element SW1 through the resistor R1L and the transistor M1L to the terminal to which the ground voltage GND2 is applied. Therefore, the gate capacitance (not shown) is discharged, and the switch control signal Vg falls from high to low. As a result, the switch element SW1 is turned off.

[0164] <Electronic Device (Second Comparative Example)> FIG. 11 is a diagram showing a second comparative example of an electronic device (= another example of a general circuit configuration to be compared with the embodiments described later).

[0165] The electronic device A of this comparative example includes a switch element SW1, a transistor M2H (e.g., a P-channel MOSFET), a transistor M2L (e.g., an N-channel MOSFET), resistors R2H and R2L, resistors R3H and R3L, a DC power supply E, and a signal transmission device 200. The signal transmission device 200 also includes a plurality of external terminals (external terminals T11, T12, T14H, T14L, T15H, and T15L in this figure) as means for establishing a connection with the outside of the device.

[0166] Note that components already mentioned are given the same reference numerals as those in FIG. 10, and redundant explanations will be omitted, and the following description will focus on the components that are mentioned for the first time.

[0167] A first end of each of the resistors R2H and R3H is connected to the external terminal T11 (=application terminal of the power supply voltage VCC2) of the signal transmission device 200. A second end of the resistor R2H and the source and back gate of the transistor M2H are all connected to the external terminal T15H (=application terminal of the sense voltage V1H) of the signal transmission device 200. A second end of the resistor R3H and the gate of the transistor M2H are all connected to the external terminal T14H (=application terminal of the gate signal HG) of the signal transmission device 200. A drain of the transistor M2H is connected to the gate of the switch element SW1 (=application terminal of the switch control signal Vg).

[0168] The resistor R2H functions as a sense resistor for generating a sense voltage V1H (=VCC2-R2H×IgH) corresponding to the gate current IgH flowing through the transistor M2H. The resistor R3H functions as a pull-up resistor for pulling up the gate signal HG to a high level (≈power supply voltage VCC2) when the external terminal T14H is in an open state (high impedance state).

[0169] A first end of each of the resistors R2L and R3L is connected to the external terminal T12 (= application terminal of the ground voltage GND2) of the signal transmission device 200. A second end of the resistor R2L and the source and back gate of the transistor M2L are all connected to the external terminal T15L (= application terminal of the sense voltage V1L) of the signal transmission device 200. A second end of the resistor R3L and the gate of the transistor M2L are all connected to the external terminal T14L (= application terminal of the gate signal LG) of the signal transmission device 200. A drain of the transistor M2L is connected to the gate of the switch element SW1 (= application terminal of the switch control signal Vg).

[0170] The resistor R2L functions as a sense resistor for generating a sense voltage V1L (=GND2+R2L×IgL) corresponding to the gate current IgL flowing through the transistor M2L. The resistor R3L functions as a pull-down resistor for pulling down the gate signal LG to a low level (≈ground voltage GND2) when the external terminal T14L is in an open state (high impedance state).

[0171] In this comparative example, the driver 224 integrated in the signal transmission device 200 can be understood as a current driver circuit configured to current-drive the switch control signal Vg. Referring to this figure, the driver 224 includes amplifiers A1H and A1L.

[0172] The inverting input terminal (-) of the amplifier A1H is connected to the external terminal T15H (= the terminal to which the sense voltage V1H is applied). The non-inverting input terminal (+) of the amplifier A1H is connected to the terminal to which the reference voltage V2H (= VCC2 - VrefH) is applied. The output terminal of the amplifier A1H is connected to the external terminal T14H (= the terminal to which the gate signal HG is applied).

[0173] When the amplifier A1H is in an operating state, the gate signal HG is generated so that the sense voltage V1H (= VCC2 - R2H x IgH) and the reference voltage V2H (= VCC2 - VrefH) coincide with each other. That is, output feedback control is performed so that the magnitude of the gate current IgH coincides with the reference current value IrefH (= VrefH / R2H). On the other hand, when the amplifier A1H is in an inoperable state, the external terminal T14H is in an open state (high impedance state).

[0174] The inverting input terminal (-) of the amplifier A1L is connected to the external terminal T15L (=the terminal to which the sense voltage V1L is applied). The non-inverting input terminal (+) of the amplifier A1L is connected to the terminal to which the reference voltage V2L (=GND2+VrefL) is applied. The output terminal of the amplifier A1L is connected to the external terminal T14L (=the terminal to which the gate signal LG is applied).

[0175] When the amplifier A1L is in an operating state, the gate signal LG is generated so that the sense voltage V1L (=GND2+R2L×IgL) and the reference voltage V2L (=GND2+VrefL) coincide with each other. That is, output feedback control is performed so that the magnitude of the gate current IgL coincides with the reference current value IrefL (=VrefL / R2L). On the other hand, when the amplifier A1L is in an inactive state, the external terminal T14L is in an open state (high impedance state).

[0176] When amplifier A1H is in an operating state and amplifier A1L is in an inactive state, a gate current IgH (=source current) flows from the application terminal of power supply voltage VCC2 to the gate of switch element SW1 via resistor R2H and transistor M2H. Therefore, the gate capacitance (not shown) is charged, and the switch control signal Vg rises from low level to high level. As a result, switch element SW1 is turned on.

[0177] On the other hand, when amplifier A1H is in an inactive state and amplifier A1L is in an active state, a gate current IgL (=sink current) flows from the gate of switch element SW1 through transistor M2L and resistor R2L to the terminal to which ground voltage GND2 is applied. Therefore, the gate capacitance (not shown) is discharged, and the switch control signal Vg falls from high to low. As a result, switch element SW1 is turned off.

[0178] <Considerations on Optimizing the Slew Rate> A common method for driving a switching element such as an IGBT, Si-MOSFET, or SiC-MOSFET is to apply a pulse voltage between the gate and source of the switching element via a gate resistor (a so-called voltage driving method), as shown in the first comparative example ( FIG. 10 ) mentioned above.

[0179] In such a voltage driving method, the slew rate (slope) of the switch control signal can be controlled by adjusting the magnitude of the gate resistors (e.g., resistors R1H and R1L). The slew rate of the switch control signal may be understood as the amount of change per unit time, di / dt, of the gate current flowing through the switch element, or the amount of change per unit time, dv / dt, of the gate voltage applied to the switch element.

[0180] However, if the slew rate of the switch control signal is reduced, output overshoot (= transient overcurrent or overvoltage) and EMI (electromagnetic interference) noise are suppressed, but the switching loss of the switch element may increase. On the other hand, if the slew rate of the switch control signal is increased, the switching loss of the switch element is reduced, but the output overshoot and EMI noise may increase.

[0181] Therefore, in the voltage driving method, the magnitude of the gate resistance must be adjusted for each switch element to be driven in consideration of the above trade-off. However, it is not necessarily easy to accurately set the slew rate of the switch control signal by adjusting the external gate resistance. Furthermore, it must be said that the degree of freedom in setting the slew rate is low.

[0182] On the other hand, the previously mentioned current driving method (FIG. 11) allows for more accurate adjustment of the slew rate of the switch control signal than the previously mentioned voltage driving method (FIG. 10). However, the switching speed of the gate current is limited by the operating speed of the output feedback loop (e.g., the previously mentioned amplifiers A1H and A1L). Therefore, it is difficult to dynamically switch the gate current to optimize the slew rate of the switch control signal.

[0183] In view of the above considerations, a novel embodiment is proposed below that can optimize the slew rate of the switch control signal Vg.

[0184] <Electronic Device (First Embodiment)> Figure 12 is a diagram showing a first embodiment of an electronic device. Electronic device A of this embodiment includes a switch element SW2, a transistor M2H, a transistor M2L, resistors R1H and R1L, resistors R2H and R2L, resistors R3H and R3L, a DC power supply E, and a signal transmission device 200. The signal transmission device 200 also includes a plurality of external terminals (external terminals T11, T12, T13H, T13L, T14H, T14L, T15H, and T15L in this figure) as means for establishing a connection with the outside of the device. These components are each provided in a secondary circuit system 200s.

[0185] The switch element SW2 may be an N-channel Si-MOSFET or SiC-MOSFET. The gate of the switch element SW2 is connected to an application terminal of the switch control signal Vg. The source and back gate of the switch element SW2 are connected to an application terminal of the ground voltage GND2 in the secondary circuit system 200s. The switch element SW2 is driven by the switch control signal Vg applied to its gate from the signal transmission device 200. For example, the switch element SW2 is turned on when the switch control signal Vg is at a high level. On the other hand, the switch element SW2 is turned off when the switch control signal Vg is at a low level. The switch element SW2 may be replaced with an IGBT (= switch element SW1) as in the first comparative example ( FIG. 10 ) and the second comparative example ( FIG. 11 ).

[0186] The signal transmission device 200 includes the aforementioned transistors M1H and M1L and amplifiers A1H and A1L. The transistors M1H and M1L can be understood as voltage driver circuits DRV1H and DRV1L, respectively, configured to voltage-drive the switch control signal Vg. The amplifiers A1H and A1L can be understood as current driver circuits DRV2H and DRV2L, respectively, configured to current-drive the switch control signal Vg.

[0187] The voltage driver DRV1H and the current driver DRV2H form an upper driver 224H that raises the switch control signal Vg from low to high. The voltage driver DRV1L and the current driver DRV2L form a lower driver 224L that lowers the switch control signal Vg from high to low.

[0188] 10 and 11, the same reference numerals are used to denote the same components, and redundant explanations will be omitted. However, for convenience of explanation, the gate current IgH described above can be understood as a sum current obtained by adding together the gate current Ig1H generated by the voltage drive circuit DRV1H and the gate current Ig2H generated by the current drive circuit DRV2H. Similarly, the gate current IgL described above can be understood as a sum current obtained by adding together the gate current Ig1L generated by the voltage drive circuit DRV1L and the gate current Ig2L generated by the current drive circuit DRV2L.

[0189] The pulse receiving circuit 223 generates a switch control signal Vg (=output pulse signal OUT) by driving the upper driver 224H and the lower driver 224L in response to received pulse signals S12 and S22 (not shown) (see FIG. 1).

[0190] The pulse receiving circuit 223 may have a function as a control circuit CTRL that arbitrarily adjusts the reference current values ​​IrefH and IrefL described above. The pulse receiving circuit 223 may also have a function as a control circuit CTRL that arbitrarily adjusts the period during which each of the voltage driving circuits DRV1H and DRV1L is in the ON state and the period during which each of the current driving circuits DRV2H and DRV2L is in the ON state.

[0191] The control circuit CTRL may perform the above adjustment based on register settings via SPI (serial peripheral interface) communication, setting data read from an internal non-volatile memory (not shown), or an external analog input signal (such as a PWM (pulse width modulation) signal).

[0192] Furthermore, the control circuit CTRL may be provided separately from the pulse receiving circuit 223 .

[0193] In this way, the electronic device A of this embodiment can be understood as a combination of the first comparative example (FIG. 10) and the second comparative example (FIG. 11) described above.

[0194] In particular, in the signal transmission device 200, the on / off states of the voltage drive circuits DRV1H and DRV1L and the current drive circuits DRV2H and DRV2L are switched at appropriate timing, thereby optimizing the turn-on control and the turn-off control, as will be described in detail below with reference to the drawings.

[0195] 13 is a diagram showing the turn-on control of the first embodiment. From the top, the diagram depicts the gate-source voltage Vgs, drain-source voltage Vds, drain-source current Ids, and gate current IgH of the switch element SW2, as well as the on / off states of the voltage driver circuit DRV1H and the current driver circuit DRV2H.

[0196] As shown in this figure, the logic level transition period Ton_tr (=times t1 to t5) when the gate-source voltage Vgs of the switch element SW2 rises from a low level (=0 V) to a high level (=Vdrv_on) includes four periods T1, T2, T3, and T4.

[0197] The period T1 (=time t1 to t2) corresponds to the period from when the charging of the gate capacitance associated with the switch element SW2 starts until the gate-source voltage Vgs of the switch element SW2 rises to the on-threshold voltage Vth of the switch element SW2, for example.

[0198] Period T2 (times t2 to t3) corresponds to, for example, the period from when the gate-source voltage Vgs of the switch element SW2 exceeds the on-threshold voltage Vth until it rises to the mirror voltage Vm_on. From another perspective, period T2 can be understood as a period during which the drain-source current Ids of the switch element SW2 increases. During period T2, the drain-source voltage Vds of the switch element SW2 drops by an amount of change ΔVdrop.

[0199] Period T3 (=times t3 to t4) corresponds to, for example, a period (so-called plateau region) during which the gate-source voltage Vgs of the switch element SW2 remains constant due to the Miller effect. During period T3, the gate-source voltage Vgs and drain-source current Ids of the switch element SW2 are basically maintained at constant values, while only the drain-source voltage Vds of the switch element SW2 decreases. Note that, during period T3, as shown in the figure, an overshoot may occur in the drain-source current Ids of the switch element SW2.

[0200] Period T4 (times t4 to t5) corresponds to the period from when the gate-source voltage Vgs of the switch element SW2 starts to rise again until it reaches a high level (Vdrv_on). At this time, the drain-source voltage Vds of the switch element SW2 drops to a voltage value Vds_on (=Ids×Ron(SW2), where Ron(SW2) is the on-resistance value of the switch element SW2).

[0201] Here, the voltage driver circuit DRV1H is turned on during a portion of the periods T1 to T4, namely, the period T1+T2 and the period T4, and is turned off during the remaining period T3, whereas the current driver circuit DRV2H is turned on during all of the periods T1 to T4.

[0202] That is, during periods T1+T2 (times t1 to t3) and T4 (times t4 to t5), the voltage driver DRV1H and the current driver DRV2H are both turned on. At this time, the gate current IgH has a current value equal to the sum of the gate currents Ig1H and Ig2H (IgH=Ig1H+Ig2H). Therefore, the rise slew rate of the gate-source voltage Vgs (switch control signal Vg) is increased.

[0203] During period T3 (times t3 to t4), the voltage driver DRV1H is turned off and the current driver DRV2H is turned on. At this time, only the gate current Ig2H flows as the gate current IgH. Therefore, the rise slew rate of the gate-source voltage Vgs (switch control signal Vg) is reduced.

[0204] In this way, by applying a gate drive method suited to each of the four periods T1 to T4, an optimal drive waveform for the switch control signal Vg can be generated. Referring to this figure, in the turn-on control of this embodiment, the gate current IgH (and therefore the rising slew rate of the switch control signal Vg) during the logic level transition period Ton_tr of the switch control signal Vg is dynamically switched from "large" to "small" to "large."

[0205] Here, the current drive circuit DRV2H is constantly maintained in the on state throughout periods T1 to T4. That is, switching control of the gate current IgH is achieved by on / off control of the voltage drive circuit DRV1H. Therefore, the problem of the slow switching speed of the gate current Ig2H in the current drive circuit DRV2H can be overcome. In particular, when the switch element SW2 is a power device capable of high-speed switching (e.g., a SiC-MOSFET), the gate drive control of this embodiment is suitable.

[0206] Furthermore, as described above, parameters such as the magnitude of the reference current value IrefH (=gate current Ig2H) and the lengths (start and end points) of the periods T1 to T4 may be arbitrarily adjusted based on SPI communication, nonvolatile memory, or an external analog input signal. For example, by adjusting the above parameters for each switch element SW2, the rising slew rate of the switch control signal Vg can be set with precision without adjusting the external resistors R1H and R2H. Therefore, it is possible to suppress both output overshoot and EMI noise and reduce switching loss.

[0207] 14 is a diagram showing a modification of the turn-on control of the first embodiment. As in the above-mentioned Fig. 13, this diagram shows, from top to bottom, the gate-source voltage Vgs, drain-source voltage Vds, drain-source current Ids, and gate current IgH of the switch element SW2, as well as the on / off states of the voltage drive circuit DRV1H and the current drive circuit DRV2H.

[0208] In this modification, during period T1 (times t1 to t2) and period T4 (times t4 to t5), both the voltage driver circuit DRV1H and the current driver circuit DRV2H are turned on. At this time, the gate current IgH has a current value equal to the sum of the gate currents Ig1H and Ig2H (IgH = Ig1H + Ig2H). Therefore, the rise slew rate of the gate-source voltage Vgs (switch control signal Vg) is increased.

[0209] During the period T2+T3 (times t2 to t4), the voltage driver DRV1H is turned off and the current driver DRV2H is turned on. At this time, only the gate current Ig2H flows as the gate current IgH. Therefore, the rise slew rate of the gate-source voltage Vgs (switch control signal Vg) is reduced.

[0210] In this way, the voltage driver circuit DRV1H may be turned on during the periods T1 and T4 and turned off during the remaining periods T2 and T3, while the current driver circuit DRV2H is turned on during all of the periods T1 to T4.

[0211] 15 is a diagram showing the turn-off control of the first embodiment. From the top, the diagram depicts the gate-source voltage Vgs, drain-source voltage Vds, drain-source current Ids, and gate current IgL of the switch element SW2, as well as the on / off states of the voltage drive circuit DRV1L and the current drive circuit DRV2L.

[0212] As shown in this figure, the logic level transition period Toff_tr (=times t6 to t10) when the gate-source voltage Vgs of the switch element SW2 falls from a high level (=Vdrv_on) to a low level (=0V) includes four periods T5, T6, T7, and T8.

[0213] The period T5 (=times t6 to t7) corresponds to the period from when the gate capacitance associated with the switch element SW2 starts to discharge until the mirror voltage Vm_on is reached. At this time, the drain-source voltage Vds of the switch element SW2 is maintained at the voltage value Vds_on (=Ids×Ron(SW2)).

[0214] Period T6 (=times t7 to t8) corresponds to, for example, a period (a so-called plateau region) during which the gate-source voltage Vgs of the switch element SW2 becomes constant due to the Miller effect. During period T6, the gate-source voltage Vgs and the drain-source current Ids of the switch element SW2 are basically maintained at constant values, while only the drain-source voltage Vds of the switch element SW2 increases.

[0215] Period T7 (times t8 to t9) corresponds to, for example, the period from when the gate-source voltage Vgs of the switch element SW2 starts to decrease again until it decreases to the on-threshold voltage Vth of the switch element SW2. From another perspective, period T7 can be understood as a period during which the drain-source current Ids of the switch element SW2 decreases. Note that during period T7, an overshoot may occur in the drain-source voltage Vds of the switch element SW2.

[0216] The period T8 (=times t9 to t10) corresponds to the period from when the gate-source voltage Vgs of the switch element SW2 falls below the on-threshold voltage Vth until it drops to low level (=0 V), for example.

[0217] Here, the voltage driver circuit DRV1L is turned on during the periods T5 and T7+T8 of the periods T5 to T8, and is turned off during the remaining period T6, whereas the current driver circuit DRV2L is turned on during the entire periods T5 to T8.

[0218] That is, during period T5 (times t6 to t7) and period T7+T8 (times t8 to t10), both the voltage driver circuit DRV1L and the current driver circuit DRV2L are turned on. At this time, the gate current IgL has a current value equal to the sum of the gate currents Ig1L and Ig2L (IgL=Ig1L+Ig2L). Therefore, the falling slew rate of the gate-source voltage Vgs (=switch control signal Vg) is increased.

[0219] On the other hand, during period T6 (times t7 to t8), the voltage driver circuit DRV1L is turned off and the current driver circuit DRV2L is turned on. At this time, only the gate current Ig2L flows as the gate current IgL. Therefore, the falling slew rate of the gate-source voltage Vgs (=switch control signal Vg) is reduced.

[0220] In this way, by applying a gate drive method suited to each of the four periods T5 to T8, an optimal drive waveform for the switch control signal Vg can be generated. Referring to this figure, in the turn-on control of this embodiment, the gate current IgL (and therefore the falling slew rate of the switch control signal Vg) during the logic level transition period Toff_tr of the switch control signal Vg is dynamically switched from "large" to "small" to "large."

[0221] Here, the current drive circuit DRV2L is constantly maintained in the on state throughout periods T5 to T8. That is, switching control of the gate current IgL is achieved by on / off control of the voltage drive circuit DRV1L. Therefore, the problem of the slow switching speed of the gate current Ig2L in the current drive circuit DRV2L can be overcome. In particular, when the switch element SW2 is a power device capable of high-speed switching (e.g., a SiC-MOSFET), the gate drive control of this embodiment is suitable.

[0222] Furthermore, as described above, parameters such as the magnitude of the reference current value IrefL (=gate current Ig2L) and the lengths (start and end points) of the periods T5 to T8 may be adjusted arbitrarily based on SPI communication, nonvolatile memory, or an external analog input signal. For example, by adjusting the above parameters for each switch element SW2, the falling slew rate of the switch control signal Vg can be set with precision without adjusting the external resistors R1L and R2L. Therefore, it is possible to suppress both output overshoot and EMI noise and reduce switching loss.

[0223] Although not shown separately, the voltage driver circuit DRV1L may be turned on during the periods T5 and T8 and turned off during the remaining periods T6 and T7, following the modified example of the turn-on control described above (FIG. 14). On the other hand, the current driver circuit DRV2L is turned on during the entire periods T5 to T8.

[0224] 16 is a diagram showing a second embodiment of an electronic device. The electronic device A of this embodiment is based on the first embodiment (FIG. 12) described above, but has modifications to the configuration of the signal transmission device 200 and the external elements.

[0225] Referring to this figure, the signal transmission device 200 includes transistors M1Ha and M1Hb (both of which are, for example, P-channel MOSFETs) instead of the transistor M1H, and external terminals T13Ha and T13Hb instead of the external terminal T13H.

[0226] The source and back gate of the transistor M1Ha are both connected to the external terminal T11. The drain of the transistor M1Ha is connected to the external terminal T13Ha. A resistor R1Ha is externally connected between the external terminal T13Ha and the gate of the switch element SW2. The transistor M1Ha connected in this manner can be understood as a voltage drive circuit DRV1Ha configured to voltage-drive the switch control signal Vg via the resistor R1Ha.

[0227] The source and back gate of the transistor M1Hb are both connected to the external terminal T11. The drain of the transistor M1Hb is connected to the external terminal T13Hb. A resistor R1Hb is externally connected between the external terminal T13Hb and the gate of the switch element SW2. The transistor M1Hb connected in this manner can be understood as a voltage drive circuit DRV1Hb configured to voltage-drive the switch control signal Vg via a resistor R1Hb different from the resistor R1Ha.

[0228] The gate current Ig1H mentioned above is divided into two systems: a gate current Ig1Ha flowing through the transistor M1Ha and a gate current Ig1Hb flowing through the transistor M1Hb.

[0229] The signal transmission device 200 also includes transistors M1La and M1Lb (both of which are, for example, N-channel MOSFETs) instead of the transistor M1L, and external terminals T13La and T13Lb instead of the external terminal T13L.

[0230] The source and back gate of the transistor M1La are both connected to the external terminal T12. The drain of the transistor M1La is connected to the external terminal T13La. A resistor R1La is externally connected between the external terminal T13La and the gate of the switch element SW2. The transistor M1La connected in this manner can be understood as a voltage drive circuit DRV1La configured to voltage-drive the switch control signal Vg via the resistor R1La.

[0231] The source and back gate of the transistor M1Lb are both connected to the external terminal T12. The drain of the transistor M1Lb is connected to the external terminal T13Lb. A resistor R1Lb is externally connected between the external terminal T13Lb and the gate of the switch element SW2. The transistor M1Lb connected in this manner can be understood as a voltage drive circuit DRV1Lb configured to voltage-drive the switch control signal Vg via a resistor R1Lb different from the resistor R1La.

[0232] The gate current Ig1L mentioned above is divided into two systems: a gate current Ig1La flowing through the transistor M1La and a gate current Ig1Lb flowing through the transistor M1Lb.

[0233] 17 is a diagram showing the turn-on control of the second embodiment. From the top, the diagram depicts the gate-source voltage Vgs, drain-source voltage Vds, drain-source current Ids, and gate current IgH of the switch element SW2, as well as the on / off states of the voltage drive circuits DRV1Ha, DRV1Hb, and current drive circuit DRV2H.

[0234] Here, differences from the turn-on control of the first embodiment (FIG. 13) will be described. Referring to this figure, the voltage driver circuit DRV1Ha is turned on during a portion of the periods T1 to T4, that is, the period T1+T2, and is turned off during the remaining periods T3 and T4. The voltage driver circuit DRV1Hb is turned on during a portion of the periods T1 to T4, that is, the period T4, and is turned off during the remaining periods T1 to T3. Meanwhile, the current driver circuit DRV2H is turned on during all of the periods T1 to T4.

[0235] That is, during the period T1+T2 (=times t1 to t3), the voltage driver circuit DRV1Ha and the current driver circuit DRV2H are turned on, and the voltage driver circuit DRV1Hb is turned off. At this time, the gate current IgH has a current value equal to the sum of the gate currents Ig1Ha and Ig2H (IgH=Ig1Ha+Ig2H). Therefore, the rise slew rate of the gate-source voltage Vgs (=switch control signal Vg) is set to the set value RSR1.

[0236] During period T3 (times t3 to t4), the voltage driver circuits DRV1Ha and DRV1Hb are both turned off, and the current driver circuit DRV2H is turned on. At this time, only the gate current Ig2H flows as the gate current IgH. Therefore, the rise-through rate of the gate-source voltage Vgs (switch control signal Vg) is reduced from the set value RSR1 to the set value RSR2.

[0237] During period T4 (times t4 to t5), the voltage driver circuit DRV1Hb and the current driver circuit DRV2H are turned on, and the voltage driver circuit DRV1Ha is turned off. At this time, the gate current IgH has a current value equal to the sum of the gate currents Ig1Hb and Ig2H (IgH = Ig1Hb + Ig2H). Therefore, the rise-through rate of the gate-source voltage Vgs (= switch control signal Vg) is increased from the set value RSR2 to the set value RSR3 (which may not be equal to RSR1).

[0238] In this way, if multiple voltage drive circuits DRV1Ha and DRV1Hb are provided, the drive waveform of the switch control signal Vg can be optimized more precisely than in the first embodiment ( FIG. 12 ). Note that the gate current IgH (and therefore the rising slew rate of the switch control signal Vg) during the logic level transition period Ton_tr of the switch control signal Vg is still dynamically switched from “large” to “small” to “large.”

[0239] Although not shown separately, the voltage drive circuit DRV1Ha may be turned on during a portion of the periods T1 to T4, T1, and turned off during the remaining periods T2 to T4, following the modified example of the turn-on control described above (FIG. 14).

[0240] Furthermore, although the figure depicts an example where Ig1Ha>Ig1Hb, the opposite may also be true, where Ig1Ha<Ig1Hb.

[0241] 18 is a diagram showing the turn-off control of the second embodiment. From the top, the diagram depicts the gate-source voltage Vgs, drain-source voltage Vds, drain-source current Ids, and gate current IgH of the switch element SW2, as well as the on / off states of the voltage drive circuits DRV1La, DRV1Lb, and current drive circuit DRV2H.

[0242] Here, differences from the turn-off control of the first embodiment (FIG. 15) will be described. Referring to this figure, the voltage driver circuit DRV1La is turned on during a portion of the period T5 to T8 (T7+T8) and is turned off during the remaining periods T5 and T6. The voltage driver circuit DRV1Lb is turned on during a portion of the period T5 to T8 (T5) and is turned off during the remaining periods T6 to T8. Meanwhile, the current driver circuit DRV2L is turned on during the entire period T5 to T8.

[0243] That is, during period T5 (times t6 to t7), the voltage driver circuit DRV1Lb and the current driver circuit DRV2L are turned on, and the voltage driver circuit DRV1La is turned off. At this time, the gate current IgL is the sum of the gate currents Ig1Lb and Ig2L (IgL = Ig1Lb + Ig2L). Therefore, the falling slew rate of the gate-source voltage Vgs (= switch control signal Vg) is set to the set value FSR1.

[0244] Meanwhile, during period T6 (times t7 to t8), both voltage driver circuits DRV1La and DRV1Lb are turned off, and current driver circuit DRV2L is turned on. At this time, only gate current Ig2L flows as gate current IgL. Therefore, the falling slew rate of gate-source voltage Vgs (= switch control signal Vg) is reduced from set value FSR1 to set value FSR2.

[0245] During period T7+T8 (times t8 to t10), the voltage driver circuit DRV1La and the current driver circuit DRV2L are turned on, and the voltage driver circuit DRV1Lb is turned off. At this time, the gate current IgL is the sum of the gate currents Ig1La and Ig2L (IgL=Ig1La+Ig2L). Therefore, the falling slew rate of the gate-source voltage Vgs (=switch control signal Vg) is increased from a set value FSR2 to a set value FSR3 (which may not be FSR1).

[0246] In this way, if multiple voltage drive circuits DRV1La and DRV1Lb are provided, the drive waveform of the switch control signal Vg can be optimized more precisely than in the first embodiment ( FIG. 12 ). Note that the gate current IgL (and therefore the falling slew rate of the switch control signal Vg) during the logic level transition period Toff_tr of the switch control signal Vg is still dynamically switched from “large” to “small” to “large.”

[0247] Although not shown separately, the voltage drive circuit DRV1La may be turned on during a portion of the periods T5 to T8, namely, period T8, and turned off during the remaining periods T5 to T7, following the modified example of the turn-on control described above (FIG. 14).

[0248] Furthermore, although the diagram shows an example where Ig1La>Ig1Lb, the opposite may also be true, where Ig1La<Ig1Lb.

[0249] <Application to Vehicles> Fig. 19 is a diagram showing the appearance of a vehicle B. Vehicle B of this configuration example is equipped with various electronic devices that operate with power supplied from a battery.

[0250] Vehicle B includes not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs / PHVs), or xEVs such as fuel cell electric vehicles (FCEVs / FCVs)).

[0251] The signal transmission device 200 described above can be incorporated into any of the electronic devices installed in the vehicle B.

[0252] <Additional Notes> According to the present disclosure, the slew rate of the switch control signal can be optimized. The following additional notes are provided regarding the present disclosure.

[0253] [Supplementary Note 1] The semiconductor device includes at least one voltage drive circuit (DRV1H, DRV1Ha, DRV1Hb, DRV1L, DRV1La, DRV1Lb) configured to voltage-drive a switch control signal (Vg), and a current drive circuit (DRV2H, DRV2L) configured to current-drive the switch control signal (Vg), The at least one voltage drive circuit (DRV1H, DRV1L) is in an on state during some periods (T1, T2, T4, T5, T7, T8) of a plurality of periods (T1 to T4, T5 to T8) included in a logic level transition period (Ton_tr, Toff_tr) of the switch control signal (Vg), and is in an off state during the remaining periods (e.g., T3, T6), and the current drive circuits (DRV2H, DRV2L) are in an on state during all of the plurality of periods (T1 to T4, T5 to T8).

[0254] [Supplementary Note 2] The at least one voltage drive circuit (DRV1Ha, DRV1Hb, DRV1La, DRV1Lb) includes a first voltage drive circuit (DRV1Ha, DRV1La) configured to be connected to an application terminal of the switch control signal (Vg) via a first resistor (R1Ha, R1La), and a second voltage drive circuit (DRV1Hb, DRV1Lb) configured to be connected to an application terminal of the switch control signal (Vg) via a second resistor (R1Hb, R1Lb) different from the first resistor (R1Ha, R1La), The logic level transition periods (Ton_tr, Toff_tr) include a first period (e.g., T1+T2, T7+T8) in which the first voltage drive circuits (DRV1Ha, DRV1La) and the current drive circuits (DRV2H, DRV2L) are turned on and the second voltage drive circuits (DRV1Hb, DRV1Lb) are turned off, and a second period (e.g., T1+T2, T7+T8) in which the current drive circuits (DRV2H, DRV2L) are turned on and the first voltage drive circuits (DRV a second period (T3, T6) during which the second voltage drive circuits (DRV1Ha, DRV1La) and the second voltage drive circuits (DRV1Hb, DRV1Lb) are turned off, and a third period (T4, T5) during which the second voltage drive circuits (DRV1Hb, DRV1Lb) and the current drive circuits (DRV2H, DRV2L) are turned on and the first voltage drive circuits (DRV1Ha, DRV1La) are turned off.

[0255] [Supplementary Note 3] The semiconductor device (200) according to Supplementary Note 1 or 2, wherein the current drive circuits (DRV2H, DRV2L) perform output feedback control so that the magnitude of the currents (Ig2H, Ig2L) flowing through the application terminals of the switch control signal (Vg) coincides with reference current values ​​(IrefH, IrefL).

[0256] [Supplementary Note 4] The semiconductor device (200) according to Supplementary Note 3, further comprising a control circuit (223, CTRL) configured to arbitrarily adjust the reference current values ​​(IrefH, IrefL).

[0257] [Supplementary Note 5] The semiconductor device (200) according to any one of Supplementary Notes 1 to 4, further comprising a control circuit (223, CTRL) configured to arbitrarily adjust a period during which each of the at least one voltage drive circuit (DRV1H, DRV1Ha, DRV1Hb, DRV1L, DRV1La, DRV1Lb) and the current drive circuit (DRV2H, DRV2L) is in an on state.

[0258] [Supplementary Note 6] The semiconductor device (200) according to any one of Supplementary Notes 1 to 5, wherein the at least one voltage drive circuit (DRV1H, DRV1Ha, DRV1Hb, DRV1L, DRV1La, DRV1Lb) and the current drive circuits (DRV2H, DRV2L) form at least one of an upper driver (224H) configured to raise the switch control signal (Vg) from a low level to a high level, and a lower driver (224L) configured to lower the switch control signal (Vg) from a high level to a low level.

[0259] [Supplementary Note 7] The semiconductor device (200) is a signal transmission device configured to transmit the switch control signal (Vg) from a primary circuit system (200p) to a secondary circuit system (200s) while insulating the primary circuit system (200p) from the secondary circuit system (200s), and the at least one voltage drive circuit (DRV1H, DRV1Ha, DRV1Hb, DRV1L, DRV1La, DRV1Lb) and the current drive circuits (DRV2H, DRV2L) are each provided in the secondary circuit system (200s). The semiconductor device (200) is described in any one of Supplementary Notes 1 to 6.

[0260] [Supplementary Note 8] An electronic device (A) comprising: a semiconductor device (200) according to any one of Supplementary Notes 1 to 7; and switch elements (SW1, SW2) configured to be driven by the semiconductor device (200).

[0261] [Supplementary Note 9] The electronic device (A) according to Supplementary Note 8, wherein the switch elements (SW1, SW2) are IGBTs, Si-MOSFETs, or SiC-MOSFETs.

[0262] [Supplementary Note 10] A vehicle (B) including the electronic device (A) according to Supplementary Note 8 or 9.

[0263] <Others> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects. Furthermore, the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0264] 5 Semiconductor device 11, 11A to 11F Low potential terminal 12, 12A to 12F High potential terminal 21, 21A to 21D Transformer 22 Low potential coil (primary coil) 23 High potential coil (secondary coil) 24 First inner end 25 First outer end 26 First spiral portion 27 Second inner end 28 Second outer end 29 Second spiral portion 31 First low potential wiring 32 Second low potential wiring 33 First high potential wiring 34 Second high potential wiring 41 Semiconductor chip 42 First main surface 43 Second main surface 44A to 44D Chip side wall 45 First functional device 51 Insulating layer 52 Insulating main surface 53A to 53D Insulating side wall 55 Bottom insulating layer 56 Top insulating layer 57 Interlayer insulating layer 58 First insulating layer 59 Second insulating layer 60 Second functional device 61 Seal conductor 62 Device region 63 Outer region 64 Seal plug conductor 65 Seal via conductor 66 First inner region 67 Second inner region 71 Through wiring 72 Low-potential connection wiring 73 Lead-out wiring 74 First connection plug electrode 75 Second connection plug electrode 76 Pad plug electrode 77 Substrate plug electrode 78 First electrode layer 79 Second electrode layer 80 Wiring plug electrode 81 High-potential connection wiring 82 Pad plug electrode 85 Dummy pattern 86 High-potential dummy pattern 87 First high-potential dummy pattern 88 Second high-potential dummy pattern 89 First region 90 Second region 91 Third region 92 First connection portion 93 First pattern 94 Second pattern 95 Third pattern 96 First periphery line 97 Second periphery line 98 First intermediate line 99 First connection line 100 Slit 130 Separation structure 140 Inorganic insulating layer141 First inorganic insulating layer 142 Second inorganic insulating layer 143 Low potential pad opening 144 High potential pad opening 145 Organic insulating layer 146 First portion 147 Second portion 148 Low potential terminal opening 149 High potential terminal opening 200 Signal transmission device 200p Primary circuit system 200s Secondary circuit system 210 Controller chip (first chip) 211 Pulse transmitting circuit (pulse generator) 212, 213 Buffer 220 Driver chip (second chip) 221, 222 Buffer 223 Pulse receiving circuit (RS flip-flop) 224 Driver 224H Upper driver 224L Lower driver 230 Transformer chip (third chip) 230a First wiring layer (lower layer) 230b Second wiring layer (upper layer) 231, 232 Transformer 231p, 232p Primary coil 231s, 232s Secondary coil 300 Transformer chip 301 First transformer 302 Second transformer 303 Third transformer 304 Fourth transformer 305 First guard ring 306 Second guard ring a1 to a8 Pads (corresponding to first current supply pads) b1 to b8 Pads (corresponding to first voltage measurement pads) c1 to c4 Pads (corresponding to second current supply pads) d1 to d4 Pads (corresponding to second voltage measurement pads) e1, e2 Pads A Electronic device A1H, A1L Amplifier B Vehicle CTRL Control circuit DRV1H, DRV1Ha, DRV1Hb, DRV1L, DRV1La, DRV1Lb Voltage drive circuit DRV2H, DRV2L Current drive circuit E DC power supply L1p, L2p Primary coil L1s, L2s, L3s, L4s Secondary coil M1H, M1Ha, M1Hb, M1L, M1La, M1Lb, M2H, M2L TransistorR1H, R1Ha, R1Hb, R1L, R1La, R1Lb, R2H, R2L, R3H, R3L Resistors SW1, SW2 Switch elements T11, T12, T13H, T13Ha, T13Hb, T13L, T13La, T13Lb, T14H, T14L, T15H, T15L External terminals T21, T22, T23, T24, T25, T26 External terminals X First direction X21, X22, X23 Internal terminals Y Second direction Y21, Y22, Y23 Wiring Z Normal direction Z21, Z22, Z23 Vias

Claims

1. A semiconductor device comprising: at least one voltage drive circuit configured to voltage-drive a switch control signal; and a current drive circuit configured to current-drive the switch control signal, wherein the at least one voltage drive circuit is turned on during a portion of a plurality of periods included in a logic level transition period of the switch control signal and turned off during the remaining periods, and the current drive circuit is turned on during all of the plurality of periods.

2. The semiconductor device according to claim 1, wherein the at least one voltage drive circuit includes a first voltage drive circuit configured to be connected to an application terminal of the switch control signal via a first resistor, and a second voltage drive circuit configured to be connected to an application terminal of the switch control signal via a second resistor different from the first resistor, and the logic level transition period includes a first period in which the first voltage drive circuit and the current drive circuit are turned on and the second voltage drive circuit is turned off, a second period in which the current drive circuit is turned on and the first voltage drive circuit and the second voltage drive circuit are turned off, and a third period in which the second voltage drive circuit and the current drive circuit are turned on and the first voltage drive circuit is turned off.

3. The semiconductor device according to claim 1 or 2, wherein said current driver circuit performs output feedback control so that the magnitude of the current flowing through the terminal to which said switch control signal is applied coincides with a reference current value.

4. The semiconductor device according to claim 3, further comprising a control circuit configured to arbitrarily adjust said reference current value.

5. The semiconductor device according to claim 1, further comprising a control circuit configured to arbitrarily adjust the periods during which said at least one voltage drive circuit and said current drive circuit are in an on state.

6. A semiconductor device according to any one of claims 1 to 5, wherein the at least one voltage driver circuit and the current driver circuit form at least one of an upper driver configured to raise the switch control signal from a low level to a high level, and a lower driver configured to lower the switch control signal from a high level to a low level.

7. The semiconductor device according to any one of claims 1 to 6, wherein the semiconductor device is a signal transmission device configured to transmit the switch control signal from the primary circuit system to the secondary circuit system while isolating the primary circuit system from the secondary circuit system, and the at least one voltage drive circuit and the current drive circuit are each provided in the secondary circuit system.

8. An electronic device comprising: a semiconductor device according to any one of claims 1 to 7; and a switch element configured to be driven by said semiconductor device.

9. The electronic device according to claim 8, wherein the switching element is an IGBT, a Si-MOSFET, or a SiC-MOSFET.

10. A vehicle equipped with an electronic device according to claim 8 or 9.

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