Liquid discharge head, recording device, and level shifter

Abstract

In a shifter body according to the present invention, a first FET of a first type and a second FET of the first type are connected in order from the power supply voltage side to the actuator side. A third FET of a second type and a fourth FET of the second type are connected in order from the actuator side to the reference potential side. An intermediate wire applies an intermediate potential between the reference potential and the power supply voltage to the gate of the second FET and the gate of the third FET. In bootstrapping, a first relay line connects an input section and the gate of the first FET. A second relay line connects the input section and the gate of the fourth FET. A capacitor is positioned on the first relay line. A diode connects the first FET side of the capacitor and the intermediate wire. When the first type is p-type, the cathode is connected to the capacitor side, and when the first type is n-type, the anode is connected to the capacitor side.

Description

Liquid ejection head, recording device and level shifter

[0001] The present disclosure relates to a liquid ejection head such as an inkjet head, a recording apparatus having the liquid ejection head, and a level shifter that can be used for the liquid ejection head.

[0002] There is known a liquid ejection head (e.g., an inkjet head) that ejects a liquid (e.g., ink) onto a recording medium (e.g., paper) (see, for example, Japanese Patent Application Laid-Open No. 2003-121994). The head has an actuator that applies pressure to the liquid to eject droplets (e.g., ink droplets) from the nozzles. The actuator operates in response to an input drive signal.

[0003] A liquid ejection head may have a level shifter that increases the amplitude of an input signal and outputs it. In the head disclosed in Patent Document 1, a switch circuit selectively connects multiple terminals that output different potentials to an actuator. This generates a drive signal having a predetermined waveform and inputs the drive signal to the actuator. The level of the signal that controls the switch circuit is then converted by the level shifter. Note that in Patent Document 1, the level shifter does not convert the level of the drive signal itself.

[0004] Various configurations of level shifters have been proposed. For example, FIG. 9 of Patent Document 2 below discloses a level shifter having four field effect transistors (FETs). Specifically, a p-type FET and an n-type FET are connected in sequence from the power supply voltage side to the reference potential side, and two such pairs of FETs are provided in parallel. A signal is input to the gate of the n-type FET and output from between the p-type FET and the n-type FET.

[0005] International Publication No. 2022 / 114002 Japanese Patent Application Laid-Open No. 2005-101965

[0006] A liquid ejection head according to one aspect of the present disclosure includes an actuator that ejects liquid from a nozzle and a level shifter that converts the level of a drive signal from an input section and inputs the converted signal to the actuator. The level shifter includes a shifter body connected to the actuator and a bootstrap interposed between the input section and the shifter body. One of the p-type and n-type FETs is referred to as a first type, and the other of the p-type and n-type FETs is referred to as a second type. In this case, the shifter body includes a first FET of the first type, a second FET of the first type, a third FET of the second type, and a fourth FET of the second type, and intermediate wiring. The first FET and the second FET are connected in this order from the power supply voltage side to the actuator. The third FET and the fourth FET are connected in this order from the actuator side to the reference potential side. The intermediate wiring applies an intermediate potential between the reference potential and the power supply voltage to the gates of the second FET and the third FET. The bootstrap has a first relay line, a second relay line, a capacitor, and a diode. The first relay line connects the input section and the gate of the first FET. The second relay line connects the input section and the gate of the fourth FET. The capacitor is located on the first relay line. The diode connects the first FET side of the capacitor to the intermediate wiring. If the first type is p-type, the cathode of the diode is connected to the capacitor side, and if the first type is n-type, the anode is connected to the capacitor side.

[0007] A liquid ejection head according to one aspect of the present disclosure includes a chip, a rigid wiring substrate, and a level shifter. The chip includes a nozzle and an actuator for ejecting liquid from the nozzle. The wiring substrate supports the chip and is electrically connected to the chip. The level shifter converts the level of a drive signal and inputs it to the actuator. At least a portion of the level shifter is included in the wiring substrate or is mounted on the wiring substrate.

[0008] A recording apparatus according to one aspect of the present disclosure includes a moving unit that relatively moves the liquid ejection head and a recording medium onto which the liquid ejected from the nozzles lands.

[0009] A level shifter according to one aspect of the present disclosure converts the level of a signal from an input section and outputs the converted signal to an output section. The level shifter includes a shifter body connected to the output section and a bootstrap interposed between the input section and the shifter body. One of the p-type and n-type FETs is referred to as a first type, and the other of the p-type and n-type FETs is referred to as a second type. The shifter body includes a first FET of the first type, a second FET of the first type, a third FET of the second type, and a fourth FET of the second type, and intermediate wiring. The first FET and the second FET are connected in this order from the power supply voltage side to the output section. The third FET and the fourth FET are connected in this order from the output section side to the reference potential side. The intermediate wiring applies an intermediate potential between the reference potential and the power supply voltage to the gates of the second FET and the third FET. The bootstrap includes a first relay line, a second relay line, a capacitor, and a diode. The first relay line connects the input section and the gate of the first FET. The second relay line connects the input section and the gate of the fourth FET. The capacitor is located on the first relay line. The diode connects the first FET side of the capacitor and the intermediate wiring. If the first type is p-type, the cathode is connected to the capacitor side, and if the first type is n-type, the anode is connected to the capacitor side.

[0010] 1. A schematic perspective view of a recording apparatus according to an embodiment. A perspective view showing an outline of a liquid ejection head of the recording apparatus of FIG. 1. An exploded perspective view of the liquid ejection head of FIG. 2. A cross-sectional view taken along line IV-IV of FIG. 2. A perspective view showing an outline of a chip of the liquid ejection head of FIG. 2. An exploded perspective view of the chip of FIG. 5. A perspective view of a portion of the chip showing a cross-section taken along line VII-VII of FIG. 5. A schematic plan view showing an enlarged view of region VIII of FIG. 2. A cross-sectional view showing another example of a driver IC. A block diagram showing the configuration of a signal processing system of the recording apparatus of FIG. 1. A block diagram showing details of range XI of FIG. 10. A block diagram showing details of range XII of FIG. 11. A circuit diagram showing the configuration of the level shifter shown in FIG. 12. A schematic diagram showing the operation of the level shifter of FIG. 13. A schematic diagram showing an example of a drive signal input to the level shifter of FIG. 13. A circuit diagram showing another example of a FET.

[0011] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The drawings used in the following description are schematic. Therefore, for example, the dimensional ratios in the drawings do not necessarily correspond to the actual ones. Furthermore, the dimensional ratios may not match between drawings. Certain shapes and / or dimensions may be exaggerated, and details may be omitted. However, the above does not deny that the actual shapes and / or dimensions may be as shown in the drawings, or that features of shapes and / or dimensions may be extracted from the drawings.

[0012] For convenience, the drawings may include a Cartesian coordinate system D1D2D3. As will be understood from the description below, in the configurations illustrated in the drawings, the term "D1 direction" may be replaced with the term "direction intersecting the transport direction of the recording medium" and / or the term "longitudinal direction of the head." The term "D2 direction" may be replaced with the term "transport direction" and / or the term "shortitudinal direction of the head." The term "D3 direction" may be replaced with the term "normal direction of the ejection surface of the head" and / or the term "opposing direction between the head and the recording medium." The liquid ejection head and recording apparatus according to the embodiment may be used in any orientation. However, for convenience, terms may be used assuming that the +D3 side is upward.

[0013] 1 is a perspective view that schematically shows a printer 1 (an example of a recording device) according to an embodiment. The printer 1 is configured as a color printer that forms an image on printing paper P. Specifically, when the printing paper P is transported in the direction D2, four heads 3 (an example of a liquid ejection head) positioned above the printing paper P eject ink (an example of a liquid) toward the printing paper P.

[0014] 7 is a cross-sectional view of a portion of the underside (nozzle surface 5a) of the head 3. The head 3 has nozzles 9 (nozzles 9A in FIG. 7) that open to the nozzle surface 5a, and actuators 11 that apply pressure to flow paths leading to the nozzles 9. When a drive signal is input to the actuator 11, ink droplets (an example of liquid droplets) are ejected from the nozzles 9.

[0015] Fig. 13 is a circuit diagram showing the configuration of a post-stage shifter 101 (an example of a level shifter) that inputs a drive signal to the actuator 11. Fig. 14 is a schematic diagram showing the operation of the post-stage shifter 101. Note that although it is referred to as the post-stage shifter 101 for convenience, a pre-stage shifter 135 (described later) is not an essential requirement for the printer 1.

[0016] The post-stage shifter 101 converts the level of a drive signal (sometimes referred to as "signal Vin1") input to the input unit 103. Then, the post-stage shifter 101 outputs the drive signal (sometimes referred to as "signal Vout") with the converted level to the output unit 105. The signal Vout is input to the actuator 11 connected to the output unit 105. By converting the level of the drive signal (or, from another perspective, increasing the amplitude) by the post-stage shifter 101, the drive signal has an amplitude corresponding to, for example, the amount of operation required of the actuator 11.

[0017] The rear-stage shifter 101 has a shifter body 107 connected to the actuator 11 (output unit 105) and a bootstrap 109 interposed between the input unit 103 and the shifter body 107. The shifter body 107 is connected to a power supply voltage Vdd (assumed to be a positive potential unless otherwise specified) and a reference potential GND, and selectively outputs a low-level (e.g., reference potential GND) or high-level (e.g., power supply voltage Vdd) signal to the output unit 105 in accordance with a signal input from the input unit 103 via the bootstrap 109. When the signal Vin1 from the input unit 103 is high, the bootstrap 109 raises the level of the signal and inputs it to the shifter body 107. This enables the shifter body 107 to perform the output operation described above, as will be understood from the description below.

[0018] The shifter body 107 has, for example, the following components: A first p-type FET 111A and a second p-type FET 111B: Connected in this order from the power supply voltage Vdd side to the output unit 105 side. A third n-type FET 111C and a fourth n-type FET 111D: Connected in this order from the output unit 105 side to the reference potential GND side. An intermediate wiring 113: Applying an intermediate potential Vm (for example, (Vdd-GND) / 2) between the reference potential GND and the power supply voltage Vdd to the gate of the second FET 111B and the gate of the third FET 111C.

[0019] The bootstrap 109 has, for example, the following components: First relay line 115: Connects the input unit 103 and the gate of the first FET 111A. Second relay line 117: Connects the input unit 103 and the gate of the fourth FET 111D. Capacitor 119: Located on the first relay line 115. Diode 121: The cathode is connected to the first FET 111A side of the capacitor 119. The anode is connected to the intermediate wiring 113.

[0020] By including the above-described components in the shifter main body 107, as will be described in detail later, for example, a voltage ((Vdd-GND) / 2) that is approximately half the potential difference between the power supply voltage Vdd and the reference potential GND is applied to each FET. In other words, the potential difference (Vdd-GND) is not applied to each FET. This allows the withstand voltage of the FET to be lowered compared to the voltage of the drive signal input to the actuator 11. As a result, for example, as will be described later, TFTs (Thin Film Transistors) built into a Low Temperature Polycrystalline Silicon (LTPS) substrate of the head 3 can be used as the FETs.

[0021] Furthermore, since the bootstrap 109 includes the above-described components, as will be described in detail later, it can generate a signal Vin2 that oscillates between the intermediate potential Vm and the power supply voltage Vdd based on a signal Vin1 that oscillates between the reference potential GND and the intermediate potential Vm, and input the signal Vin2 to the first FET 111A. This in turn can generate a signal Vout that oscillates between the reference potential GND and the power supply voltage Vdd. In other words, the combination of the bootstrap 109 and the shifter main body 107 doubles the amplitude of the drive signal. Moreover, the configuration is simple.

[0022] The configuration of the post-stage shifter 101 in the illustrated example is based on the premise that the power supply voltage Vdd is a positive potential. A similar configuration can be adopted even when the power supply voltage Vdd is a negative potential. In that case, however, the configuration of the post-stage shifter 101 is such that the first FET 111A and the second FET 111B are n-type, the third FET 111C and the fourth FET 111D are p-type, and the orientation of the diode 121 is reversed. As described above, the intermediate potential Vm is a potential intermediate between the reference potential GND and the power supply voltage Vdd, but is a negative potential. In the description of the embodiments, the illustrated configuration is basically taken as an example.

[0023] The above is an overview of the embodiment. Below, the details of the embodiment will be explained roughly in the following order: 1. Printer in general (Fig. 1) 2. Head (Figs. 2 to 4) 2.1. Overview of the new head structure 2.2. Overall configuration of the head 3. Chip (Figs. 5 to 7) 3.1. Chip in general 3.2. Chip outer shape and terminals 3.3. Flow path and actuator 3.4. Chip structural type 3.5. Specific examples of MEMS chips 4. Wiring substrate 4.1. Wiring substrate in general 4.2. Specific examples of circuits (Fig. 8) 5. Driver IC 5.1. Example of chip type 5.2. Example of built-in type (Fig. 9) 6. Discharge operation (Fig. 15) 7. Configuration of signal processing system 7.1. Overall configuration of signal processing system (Fig. 10) 7.2. Configuration of signal processing system for each chip (Fig. 11) 7.3. Configuration of signal processing system for each actuator (Fig. 12) 7.4. Post-stage shifter 7.4.1. Configuration of post-stage shifter (Fig. 13) 7.4.2. Operation of post-stage shifter (Fig. 14) 7.4.3. Other examples of FET (Fig. 16) 7.5. Hardware of signal processing system 8. Summary of embodiments

[0024] (1. Printer in General) The printer 1 (FIG. 1) may have various configurations, excluding the configuration related to the post-stage shifter 101, and may have, for example, a known configuration. The printer 1 illustrated in FIG. 1 is merely an example. Below, the printer 1 in general will be briefly described, taking the configuration of the printer 1 illustrated in FIG. 1 as an example.

[0025] The printer 1 is configured as, for example, a so-called line printer. That is, the head 3 has a length that spans almost the entire width (direction D1) of the printing paper P transported in direction D2, and prints on the printing paper P without moving itself. However, the printer 1 is not limited to a line printer. For example, the printer 1 may be a serial printer. In a serial printer, for example, movement of the head in a direction intersecting the transport direction of the printing paper P and transport of the printing paper P are alternated, and printing is performed during movement in direction D1. Note that, for convenience, in the description of the embodiments, a line printer may be assumed without special mention.

[0026] The printer 1 has, for example, four (in other words, multiple) heads 3. Note that a portion that includes a combination of the four heads 3 and functions as a head may be referred to as a unit 13. The four heads 3 are arranged, for example, in the transport direction of the printing paper P. The four heads 3 correspond to inks of different colors (four color inks). The four color inks are, for example, magenta (M), yellow (Y), cyan (C), and black (K). This allows the printer 1 to function as a color printer.

[0027] Unlike the above description, the printer 1 may print in a single color, or conversely, may print in more than four colors. In other words, the number of colors is arbitrary. Two or more heads 3 may correspond to one color. In this case, for example, the resolution can be increased. Conversely, one head 3 may correspond to two or more colors. As can be understood from the above, the number of heads 3 that the printer 1 has is arbitrary.

[0028] The multiple heads 3 of the unit 13 may be fixed to one another by any suitable method. In the example of Fig. 1, the multiple heads 3 are supported by a support member 15 of the unit 13, and are thereby fixed to one another. The support member 15 has, for example, four openings (not shown) (i.e., the same number as the number of heads 3) that expose the four heads 3 downward.

[0029] The printer 1 prints on, for example, sheets of paper as printing paper P. However, the printing paper P may also be roll paper. The size of the printing paper P (or, from another perspective, the length of the head 3 in the D1 direction) is also arbitrary. For example, the printing paper P may be small like a receipt, a size commonly used in an office, or large like a poster.

[0030] The transport device 17 for transporting the printing paper P may have any configuration. The example in Fig. 1 illustrates a configuration in which the printing paper P is transported by transporting a belt that adsorbs the printing paper P. Other configurations include a configuration in which the printing paper P is transported by rotating rollers that sandwich the printing paper P, and a configuration in which the printing paper P is transported by rotating a drum wrapped around the printing paper P. The transport device 17 is an example of a moving unit that moves the head (3) and the recording medium (P) relative to each other.

[0031] The printer 1 may have, in addition to the head 3 (or, from another perspective, the unit 13) and the transport device 17 already described, a controller 19 that controls the head 3 and the transport device 17. The controller 19 is configured to include, for example, a computer, and controls the head 3 and the transport device 17 (its motor 17a) based on print data that includes image data (which is a broad concept that includes text).

[0032] The printer 1 may have any components other than those described above. For example, the printer 1 may have a drying device that accelerates drying of the ink, an application device that uniformly applies a transparent coating agent to the printing paper P, and a cleaning device that cleans the head 3. Note that the printer 1 may use the head 3 to apply a coating agent in addition to or instead of printing with colored ink.

[0033] (2. Head) The head 3 may have various configurations, for example, a known configuration, as long as it has the post-stage shifter 101. In the description of the embodiment, a novel configuration will be exemplified. Other examples of heads that may have the post-stage shifter 101 include the following configurations (see also Patent Document 1).

[0034] Another example of a head includes, for example, a head body and a flexible substrate connected to the head body. The head body includes a nozzle and an actuator that ejects liquid (e.g., droplets) from the nozzle. The flexible substrate contributes to electrically connecting the actuator to, for example, a driving IC (Integrated Circuit) that drives the actuator.

[0035] Furthermore, the head according to the other example described above includes, for example, multiple head bodies and a frame that supports the multiple head bodies. The multiple head bodies are arranged, for example, in a staggered pattern as viewed from the recording medium. This makes it possible to realize, for example, a line head having a length that spans almost the entire width of the recording medium while using a small head body. The frame is a purely structural member and plays no role from an electrical perspective.

[0036] (2.1. Outline of the Novel Structure of the Head) Fig. 2 is a perspective view of the head 3 (the whole head 3 or at least a part of the head 3 on the side of the printing paper P). Fig. 3 is an exploded perspective view of the head 3.

[0037] The head 3 has a plurality of chips 5 that eject ink droplets (liquid droplets) and directly contribute to printing, and a wiring substrate 7 (rigid substrate) that supports the plurality of chips 5. When viewed in the D3 direction (viewing the head 3 from the printing paper P), the plurality of chips 5 are arranged in two staggered rows along the D1 direction. This allows, for example, a line head that has a length that spans almost the entire width of the printing paper P while using small chips 5. Of the plurality of chips 5, the one on the -D2 side is sometimes referred to as chip 5A, and the one on the +D2 side is sometimes referred to as chip 5B. Unlike the example shown, the head 3 may have only one chip 5.

[0038] FIG. 5 is a perspective view of the chip 5 (5B) as seen from the side of the printing paper P. The chip 5 has a plurality of nozzles 9 (as described above). The arrangement of the plurality of nozzles 9 is arbitrary. In the example of FIG. 5, the plurality of nozzles 9 are arranged in two staggered rows along the D1 direction when viewed in the D3 direction (with 9A on the -D2 side and 9B on the +D2 side). Note that, because FIG. 5 is a schematic diagram, the nozzles 9 are shown large relative to the size of the chip 5, and the number of nozzles 9 in one chip 5 is shown to be small. In reality, the nozzles 9 may be smaller and the number of nozzles 9 may be greater than in FIG. 5.

[0039] 7, which was referred to in the overview of the embodiment, is a perspective view of a part of the chip 5 (5B) showing a cross section taken along line VII-VII in Fig. 5. The chip 5 has an actuator 11 (already described) for each nozzle 9.

[0040] As described above, in the illustrated example, the multiple chips 5 are supported by the wiring board 7. The wiring board 7 is also electrically connected to the chips 5. As a result, for example, the wiring board 7 contributes to inputting a drive signal to the actuator 11. In this way, the wiring board 7 functions as a member that doubles as a flexible substrate and a frame in the head according to the other example described above. This reduces the number of parts. As a result, for example, cost reduction and / or miniaturization can be expected.

[0041] (2.2. Overall Configuration of Head) In addition to the multiple chips 5 and wiring board 7, the head 3 may include, for example, the following components: At least one (multiple in the illustrated example) driver IC 21: For example, including a post-stage shifter 101 (i.e., driving the actuator 11). Control IC 23: For example, controlling the driver IC 21. Signal board 25: For example, made of a flexible board, and inputs control signals from outside the head 3 (from another perspective, the controller 19) to the control IC 23 via the wiring board 7. At least one (two in the illustrated example) power board 27: For example, made of a flexible board, and applies power (from another perspective, potential) from outside the head 3 to the wiring board 7 and electronic components (for example, the driver IC 21) mounted on the wiring board 7.

[0042] The multiple driver ICs 21 are arranged in a staggered pattern in two rows, for example, when viewed in the D3 direction, so as to be positioned between the multiple chips 5. That is, the multiple chips 5 and the multiple ICs 21 are alternately arranged in two rows, forming a first row 29A on the -D2 side and a second row 29B on the +D2 side. Of the multiple driver ICs 21, the one on the -D2 side may be referred to as driver IC 21A, and the one on the +D2 side may be referred to as driver IC 21B. The number of driver ICs 21 is, for example, the same as the multiple chips 5. Each driver IC 21 controls one chip 5. More specifically, for example, each driver IC 21 controls the chips 5 adjacent to each other in the D2 direction.

[0043] The number and arrangement of the driving ICs 21, control ICs 23, signal boards 25, and power boards 27 may be different from the illustrated example. For example, the driving ICs 21 do not have to be arranged in a staggered pattern. The control ICs 23 may not be provided. Two sets of control ICs 23 and signal boards 25 may be provided on both longitudinal sides of the wiring board 7. Furthermore, for example, the power board 27 may be extended to both longitudinal sides of the wiring board 7. The power board 27 does not have to fit within the width (D2 direction) of the wiring board 7. The power board 27 may be provided at multiple positions in the D1 direction and extend in the D2 direction. The signal board 25 and the power board 27 may be integrated. A connector may be provided on the wiring board 7 instead of the flexible boards (25, 27). Note that, for convenience, in describing the embodiments, the illustrated example may be used as a premise unless otherwise specified.

[0044] FIG. 4 is a cross-sectional view taken along line IV-IV in FIG.

[0045] As shown in Figures 2 to 4, the multiple chips 5, driver IC 21, and control IC 23 are mounted, for example, on the +D3 side surface of the wiring board 7 (the surface opposite the printing paper P). The wiring board 7 has multiple openings 31 (Figures 3 and 4) that expose the multiple chips 5 on the -D3 side. This allows the chips 5 to eject ink on the -D3 side. The signal board 25 and power board 27 are bonded to the +D3 side surface of the wiring board 7.

[0046] Unlike the illustrated example, the chip 5 may be mounted on the surface of the wiring substrate 7 on the -D3 side. From another perspective, the relationship between the direction in which the chip 5 is bonded to the wiring substrate 7 and the direction in which the nozzles 9 open is arbitrary. The wiring substrate 7 may also have a conductor layer on the surface on the -D3 side. In such an embodiment, the opening 31 of the wiring substrate 7 may contribute to, for example, the supply of ink to the chip 5.

[0047] The head 3 may have components other than those described above. For example, although not specifically shown, the following components may be provided: A plurality of first flow path members that are individually (one-to-one) stacked on the +D3 side of a plurality of chips 5 and supply liquid; A second flow path member that is commonly stacked on the +D3 side of the plurality of first flow path members and supplies liquid to the plurality of first flow path members; A control board that is connected to the wiring board 7 via the signal board 25 and the power board 27; A heat sink that cools the control board; A housing that is placed over the wiring board 7 from above and that houses the various components described above.

[0048] For example, in the case where the above-mentioned components not shown are provided, only the combination of the components shown in the figures may be regarded as the head, or only the chip 5 and the wiring board 7 may be regarded as the head. Also, only the combination of the components shown in the figures may be distributed as the head, or only the combination of the chip 5 and the wiring board 7 may be distributed, with the other components being added later.

[0049] (3. Chip) (3.1. Chip in general) The chip 5 may have various configurations as long as it has a nozzle 9 and an actuator 11. For example, the ink ejection method may be a piezoelectric method, a thermal method, or another method. In a piezoelectric method, ink is ejected by applying pressure to the ink through deformation of a piezoelectric body. In a thermal method, ink is ejected by applying pressure to the ink by heating the ink to generate bubbles. Other methods include, for example, a method that uses electrostatic force to attract charged ink, a method that uses ultrasonic energy, and a method that uses electrostatic force to vibrate the wall of a pressure chamber that contains ink.

[0050] As can be understood from the above, the term "actuator" may be interpreted broadly. That is, the actuator (11) may have various configurations as long as it can convert an input electrical signal into movement of ink (liquid). For example, the actuator (11) may be one that generates displacement, such as a piezoelectric element, one that generates heat, such as a thermal heater, or one that directly applies electrostatic force to ink. In the description of the embodiment, a piezoelectric element will be taken as an example.

[0051] As described above, the multiple chips 5 are arranged in a staggered pattern in, for example, two rows. In this case, the total number of chips 5 may be three or more. The total number of chips 5 may be an even number (as in the illustrated example) or an odd number. In different rows, the ends of the chips 5 in the D1 direction overlap each other when viewed in the D2 direction. This makes it possible to print without gaps in the D1 direction. In each row, the pitch (e.g., center-to-center distance) of the multiple chips 5 is generally constant. The chips 5 may also be arranged in three or more rows.

[0052] (3.2. Chip Outer Shape and Terminals) The outer shape of the chip 5 is arbitrary. In the examples of FIGS. 2 to 5, the chip 5 is roughly a thin rectangular parallelepiped with the D1 direction as the longitudinal direction and the D3 direction as the thickness direction. More specifically, as shown in FIGS. 4 and 5, the chip 5 has a rectangular parallelepiped main body 5e and two flanges 5f protruding on both sides in the D2 direction from the +D3 side (the side opposite the nozzles 9) of the main body 5e. The lower surface of the main body 5e forms a nozzle surface 5a where the multiple nozzles 9 open.

[0053] The main body 5e is inserted into the opening 31 from the +D3 side. The flange 5f engages with the wiring board 7 from the +D3 side around the opening 31. As will be described later, the flange 5f has its lower surface joined to the upper surface of the wiring board 7, thereby contributing to the fixing and / or electrical connection of the chip 5 to the wiring board 7. Unlike the illustrated example, the shape of the chip 5 may be, for example, a rectangular parallelepiped.

[0054] The chip 5 and the wiring board 7 may be electrically connected in any manner. In other words, the terminals of the chip 5 may be provided in any manner. In the illustrated example, the chip 5 has a plurality of terminals 35 ( FIG. 5 ) made of layered conductors on the underside of the flange 5 f. Meanwhile, the wiring board 7 has pads 37 ( FIG. 4 ) around the opening 31 to be bonded to the terminals 35. The terminals 35 and the pads 37 are electrically connected by being bonded to each other while facing each other.

[0055] Unlike the illustrated example, for example, a terminal located on the upper surface of the chip 5 and a pad located on the upper surface of the wiring substrate 7 may be connected by a bonding wire. Also, for example, a pin-shaped terminal protruding from the chip 5 may be joined to a pad located on the upper surface of the wiring substrate 7. Also, for example, a pin protruding from the chip 5 may be inserted into the wiring substrate 7 to perform through-hole mounting.

[0056] The terminals 35 and the pads 37 may be joined by any method. For example, an anisotropic conductive film (ACF) connection may be used. More specifically, for example, thermocompression bonding may be performed by sandwiching an ACF between substantially the entire lower surface of the flange 5f and the upper surface of the wiring board 7. The portion of the ACF sandwiched between the terminals 35 and the pads 37 may contribute to fixation and electrical connection. The other portion of the ACF may contribute to fixation (and insulation).

[0057] The terminals 35 include, for example, terminals 35D to which drive signals for driving the actuators 11 are input, and at least one terminal 35G (FIG. 4) to which a reference potential is applied. The potential difference between the reference potential and the drive signal is utilized to drive the actuators 11.

[0058] (3.3. Flow Channel and Actuator) As will be understood from the above description, the ink flow channel (including the nozzle 9) and the actuator 11 may have any configuration. An example is shown below.

[0059] FIG. 6 is an exploded perspective view of the chip 5 (5B).

[0060] As shown in Figures 6 and 7, a common flow path 47 opens onto the top surface of the chip 5. Ink is supplied to the common flow path 47 from a flow path member (not shown) that is overlaid on the top surface of the chip 5. As shown in Figure 7, a plurality of individual flow paths 49 communicate with the common flow path 47. Each individual flow path 49 has, in order from the common flow path 47 side, a supply path 49a, a pressure chamber 51, and a nozzle 9. Ink from the common flow path 47 is replenished into the pressure chamber 51 via the supply path 49a. Liquid is ejected from the nozzle 9 when pressure is applied to the pressure chamber 51 by the actuator 11.

[0061] The specific shapes and dimensions of the common flow path 47 and the multiple individual flow paths 49 are arbitrary. In the illustrated example, the common flow path 47 extends linearly in the longitudinal direction of the chip 5 at a position toward the center of the chip 5 in the width direction. The multiple individual flow paths 49 generally extend from the common flow path 47 to one side or the other in the width direction of the chip 5, and a nozzle 9 is located at the tip of each individual flow path 49. The nozzle 9 opens directly into the pressurizing chamber 51.

[0062] 7 is a so-called unimorph type piezoelectric actuator. The actuator 11 has, for example, a vibration plate 53, a lower electrode 55, a piezoelectric body 57, and an upper electrode 59, in that order from the pressure chamber 51 side. These, for example, generally cover the pressure chamber 51. The piezoelectric body 57 is polarized in the thickness direction.

[0063] When a voltage is applied to the piezoelectric body 57 in the thickness direction by the lower electrode 55 and the upper electrode 59, the piezoelectric body 57 expands or contracts in the planar direction. This deformation is restricted by the vibration plate 53, so that the actuator 11 bends toward the pressure chamber 51 or the opposite side like a bimetal. This bending deformation is used to apply pressure to the pressure chamber 51, causing ink to be ejected from the nozzle 9.

[0064] (3.4. Chip Structural Type) The outline of the chip 5, the terminals 35, the flow paths (47 and 49), the actuator 11, and the like described so far may be realized by any of a variety of structural types. For example, the chip 5 may be configured by a MEMS (Micro Electro Mechanical Systems) chip. A MEMS chip includes, for example, one or more chip substrates on which mechanical elements and / or electrical elements are formed by microfabrication technology on a base substrate. Two or more chip substrates are, for example, stacked. The base substrate may be, for example, a silicon substrate. However, the material of the base substrate may be a material other than silicon (for example, glass or an organic material). The mechanical and electrical elements of the chip substrate, with respect to the chip 5, are, for example, the flow paths (47 and 49), the actuator 11, and the terminals 35.

[0065] In a MEMS chip including multiple chip substrates, each chip substrate may have only one of mechanical elements and electrical elements. From another perspective, the mechanical elements and electrical elements may be provided on separate substrates. When the MEMS chip is a stack of multiple substrates, all of the multiple substrates may be MEMS-related chip substrates, or only some of the substrates may be MEMS-related chip substrates.

[0066] Microfabrication techniques related to MEMS are usually performed on a mother substrate (wafer) from which a large number of base substrates are obtained. Examples of microfabrication techniques include: thin film formation by PVD (Physical Vapor Deposition, e.g., sputtering), CVD (Chemical Vapor Deposition), or ALD (Atomic Layer Deposition); patterning of the above thin film using photolithography; and etching of the base substrate using photolithography. The precision of the microfabrication may be, for example, 20 μm or less, 10 μm or less, or 2 μm or less in a plan view.

[0067] Unlike the above description, the chip 5 does not have to be a MEMS chip. For example, the chip 5 may be formed by bonding a flow path member including the nozzle 9 and an actuator substrate including the actuator 11 together. In this case, the flow path member may be formed by bonding a plurality of stacked plates (metal plates and / or resin plates) together with an adhesive. Each plate may have recesses and / or through holes that become the flow paths formed by wet etching. The actuator substrate may be fabricated by stacking and firing ceramic green sheets to which a conductive paste is applied in a predetermined pattern.

[0068] (3.5. Specific Example of MEMS Chip) When the chip 5 is configured by a MEMS chip, the specific configuration thereof is arbitrary. An example is shown below.

[0069] 6, the chip 5 is configured, for example, by stacking multiple (four in the illustrated example) chip substrates (as already described) in the D3 direction and bonding them together. More specifically, a nozzle substrate 39, an actuator substrate 41, a support substrate 43, and a relay substrate 45 are stacked in this order from the -D3 side (the side of the printing paper P).

[0070] The nozzle substrate 39 has, for example, a plurality of nozzles 9. The actuator substrate 41 has, for example, a plurality of actuators 11, and has flow paths that supply ink to the plurality of nozzles 9. The support substrate 43, for example, contributes to the reinforcement of the nozzle substrate 39 and the actuator substrate 41, and has flow paths and circuits (which may be simple wiring) that lead to the flow paths and circuits of the actuator substrate 41. The relay substrate 45 has, for example, flow paths and circuits that lead to the flow paths and circuits of the support substrate 43, and also has a flange 5 f.

[0071] These chip substrates may be bonded together by an appropriate bonding method. For example, the chip substrates may be bonded directly without an adhesive, or may be bonded together using an adhesive. Note that in FIG. 7, the adhesive may be omitted regardless of whether direct bonding is used. The thickness of each chip substrate may be set appropriately depending on the functions required of each chip substrate. For example, the thickness of each of the nozzle substrate 39 and the actuator substrate 41 is 20 μm or more and 100 μm or less. The thickness of each of the support substrate 43 and the relay substrate 45 is 200 μm or more and 1000 μm or less.

[0072] Each chip substrate (39, 41, 43, and 45) is configured as follows, for example:

[0073] The nozzle substrate 39 is configured by forming a plurality of nozzles 9 on a base substrate using microfabrication technology. The base substrate is, for example, a silicon substrate. The shape and dimensions of the nozzles 9 are arbitrary.

[0074] 7, the actuator substrate 41 is configured by forming a laminated film 41b on a base substrate 41a by microfabrication technology. The laminated film 41b includes the actuator 11.

[0075] The base substrate 41a is, for example, a silicon substrate. The pressure chamber 51 and a part of the supply path 49a are formed on the base substrate 41a by microfabrication technology. The specific shapes and dimensions of the pressure chamber 51 and the supply path 49a are not limited.

[0076] The laminated film 41b has, for example, at least four layers including the above-mentioned diaphragm 53, lower electrode 55, piezoelectric body 57, and upper electrode 59. Although not particularly shown, the laminated film 41b may include layers other than those described above. For example, the laminated film 41b may have an insulating layer that covers the metal layer to prevent ink from contacting the metal layer, or an insulating layer that covers the metal layer including the lower electrode 55 and the metal layer including the upper electrode 59 to insulate them from each other.

[0077] 7, the metal layer (reference potential layer) including the lower electrode 55 has, for example, a wiring (reference numeral omitted) extending from the lower electrode 55 to the side of the terminal 35G already described (the +D2 side in the chip 5B), and a terminal 61G (see also FIG. 6) located at the end of the wiring. The terminal 61G is connected to the terminal 35G via the support substrate 34. In the example of FIG. 6, the terminal 61G is common to a plurality of actuators 11.

[0078] 7, the metal layer including the upper electrode 59 has, for example, a wiring (reference numeral omitted) extending from the upper electrode 59 to the side of the terminal 35D already described (the -D2 side in the case of the chip 5B), and a terminal 61D (see also FIG. 6) located at the end of the wiring. The terminal 61D is connected to the terminal 35D via the support substrate 34.

[0079] The support substrate 43 is configured by forming appropriate shapes and conductors on a base substrate (reference numeral omitted) using microfabrication technology. As described above, the base substrate is, for example, a silicon substrate. The shapes formed on the base substrate include, for example, a through-hole (slit) that forms a portion of the lower side of the common flow path 47, and a recess (groove) that accommodates the actuator 11 and is formed on the underside of the base substrate. The conductor formed on the base substrate is, for example, a through-conductor 43b that connects terminals 61D and 61G of the actuator substrate 41 to terminals 35D and 35G on the underside of the flange 5f.

[0080] The relay substrate 45 is formed wider in the D2 direction than the support substrate 43. As a result, the previously described flange 5f is formed by the edge of the relay substrate 45. The relay substrate 45 is formed by forming an appropriate shape and conductors on a base substrate (reference numeral omitted) using microfabrication technology. As previously described, the base substrate is, for example, a silicon substrate. The shape formed on the base substrate is, for example, a through-hole (slit) that forms a portion of the upper side of the common flow path 47. The conductors formed on the base substrate are, for example, the previously described terminals 35D and 35G.

[0081] The actuator substrate 41 and the support substrate 43 are bonded together via, for example, ACF 63. This electrically connects the plurality of terminals 61D and 61G of the actuator substrate 41 to the plurality of through conductors 43b of the support substrate 43 individually. The support substrate 43 and the relay substrate 45 are bonded together via, for example, ACF 65. This electrically connects the plurality of through conductors 43b of the actuator substrate 41 to the plurality of terminals 35D and 35G of the relay substrate 45 individually.

[0082] (4. Wiring Board) (4.1. General Wiring Boards) The wiring board 7 shown in FIGS. 2 to 4 may be of any type as long as it is a rigid board. For example, the wiring board 7 may be a single-sided board having a conductor layer on only one side of an insulating substrate, a double-sided board having conductor layers on both sides of an insulating substrate, or a multi-layer board having three or more conductor layers. Furthermore, the wiring board 7 having two or more conductor layers may be a build-up type in which insulating layers and conductor layers are sequentially formed on the top surface of a core insulating substrate, or may be a type in which combinations of insulating layers and conductor layers are bonded together. The material of the insulating substrate is also arbitrary, and may be, for example, resin, ceramic, or glass.

[0083] In one example, the wiring substrate 7 may be a low-temperature polycrystalline silicon (LTPS) substrate. The LTPS substrate is fabricated by, for example, polycrystallizing amorphous silicon formed on a glass substrate at a low temperature of 600°C or less using laser annealing or the like. That is, although not specifically shown, the LTPS substrate includes a glass substrate and an LTPS layer overlying the glass substrate. A circuit including elements such as thin film transistors (TFTs) may be configured by doping the LTPS layer, forming a thin film (e.g., a metal film and / or an insulating film), and patterning the thin film. A circuit including an LTPS layer is sometimes referred to as an LTPS circuit.

[0084] The pattern of the conductor layer of the wiring board 7 (or, from another perspective, the circuit configuration) is arbitrary as long as it is possible to mount the chip 5 and to electrically connect the chip 5 to other electrical elements (here, the driving IC 21). In the illustrated example, the wiring board 7 is configured so that the driving IC 21 and the control IC 23 can be mounted thereon. Unlike the illustrated example, for example, the wiring board 7 may be configured to simply act as an intermediary between the chip 5 and the flexible substrate, and the driving IC 21 and the like may be mounted on the flexible substrate. Even in this case, the degree of freedom in the connection position and shape of the flexible substrate is improved compared to, for example, an embodiment in which a flexible substrate is connected to multiple chips 5.

[0085] The wiring board 7 (its circuit) may simply have wiring, or may have electronic elements. The electronic elements may be, for example, passive elements or active elements. Furthermore, the electronic elements may be, for example, switches, registers, latch circuits, ICs, or power supply circuits. When the wiring board 7 has electronic elements, the electronic elements may be either built-in or embedded. The former electronic elements are, for example, manufactured integrally with the substrate portion of the wiring board 7 at the same time as the wiring board 7 is manufactured. In the latter electronic elements, for example, a pre-manufactured electronic element (e.g., an IC chip) is embedded in the substrate portion of the wiring board 7 when the wiring board 7 is manufactured.

[0086] The wiring board 7 may have any shape and size. For example, the wiring board 7 may have a substantially rectangular shape with the D2 direction as its longitudinal direction.

[0087] (4.2. Specific Examples of Circuits) As described above, the wiring board 7 may have various wirings and / or circuits. The arrangement thereof is also arbitrary. An example is shown below.

[0088] 8 is a schematic plan view showing the wiring board 7 in region VIII of FIG. 2. In this figure, the chip 5, the driver IC 21, and the control IC 23 are also shown by dotted lines. For convenience of illustration, the number of wires on the wiring board 7 may be shown to be significantly less than the actual number. In FIG. 8, only a portion of the wiring board 7 is shown. However, with the exception of a portion (for example, a portion related to the control IC 23), the same configuration as shown in the figure is generally repeated on the -D1 side.

[0089] The wiring board 7 has, for example, the following configuration in the signal path from the signal board 25 to the chip 5: At least one pad 69 (two in the illustrated example): connected to the signal board 25. At least one wire 71 (two in the illustrated example): extending from the pad 69 to some of the pads 73 described below. Pads 73: mounted with the control IC 23. Wires 75: extending from pads 73 to which the wire 71 is not connected and reaching the relay circuit 67 described below. At least one relay circuit 67 (the same number as the driver ICs 21 in the illustrated example): having, for example, a bootstrap 109 (already described). Wires 77: extending from the relay circuit 67 to some of the pads 79 described below. Pads 79: mounted with the driver ICs 21. Wires 81: extending from pads 79 to which the wire 77 is not connected and reaching some of the pads 37 to which the chip 5 is mounted.

[0090] The wiring board 7 has, for example, the following configuration in the paths from the power board 27 to the chips 5 and the like: At least one each of pads 83A and 83B (the same number as the number of driver ICs 21 in the illustrated example): To which the power board 27 is connected. Of the pads 83A and 83B, one is applied with a reference potential from the power board 27, and the other is applied with a power supply voltage (power supply potential) from the power board 27. At least one pad 83C (the same number as the number of chips 5 in the illustrated example): To which the power board 27 is connected. A reference potential is applied from the power board 27. Multiple wires 85: Each extending from the pad 83A or 83B to a pad 79 (or, from another perspective, the driver IC 21) and the relay circuit 67. At least one wire 87 (multiple in the illustrated example): Extending from the pad 83C to a pad 37 to which the wire 81 is not connected. In FIG. 8, the paths from the pads 83A to 83C to the control IC 23 are omitted.

[0091] (5. Driver IC) (5.1. Chip-Type Example) The driver IC 21 shown in FIGS. 2 to 4 is, for example, a chip-type component. The driver IC 21 may have a package surrounding a semiconductor substrate, or may be a bare chip without a package. The driver IC 21 may be mounted in any manner. In the example of FIG. 4, the driver IC 21 has terminals 21a made of a layered conductor on its underside, and is surface-mounted on the wiring substrate 7. Other embodiments include, for example, the various embodiments described in the description of the chip 5 (mounting using bonding wires, surface mounting of pin-shaped terminals, or through-hole mounting). The bonding material used in the surface mounting is also arbitrary. In the illustrated example, bonding is performed using an ACF (not shown), similar to the chip 5. Of course, solder or a conductive adhesive may also be used. As can be understood from the above description, the driver IC 21 may be mounted using COG (chip-on-glass) mounting.

[0092] (5.2. Example of Built-in Type) Fig. 9 is a cross-sectional view showing another example of a driver IC, and corresponds to Fig. 4. For convenience, the wiring board 7 and driver IC 21 in this example may be given the additional reference character E.

[0093] In this example, the driving IC 21E is included in the wiring substrate 7E. More specifically, the driving IC 21E is built into the wiring substrate 7E. Such a driving IC 21E may be configured, for example, by an LTPS circuit included in the LTPS substrate serving as the wiring substrate 7E. The driving IC 21E does not have a terminal (see terminal 21a in FIG. 4) that is joined to the wiring substrate 7E. The relay circuit 67 may be provided in a manner that is distinguishable from the driving IC 21E, or may be provided in a manner that is indistinguishable from the driving IC 21E. Although not specifically shown, the control IC may also be included in the wiring substrate 7E (e.g., an LTPS circuit) like the driving IC 21E.

[0094] In the description of the embodiment, for convenience, unless otherwise specified, the driver IC 21 is assumed to be a chip type.

[0095] (6. Ejection Operation) Figure 15 is a schematic diagram for explaining an example of the liquid ejection operation by the head 3. More specifically, the upper, middle, and lower diagrams in Figure 15 each show an example of the change over time in the drive signal Sg input to the actuator 11 (more specifically, the upper electrode 59). In these diagrams, the horizontal axis represents time t, and the vertical axis represents the potential of the drive signal Sg.

[0096] The drive signal Sg is input to the actuator 11 in response to a single ejection request. A plurality of types of drive signals Sg, each set to eject different amounts of liquid, are prepared for the head 3. One of the drive signals Sg is selected and input to the actuator 11 in accordance with the content of the image to be formed (or, from another perspective, the density of the dots).

[0097] The upper, middle, and lower diagrams in FIG. 15 show examples of different types of drive signals Sg. Each of the different types of drive signals Sg includes a pulse with two values ​​(low level and high level). The pulse height (potential V Ｌ and potential V ＨThe plurality of types of drive signals Sg have the same potential difference between them. The plurality of types of drive signals Sg differ from one another in the number of pulses and / or pulse width (time length of each pulse).

[0098] The drive signal Sg in the illustrated example is for ejecting liquid by what is called a pull-shot operation. The basic operation is as follows.

[0099] The potential of the lower electrode 55 (common electrode) is always, for example, a reference potential (potential V Ｌ Before a discharge request is made, the potential of the upper electrode 59 is set to a potential V Ｈ At this time, the actuator 11 is bent toward the pressure chamber 51 due to the deformation of the piezoelectric body 57 (the polarization direction of the piezoelectric body 57 is set so that this occurs).

[0100] When an ejection request is made, the potential of the lower electrode 55 is changed to a potential V Ｌ and again the potential V Ｈ At this time, the actuator 11 reduces its bending (or even eliminates the bending or bends in the opposite direction) and bends again toward the pressure chamber 51. Basically, at this time, a droplet is ejected.

[0101] Conversely, the pull-and-hit drive signal Sg may be maintained at a potential lower than the reference potential before an ejection request is made, and raised to the reference potential in response to an ejection request (from another perspective, the polarization direction of the piezoelectric element 57 may be opposite to that described above). The drive signal Sg is not limited to one that ejects liquid by pull-and-hit. For example, the drive signal Sg may be one that bends the flat actuator 11 toward the pressure chamber 51 in response to an ejection request before an ejection request is made. However, for convenience, in describing the embodiments, the illustrated example may be used as a premise without any particular mention.

[0102] (7. Configuration of Signal Processing System) (7.1. Overall Configuration of Signal Processing System) FIG. 10 is a block diagram showing an example of the configuration of the signal processing system in the printer 1.

[0103] This diagram shows the configuration of a signal processing system from the controller 19 shown in the upper row to the multiple chips 5 shown in the lower row. As the reference number for the head 3 is attached to the right side of the diagram, the multiple blocks shown below the controller 19 indicate the configuration of the signal processing system within the head 3.

[0104] A signal corresponding to an image is input from the controller 19 to the head 3, and a drive signal Sg is generated by executing various processes within the head 3. The drive signal Sg is then input individually to the multiple actuators 11 possessed by each chip 5. Specifically, for example, it is as follows.

[0105] The controller 19 causes the head 3 to repeatedly eject droplets at a predetermined printing cycle. This operation is combined with the movement of the print paper P in the D2 direction to form a two-dimensional image. The controller 19 (or a circuit interposed between the controller 19 and a first distribution circuit 91, which will be described later) outputs a signal to the head 3, for example, for each printing cycle, that includes information on the amount of droplets to be ejected from the plurality of nozzles 9 (which may be 0). This control signal may be a serial signal or a parallel signal.

[0106] The control signal input to the head 3 passes through a first distribution circuit 91 provided in common to all (multiple) chips 5, and then through a processing unit 93 and a shifter group 95 provided for each chip 5. In this process, the control signal is converted into a drive signal Sg. At this time, the multiple processing units 93 also refer to a signal from a waveform generation unit 97.

[0107] For convenience, the first distribution circuit 91 is conceptually regarded as one circuit, but it may be configured by a plurality of circuits to which parallel signals from the controller 19 are distributed. Furthermore, although the processing unit 93 and the shifter group 95 are functionally or conceptually provided for each chip 5, the circuit configuration does not necessarily have to be such.

[0108] Specifically, the first distribution circuit 91 converts the serial signal (which may be included in the parallel signal) contained in the control signal input from the controller 19 into a parallel signal. Then, the first distribution circuit 91 distributes the parallel signals to the multiple processing units 93. The number of control signals output in parallel by the first distribution circuit 91 is, for example, equal to or greater than the number of the multiple processing units 93 (for example, an integer multiple of the number of processing units 93). In other words, one or more control signals are generated for each processing unit 93. The processing after the processing unit 93 will be described below.

[0109] (7.2. Configuration of signal processing system for each chip) Fig. 11 is a block diagram showing details of range XI in Fig. 10. That is, Fig. 11 shows the configuration of the signal processing system for each chip 5. The arrows on the right side of the figure indicate the ranges of the processing unit 93 and the shifter group 95.

[0110] The control signal distributed to each processing unit 93 passes in order through a second distribution circuit 99 (part of the processing unit 93) provided in common to multiple (all) actuators 11 of each chip 5, and then through a selector 123 (part of the processing unit 93) and a shift unit 125 (part of the shifter group 95) provided for each of the multiple actuators 11. In this process, the control signal is converted into a drive signal Sg. At this time, the multiple selectors 123 also refer to the signal from the waveform generation unit 97.

[0111] For convenience, the second distribution circuit 99 is conceptually regarded as one circuit, but it may be configured by a plurality of circuits to which parallel signals from the first distribution circuit 91 are distributed. Furthermore, although the first distribution circuit 91 and the second distribution circuit 99 are functionally or conceptually separate entities, the circuit configuration does not necessarily have to be regarded in this way.

[0112] Specifically, the second distribution circuit 99 converts the serial signal (which may be included in the parallel signal) contained in the control signal input from the first distribution circuit 91 into a parallel signal. Then, the second distribution circuit 99 distributes the parallel signals to the selectors 123. The number of control signals output in parallel by the second distribution circuit 99 is, for example, equal to or greater than the number of the selectors 123 (for example, an integer multiple of the number of the selectors 123). In other words, one or more control signals are generated for each selector 123. The processing after the selector 123 will be described below.

[0113] (7.3. Configuration of signal processing system for each actuator) Fig. 12 is a block diagram showing details of range XII in Fig. 11. That is, Fig. 12 shows the configuration of a signal processing system for each actuator 11. The arrows on the right side of the figure indicate the ranges of the selector 123 and the shift unit 125.

[0114] The selector 123 selects one of the plurality of drive signals Sg (eight drive signals Sg0 to Sg7 in the illustrated example) generated by the waveform generating unit 97 based on the control signal input from the second distribution circuit 99, and outputs the selected signal to the shifting unit 125. The shifting unit 125 converts the level of the input drive signal Sg (in other words, increases the amplitude) and inputs the converted signal to the actuator 11.

[0115] Specifically, for example, the selector 123 has, in order from the second distribution circuit 99 side to the shift unit 125 side, a decoder 127 and a switch unit 129. The switch unit 129 can selectively connect, for example, a plurality of wirings 131 extending from the waveform generation unit 97 to the shift unit 125. A plurality of drive signals Sg are input as parallel signals from the waveform generation unit 97 to the plurality of wirings 131. The decoder 127 controls the switch unit 129 based on the control signal input from the second distribution circuit 99. Note that the plurality of wirings 131 may be common to other selectors 123 and other processing units 93.

[0116] The specific configurations of the decoder 127 and the switch unit 129 are arbitrary. In Fig. 12, a switch 133 that switches between connection and disconnection between the wiring 131 and the shift unit 125 is provided for each of the multiple wirings 131. Based on the input control signal, the decoder 127 outputs parallel signals including the same number of signals as the number of the multiple switches 133. The signal input to each switch 133 is a 2-bit signal that controls ON / OFF.

[0117] The shift unit 125 has, for example, a pre-stage shifter 135 which is a level shifter, and the above-mentioned post-stage shifter 101, in that order from the selector 123 side to the actuator 11 side. The amplitude of the drive signal Sg is increased by the pre-stage shifter 135, and is further increased by the post-stage shifter 101. As a result, for example, the amplitude of the drive signal Sg finally input to the actuator 11 is increased compared to when there is only one level shifter. Note that, unlike the example shown in the figure, the pre-stage shifter 135 may not be provided, or conversely, another level shifter may be provided in series.

[0118] As will be described later, the post-stage shifter 101 reverses the low and high levels of the input signal (or, from another perspective, reverses the rising and falling edges) and outputs the signal (inverts the signal). Therefore, the pre-stage shifter 135 outputs a drive signal Sg whose low and high levels are reversed from those of the drive signal Sg (which is ultimately input to the actuator 11) illustrated in FIG. 15. Note that the pre-stage shifter 135 may or may not have a function to invert a signal. From another perspective, the drive signal Sg generated by the waveform generating unit 97 and the drive signal Sg output by the post-stage shifter 101 may have the same low or high level pulses, or the pulses may be reversed.

[0119] As mentioned in the overview of the embodiment and as will be described later, a signal that oscillates between a low level (e.g., a reference potential GND) and an intermediate potential Vm is input to the rear-stage shifter 101. Accordingly, the front-stage shifter 135 outputs the signal. Note that the reference potential GND is not limited to 0 V, but for convenience, the description of the embodiment may be given on the assumption that the reference potential GND is 0 V.

[0120] The specific values ​​of the amplitude of the drive signal Sg input to the pre-stage shifter 135, the amplitude of the drive signal Sg output from the pre-stage shifter 135, and the amplitude of the drive signal Sg output from the post-stage shifter 101 are arbitrary. For example, they are 6 V, 16 V, and 32 V, respectively. Note that the withstand voltage of FETs generally used in level shifters in fields such as displays is 16 V or less. In other words, a general level shifter cannot generate a drive signal Sg with an amplitude of 32 V as described above.

[0121] (7.4. Post-Stage Shifter) (7.4.1. Configuration of Post-Stage Shifter) In the post-stage shifter 101 shown in FIG. 13, as described above, the first FET 111A to the fourth FET 111D are connected in this order from the power supply voltage Vdd side to the reference potential GND side. Just to be clear, the p-type FETs (111A and 111B) have their sources connected to the power supply voltage Vdd side and their drains connected to the reference potential GND side. The n-type FETs (111C and 111D) have their drains connected to the power supply voltage Vdd side and their sources connected to the reference potential GND side.

[0122] Although not specifically labeled, the four FETs can be expressed as being connected in series between a supply section to which the power supply voltage Vdd is supplied and a reference potential section to which the reference potential GND is applied. Each of the supply section and the reference potential section may be a conductor such as a signal line or a terminal.

[0123] Each of the four FETs is an enhancement type FET. Just to be clear, the p-type FETs (111A and 111B) have a gate-source voltage (hereinafter referred to as "voltage V ＧＳWhen the voltage V ＧＳ When the threshold voltage is reached or exceeded, the drain-source becomes conductive.

[0124] The threshold voltage is the voltage V when the drain-source current is 1 μA or 10 μA. ＧＳ In the embodiments, the threshold voltage may be set to such a value. However, the threshold voltage may be greater than the above-described value. For convenience, in the description of the embodiments, the threshold voltage may be assumed to be sufficiently small (close to 0 V), and strictness may be ignored.

[0125] The intermediate wiring 113 includes at least one wiring. In the illustrated example, the intermediate wiring 113 branches from the intermediate potential Vm side and reaches the gate of the second FET 111B and the gate of the third FET 111C. Therefore, the intermediate wiring 113 not only applies the intermediate potential Vm to the two gates but also short-circuits them. Note that, unlike the illustrated example, the intermediate wiring 113 may include two wirings connected to the two gates in parallel with each other.

[0126] Just to be clear, the term "wiring" is a name that focuses on the function of applying the intermediate potential Vm to the gate. Therefore, the structure does not have to be linear. The same applies to the first relay line 115, the second relay line 117, etc.

[0127] As described above, the intermediate potential Vm is an intermediate potential between the reference potential GND and the power supply voltage Vdd. Here, "intermediate" does not only mean "middle" ((Vdd-GND) / 2), but may also mean any potential between the reference potential GND and the power supply voltage Vdd. Furthermore, the intermediate potentials Vm applied to the second FET 111B and the third FET 111C may be different from each other. As will be understood from the explanation below, even in these cases, the voltage applied to the FET is subtracted from Vdd-GND.

[0128] However, the closer the intermediate potential Vm is to the midpoint potential ((Vdd-GND) / 2) between the reference potential GND and the power supply voltage Vdd, the more the voltage applied to the FET is reduced and the amplitude of Vout becomes larger. Therefore, for example, the intermediate potential Vm may be set to 0.40 or more and 0.60 or less, 0.45 or more and 0.55 or less, or 0.49 or more and 0.51 or less with respect to the potential difference (Vdd-GND). Note that 0.49 or more and 0.51 or less may be considered to be the midpoint potential.

[0129] From another perspective, the intermediate potential Vm may be set to be the same as the power supply voltage of the pre-stage shifter 135 (and / or the high-level potential of the pre-stage shifter 135). In this case, the intermediate wiring 113 may or may not be connected to a wiring (not shown) that applies the power supply voltage to the pre-stage shifter 135.

[0130] The input section 103 is made up of conductors such as signal lines and / or terminals, and is connected to the output side of the pre-stage shifter 135. The output section 105 is made up of conductors such as signal lines and / or terminals, and is connected to the upper electrode 59 (individual electrode) of the actuator 11. The first relay line 115 and the second relay line 117 branch off from the input section 103 and reach the gate of the first FET 111A or the gate of the fourth FET 111D.

[0131] The capacitance of capacitor 119 may be set appropriately so as to achieve the effect described below. As an example, the capacitance of capacitor 119 may be set to 100 pF or more. In this case, the difference between the low-level potential of Vout and the reference potential GND can be set to 0.02 V or less. As will be understood from the explanation below, the capacitance of capacitor 119 does not basically affect the high-level potential of Vout (strictly speaking, it does affect it, but the difference is slight).

[0132] The diode 121 allows current to flow from the intermediate wiring 113 to the first relay line 115 (more specifically, the portion between the capacitor 119 and the first FET 111A) and prohibits current from flowing in the opposite direction. The breakdown voltage is set to be greater than the high-level potential of the signal Vin1, for example.

[0133] When it is said that the cathode is connected to the side of first FET 111A of capacitor 119, the portion to which the cathode is directly connected may be the electrode of capacitor 119 on the side of first FET 111A, or the portion of first relay line 115 between the electrode and the gate of first FET 111A, or the gate of first FET 111A. Similarly, with regard to the connection (electrical connection) between the anode and other components, the portion of direct connection (connection position from a structural perspective) is arbitrary.

[0134] (7.4.2. Operation of the Post-Stage Shifter) The upper diagram in FIG. 14 shows the operation when a rising edge of a pulse is input as signal Vin1. The lower diagram in FIG. 14 shows the operation when a falling edge of a pulse is input as signal Vin1. For convenience, the low level of signal Vin1 is set to 0 V, and the high level of signal Vin1 is set to 16 V. Furthermore, the power supply voltage Vdd is set to 32 V, the reference potential GND is set to 0 V, and the intermediate potential Vm is set to 16 V.

[0135] When the signal Vin1 is 0 V, the fourth FET 111D has a gate-source voltage (voltage V ＧＳ ) is 0 V, the first FET 111A is turned off (non-conducting). The gate of the first FET 111A is supplied with an intermediate potential Vm via a diode 121. In other words, the signal Vin2 input to the gate is 16 V. At this time, the first FET 111A is turned off (non-conducting). ＧＳ is negative, the second FET 111B is ON (conducting state). ＧＳ becomes negative and is turned ON. With the FETs (111A, 111B, and 111D) in the above-described state, the signal Vout is at the power supply voltage Vdd (32 V). Furthermore, the capacitor 119 is charged to 16 V by being supplied with the intermediate potential Vm via the diode 121.

[0136] When the signal Vin1 rises from 0 V to 16 V, the fourth FET 111D is connected to the voltage V ＧＳ becomes positive, so the third FET 111C is turned ON. ＧＳbecomes positive and is turned ON. The signal Vin2 becomes 32 V, which is the sum of 16 V of the signal Vin1 and the 16 V stored in the capacitor 119. As a result, the first FET 111A is turned ON by the voltage V ＧＳ becomes 0 and is turned OFF. As a result of the FETs (111A, 111C, and 111D) operating as described above, the signal Vout falls from 32 V to 0 V. Note that the probability that the signal Vin2 (32 V) is applied to the intermediate wiring 113 is reduced by the diode 121. Furthermore, as shown by the arrow, a current flows from the output section 105 to the reference potential section via the third FET 111C and the fourth FET 111D.

[0137] While the signal Vin1 is at 16 V, ideally, no charge leaks between the capacitor 119, the first FET 111A, and the diode 121, and the signal Vin2 is maintained at 32 V. Consequently, the signal Vout is also maintained at 0 V. Even if leakage occurs, the period of the drive signal Sg is short (for example, 100 μs or less), so the effect of the leakage can be ignored.

[0138] When the signal Vin1 falls from 16 V to 0 V, the signal Vin1 returns to the state described above where it is 0 V. This causes the signal Vout to rise from 0 V to 32 V. Furthermore, as shown by the arrow, a current flows from the supply portion of the power supply voltage Vdd to the output portion 105 via the first FET 111A and the second FET 111B.

[0139] When the signal Vin1 is 0 V, the potential between the first FET 111A and the second FET 111B is 32 V. Furthermore, the potential between the third FET 111C and the fourth FET 111D is 16 V. Considering the potentials of the signals Vin2 and Vout when the signal Vin1 is 0 V (as described above), as well as the power supply voltage Vdd (32 V) and the reference potential GND (0 V), the potential difference between any two of the source, gate, and drain in each FET is 16 V or 0 V, not 32 V.

[0140] When the signal Vin1 is 16 V, the potential between the first FET 111A and the second FET 111B is 16 V. Furthermore, the potential between the third FET 111C and the fourth FET 111D is 0 V. Considering the potentials of the signal Vin2 and the signal Vout (as described above) when the signal Vin1 is 16 V, as well as the power supply voltage Vdd (32 V) and the reference potential GND (0 V), the potential difference between any two of the source, gate, and drain in each FET is 16 V or 0 V, not 32 V.

[0141] (7.4.3. Other Examples of FETs) Figure 16 is a circuit diagram showing another example of the FET 111 (111A to 111D). As shown in this figure, the FET 111 may be configured by connecting multiple FETs 111a in parallel. Similarly, various components such as the capacitor 119 and the diode 121 may be configured by connecting multiple components in parallel and / or in series.

[0142] (7.5. Hardware of the Signal Processing System) Each of the functional units of the signal processing system in the head 3 described above may be configured by appropriate hardware.

[0143] For example, as indicated by the reference numerals of the driver IC 21 on the right side of Fig. 10, the shifter group 95 may be included in the driver IC 21. Also, as indicated by the reference numerals on the right side of Fig. 10, the processing unit 93 may be configured by an internal circuit 139 included in the wiring board 7. The first distribution circuit 91 and the waveform generating unit 97 may be configured by an external circuit 137.

[0144] The internal circuit 139 is a circuit (for example, an LTPS circuit; the same applies below) built into the wiring substrate 7 and / or a circuit of a chip embedded in the wiring substrate 7. As described above, the driving IC 21 may be built into or embedded in the wiring substrate 7, but for convenience, it is excluded from the internal circuit 139 referred to here. The relay circuit 67 (described above) illustrated in FIG. 8 is an example of the internal circuit 139.

[0145] The external circuit 137 is, for example, a circuit within the head 3, and is closer to the controller 19 than the internal circuit 139 (part or all of it). Examples of such circuits include: A circuit of a chip (for example, the control IC 23 in FIG. 2) mounted on the wiring board 7; A circuit of another wiring board (for example, the signal board 25 in FIG. 2) connected to the wiring board 7; A circuit of a chip mounted on the other wiring board; A circuit of yet another wiring board connected to the other wiring board; A circuit of a chip mounted on the yet other wiring board.

[0146] The above is merely an example and may be modified as appropriate. For example, a part of the processing unit 93 (e.g., the second distribution circuit 99) may be provided in the external circuit 137. Conversely, a part or all of the first distribution circuit 91 may be provided in the internal circuit 139.

[0147] 13, the shifter body 107 may be included in the driver IC 21, while the bootstrap 109 may be included in the internal circuit 139 (e.g., the relay circuit 67). Of course, both may be included in the driver IC 21.

[0148] As can be understood from the above description, each component may be part or all of a chip, or may be a circuit built into the wiring substrate 7. The combination of which components are chips or built-in circuits is also arbitrary. For example, the shifter body 107 (another aspect is an FET) may be included in a chip mounted on the wiring substrate 7, while the bootstrap 109 (another aspect is the capacitor 119 and the diode 121) may be built into the wiring substrate 7. Alternatively, both the shifter body 107 and the bootstrap 109 may be built into the wiring substrate 7.

[0149] As can be seen from the above, the FETs (111A to 111D) may or may not be TFTs. Similarly, the capacitor 119 and the diode 121 may have any structure. Furthermore, at least some of the four FETs (for example, 111B and 111C) may be included in a complementary metal-oxide-semiconductor (CMOS).

[0150] (8. Summary of the embodiment) As described above, the head 3 according to the embodiment has an actuator 11 and a level shifter (post-stage shifter 101). The actuator 11 ejects liquid from the nozzles 9. The post-stage shifter 101 converts the level of the drive signal Sg from the input unit 103 and inputs it to the actuator 11. The post-stage shifter 101 has a shifter main body 107 and a bootstrap 109. The shifter main body 107 is connected to the actuator 11. The bootstrap 109 is interposed between the input unit 103 and the shifter main body 107.

[0151] The shifter body 107 includes a first FET 111A to a fourth FET 111D and an intermediate wiring 113. The first FET 111A and the second FET 111B are connected in this order from the power supply voltage Vdd side to the actuator 11 side. The first FET 111A and the second FET 111B are first-type FETs (p-type in the embodiment), which are either p-type or n-type. The third FET 111C and the fourth FET 111D are connected in this order from the actuator 11 side to the reference potential GND side. The third FET 111C and the fourth FET 111D are second-type FETs (n-type in the embodiment), which are the other of p-type and n-type. The intermediate wiring 113 applies an intermediate potential Vm, which is intermediate between the reference potential GND and the power supply voltage Vdd, to the gates of the second FET 111B and the third FET 111C.

[0152] The bootstrap 109 has a first relay line 115, a second relay line 117, a capacitor 119, and a diode 121. The first relay line 115 connects the input unit 103 and the gate of the first FET 111A. The second relay line 117 connects the input unit 103 and the gate of the fourth FET 111D. The capacitor 119 is located on the first relay line 115. The diode 121 connects the first FET 111A side of the capacitor 119 to the intermediate wiring 113 with the cathode facing the capacitor 119 if the first type is p-type (in the example shown), and with the anode facing the capacitor 119 if the first type is n-type.

[0153] 14, the voltage applied to each FET can be made smaller than the potential difference (Vdd-GND), and can be set to approximately (Vdd-GND) / 2 at the minimum. As a result, for example, FETs with low voltage resistance can be used.

[0154] Intermediate wiring 113 may short-circuit the gate of second FET 111B and the gate of third FET 111C.

[0155] In this case, for example, when it is intended to apply the same potential (e.g., Vdd / 2) as the intermediate potential Vm to both gates, the likelihood of a potential difference occurring between the two gates is reduced, and the configuration for applying the intermediate potential Vm to the two gates is simple.

[0156] The head 3 may have a chip 5 and a rigid wiring board 7. The chip 5 may have a nozzle 9 and an actuator 11. The wiring board 7 may support the chip 5 and be electrically connected to the chip 5.

[0157] In this case, for example, as described above, the wiring board 7 serves both as a wiring board for transmitting signals to the chip 5 and as a frame for supporting the chip 5. As a result, for example, the number of components can be reduced and the chip 5 can be made smaller.

[0158] The chip 5 may be a MEMS chip, and the wiring substrate 7 may be an LTPS substrate.

[0159] In this case, for example, because the chip 5 is a MEMS chip, the nozzles 9, actuators 11, terminals 35, etc. can be formed with high density and precision by microfabrication. Furthermore, for example, because the wiring substrate 7 is an LTPS substrate, the pads 37 connected to the terminals 35, etc. can be formed with high density and precision by microfabrication. Therefore, when the nozzles 9, terminals 35, etc. are densified to reduce the chip 5 in size, the likelihood of limitations imposed by the dimensional precision of the wiring substrate 7 is reduced. Conversely, the likelihood of the miniaturization of the wiring substrate 7 being limited by the dimensional precision of the chip 5 is reduced. Furthermore, when forming circuits (e.g., bootstrap 109 and / or post-stage shifter 101) on the wiring substrate 7, the circuits can be miniaturized if the wiring substrate 7 is an LTPS substrate. These factors contribute to the miniaturization of the head 3.

[0160] The shifter body 107 (or, from another point of view, the driver IC 21 including the shifter body 107 ) may be included in the wiring board 7 or may be mounted on the wiring board 7 .

[0161] In this case, for example, the wiring board 7 not only contributes to the transmission of signals to the actuator 11 but also contributes to the arrangement of the shifter body 107 (driver IC 21), which is expected to further reduce the number of parts, leading to cost reduction and / or miniaturization.

[0162] The shifter body 107 may be configured by a built-in circuit (for example, an LTPS circuit) that the wiring board 7 has.

[0163] In this case, for example, the process of fabricating the shifter body 107 (a chip including the shifter body 107) separately from the wiring board 7 or mounting the shifter body 107 on the wiring board 7 becomes unnecessary. As a result, for example, cost reduction is expected. Also, the shifter body 107 as an LTPS circuit does not need to ensure strength like a chip, so it can be made thinner. Consequently, it is expected that the head 3 can be made thinner.

[0164] The bootstrap 109 may be configured by a built-in circuit (for example, an LTPS circuit) that the wiring board 7 has.

[0165] In this case, cost reduction and thinning can be expected, as in the case where the shifter body 107 is a built-in circuit. Also, the bootstrap 109 can be adjacent to or integrated with the shifter body 107 included in or mounted on the wiring board 7. As a result, further miniaturization can be achieved and power loss can be reduced.

[0166] The head 3 may have a switch unit 129. The switch unit 129 may select one drive signal from a plurality of drive signals Sg0 to Sg7 having mutually different waveforms and input the selected drive signal (directly or indirectly) to the input unit 103. The switch unit 129 may be configured by a built-in circuit included in the wiring board 7.

[0167] In this case, for example, it is expected that the head 3 can be further miniaturized. Also, the switch section 129 can be adjacent to or integrated with the post-stage shifter 101 included in or mounted on the wiring board 7.

[0168] The head 3 may have a pre-stage level shifter (pre-stage shifter 135) that converts the level of the drive signal Sg and inputs it to the input unit 103. The pre-stage shifter 135 may be included in the wiring board 7 or may be mounted on the wiring board 7.

[0169] In this case, for example, two-stage level shifting is performed by the front-stage shifter 135 and the rear-stage shifter 101, so the final amplitude can be increased while reducing the burden on each level shifter. Furthermore, the wiring substrate 7 is also used for arranging the front-stage shifter 135, which is expected to reduce costs and / or reduce the size.

[0170] The head 3 may have a plurality of chips 5 supported on the same wiring substrate 7 .

[0171] In this case, for example, a head 3 is realized that can perform band-shaped printing over a range longer than the length (direction D1) of the tip 5. For example, as illustrated in Figures 2 and 3, a line head that can print across the width of paper is realized by a tip 5 that is shorter than the width of the paper. As a result, for example, compared to an embodiment that uses a long tip that spans the width of paper (such an embodiment may also be included in the technology disclosed herein), it is easier to improve the dimensional accuracy of the flow path shape, etc., and to improve the strength of the entire head.

[0172] In a plan view of the wiring substrate 7, the plurality of chips 5 may be arranged in a staggered pattern in two rows. In a plan view of the wiring substrate 7, the plurality of shifter bodies 107 (driver ICs 21 including the shifter bodies 107) may be arranged in a staggered pattern in two rows so as to be located between the plurality of chips 5.

[0173] When realizing a head 3 capable of printing over a range longer than the length of the chips 5 (direction D1) using multiple chips 5, if there is only one row of chips 5, there will be areas between adjacent chips 5 where no printing occurs. For this reason, multiple chips 5 are arranged in two or more rows in a staggered pattern, with their ends in the direction D1 overlapping. In this case, the staggered arrangement creates dead space on the wiring board 7 where no chips 5 are located. This dead space can be used as a placement position for the shifter body 107. As a result, the head 3 can be made smaller. This is made possible by using the wiring board 7 as a member supporting the multiple chips 5.

[0174] From another perspective, the head 3 according to the embodiment has a chip 5, a rigid wiring board 7, and a level shifter (post-stage shifter 101). The chip 5 has nozzles 9 and actuators 11 that eject liquid from the nozzles 9. The wiring board 7 supports the chip 5 and is electrically connected to the chip 5. The post-stage shifter 101 converts the level of the drive signal Sg and inputs it to the actuator 11. At least a portion of the post-stage shifter 101 is included in the wiring board 7 or is mounted on the wiring board 7.

[0175] In this case, for example, the wiring board 7 serves as a wiring board for transmitting signals to the chip 5, a frame for supporting the chip 5, and a wiring board on which the post-stage shifter 101 is disposed. As a result, for example, cost reduction and / or miniaturization can be achieved. From the above perspective, the post-stage shifter 101 does not need to have the four FETs (111A to 111D) connected in series, and does not need to have the bootstrap 109.

[0176] The technology according to the present disclosure is not limited to the above-described embodiments and may be implemented in various forms.

[0177] The recording device may be a plotter. The recording device may be a handheld printer that is held and moved by a user and moves relative to the recording medium. The recording device may be one in which the recording medium and the head are moved relative to each other by moving the head using a robot or the like.

[0178] The recording medium is not limited to paper, and may be, for example, cloth, wood, tile, a printed wiring board (more specifically, an insulating layer on which a conductive pattern is printed), or a car body.

[0179] The head may be used for purposes other than recording devices. For example, the head may be used to prepare chemicals. Specifically, the head may eject a predetermined amount of liquid chemical or a liquid containing a chemical toward a reaction vessel or the like.

[0180] As can be understood from the examples of the recording medium and the like given above, the liquid is not limited to ink, but may be, for example, paint or a conductive material printed on a printed wiring board.

[0181] 1...printer (recording device), 3...head (liquid ejection head), 5...chip, 7...wiring board, 9...nozzle, 11...actuator, 101...post-stage shifter (level shifter), 103...input section, 105...output section, 107...shifter body, 109...bootstrap, 111A...first FET, 111B...second FET, 111C...third FET, 111D...fourth FET, 113...intermediate wiring, 115...first relay line, 117...second relay line, 119...capacitor, 121...diode.

Claims

1. A liquid ejection device comprising: an actuator for ejecting liquid from a nozzle; and a level shifter for converting the level of a drive signal from an input section and inputting the converted signal to the actuator, wherein the level shifter comprises: a shifter body connected to the actuator; and a bootstrap interposed between the input section and the shifter body, wherein one of the p-type and n-type FETs is referred to as a first type and the other of the p-type and n-type FETs is referred to as a second type, wherein the shifter body comprises: a first FET of the first type and a second FET of the first type connected in this order from a power supply voltage side to the actuator side; a third FET of the second type and a fourth FET of the second type connected in this order from the actuator side to a reference potential side; and intermediate wiring for applying an intermediate potential between the reference potential and the power supply voltage to the gates of the second FET and the third FET, wherein the bootstrap comprises: a first relay line connecting the input section and the gate of the first FET; a second relay line connecting the input section and the gate of the fourth FET; a diode connecting the first FET side of the capacitor to the intermediate wiring, the cathode of which is connected to the capacitor side when the first type is p-type, and the anode of which is connected to the capacitor side when the first type is n-type.

2. The liquid ejection head according to claim 1, wherein the intermediate wiring shorts the gate of the second FET and the gate of the third FET.

3. A liquid ejection head as described in claim 1 or 2, comprising: a chip having the nozzle and the actuator; and a rigid wiring board that supports the chip and is electrically connected to the chip.

4. The liquid ejection head according to claim 3, wherein the chip is a MEMS chip, and the wiring substrate is an LTPS substrate.

5. The liquid ejection head according to claim 3 or 4, wherein the shifter body is included in the wiring board or is mounted on the wiring board.

6. The liquid ejection head according to claim 5, wherein said shifter body is constituted by a built-in circuit provided on said wiring board.

7. The liquid ejection head according to any one of claims 3 to 6, wherein the bootstrap is constituted by a built-in circuit provided on the wiring board.

8. A liquid ejection head as described in any one of claims 3 to 7, further comprising a switch section which selects one of a plurality of drive signals having mutually different waveforms and inputs the selected drive signal to the input section, the switch section being constituted by a built-in circuit included in the wiring board.

9. A liquid ejection head as described in any one of claims 3 to 8, further comprising a front-stage level shifter that converts the level of the drive signal and inputs it to the input section, the front-stage level shifter being included in the wiring board or mounted on the wiring board.

10. The liquid ejection head according to any one of claims 3 to 9, comprising a plurality of said chips supported on the same wiring substrate.

11. A liquid ejection head as described in claim 10, wherein, in a planar view of the wiring board, a plurality of the chips are arranged in a staggered pattern in two rows, and, in a planar view of the wiring board, a plurality of the shifter bodies are arranged in a staggered pattern in two rows so as to be positioned between a plurality of the chips.

12. A liquid ejection head comprising: a chip having a nozzle and an actuator for ejecting liquid from the nozzle; a rigid wiring board supporting said chip and electrically connected to said chip; and a level shifter converting the level of a drive signal and inputting it to said actuator, wherein at least a portion of said level shifter is included in said wiring board or is mounted on said wiring board.

13. A recording device comprising: a liquid ejection head according to any one of claims 1 to 12; and a moving section that relatively moves the liquid ejection head and a recording medium on which the liquid ejected from the nozzles lands.

14. A level shifter which converts the level of a signal from an input section and outputs it to an output section, comprising: a shifter body connected to the output section; and a bootstrap interposed between the input section and the shifter body, wherein one of the p-type and n-type FETs is referred to as a first type, and the other of the p-type and n-type FETs is referred to as a second type, the shifter body comprises: a first FET of the first type and a second FET of the first type connected in this order from the power supply voltage side to the output section side; a third FET of the second type and a fourth FET of the second type connected in this order from the output section side to a reference potential side; and intermediate wiring which applies an intermediate potential between the reference potential and the power supply voltage to the gates of the second FET and the third FET, and the bootstrap comprises: a first relay line connecting the input section and the gate of the first FET; a second relay line connecting the input section and the gate of the fourth FET; and a capacitor located on the first relay line. a diode connecting the first FET side of the capacitor and the intermediate wiring, the cathode of which is connected to the capacitor side when the first type is p-type, and the anode of which is connected to the capacitor side when the first type is n-type.

Images