Display driving device and driving method therefor

Abstract

A method for controlling a display driving device according to an embodiment of the present invention comprises the steps of: receiving a first clock signal from the outside; performing a write operation on a memory according to the received first clock signal; generating a second clock signal inside; and performing a read operation on the memory according to the generated second clock signal.

Description

Display driving device and control method thereof

[0001] The present invention is applicable to VR (Virtual Reality) devices, LCD (Liquid Crystal Display), mobile devices, etc. However, for example, it is directly or indirectly related to technology using a partial frame buffer.

[0002] A partial frame buffer is a display technology method that stores and processes only a portion of the screen, rather than the entire screen, in memory. This method is primarily used in VR devices, mobile devices, e-paper displays, and low-power display devices, and has the advantage of reducing power consumption because the entire screen is not updated every time.

[0003] Furthermore, power efficiency is improved because only the necessary portions of the screen are updated, rather than the entire screen. Therefore, when changes occur in a specific part of the screen, only that portion can be quickly updated.

[0004] Additionally, memory usage is reduced by storing only the necessary portions of the frame instead of storing the entire frame in memory. This reduces hardware costs and improves the overall resource efficiency of the system.

[0005] Meanwhile, the display refresh rate (refresh rate) is a numerical value indicating how many images can be displayed on the screen per second, measured in hertz (Hz). For example, a 60Hz monitor means the screen can be divided into 60 stages and displayed in one second. A higher refresh rate means more images can be displayed per second, resulting in smoother motion.

[0006] However, according to the conventional technology, since the read speed for the memory within the display driving device is fixed regardless of the change in the display refresh rate, there was a problem in which the memory abnormally reached a full state or, conversely, an empty state.

[0007] One embodiment of the present invention is intended to solve the above-described problem, and has as its primary purpose the phenomenon of memory abnormally reaching a full state or, conversely, an empty state.

[0008] Another purpose of one embodiment of the present invention is to compare a read address and a write address and automatically vary a control signal of an oscillator to optimize memory usage.

[0009] A method for controlling a display driving device according to an embodiment of the present invention for achieving the above-described technical task includes the steps of receiving a first clock signal from an external source, executing a write operation on a memory according to the received first clock signal, generating a second clock signal internally, and executing a read operation on the memory according to the generated second clock signal. In particular, the second clock signal is designed to change according to the first clock signal.

[0010] The step of generating a second clock signal within the above further includes a step of comparing a write address and a read address at the first time of executing a read operation.

[0011] A control method of a display driving device according to one embodiment of the present invention further includes a step of increasing the frequency of the second clock signal when, as a result of the comparison, the difference between the write address and the read address is greater than or equal to the first reference value.

[0012] A control method of a display driving device according to one embodiment of the present invention further includes a step of reducing the frequency of the second clock signal when, as a result of the comparison, the difference between the write address and the read address is less than or equal to a second reference value.

[0013] The first clock signal received from the outside is related to either 60 Hz or 120 Hz, which is a display refresh rate generated by an AP (Application Processor), and the second clock signal generated internally is characterized in that it is generated by an oscillator.

[0014] A method for controlling a display driving device according to one embodiment of the present invention further includes a step of transmitting an error flag indicating that the memory is full or empty to the AP.

[0015] A display driving device according to one embodiment of the present invention includes a first controller that receives a first clock signal from an external source and executes a write operation on a memory according to the received first clock signal, a generation unit that internally generates a second clock signal, and a second controller that executes a read operation on the memory according to the generated second clock signal. In particular, the second clock signal may be changed according to the first clock signal.

[0016] According to one embodiment of the present invention, the above-mentioned technical problem is solved and a new optimized operation method of partial memory or partial frame memory is proposed.

[0017] However, effects not explicitly mentioned herein can also be understood by those skilled in the art through the intent of the entire specification.

[0018] Figure 1 illustrates components of a device for controlling partial memory according to the prior art.

[0019] FIG. 2 illustrates an example of a read operation and a write operation for the partial memory of the device illustrated in FIG. 1.

[0020] FIG. 3 illustrates another example of a read operation and a write operation for the partial memory of the device illustrated in FIG. 1.

[0021] Figure 4 illustrates components of a device according to one embodiment of the present invention.

[0022] Figure 5 illustrates detailed components of the OSC controller illustrated in Figure 4.

[0023] Figure 6 illustrates data stored in the memory illustrated in Figure 5.

[0024] FIG. 7 illustrates an example of a read operation and a write operation for the partial memory of the device illustrated in FIG. 4.

[0025] FIG. 8 illustrates another example of a read operation and a write operation for the partial memory of the device illustrated in FIG. 4.

[0026] Figure 9 is a flow chart illustrating a control method of a device according to one embodiment of the present invention.

[0027] And, FIG. 10 is a detailed flow chart illustrating step S930 illustrated in FIG. 9 in more detail.

[0028] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0029] Throughout the specification, identical reference numbers refer to substantially identical components. In the following description, detailed descriptions of components and functions not related to the core components of the present invention and those known in the art may be omitted.

[0030] In this specification, when the terms "includes," "has," and "consists of," are used, other parts may be added, unless "only" is used. When a component is expressed in the singular, it includes the plural unless otherwise explicitly stated.

[0031] When interpreting a component, it is interpreted as including the error range even if there is no separate explicit description.

[0032] While terms like "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, a "first" component referred to below may also be a "second" component within the technical scope of the present invention.

[0033] The term "at least one" should be understood to include all possible combinations of one or more associated items. For example, "at least one of the first, second, and third items" can mean any combination of items that can be represented by two or more of the first, second, and third items, as well as each of the first, second, and third items.

[0034] The individual features of the various embodiments of the present invention can be partially or wholly combined or combined with each other, and various technical linkages and operations are possible, and each embodiment can be implemented independently of each other or implemented together in a related relationship.

[0035] Figure 1 illustrates components of a device for controlling partial memory according to prior art. The term "partial memory" used in the present specification refers to, for example, a partial frame buffer.

[0036] Typically, a framebuffer stores all the pixels displayed on the display. On platforms that support layers, an application can include multiple layers, each smaller than the display size.

[0037] On platforms that provide separate memory for the display, a partial framebuffer can be used to store only the pixels that need to be redrawn. Therefore, a partial framebuffer has the technical advantage of minimizing the amount of data that needs to be transmitted to the display.

[0038] Meanwhile, according to the prior art, the processor (100) illustrated in FIG. 1 transmits an AP clock signal (AP_CLK) and data for a write operation (Write data) to a write controller (110). Here, the processor (100) may correspond to, for example, an AP (Application Processor), but is not necessarily limited thereto.

[0039] The write controller (110) transmits an address for a write operation (Memory Write address) and data for a write operation (Write data) to the partial memory (120).

[0040] Meanwhile, the partial memory (120) receives an address for a read operation (Memory read address) from the read controller (130) and transmits data for a read operation (Read data) corresponding to the received address to the read controller (130).

[0041] However, according to the prior art, the read controller (130) performs an operation of reading data from the partial memory (120) at a fixed speed, regardless of changes in the AP clock signal transmitted by the processor (100). Technical problems arising in this regard will be described in more detail below with reference to FIGS. 2 and 3.

[0042] FIG. 2 illustrates an example of a read operation and a write operation for the partial memory of the device illustrated in FIG. 1.

[0043] First, for the convenience of explanation, let's assume that when the number of display lines for processing one frame is 200, the partial memory can process 100 lines.

[0044] At this time, as shown in Fig. 2, since the write operation (210) of the partial memory and the read operation (220) of the partial memory are initially performed at the same speed, an error does not occur when the partial memory is full or an error does not occur when the partial memory is empty.

[0045] However, technical issues arise when a write operation is accelerated or slowed down beyond the initially set speed due to a request from an AP or similar. A related embodiment will be described below with reference to FIG. 3.

[0046] FIG. 3 illustrates another example of a read operation and a write operation for the partial memory of the device illustrated in FIG. 1.

[0047] As described above, in FIG. 3, no particular problem occurs when the initial write operation (330) of the partial memory and the initial read operation (340) of the partial memory are initially set to the same speed.

[0048] However, when the AP performs a fast write operation (310) on the partial memory for the purpose of increasing the display frequency, a defect occurs in that the initially set fixed speed read operation (340) cannot read all the data written to the partial memory.

[0049] Meanwhile, even when the AP performs a slow write operation (320) to the partial memory for the purpose of slowing down the display frequency, a defect occurs in that the initially set fixed speed read operation (340) cannot read all the data written to the partial memory.

[0050] On the other hand, one embodiment of the present invention solves the above-mentioned technical problem and proposes a new optimized operation method of partial memory or partial frame memory.

[0051] To implement this, for example, the control signal of the oscillator is designed to be automatically generated by comparing the address for a write operation with the address for a read operation.

[0052] More specific examples will be described in more detail with reference to FIG. 4, etc. below.

[0053] Figure 4 illustrates components of a device according to one embodiment of the present invention.

[0054] A display driving device (480) according to one embodiment of the present invention includes a first controller that receives a first clock signal (e.g., AP_CLK, etc., shown in FIG. 4) from the outside and executes a write operation on a memory according to the received first clock signal, a generation unit that internally generates a second clock signal (e.g., Oscillator CLK, etc., shown in FIG. 4), and a second controller that executes a read operation on the memory according to the generated second clock signal. Furthermore, the second clock signal is designed to be changed according to the first clock signal, for example.

[0055] Here, the first controller may correspond to, for example, the writing controller (410) illustrated in FIG. 4.

[0056] Furthermore, the generation unit may correspond to, for example, the OSC controller (450) or OSC generation unit (460) illustrated in FIG. 4.

[0057] And, the second controller may correspond to, for example, the read controller (430) illustrated in FIG. 4.

[0058] Meanwhile, the display driving device (480) illustrated in FIG. 4 may be, for example, a T-CON (Timing Controller), an MCU (Microcontroller Unit), etc., the processor (400) may be, for example, an AP, etc., and the driver IC (440) may be, for example, a source driver IC or a panel, etc.

[0059] Of course, designing the display driver (480) and driver IC (440) as one chip rather than separate chips also falls within the scope of another right of the present invention.

[0060] Referring to FIG. 4, more specifically, the processor (400) transmits an AP clock signal (AP_CLK) and data for a write operation (Write data) to a write controller (410).

[0061] The write controller (410) transmits an address for a write operation (Memory Write address) and data for a write operation (Write data) to the partial memory (420).

[0062] Meanwhile, the partial memory (420) receives an address for a read operation (Memory read address) from the read controller (430) and transmits data for a read operation (Read data) corresponding to the received address to the read controller (430).

[0063] However, unlike the prior art, the display driving device (480) according to one embodiment of the present invention has an OSC controller (450) and an OSC generation unit (460) added.

[0064] The OSC controller (450) receives a write address transmitted by the write controller (410) to the partial memory (420), and further receives a read address transmitted by the read controller (430) to the partial memory (420).

[0065] And, the OSC controller (450) compares the write address and the read address.

[0066] As a result of the above comparison, if the difference between the write address and the read address is greater than or equal to the first reference value, the OSC controller (450) transmits a command (OSC_TRIM) for changing the frequency of the second clock signal to the OSC generation unit (460). Then, the OSC generation unit (460) increases the frequency of the second clock signal (e.g., the Oscillator CLK illustrated in FIG. 4) according to the above-described command (OSC_TRIM).

[0067] On the other hand, if the difference between the write address and the read address is less than or equal to the second reference value as a result of the comparison, the OSC controller (450) transmits a command (OSC_TRIM) for changing the frequency of the second clock signal to the OSC generation unit (460). Then, the OSC generation unit (460) reduces the frequency of the second clock signal (e.g., the Oscillator CLK illustrated in FIG. 4) according to the above-described command (OSC_TRIM).

[0068] According to one embodiment of the present invention, for example, at the time of starting a read operation, an OSC controller (450) and an OSC generation unit (460) that change the clock speed of the oscillator by referring to an address for a write operation are added. Therefore, in the partial memory of the prior art, there is an advantage in that both the full phenomenon in which data is full and the empty phenomenon in which data becomes empty can be resolved.

[0069] However, due to errors in design, etc., there is a possibility that an error may occur in which the read speed and write speed for the partial memory (420) do not change equally despite normal operation of the OSC controller (450) and the OSC generation unit (460).

[0070] In this case, the OSC controller (450) transmits an error flag indicating a full phenomenon in which data is filled in the partial memory or an error flag indicating an empty phenomenon in which data is emptied in the partial memory to the processor (400).

[0071] Accordingly, the processor (400) can additionally readjust the first clock signal (e.g., AP_CLK, etc., shown in FIG. 4) depending on the type of error flag received from the OSC controller (450).

[0072] Meanwhile, the detailed components of the OSC controller (450) illustrated in FIG. 4 will be described in more detail with reference to FIG. 5 below.

[0073] Figure 5 illustrates detailed components of the OSC controller illustrated in Figure 4.

[0074] As shown in FIG. 5, the OSC controller (450) includes a comparison module (451) and a memory (452).

[0075] The comparison module (451), as described above, is designed to compare a write address and a read address and transmit the address difference value to the memory (452).

[0076] The memory (452) outputs a command (OSC_TRIM) to the outside (e.g., an OSC generation unit, etc.) to determine whether to change the frequency of the second clock signal to some extent based on the address difference value.

[0077] Meanwhile, the table stored in the memory (452) illustrated in FIG. 5 will be described in more detail with reference to FIG. 6 below.

[0078] Figure 6 illustrates data stored in the memory illustrated in Figure 5.

[0079] For example, when the write speed of the memory according to the first clock signal received from the initial AP and the read speed of the memory according to the second clock signal are the same, it is assumed that the address difference value is 15.

[0080] In this case, the data for changing the OSC (oscillator) frequency corresponding to the second clock signal corresponds to C, as shown in Fig. 6. The frequency change of the oscillator can be set by changing, for example, the value of the resistor R and the value of the capacitor C.

[0081] Meanwhile, if the difference between the read address and the write address of the memory is reduced to 5 or 10 due to a change in the first clock signal (e.g., an increase in the write speed to the memory), the frequency of the oscillator corresponding to the second clock signal is set to slow based on A or B, which is data for changing the frequency of the oscillator, with reference to the table shown in FIG. 6.

[0082] On the other hand, if the difference between the read address and the write address of the memory increases to 20 or 25 due to a change in the first clock signal (e.g., a decrease in the read speed for the memory), the frequency of the oscillator corresponding to the second clock signal is quickly set based on D or E, which is data for changing the frequency of the oscillator, by referring to the table shown in FIG. 6.

[0083] FIG. 7 illustrates an example of a read operation and a write operation for the partial memory of the device illustrated in FIG. 4.

[0084] According to one embodiment of the present invention, at a first time point (time_read_start1) (710) of a read operation, if the difference between the read address and the write address is greater than or equal to a first reference value by referring to an address (write_address@read_start) (740) of a memory related to reading, the oscillator frequency is quickly set to increase the display frequency. The read operation is performed (700) faster than in the prior art (701).

[0085] Accordingly, due to the frequency of the oscillator being set quickly in this way, there is a technical effect in that the second point in time (time_rea_start2) of the read operation is brought forward to the point in time (721) according to an embodiment of the present invention compared to the point in time (720) according to the prior art.

[0086] That is, when the AP performs a fast write operation (700) on the partial memory for the purpose of increasing the display frequency, the read operation is also automatically performed quickly (703), enabling the fast display implementation desired by the AP.

[0087] On the other hand, according to the prior art, when the AP executes a fast write operation (700), there was a problem that the partial memory becomes full (750) at an arbitrary point in time (730) (time_full). Here, the full state of the partial memory occurs at the point where the second fast write operation (700) and the general read operation (702) meet. In other words, it means that the write operation occurs in a state where the partial memory has not read all of the data of the address.

[0088] FIG. 8 illustrates another example of a read operation and a write operation for the partial memory of the device illustrated in FIG. 4.

[0089] According to one embodiment of the present invention, at a first time point (time_read_start1) (420) of a read operation, if the difference between the read address and the write address is less than or equal to a second reference value by referring to the address (write_address@read_start) (850) of the memory related to the read, the oscillator frequency is set to slow, thereby lowering the display frequency. The read operation is performed (803) more slowly than in the prior art (802).

[0090] Accordingly, due to the frequency of the oscillator being set slowly in this way, there is a technical effect that the second point in time (time_rea_start2) of the read operation is pushed back to the point in time (831) according to an embodiment of the present invention compared to the point in time (830) according to the prior art.

[0091] That is, when the AP performs a slow write operation (801) to the partial memory for the purpose of slowing down the display frequency, the read operation is also automatically performed slowly (803), enabling the slow display implementation desired by the AP.

[0092] On the other hand, according to the prior art, when the AP performs a slow write operation (801), there was a problem that the partial memory becomes empty (810) at a random point in time (820) (time_empty). Here, the empty state of the partial memory occurs at the point where the first slow write operation (801) and the general read operation (802) meet. In other words, when the AP performs a slow write operation, the partial memory does not write data that needs to be read, so it means that unwanted past data is read again.

[0093] Figure 9 is a flowchart illustrating a control method for a device according to one embodiment of the present invention. It is technically possible for those skilled in the art to further interpret Figure 9 by referring to the previous drawings.

[0094] First, a display driving device according to an embodiment of the present invention receives a first clock signal from the outside (S910). Here, the outside corresponds to the processor (400) of the previous drawing 4, and the first clock signal corresponds to, for example, AP_CLK of the previous drawing 4.

[0095] Furthermore, the display driving device according to one embodiment of the present invention executes a write operation on memory according to the received first clock signal (S920). Here, the memory corresponds to, for example, the partial memory (420) illustrated in FIG. 4.

[0096] In addition, the display driving device according to one embodiment of the present invention generates a second clock signal internally (S930). This operation may be performed by at least one of the OSC controller (450) or the OSC generation unit (460) illustrated in FIG. 4, and the second clock signal may correspond to, for example, the Oscillator CLK illustrated in FIG. 4.

[0097] And, the display driving device according to one embodiment of the present invention executes a read operation on the memory according to the generated second clock signal (S940).

[0098] In particular, as described above, the second clock signal is changed according to the first clock signal. More specific embodiments related to this will be described in more detail below in FIG. 10.

[0099] And, FIG. 10 is a detailed flow chart illustrating step S930 illustrated in FIG. 9 in more detail.

[0100] A display driving device according to one embodiment of the present invention compares a write address and a read address, for example, at the first time a read operation is performed (S931).

[0101] First, the display driving device according to one embodiment of the present invention determines whether the difference between the write address and the read address is greater than or equal to a first reference value (S932).

[0102] As a result of the above judgment (S932), if the difference between the write address and the read address is greater than or equal to the first reference value, the display driving device according to one embodiment of the present invention increases the frequency of the second clock signal (S933).

[0103] On the other hand, if the difference between the write address and the read address is not greater than the first reference value as a result of the above judgment (S932), the display driving device according to one embodiment of the present invention determines whether the difference between the write address and the read address is less than or equal to the second reference value (S934).

[0104] As a result of the above judgment (S934), if the difference between the write address and the read address is not less than the second reference value, the display driving device according to one embodiment of the present invention returns to step S931.

[0105] On the other hand, if the difference between the write address and the read address is less than or equal to the second reference value as a result of the above judgment (S934), the display driving device according to one embodiment of the present invention reduces the frequency of the second clock signal (S935).

[0106] Those skilled in the art will appreciate that the present invention described above can be implemented in other specific forms without changing the technical idea or essential features thereof.

[0107] Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims described below rather than the detailed description above, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included within the scope of the present invention.

[0108] Various embodiments for implementing the present invention have been described in detail in the previous table of contents.

[0109] The present invention is applicable to VR (Virtual Reality) devices, LCD (Liquid Crystal Display), and mobile devices, and thus its industrial applicability is recognized.

Claims

1. A method for controlling a display driving device, A step of receiving a first clock signal from an external source; A step of executing a write operation to a memory according to the first clock signal received above; A step of generating a second clock signal internally; A step of executing a read operation on the memory according to the second clock signal generated above. Including, but not limited to, A control method for a display driving device, characterized in that the second clock signal is changed according to the first clock signal.

2. In paragraph 1, The step of generating a second clock signal within the above is: At the first time a read operation is performed, Step of comparing the write address and the read address A method for controlling a display driving device further comprising:

3. In paragraph 2, As a result of the above comparison, If the difference between the above write address and the above read address is greater than or equal to the first reference value, A step of increasing the frequency of the second clock signal A method for controlling a display driving device, characterized in that it further includes:

4. In paragraph 3, As a result of the above comparison, If the difference between the above write address and the above read address is less than or equal to the second reference value, Step of reducing the frequency of the second clock signal A method for controlling a display driving device, characterized in that it further includes:

5. In paragraph 1, The first clock signal received from the above external source is, It is related to either 60Hz or 120Hz, which is the display refresh rate generated by the AP (Application Processor). A method for controlling a display driving device, characterized in that the second clock signal generated internally is generated by an oscillator.

6. In paragraph 5, A step of transmitting an error flag to the above AP indicating that the above memory is full or empty. A method for controlling a display driving device, characterized in that it further includes:

7. In the display driving device, A first controller which receives a first clock signal from the outside and executes a write operation on a memory according to the received first clock signal; A generation unit that generates a second clock signal internally; A second controller that performs a read operation on the memory according to the second clock signal generated above. Including, but not limited to, A display driving device, characterized in that the second clock signal changes according to the first clock signal.

8. In paragraph 7, The above generating unit, At the minimum time to perform a read operation, A comparison unit that compares the write address and the read address. A display driving device further comprising:

9. In paragraph 8, As a result of the above comparison, If the difference between the above write address and the above read address is greater than or equal to the first reference value, The above generating unit, A display driving device characterized by increasing the frequency of the second clock signal.

10. In paragraph 9, As a result of the above comparison, If the difference between the above write address and the above read address is less than or equal to the second reference value, The above generating unit, A display driving device characterized by reducing the frequency of the second clock signal.

11. In paragraph 7, The first clock signal received from the above external source is, It is related to either 60Hz or 120Hz, which is the display refresh rate generated by the AP (Application Processor). A display driving device, characterized in that the above generating unit includes an oscillator.

12. In paragraph 11, The above generating unit, A display driving device characterized in that it transmits an error flag to the AP indicating that the memory is full or empty.

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