Reconfigurable LNA with high IP2 mode

Abstract

A reconfigurable amplifier is disclosed with an analog subtractor having a radio frequency (RF) output terminal (46), an in-phase terminal (48), and an out-of-phase terminal (50). A first amplifier transistor has a first current input coupled to the in-phase terminal and a first current output coupled to a fixed voltage node (G1) forming a main path, and a first control terminal coupled to an RF input terminal (38). A second amplifier transistor has a second current input coupled to the out-of-phase terminal and a second current output coupled to the fixed voltage node forming an auxiliary path, and a second control terminal coupled to the first current terminal, wherein second-order intermodulation distortion components cancel as signals in the auxiliary path are subtracted from signals within the main path when the auxiliary path is enabled.

Description

RECONFIGURABLE LNA WITH HIGH IP2 MODERelated Applications

[0001] This application claims the benefit of provisional patent application serial number 63 / 600,852, filed November 20, 2023, the disclosure of which is hereby incorporated herein by reference in its entirety.Field of the Disclosure

[0002] The present disclosure relates to low-noise amplifiers that are reconfigurable to provide improved linearization.Background

[0003] There are many radios in a mobile handset that may be operating simultaneously that need to coexist. These radios may be simultaneously transmitting while the handset is trying to receive a wanted signal within a received signal path. Multiple transmitter signals may undergo intermodulation and generate an in-band blocking signal that will desensitize the receiver that is receiving the desired signal. In this case the receiver is considered a “victim.”

[0004] The “victim” receiver is typically protected from transmitter blocker signals by way of a high rejection filter prior to a low-noise amplifier (LNA). Undesirably, the high rejection filter needs to provide a substantially greater than 60dB rejection of the blocker signals to stop the blocker signals from desensitizing the “victim” receiver through intermodulation. Such a high rejection filter is difficult to implement and has a relatively high insertion loss. Thus there remains a need for an LNA with substantially improved high out-of- band linearity to allow for a lower rejection requirement which in turn provides a relaxation in filter attenuation requirement.

[0005] A reconfigurable amplifier is disclosed with an analog subtractor having a radio frequency (RF) output terminal, an in-phase terminal, and an out-of-phase terminal. A first amplifier transistor has a first current input coupled to the in-phase terminal and a first current output coupled to a fixedvoltage node forming a main path, and a first control terminal coupled to an RF input terminal. A second amplifier transistor has a second current input coupled to the out-of-phase terminal and a second current output coupled to the fixed voltage node forming an auxiliary path, and a second control terminal coupled to the first current terminal, wherein second-order intermodulation distortion components cancel as signals in the auxiliary path are subtracted from signals within the main path when the auxiliary path is enabled.

[0006] In another aspect, any of the foregoing aspects individually or together, and / or various separate aspects and features as described herein, may be combined for additional advantage. Any of the various features and elements as disclosed herein may be combined with one or more other disclosed features and elements unless indicated to the contrary herein.

[0007] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.Brief Description of the Drawing Figures

[0008] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0009] FIG. 1 is a diagram of an embodiment of a reconfigurable low-noise amplifier (LNA) that is structured in accordance with the present disclosure.

[0010] FIG. 2A is a graph of input-referred second-order intercept (IIP2) as a function of input power.

[0011] FIG. 2B is a graph of IIP2 extrapolated from P1=P1 as a function of input power.

[0012] FIG. 3 is a diagram of an embodiment of the reconfigurable LNA that depicts an exemplary structure that employs an autotransformer as an analog subtractor for the embodiment of FIG. 1 .

[0013] FIG. 4 is a graph of IIP2 versus a blocker signal at a given victim freguency.

[0014] FIG. 5 is a diagram of an embodiment of the reconfigurable LNA that includes a phase shifter in an auxiliary path.

[0015] FIG. 6 is a diagram of an embodiment of the reconfigurable LNA that includes an input match tuner that is configured to provide phase shift.

[0016] FIG. 7 is a graph of IIP2 versus a blocker signal at a given victim frequency without employing phase compensation or amplitude compensation.

[0017] FIG. 8 is a diagram of a complementary metal-oxide semiconductor (CMOS)-based embodiment of a reconfigurable LNA that is structured in accordance with the present disclosure.

[0018] FIG. 9 is a diagram of a CMOS-based embodiment of a reconfigurable LNA that includes additional cascode transistors in accordance with the present disclosure.

[0019] FIG. 10A is a graph of IIP2 versus F1 performance of the CMOSbased embodiment of FIG. 8.

[0020] FIG. 10B is a graph of noise factor (NF) versus frequency performance of the CMOS-based embodiment of FIG. 8.

[0021] FIG. 10C is a graph of the scattering parameter S21 versus frequency performance of the CMOS-based embodiment of FIG. 8.

[0022] FIG. 11 is a CMOS embodiment of the reconfigurable LNA that includes additional amplifier branches that are configured to be selectably enabled and disabled within the auxiliary path.

[0023] Fig. 12 is a diagram of an embodiment of the CMOS version of the reconfigurable LNA that includes the input match tuner that is configured to provide phase shift.

[0024] FIG. 13 is a graph of IIP2 versus a blocker signal for the CMOS version of the reconfigurable LNA at a given victim frequency without employing phase compensation or amplitude compensation.

[0025] FIG. 14 is a diagram showing how the disclosed reconfigurable amplifier may interact with user elements such as wireless communication devices.Detailed Description

[0026] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0027] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0028] It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

[0029] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and / or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0031] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0032] Embodiments are described herein with reference to schematic illustrations of embodiments of the disclosure. As such, the actual dimensions of the layers and elements can be different, and variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are expected. For example, a region illustrated or described as square or rectangular can have rounded or curved features, and regions shown as straight lines may have some irregularity. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the disclosure. Additionally, sizes of structures or regions may be exaggerated relative to other structures or regions for illustrativepurposes and, thus, are provided to illustrate the general structures of the present subject matter and may or may not be drawn to scale. Common elements between figures may be shown herein with common element numbers and may not be subsequently re-described.

[0033] The present disclosure provides linearization circuitry for a reconfigurable low-noise amplifier (LNA) that when enabled improves out-of- band (OOB) second-order input intercept point (IIP2) by around 20dB with a very modest increase in LNA noise factor (NF). For example, in at least some embodiments the NF is no more than 0.3 dB when the high linearity IIP2 mode is enabled. An advantage provided by the disclosed reconfigurable LNA is that the linearization causes second-order intermodulation distortion (IMD2) cancellation at a given victim frequency over a wide range of IMD2 blocker combinations.

[0034] In some embodiments, the linearization circuitry may be selectably disabled in a first LNA mode when problematic pairs of blockers are not present. Problematic high-powered blockers are primarily generated from within the user equipment such as a handset and are known in advance. A baseband processor can therefore be programmed to decide if a second LNA mode that enables the linearization circuitry will give the better sensitivity: The first LNA mode is a very low noise mode (NF ~ 0.9dB, OOB I IP2 ~0dBm).The second LNA mode is a low noise / high IP2 mode (NF ~ 1.2dB, OOB IIP2 >+20dBm).

[0035] Another advantage of at least some embodiments is selective tunability of IMD2 cancellation as a function of the victim frequency using the sub-band information. The sub-band is known ahead of a signal burst and therefore, the IMD2 cancellation can be maximized for a known receiver frequency that may fall victim to blocker signal intermodulation. This tuning may adjust phase and / or amplitude tuning of a cancellation path and tuning of the input match.

[0036] Moreover, the reconfigurable LNA provides enhanced receiver coexistence performance where intermodulation between other transmit signals in the user equipment causes desensitization of the receiver through second-order intermodulation. The disclosed linearization circuitry has relatively small size in comparison to high rejection circuitry that it replaces and is of a lower financial cost. Further still, the circuit structures making up the reconfigurable LNA may be applied to existing LNA topology used in cellular RF front-ends.

[0037] FIG. 1 is a diagram of an embodiment of a reconfigurable low-noise amplifier (LNA) 10 that is structured in accordance with the present disclosure.

[0038] The reconfigurable LNA 10 has a first transistor Q1 having a first collector 12, a first base 14, and a first emitter 16. A second transistor Q2 has a second collector 18, a second base 20, and a second emitter 22. A third transistor Q3 has a third collector 24, a third base 26, and a third emitter 28. A fourth transistor Q4 has a fourth collector 30, a fourth base 32, and a fourth emitter 34. In the exemplary embodiment of FIG. 1 , the first transistor Q1 , the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs). However, it is to be understood that other transistor technologies may be used to realize the reconfigurable LNA 10. Examples of the reconfigurable LNA 10 using field-effect transistors (FETs) fabricated using complementary metal oxide semiconductor (CMOS) processes are described subsequently in this disclosure.

[0039] The first emitter 16 of the first transistor Q1 is degenerated by an emitter inductor LE1 that is coupled between a fixed voltage node G1 and the first emitter 16. In this exemplary embodiment, the fixed voltage node is ground. The first base 14 is coupled to a first base bias terminal 36 through a first bias resistor RB1 . In operation, a first bias voltage VB1 is applied to the first base bias terminal 36. The first base 14 is also coupled to a radio frequency (RF) input terminal 38 through a first coupling capacitor CC1 that is coupled to impedance matching circuitry such as a matching inductor LMATCHI . The RF input terminal 38 is labeled RFIN. The first collector 12 is coupled to the second emitter 22 to place the first transistor Q1 and the second transistorQ2 in a cascode configuration. The second base 20 is coupled to a cascode bias input 40. The first transistor Q1 is configured as a common-emitter amplifier and the second transistor Q2 is configured as a common-base amplifier. In operation, a bias voltage VCAS1 is applied to the cascode bias input 40.

[0040] The reconfigurable LNA 10 provides a high IP2 by employing enhanced linearization generated through an auxiliary path made up of linearization circuitry 42 shown within a dashed box in FIG. 1 . The linearization circuitry 42 comprises an analog subtractor 44 having an RF output terminal 46 labeled RFOUT, an in-phase terminal 48 labeled with a plus symbol, and an out-of-phase terminal 50 labeled with a minus sign.

[0041] The second collector 18 of the second transistor Q2 is coupled to the in-phase terminal 48 of the analog subtractor 44. The third emitter 28 of third transistor Q3 is coupled to the fixed voltage node G1 with no intervening degeneration element. The third collector 24 is coupled to the fourth emitter 34 to place the third transistor Q3 and the fourth transistor Q4 into a cascode configuration. The third base 26 of the third transistor Q3 is coupled to a second base bias terminal 52 through a second bias resistor RB2. In operation, a second bias voltage VB2 is applied to the second base bias terminal 52. A second coupling capacitor CC2 is coupled between the third base 26 of the third transistor Q3 and the first collector 12 of the first transistor Q1 and the second emitter 22 of the second transistor Q2. The fourth base 32 of the fourth transistor Q4 is coupled to the cascode bias input 40. The fourth collector 30 is coupled to the out-of-phase terminal 50.

[0042] Current flowing through the third transistor Q3 and the fourth transistor Q4 within the auxiliary path is subtracted from a main signal path to provide the IMD2 cancellation. The auxiliary path receives signals from the second emitter 22 of the second transistor Q2 that includes desired signals, blocker signals, and IMD2 distortion components. These signals become amplified current signals by way of the amplifier gain (Gm) of the third transistor Q3 along with some additional distortion generated in the auxiliary path.

[0043] The amplifier gain Gm and the phase shift provided within the auxiliary path cause the IMD2 signal output from the fourth transistor Q4 tohave the same amplitude and substantially the same phase of the IMD2 component in the main signal path that includes the second transistor Q2. As a result, the IMD2 components cancel as signals in the auxiliary path and are subtracted from signals within the main signal path, yielding an improved I IP2 as illustrated in the graphs shown in FIG. 2A and FIG. 2B. The phase of the wanted signal component in the auxiliary path and the main path are approximately 180 degrees out of phase. Therefore, after subtraction a gain boost of ~ 2-3dB is provided to the fundamental components in the signal path when the auxiliary path is enabled. The gain boost combined with the auxiliary path tapping the signals after the first amplification by the first transistor Q1 explains why there is a relatively modest increase of ~ 0.3dB in NF when the auxiliary path is enabled.

[0044] FIG. 3 is a diagram of an embodiment of the reconfigurable LNA 10 that depicts an exemplary structure that employs an autotransformer LT1 as the analog subtractor 44. The autotransformer LT1 has a center tap 52 that is coupled to a supply terminal 54 that receives a supply voltage Vcc. The center tap 52 is between two windings of the autotransformer LT1 . The two windings have a coupling coefficient denoted by k, which is a unitless value of magnetic coupling between the two windings. A tuning capacitor CT1 is coupled in parallel with the autotransformer LT1 and has a capacitance sized to efficiently pass desired frequencies through the autotransformer LT1 . While the autotransformer LT1 performs relatively very well as the analog subtractor 44, it is but one of many possible analog subtractor elements and / or circuits that may be used without exceeding the scope of the present disclosure. In this exemplary embodiment of the reconfigurable LNA 10, a third coupling capacitor CC3 is coupled between the RF output terminal 46 and the second collector 18 of the second transistor Q2.

[0045] A relatively large advantage of the reconfigurable LNA 10 is that the provided IMD2 cancellation works over a wide range of IMD blocker frequencies and works for IMD2 products that may be generated from the product of two blocker frequencies, IMD2[+1 , +1] or their difference IMD2[-1 , +1], This property is shown in a simulation graph where the IIP2 is plotted as a function of F1 and F2 for a given victim frequency F_IM2 (i.e. , for IMD2[+1 ,+1] F2 = FJMD2-F1 and for IMD2[-1 ,+1] F2 = FJMD2+F1 ).FIG. 4 is a graph of I IP2 versus a blocker signal at a given victim frequency. Notice that a 20.5 dBm difference between when the auxiliary path is enabled and disabled is maintained over a bandwidth of at least 1 .2 GHz.

[0046] The relative phase of the IMD2 product in the main path and the auxiliary path are substantially in-phase, and as a result the IMD2 is canceled through subtraction. As the victim frequency is changed, there is a slight change in the relative signal amplitude and phase, which in turn degrades the 11 P2. FIG. 5 is a schematic of an exemplary version of the reconfigurable LNA 10 that is configured to reduce the degradation of IIP2 as the victim frequency is changed. In this embodiment, the reconfigurable LNA 10 configured to adjust the magnitude IMD2 components in the auxiliary path as a function of a sub-band that is the known victim frequency through the adjusting of the second bias voltage VB2. The relative phase shift between main and auxiliary path as a function of sub-band is small (< ±20deg) and can be adjusted as a function of sub-band by way of one of at least two embodiments. One embodiment depicted schematically in FIG. 5 includes a tunable phase shifter 56 coupled within the auxiliary path. A processor 60 has a processor output 62 through which the processor adjusts the tunable phase shifter 56. The processor 60 has been configured to tune the tunable phase shifter 56 as a function of victim frequency, which is known to the processor 60.

[0047] Another embodiment depicted in FIG. 6 includes tunable input impedance matching circuitry 58 that has an impedance matching capacitor CMATCHI coupled in parallel with the matching inductor LMATCHI . In this case, the processor 60 has been configured to adjust the capacitance of the impedance matching capacitor as a function of the know victim frequency. The two embodiments work in slightly different ways. The phase shift in the auxiliary path allows for fine adjustment of the auxiliary path’s IMD2 component, whereas tuning the input match adjusts the phase of the IMD2 component created in the main path by the first transistor Q1 . Both embodiments have their own advantages. The embodiment of FIG. 5 has a smaller impact on NF, whereas the tunable input matching circuitry 58 of embodiment of FIG. 6 may be configured as a parallel LC notch filter to provide additional high frequency filtering.

[0048] FIG. 7 is a graph of I IP2 versus a blocker signal at a given victim frequency without employing phase compensation or amplitude compensation. The dashed line shows gain of the reconfigurable LNA 10 with the auxiliary path active and cancelling the unwanted signals, whereas the solid curved line near the bottom of the graph shows 11 P2 performance with the auxiliary path inactive. Note that this exemplary embodiment of the reconfigurable LNA 10 with the auxiliary path active provides at least +20 dBm I IP2 enhanced performance over a 300 MHz bandwidth in comparison to operation when the auxiliary path is made inactive. Notice also that the I IP2 performance is enhanced by 10.6 dBm at 3.3 GHz, and the IIP2 performance is enhanced by 11 dBm at 4.2 GHz. A maximum enhancement of I IP2 performance of 31 dBm occurs at 3.7 GHz.

[0049] FIG. 8 is a diagram of a CMOS-based embodiment of a reconfigurable LNA 10 that is structured in accordance with the present disclosure. In this exemplary CMOS version of the reconfigurable LNA 10, a first field-effect transistor (FET) N1 has a first drain 64, a first gate 66, and a first source 68. A second FET N2 has a second drain 70, a second gate 72, and a second source 74. A third FET N3 has a third drain 76, a third gate 78, and a third source 80. A fourth FET N4 has a fourth drain 82, a fourth gate 84, and a fourth source 86.

[0050] The first drain 64 of the first FET N1 is degenerated by a source inductor LS1 that is coupled between the fixed voltage node G1 and the first source 68. In this exemplary embodiment, the fixed voltage node is ground. The first gate 66 is coupled to a first gate bias terminal 88 through a first gate resistor RG1 . In operation, a first gate voltage VG1 is applied to the second gate 72. The first gate 66 is also coupled to the radio frequency (RF) input terminal 38 through the first coupling capacitor CC1 that is coupled to impedance matching circuitry such as the matching inductor LMATCHI . The first drain 64 is coupled to the second source 74 to place the first FET N1 and the second FET N2 in a cascode configuration. The second gate 72 is coupled to the cascode bias input 40. The first FET N1 is configured as a commonsource amplifier and the second FET N2 is configured as a common-gate amplifier. In operation, the bias voltage VCAS1 is applied to the cascode bias input 40.

[0051] The CMOS version of the reconfigurable LNA 10 provides a high IP2 by employing enhanced linearization generated through an auxiliary path made up of CMOS linearization circuitry 90 shown within a dashed box in FIG. 8. The CMOS linearization circuitry 90 comprises the analog subtractor 44 having the RF output terminal 46 labeled RFOUT, the in-phase terminal 48 labeled with the plus symbol, and the out-of-phase terminal 50 labeled with the minus sign.

[0052] The second drain 70 of the second FET N2 is coupled to the in- phase terminal 48 of the analog subtractor 44. The third source 80 of third FET N3 is coupled to the fixed voltage node G1 with no intervening degeneration element. The third drain 76 of the third FET N3 is coupled to the fourth source 86 of the fourth FET N4 to place the third FET N3 and the fourth FET N4 into a cascode configuration. The third gate 78 of the third FET N3 is coupled to a second gate bias terminal 92 through a second gate resistor RG2. In operation, a second gate voltage VG2 is applied to the second gate bias terminal 92. The second coupling capacitor CC2 is coupled between the third gate 78 of the third FET N3 and the first drain 64 of the first FET N1 and the second source 74 of the second FET N2. The fourth gate 84 of the fourth FET N4 is coupled to the cascode bias input 40. The fourth drain 82 is coupled to the out-of-phase terminal 50.

[0053] Current flowing through the third FET N3 and the fourth FET N4 within the auxiliary path is subtracted from the main signal path to provide the IMD2 cancellation. The auxiliary path receives signals from the second source 74 of the second FET N2 that includes desired signals, blocker signals, and IMD2 distortion components. These signals become amplified current signals by way of the amplifier gain (Gm) of the third FET N3 along with some additional distortion generated in the auxiliary path.

[0054] The amplifier gain Gm and the phase shift provided within the auxiliary path cause the IMD2 signal output from the fourth FET N4 to have the same amplitude and substantially the same phase of the IMD2 component in the main signal path that includes the second FET N2. As a result, the IMD2 components cancel as signals in the auxiliary path and are subtracted from signals within the main signal path, yielding an improved IIP2.

[0055] FIG. 9 is a diagram of a CMOS-based embodiment of a reconfigurable LNA 10 that includes additional cascode transistors in accordance with the present disclosure. In this exemplary embodiment, the additional cascode transistors are a fifth FET N5 and a sixth FET N6. The fifth FET N5 has a fifth drain 94, a fifth gate 96, and a fifth source 98. The sixth FET N6 has a sixth drain 100, a sixth gate 102, and a sixth source 104. The fifth drain 94 of the fifth FET N5 is coupled to the in-phase terminal 48, and the fifth source 98 of the fifth FET N5 is coupled to the second drain 70 of the second FET N2, resulting in a double cascode structure within the main path. The drain 100 of the sixth FET N6 is coupled to the out-of-phase terminal 50, and the source 104 of the sixth FET N6 is coupled to the drain 82 of the fourth FET N4 to configure a double cascode structure within the auxiliary path. A second cascode bias input 106 is coupled to both the fifth gate 96 of the fifth FET N5 and the sixth gate 102 of the sixth FET N6. In operation, a second bias voltage VCAS2 is applied to the second cascode bias input 106.

[0056] FIG. 10A is a graph of IIP2 versus F1 performance of the CMOSbased embodiment of FIG. 8. FIG. 10B is a graph of noise factor (NF) versus frequency performance of the CMOS-based embodiment of FIG. 8. FIG. 10C is a graph of the scattering parameter S21 versus frequency performance of the CMOS-based embodiment of FIG. 8. The dashed curves in FIGS. 10A, 10B, and 10C represent performance of the reconfigurable amplifier 10 when the auxiliary path in a high IP2 mode is active / enabled. The solid curves in FIGS. 10A, 10B, and 10C represent performance of the reconfigurable amplifier 10 when the auxiliary path in a low-noise mode is not active / disabled.

[0057] FIG. 11 is a CMOS embodiment of the reconfigurable LNA 10 that includes a first amplifier branch 108, a second amplifier branch 110, and an Nth amplifier branch 112 that are configured to be selectably enabled and disabled within the auxiliary path, wherein N is a natural counting number. The first amplifier branch 108 is made up of the NFETs N3, N4, and N6. In this exemplary embodiment, a first switch FET A1 has a first switch source 114 coupled to the third drain 80 of the third FET N3 and a switch drain 118 coupled to the fixed voltage node G1. A first switch gate 116 is configured toreceive a first enable / disable signal ENABLE-1 generated by the processor 60 and in response to allow current to flow through the first branch 108 when the ENABLE-1 signal is an enable condition and to prevent current flow through the first branch 108 when the ENABLE-1 signal is a disable condition.

[0058] The second amplifier branch 110 is made up of NFETS N3-2, N4-2, and N6-2 that are coupled together like the FETS N3, N4, and N6 to form a second selectable portion of the auxiliary path. A second switch FET A2 is coupled between the NFETS N3-2, N4-2, and N6-2 and the fixed voltage node G1 . A second switch gate 120 is configured to receive a second enable / disable signal ENABLE-2 generated by the processor 60 and in response to allow current to flow through the second branch 110 when the ENABLE-2 signal is an enable condition and to prevent current flow through the second branch 110 when the ENABLE-2 signal is a disable condition.

[0059] The Nth amplifier branch 112 is made up of NFETs N3-N, N4-N, and N6-N that are coupled together like the FETs N3, N4, and N6 to form an Nth selectable portion of the auxiliary path. An Nth switch FET AN is coupled between the NFETs N3-N, N4-N, and N6-N and the fixed voltage node G1. A Nth switch gate 122 is configured to receive an Nth enable / disable signal ENABLE-N generated by the processor 60 and in response to allow current to flow through the Nth branch 112 when the ENABLE-N signal is an enable condition and to prevent current flow through the Nth branch 112 when the ENABLE-N signal is a disable condition. Moreover, in some versions of the embodiment of FIG. 11 , the first amplifier branch 108, the second amplifier branch 110, and the Nth amplifier branch 112 need not provide uniform amplification. For example, the first amplifier branch 108, the second amplifier branch 110, and the Nth amplifier branch 112 may have differing numbers of cascaded FETs or the transconductance of the FETs between the amplifier branches may be different.

[0060] The processor 60 is configured to output the enable / disable signals ENABLE-1 , ENABLE-2, and ENABLE-N though the processor output 62, which may be a serial bus or a parallel bus in the exemplary embodiment of FIG. 11. It is to be understood that intervening circuitry such as gate drivers and address decoders (not shown) may be employed to level shift and / orselectively address the switch FETS A1 through AN and the tunable phase shifter 56 depending on specific applications.

[0061] Fig. 12 is a diagram of an embodiment of the CMOS version of the reconfigurable LNA 10 that includes the input match tuner 58 that is configured to provide phase shift to allow the IMD2 components to cancel as signals in the auxiliary path are subtracted from signals within the main signal path, yielding an improved IIP2. FIG. 13 is a graph of IIP2 versus a blocker signal for the CMOS version of the reconfigurable LNA 10 at a given victim frequency without employing phase compensation or amplitude compensation.

[0062] With reference to FIG. 14, the concepts described above may be implemented in various types of wireless communication devices or user elements 124, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, and the like that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, and near-field communications. The user elements 124 will generally include a control system 126, a baseband processor 128, transmit circuitry 130, receive circuitry 132 that includes the reconfigurable LNA 10, antenna switching circuitry 134, multiple antennas 136, and user interface circuitry 138. The receive circuitry 132 receives radio frequency signals via the antennas 136 and through the antenna switching circuitry 134 from one or more basestations. A low-noise amplifier and a filter (not shown) cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams.

[0063] The baseband processor 128 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations. The baseband processor 128 is generally implemented in one or more digital signal processors (DSPs) and application-specific integrated circuits (ASICs).

[0064] For transmission, the baseband processor 128 receives digitized data, which may represent voice, data, or control information, from the controlsystem 126, which it encodes for transmission. The encoded data are output to the transmit circuitry 130, where they are used by a modulator (not shown) to modulate a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier (not shown) amplifies the modulated carrier signal to a level appropriate for transmission and delivers the modulated carrier signal to the antennas 136 through the antenna switching circuitry 134. The antennas 136 and the replicated transmit circuitry 130 and receive circuitry 132 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0065] It is contemplated that any of the foregoing aspects, and / or various separate aspects and features as described herein, may be combined for additional advantage. Any of the various embodiments as disclosed herein may be combined with one or more other disclosed embodiments unless indicated to the contrary herein.

[0066] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

AMENDED CLAIMS received by the International Bureau on 24 March 2025 (24.03.2025)What is claimed is:1 . A reconfigurable amplifier comprising:• an analog subtractor having a radio frequency (RF) output terminal (46), an in-phase terminal (48), and an out-of-phase terminal (50);• a first amplifier transistor having a first current input terminal coupled to the in-phase terminal and a first current output terminal coupled to a fixed voltage node (G1 ) forming a main path, and a first control terminal coupled to an RF input terminal (38);• a second amplifier transistor having a second current input terminal coupled to the out-of-phase terminal and a second current output terminal coupled to the fixed voltage node forming an auxiliary path, and a second control terminal coupled to the first current input terminal, wherein second-order intermodulation components substantially cancel as signals in the auxiliary path are subtracted from signals within the main path when the auxiliary path is enabled; and• a tunable phase shifter coupled within the auxiliary path and configured to fine-tune cancellation of the second-order intermodulation components as a function of a sub-band that is known ahead of a signal burst.

2. The reconfigurable amplifier of claim 1 further comprising a switch transistor coupled between the second amplifier transistor and the fixed voltage node, wherein the switch transistor has a control terminal configured to receive an enable / disable signal.

3. The reconfigurable amplifier of claim 2 further comprising a processor having a processor output in communication with the control input of the switch transistor, wherein the processor is configured to turn on the switch transistor to enable the auxiliary path in a high second-order intercept mode in which the second-order intermodulation components in the auxiliary path are subtracted from signals within the main path, and turn off the switch transistorto disable the switch transistor in a lower noise mode that improves noise factor.

4. The reconfigurable amplifier of claim 1 wherein the fixed voltage node is ground.

5. The reconfigurable amplifier of claim 1 wherein the first amplifier transistor and the second amplifier transistor are field-effect transistors (FETs) configured in a cascode configuration.

6. The reconfigurable amplifier of claim 1 further comprising a degeneration element coupled between the fixed voltage node and the first current input of the first amplifier transistor.

7. The reconfigurable amplifier of claim 1 wherein the analog subtractor comprises an autotransformer having a center tap coupled to a supply terminal that receives a supply voltage, and two windings with a coupling coefficient, and further comprising a tuning capacitor coupled in parallel with the autotransformer.

8. (Cancelled).

9. The reconfigurable amplifier of claim 1 further comprising tunable input impedance matching circuitry coupled in parallel with impedance matching circuitry between the RF input terminal and the first control terminal, wherein the tunable input impedance matching circuitry has an impedance matching capacitor the capacitance of which is adjustable as a function of the known victim frequency.

10. The reconfigurable amplifier (10) of claim 1 further comprising a third amplifier transistor (N3) having a third current input terminal (70) coupled to the in-phase terminal (48), a third current output terminal (74) coupled to the first current input terminal (64) of the first amplifier transistor (N1 ), and a thirdcontrol terminal (72) coupled to a first cascode bias input (40), and a fourth amplifier transistor (N4) having a fourth current input terminal (82) coupled to the out-of-phase terminal (50), a fourth current output terminal (86) coupled to the second current input terminal (76) of the second amplifier transistor (N2), and a fourth control terminal (84) coupled to the first cascode bias input (40) , wherein the auxiliary path receives signals that include desired signals, blocker signals, and second-order intermodulation distortion components.

11. The reconfigurable amplifier of claim 10 further comprising a fifth amplifier transistor (N5) having a fifth current input terminal (94) coupled to the in- phase terminal (48), a fifth current output terminal (98) coupled to the third current input terminal (70) of the third amplifier transistor (N3), and a fifth control terminal (96) coupled to a second cascode bias input (106) , and a sixth amplifier transistor (N6) having a sixth current input terminal (100) coupled to the out-of-phase terminal (50), a sixth current output terminal (104) coupled to the fourth current input terminal (82) of the fourth amplifier transistor (N4), and a sixth control terminal (102) coupled to the second cascode bias input (106).

12. The reconfigurable amplifier of claim 1 further comprising a first selectively enabled and disabled amplifier branch in parallel with the auxiliary path, and a second selectively enabled and disabled amplifier branch in series with the auxiliary path, wherein each amplifier branch has a switch transistor having a control terminal configured to receive an enable / disable signal generated by a processor.

13. The reconfigurable amplifier of claim 12 further comprising N-1 additional selectively enabled and disabled amplifier branches in parallel with the second amplifier branch, wherein each amplifier branch has a switch transistor having a control terminal configured to receive an enable / disable signal generated by the processor.

14. The reconfigurable amplifier of claim 1 further comprising input match tuner circuitry that provides phase shift to allow the second-order intermodulation components to cancel as signals in the auxiliary path are subtracted from signals within the main path, yielding an improved input second-order intercept point (IIP2).

15. A method of operating a reconfigurable amplifier having an analog subtractor having an in-phase terminal (48) and an out-of-phase terminal (50) with a first amplifier branch (108) coupled within a main path between the in- phase terminal and at least a second amplifier branch (110) that is selectably enabled within an auxiliary path coupled between the out-of-phase terminal and ground, the method comprising:• applying a radio frequency (RF) signal to an RF input of the first amplifier branch;• coupling an amplified version of the RF signal to the at least second amplifier branch;• enabling the at least second amplifier branch, wherein second-order intermodulation components substantially cancel as signals in the auxiliary path are subtracted from signals within the main path when the auxiliary path is enabled; and• adjusting the phase shift within the auxiliary path as a function of a subband that is known ahead of a signal burst to fine-tune cancellation of second-order intermodulation components.

16. The method of claim 15 further comprising receiving an enable / disable signal from a processor and controlling at least the second amplifier branch based on an enable / disable signal.

17. The method of claim 15 wherein the first amplifier branch comprises a first field-effect transistor (FET) having a first drain, a first gate, and a first source, and further comprising applying a first gate voltage to the first gate of the first FET.

18. The method of claim 15 wherein coupling an amplified version of the RF signal to the at least second amplifier branch comprises passing the amplified RF signal through impedance matching circuitry coupled between the first amplifier branch and at least the second amplifier branch.

19. The method of claim 17 further comprising degenerating a current input of the first amplifier transistor by coupling a source inductor between a fixed voltage node and the first source of the first FET.

20. The method of claim 15 wherein enabling at least the second amplifier branch comprises applying a bias voltage to a cascode bias input coupled to a gate of a third field-effect transistor (FET) in the auxiliary path.

21. The method of claim 15 further comprising applying a first enable / disable signal to a control terminal of a switch transistor coupled between the second amplifier branch and ground, wherein enabling at least the second amplifier branch comprises turning on the switch transistor in response to the first enable / disable signal.

22. The method of claim 15 further comprising receiving a second enable / disable signal from a processor and applying the second enable / disable signal to the control terminal of the switch transistor to control at the least second amplifier branch.

23. (Cancelled).

24. The method of claim 15 wherein enabling at least the second amplifier branch comprises selectively enabling multiple amplifier branches in parallel and series within the auxiliary path, each having a switch transistor controlled by an enable / disable signal from a processor.

25. A wireless communication device comprising:• a baseband processor (128) configured to encode a digitized version of radio frequency (RF) signals to generate encoded data;• transmit circuitry (130) configured to receive the encoded data from the baseband processor and to modulate a carrier signal with the encoded data; and• a reconfigurable amplifier comprising:• an analog subtractor having an RF output terminal (46), an in- phase terminal (48), and an out-of-phase terminal (50);• a first amplifier transistor having a first current input terminal coupled to the in-phase terminal and a first current output terminal coupled to a fixed voltage node (G1 ) forming a main path, and a first control terminal coupled to an RF input terminal (38);• a second amplifier transistor having a second current input terminal coupled to the out-of-phase terminal and a second current output terminal coupled to the fixed voltage node forming an auxiliary path, and a second control terminal coupled to the first current terminal, wherein second-order intermodulation components substantially cancel as signals in the auxiliary path are subtracted from signals within the main path when the auxiliary path is enabled; and• a tunable phase shifter coupled within the auxiliary path and configured to fine-tune cancellation of second-order intermodulation components as a function of a sub-band that is known ahead of a signal burst.

26. The wireless communication device of claim 25 further comprising a switch transistor coupled between the second amplifier transistor and the fixed voltage node, wherein the switch transistor has a control terminal configured to receive an enable / disable signal from a processor.

27. The wireless communication device of claim 26 wherein the processor is configured to turn on the switch transistor to enable the auxiliary path in a high second-order intercept mode and improve input second-order intercept point (IIP2), and turn off the switch transistor to disable the auxiliary path and reduce noise factor.

28. The wireless communication device of claim 25 further comprising tunable input impedance matching circuitry coupled in parallel with impedance matching circuitry between the RF input terminal and the first control terminal, wherein the tunable input impedance matching circuitry has an impedance matching capacitor the capacitance of which is adjustable as a function of the known victim frequency.

29. (Cancelled).

30. The wireless communication device of claim 25 wherein the first and second amplifier transistors are field-effect transistors (FETs) configured in a cascode configuration.

31. The wireless communication device of claim 25 further comprising a third amplifier transistor (N3) having a third current input terminal (70) coupled to the in-phase terminal (48), a third current output terminal (74) coupled to the first current input terminal (64) of the first amplifier transistor (N1 ) and a third control terminal (72) coupled to a first cascode bias input (40) , and a fourth amplifier transistor (N4) having a fourth current input terminal (82) coupled to the out-of-phase terminal (50), a fourth current output terminal (86) coupled to the second current input terminal (76) of the second amplifier transistor (N2), and a fourth control terminal (84) coupled to the first cascode bias input (40).

32. The wireless communication device of claim 31 further comprising a fifth amplifier transistor (N5) having a fifth current input terminal (94) coupled to the in-phase terminal (48), a fifth current output terminal (98) coupled to the third current input terminal (70) of the third amplifier transistor (N3), and a fifthcontrol terminal (96) coupled to a second cascode bias input (106), and a sixth amplifier transistor (N6) having a sixth current input terminal (100) coupled to the out-of-phase terminal (50), a sixth current output terminal (104) coupled to the fourth current input terminal (82) of the fourth amplifier transistor (N4), and a sixth control terminal (102) coupled to the second cascode bias input (106).

33. The wireless communication device of claim 25 further comprising first selectively enabled and disabled amplifier branch in parallel with the auxiliary path, and at least one additional selectively enabled and disabled amplifier branch in series with the auxiliary path, wherein each amplifier branch has a switch transistor having a control terminal configured to receive an enable / disable signal generated by a processor.

34. The wireless communication device of claim 25 further comprising input match tuner circuitry that provides phase shift to allow second-order intermodulation components to cancel as signals in the auxiliary path are subtracted from signals within the main path, yielding an improved input second-order intercept point (IIP2).

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