Interleaved lithography overlay control method

Abstract

An interleaved lithography overlay control method includes exposing an underlying pattern through a first mask having first alignment marks, exposing the underlying pattern through a second mask having second alignment marks, such that an overlapping boundary area in the underlying pattern is exposed through both the first mask and the second mask, and such that interleaved alignment marks are formed where respective first and second alignment marks overlap, and measuring an overlay error using the interleaved alignment marks.

Description

INTERLEAVED LITHOGRAPHY OVERLAY CONTROL METHODFIELD

[0001] The present invention relates to an interleaved lithography overlay control system and in particular, an interleaved lithography overlay control system that places an overlay control structure within an overlapping boundary.BACKGROUND

[0002] State-of-the-art overlay and alignment metrology may utilize image-based overlay (BLOSSOM) targets and diffraction-based (DBO) targets. The targets may be used to evaluate the x / y displacement relative to a common level. The data measured may be used to maintain overlay control as well as feed-forward corrections to the next wafers / lots. The overlay may be measured to a reference layer as well as multi-patterned layers, being etched into a common hard mask but evaluated as patterned lithography mark to patterned etch mark.SUMMARY

[0003] According to an aspect of the present disclosure, an interleaved lithography overlay control method includes exposing an underlying pattern through a first mask having first alignment marks, exposing the underlying pattern through a second mask having second alignment marks, such that an overlapping boundary area in the underlying pattern is exposed through both the first mask and the second mask, and such that interleaved alignment marks are formed where respective first and second alignment marks overlap, and measuring an overlay error using the interleaved alignment marks.BRIEF DESCRIPTION OF THE DRAWINGS

[0004] For a better understanding of the various described embodiments, reference should be made to the Detailed Description below, in conjunction with the following drawings in which like reference numerals refer to corresponding parts throughout the Figures.

[0005] FIG. 1 is a schematic view of a lithographic scanner 100 including an exposure unit 110, according to one or more embodiments.

[0006] FIG. 2 is a flow chart for an interleaved lithography overlay control method, according to one or more embodiments.

[0007] FIG. 3 is a plan view (e.g., top-down view) of a patterning layout 300 in the interleaved lithography overlay control system 101, according to one or more embodiments.

[0008] FIG. 4 is a plan view of the first crosses 310b and second crosses 320b in a patterning layout, according to one or more embodiments.

[0009] FIG. 5 is a plan view of the first grating structure 310d and second grating structure 320d in a patterning layout, according to one or more embodiments.

[0010] FIG. 6 is a plan view of image-based overlay control structures 690 and critical dimension -based (CD-based) control structures 695 in a patterning layout, according to one or more embodiments.

[0011] FIG.7 is a plan view of first alignment marks 310a and second alignment marks 320a in a patterning layout, according to one or more embodiments.DETAILED DESCRIPTION

[0012] As discussed above, the embodiments of the present disclosure are directed an optical proximity correction device and method of performing optical proximity correction, the various aspects of which are discussed herein in detail. The drawings are not necessarily drawn to scale. Multiple instances of an element may be duplicated where a single instance of the element is illustrated, unless absence of duplication of elements is expressly described or clearly indicated otherwise. Ordinals such as “first,” “second,” and “third” are employed merely to identify similar elements, and different ordinals may be employed across the specification and the claims of the instant disclosure. The same reference numerals refer to the same element or similar element. Unless otherwise indicated, elements having the same reference numerals are presumed to have the same composition. As used herein, a first element located “on” a second element can be located on the exterior side of a surface of the second element or on the interior side of the second element. As used herein, a first element is located “directly on” a second element if there exist a physical contact between a surface of the first element and a surface of the second element. As used herein, a “layer” refers to a continuous portion of at least one material including a region having a thickness. A layer may consist of a single material portion having a homogeneous composition, or may include multiple material portions having different compositions.

[0013] As used herein, a “conductive material” refers to a material having electrical conductivity greater than 1.0 x 105S / cm. As used herein, an “insulator material” or a “dielectric material” refers to a material having electrical conductivity less than 1.0 x 105S / cm. As used herein, a “semiconducting material” refers to a material having electricalconductivity in the range from 1.0 x 10"5S / cm to 1.0 x 105S / cm. As used herein, a “metallic material” refers to a conductive material including at least one metallic element therein. All measurements for electrical conductivities are made at the standard condition.

[0014] Patterning of any single or multi-level design (e.g., a (litho-etch)11technique or self-aligned technique) may require overlay control marks that are used to evaluate the x / y displacement of one level to another. Overlay may be evaluated between a lithographic (e.g., litho) exposure and an etched pattern prior to the exposed pattern layout (e.g., in a photoresist layer) being etched into the underlying hard mask or substrate. For interleaved lithography, in some embodiments, it may be advantageous to evaluate lithographic to lithographic (litho- 2-litho) patterned structures as well as evaluating the lithography performance of overlapping or closely adjacent structures.

[0015] One or more embodiments of the present disclosure may include an interleaved lithography overlay control system and an interleaved lithography overlay control method. In particular, the interleaved lithography overlay control system and interleaved lithography overlay control method may include interleaved lithography overlay control structures, metrology and process control.

[0016] FIG. 1 is a schematic view of a lithographic scanner 100 including an exposure unit 110, according to one or more embodiments. As illustrated in FIG. 1, the lithographic scanner 100 may include an exposure unit 110. The exposure unit 110 may include, for example, a radiation source such as an ultraviolet emitting lamp (e.g., LED or mercury lamp) or laser, or an X-ray emitter for X-ray lithography, for exposing a structure 10, such as a semiconductor device or a photonic structure (e.g., silicon photonic die) in a lithographic process. The structure 10 typically includes a substrate, such as a wafer (e.g., silicon wafer, etc.).

[0017] The lithographic scanner 100 may also include an interleaved lithography overlay control system 101 for controlling overlay in the lithographic scanner. The interleaved lithography overlay control system 101 may include an overlay setting unit 150 for correcting an overlay error in the exposure unit 110.

[0018] As further illustrated in FIG. 1, the interleaved lithography overlay control system 101 may further include an overlay metrology tool 130 for measuring overlay error for the patterning layout based on a reference layer. The overlay metrology tool 130 may generate overlay correction data that may typically be used to make adjustments to the exposure unit 110.

[0019] The overlay metrology tool 130 may use the overlay control structure to measure x / y overlay error. The overlay metrology tool 130 may measure x / y overlay error by a vertical-to-vertical edge and a horizontal-to-horizontal edge for a plurality of overlay control structures. The overlay metrology tool 130 may measure overlay error as a litho-to-litho mark and a litho-to-etch mark.

[0020] The interleaved lithography overlay control system 101 may further include an overlay error correction unit 140 that generates overlay error correction data for performing alignment (e.g., re-alignment or alignment correction) for the patterning layout to correct the overlay error. The overlay error correction unit 140 may generate overlay error correction data for performing alignment between sub-level exposures by the exposure unit 110. The overlay error correction unit 140 may transmit the overlay error correction data to the overlay setting unit 150. The overlay setting unit 1 0 may use the overlay error correction data to control the exposure unit 110 to correct the overlay error.

[0021] FIG. 2 is a flow chart for an interleaved lithography overlay control method, according to one or more embodiments. As illustrated in FIG. 2, Step 210 of the interleaved lithography overlay control method may include exposing an underlying pattern through a first mask 310 having first alignment marks (310a, 310b, 310c and / or 3 lOd). Step 220 may include exposing the underlying pattern through a second mask 320 having second alignment marks (320a, 320b, 320c and / or 320d), such that an overlapping boundary area 330 in the underlying pattern is exposed through both the first mask 310 and the second mask 320, and such that interleaved alignment marks (400b, 330d and / or 690) are formed where respective first and second alignment marks overlap. Step 230 may include measuring an overlay error using the interleaved alignment marks (400b, 330d and / or 690).

[0022] FIG. 3 is a plan view (e.g., top-down view) of a patterning layout 300 that may be used by the interleaved lithography overlay control system 101, according to one or more embodiments. The patterning layout 300 may include a first mask 310 (e.g., first prime mask) including a first pattern 301. The first mask 310 (e.g., mask used in a first exposure field) may include various overlay control structures for controlling overlay. The overlay control structures may include first alignment marks 310a, first crosses 310b, first triangles 310c (e.g., flare structures), and first grating structures 310d.

[0023] The patterning layout 300 may also include a second mask 320 (e.g., second prime mask) including a second pattern 302. The second mask 320 (e.g., second exposure field) may also include various overlay control structures for controlling overlay. The controlstructures may include second alignment marks 320a, second crosses 320b, second triangles 320c (e.g., flare structures), and second grating structures 320d.

[0024] The patterning layout 300 may also include an overlapping boundary area 330 between the first mask 310 and the second mask 320. In the overlapping boundary area 330, the first mask 310 may overlap the second mask 320, and vice versa. The first alignment marks 310a and second alignment marks 320a may be located outside the overlapping boundary area 330. The first crosses 310b, second crosses 320b, first triangles 310c and second triangles 320c may located in the overlapping boundary area 330 and outside the overlapping boundary area 330. Some of the first crosses 310b and second crosses 320b may be located entirely in the overlapping boundary area 330, while the remaining first cross and second crosses are located entirely outside the overlapping boundary area 330. In contrast, each of the first triangles 310c and second triangles 320c may include a portion that is placed in the overlapping boundary area 330 and outside the overlapping boundary area 330. The first grating structure 310d and second grating structure 320d may be located entirely outside the overlapping boundary area 330. An interleaved grating structure 330d including elements of the first grating structure 310d and second grating structure 320d may be located entirely inside the overlapping boundary area 330.

[0025] As illustrated in FIG. 3, the interleaved lithography overlay control system 101 may utilize the first crosses 310b and second crosses 320b for x / y overlay measurement. The first crosses 310b and second crosses 320b may be designed, for example, according to image-based overlay (BLOSSOM) or diffraction-based overlay (DBO) marks. As noted above, the first crosses 310b and second crosses 320b may be placed both within the overlapping boundary area 330 (e.g., stitched interface) as well as outside the overlapping boundary to deconvolve proximity effects.

[0026] An x / y overlay may be measured by vertical-to- vertical edge and horizontal-to- horizontal edge for both the in and out of boundary marks. A common overlay target may also be included to provide global overlay data, both inside and outside the overlapping boundary. Overlay may be thereby measured as a litho-to-litho mark as well as litho-to-etch mark.

[0027] The interleaved lithography overlay control system 101 may also utilize the first triangles 310c and second triangles 320c for multiple exposure flare verification. A pitch of the first triangles 310c and second triangles 320c may be varied according to the projected flare of the exposure conditions so that the effect can be observed and the minimal spacing threshold monitors. As overlay varies, the first triangles 310c and second triangles 320c canbe measured via microscopy (e.g., CD-SEM) to evaluate the changing impact of flare of the critical components.

[0028] The interleaved lithography overlay control system 101 may also utilize the first alignment marks 310a and second alignment marks 320a for each sub-level. The first alignment marks 310a and second alignment marks 320a may be designed according to standard alignment marks. The first alignment marks 310a and second alignment marks 320a may be placed in each sub-level during exposure. The first alignment marks 310a and second alignment marks 320a may be added to the scanner alignment protocol as well as the reference layer alignment marks to reduce overlay errors.

[0029] FIG. 4 is a plan view of the first crosses 310b and second crosses 320b in a patterning layout, according to one or more embodiments. As illustrated in FIG. 4, the patterning layout may also include third crosses 400b. The third crosses 400b may be an interleaved cross formed by interleaving the first crosses 310b and second crosses 320b. The solid arrows 401 may indicate an x-overlay measurement by the overlay metrology tool 130. The dashed arrows 402 may indicate a y-overlay measurement by the overlay metrology tool 130.

[0030] As illustrated in FIG. 4, the interleaved lithography overlay control system 101 may include BLOSSOM-like overlay control structures for interleaved lithography patterning. In particular, the interleaved lithography overlay control system 101 may utilize a cross-design with x / y position. The crosses may be designed to a grid in a common layout of the patterning level and later decomposed according to critical component sub-patterning levels. A pitch and critical dimension (CD) of the crosses (e.g., first crosses 310b, second crosses 320b, and / or third crosses 400b) may be determined by the critical level design, and match anchor dimension. Further, optical proximity correction (OPC) may be tuned for each of the crosses on its own sub-level based on the source-mask optimization for that critical component.

[0031] The interleaved lithography overlay control system 101 may also place the crosses both in the overlapping boundary of two sub-level exposures as well as outside of the overlapping boundary. The redundant placement may allow for deconvolution of any flare or other induced proximity effects both along the ‘x’ and ‘y’ coordinates. Further, standard overlay metrology tools (e.g., overlay metrology tool 130) may be used to measure the sub- level-to-sub-level and sub-level to reference layer overlay error. The interleaved lithography overlay control system 101 may also implement process control by multiplexing marks andmeasurement based on the number of overlapping exposure fields as well as to the underlying reference layer, or zero layer, if the interleaved exposure is the first device exposure level.

[0032] FIG. 5 is a plan view of the first grating structure 310d and second grating structure 320d in a patterning layout, according to one or more embodiments. As illustrated in FIG. 5, the patterning layout may also include third grating structure 330d. The third grating structure 330d may be an interleaved grating structure formed by interleaving the first grating structure 3 lOd and second grating structure 320d. The solid arrows 501 may indicate an x-overlay measurement by the overlay metrology tool 130. The cross-hatched arrows 502 may indicate a y-overlay measurement by the overlay metrology tool 130.

[0033] The first grating structure 310d and second grating structure 320d may be used by the overlay metrology tool 130 for litho-to-litho comparison. The third grating structure 330d may be used by the overlay metrology tool 130 as a litho-to-etch reference structure.

[0034] The first grating structure 310d, second grating structure 320d and third grating structure 330d (e.g., diffraction-based overlay control structures) may be used by the interleaved lithography overlay control system 101 for interleaved lithography patterning. In particular, the first grating structure 310d, second grating structure 320d and third grating structure 330d may be designed to have a near-isolated pitch to prevent flare interaction, and a CD may match an anchor of a component sub-level. Further, OPC may be tuned for each of the first grating structure 310d, second grating structure 320d and third grating structure 330d on its own sub-level based on the source-mask optimization for that critical component.

[0035] The first grating structure 310d, second grating structure 320d and third grating structure 330d may be duplicated for each sub-level, incorporating the anchor level and placed outside the overlapping boundary area 330. The overlay metrology tool 130 may include a standard overlay metrology tool and use the first grating structure 310d, second grating structure 320d and third grating structure 330d to measure the sub-level-to-sub-level and sub-level to reference layer overlay error. Process control may be implemented by multiplexing marks and performing measurement based on the number of overlapping exposure fields as well as to the underlying reference layer, or zero layer, if the interleaved exposure is the first device exposure level.

[0036] FIG. 6 is a plan view of image-based overlay control structures 690 and critical dimension-based (CD-based) control structures 695 in a patterning layout, according to one or more embodiments. The image-based overlay control structures 690 and / or critical dimension-based (CD-based) control structures 695 may be utilized by the interleaved lithography overlay control system 101 to control overlay. The first arrows 601 may indicatean x-overlay measurement by the overlay metrology tool 130. The second arrows 602 may indicate a y-overlay measurement by the overlay metrology tool 130.

[0037] The image-based overlay control structures 690 may include the first triangles 310c and second triangles 320c. The image-based overlay control structures 690 may include flare-sensitive control structures. The image-based overlay control structures 690 may include a plurality of different designs (e.g., at least four different designs) to evaluate the impact of flare and other proximity concerns. For triangular interlacing (e.g., interlacing between the first triangles 10c and second triangles 320c), triangles incorporating the minimum and maximum CD / pitch of the sub-levels to be matched may be laid out at various spacings. Blurring of the tips may occur if the overlay drives proximity errors. Evaluation by the overlay metrology tool 130 may be image-based.

[0038] As illustrated in top right of FIG. 6, the first triangles 310c and second triangles 320c may be arranged (e.g., interleaved) in the form of a starburst. An optical microscope or scanning electron microscope (SEM) may be used to evaluate the starburst for blurring. Critical dimension (CD) and pitch may vary from the inner to the outer radius and may be chosen based on the requirements of the interleaved layers. Evaluation by the overlay metrology tool 130 may again be image-based.

[0039] As further illustrated in FIG. 6, the critical dimension-based (CD-based) control structures 695, may include, for example, first bar structures 610c (e.g., in a first mask) and second bar structures 620c (e.g., in a second mask). The first bar structures 610c and second bar structures 620c may have an interlaced arrangement. The interlaced bar structures may be used to determine the effect of flare by varying the spacing between two same CD bars in both the x-direction and the y-direction. Bulges in the lines may indicate the effect of flare and may be measured via CD SEM of the line or space. Close proximity holes / pillars may also be used to determine the effect of flare and other proximity effects by varying the x / y pitch of the contacts and measuring the ellipticity of the contacts. Proximity issues may manifest as deviations from a typical circular shape that can be assessed via isolated holes / pillars.

[0040] The image-based overlay control structures 690 and critical dimension-based (CD-based) control structures 695 may be placed in the overlapping boundary. Overlay measurement by the overlay measurement tool 130 may be image-based and / or CD-based. Process control may be implemented, for example, by establishing an initial baseline derived from the design / ground rules for overlay control. This may benchmark the impact ofproximity effects on the control and main features. Evaluating the effect of process variation on the magnitude of the proximity effect may establish the control limits.

[0041] FIG.7 is a plan view of first alignment marks 310a and second alignment marks 320a in a patterning layout, according to one or more embodiments. As illustrated in FIG. 7, the first mask 310 in the patterning layout may also include third alignment marks 310e and the second mask 320 in the patterning layout may also include fourth alignment marks 320e. The first alignment marks 310a and second alignment marks 320a may be arranged in the x- direction, and the third alignment marks 310e and fourth alignment marks 320e may be arranged in the y-direction. Each of the first alignment marks 310a, second alignment marks 320a, third alignment marks 3 lOe and fourth alignment marks 320e may be placed by the overlay control structure placement unit 106 outside the overlapping boundary area 330.

[0042] The interleaved lithography overlay control system 101 may include sub-level-to- sub-level alignment. In this case, the first alignment marks 310a, second alignment marks 320a, third alignment marks 310e and fourth alignment marks 320e may be designed according to the scanner manufacturer’s instructions to ensure they are machine readable. The first alignment marks 310a, second alignment marks 320a, third alignment marks 310e and fourth alignment marks 320e may be typically placed in the frame, and outside of the prime area. To improve alignment of litho-to-litho sub-levels in a common patterning level, the first alignment marks 310a, second alignment marks 320a, third alignment marks 310e and fourth alignment marks 320e may be placed near the overlapping boundary area 330 (e.g., stitching interface).

[0043] Measurement in this case may be conducted according to the scanner manufacture’s instructions. However, as each litho sub-level is processed, the number of alignment marks (e.g., first alignment marks 310a, second alignment marks 320a, third alignment marks 310e and fourth alignment marks 320e) used may be increased according to the number of additional alignment features patterned by the previous sub-levels. Process control may be implemented for example, by increasing the number of alignment marks used as well as utilizing alignment marks in the prime area near critical boundaries / interfaces. This may improve the overall overlay performance of litho sub-levels.

[0044] The interleaved lithography overlay control system 101 may include features that provide improvements over typical systems. In particular, the interleaved lithography overlay control system 101 may introduce interleaved overlay marks (image and / or diffraction based) in a prime area near stitching / boundary interfaces, to decrease overlay error. The interleaved lithography overlay control system 101 may include diagnostics ofstitched / overlaid / interwoven vs. isolated overlay marks. Furthermore, additional control structures at stitching / interwoven sub-levels may allow for improved overlay / alignment performance. Still further, separation of critical components to different sub-levels in interleaving lithography may allow for independent source-mask optimization.

[0045] The interleaved lithography overlay control system 101 may include steps for evaluating overlay and conducting alignment relative to a reference layer and between sublevel exposures. These steps may allow for improved process control for critical structures. The interleaved lithography overlay control system 101 may also introduce alignment marks in the prime area near stitching / boundary interfaces, to decrease overlay error. The interleaved lithography overlay control system 101 may also introduce new flare monitoring / control structures. These structures may provide a device / component read of proximity errors incurred by interleaving lithography.

[0046] The interleaved lithography overlay control system 101 of the embodiments of the present disclosure may be especially helpful for improving overlay performance in the areas of interleaving lithography and stitched reticle fields. The embodiments may be utilized by foundries to design improved control schemes and metrology steps / techniques. The embodiments may be implemented in any device requiring stitched fields or invoking interleaving lithography. The embodiments may be especially beneficial in the area of interposers or large area chip manufacturing for electronics or photonics.

[0047] The following are example embodiments.

[0048] Example 1. An interleaved lithography overlay control method comprises: exposing an underlying pattern through a first mask having first alignment marks; exposing the underlying pattern through a second mask having second alignment marks, wherein an overlapping boundary area in the underlying pattern is exposed through both the first mask and the second mask, and wherein interleaved alignment marks are formed where respective first and second alignment marks overlap; and measuring an overlay error using the interleaved alignment marks.

[0049] Example 2. The method of example 1 , wherein the overlay error is measured using the interleaved alignment marks in addition to using the first alignment marks and the second alignment marks located at least partially outside the overlapping boundary area.

[0050] Example 3. The method of examples 1 or 2, further comprising correcting the overlay error.

[0051] Example 4. The method of any of examples 1-3, wherein the first alignment marks, the second alignment marks and the interleaved alignment marks comprise crossstructures, and measuring the overlay error comprises measuring an x / y overlay error using the cross structures.

[0052] Example 5. The method of any of examples 1-4, wherein the cross structures are located both entirely within the overlapping boundary area and entirely outside the overlapping boundary area, and the step of measuring the x / y overlay error comprises measuring a vertical-to-vertical edge and a horizontal-to-horizontal edge for the cross structures.

[0053] Example 6. The method of any of examples 1 -5, wherein the overlay error is measured based on a lithography-to-lithography mark and as a lithography-to-etch mark.

[0054] Example 7. The method of any of examples 1-6, wherein the correcting the overlay error comprises correcting the overlay error in a lithographic scanner that includes an exposure unit by generating overlay error correction data and performing alignment between sub-level exposures by the exposure unit using the overlay error correction date.

[0055] Example 8. The method of any of examples 1-7, wherein the first alignment marks and the second alignment marks comprise plurality of triangles for flare verification in multiple exposures by the exposure unit.

[0056] Example 9. The method of any of examples 1-8, wherein each of the plurality of triangles is located partially outside the overlapping boundary area and partially inside the overlapping boundary area.

[0057] Example 10. The method of any of examples 1-9, wherein the first alignment marks and the second alignment marks comprise grating shaped diffraction-based overlay control structures.

[0058] Example 11. The method of any of examples 1-10, wherein the measuring the overlay error comprises measuring sub-level-to-sub-level overlay error and sub-level to reference layer overlay error using the plurality of diffraction-based overlay control structures.

[0059] Example 12. The method of any of examples 1-11, wherein the interleaved alignment marks comprise interleaved grating shaped diffraction-based overlay control structures located in the overlapping boundary area.

[0060] The preceding description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to theembodiments shown herein but is to be accorded the widest scope consistent with the following claims and the principles and novel features disclosed herein.

Claims

CLAIMS1. An interleaved lithography overlay control method, comprising: exposing an underlying pattern through a first mask having first alignment marks; exposing the underlying pattern through a second mask having second alignment marks, wherein an overlapping boundary area in the underlying pattern is exposed through both the first mask and the second mask, and wherein interleaved alignment marks are formed where respective first and second alignment marks overlap; and measuring an overlay error using the interleaved alignment marks.

2. The method of claim 1 , wherein the overlay error is measured using the interleaved alignment marks in addition to using the first alignment marks and the second alignment marks located at least partially outside the overlapping boundary area.

3. The method of claim 2, further comprising correcting the overlay error.

4. The method of claim 3, wherein the first alignment marks, the second alignment marks and the interleaved alignment marks comprise cross structures, and measuring the overlay error comprises measuring an x / y overlay error using the cross structures.

5. The method of claim 4, wherein the cross structures are located both entirely within the overlapping boundary area and entirely outside the overlapping boundary area, and the step of measuring the x / y overlay error comprises measuring a vertical-to-vertical edge and a horizontal-to-horizontal edge for the cross structures.

6. The method of claim 3, wherein the overlay error is measured based on a lithography- to-lithography mark and as a lithography-to-etch mark.

7. The method of claim 3, wherein the correcting the overlay error comprises correcting the overlay error in a lithographic scanner that includes an exposure unit by generating overlay error correction data and performing alignment between sub-level exposures by the exposure unit using the overlay error correction date.

8. The method of claim 7, wherein the first alignment marks and the second alignment marks comprise plurality of triangles for flare verification in multiple exposures by the exposure unit.

9. The method of claim 8, wherein each of the plurality of triangles is located partially outside the overlapping boundary area and partially inside the overlapping boundary area.

10. The method of claim 2, wherein the first alignment marks and the second alignment marks comprise grating shaped diffraction-based overlay control structures.

11. The method of claim 10, wherein the measuring the overlay error comprises measuring sub-level-to-sub-level overlay error and sub-level to reference layer overlay error using the plurality of diffraction-based overlay control structures.

12. The method of claim 10, wherein the interleaved alignment marks comprise interleaved grating shaped diffraction-based overlay control structures located in the overlapping boundary area.

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