Three-dimensional vertical memristor and manufacturing method therefor

Abstract

Provided in the present application are a three-dimensional vertical memristor and a manufacturing method therefor. The three-dimensional vertical memristor comprises: a substrate; alternately stacked on the substrate, insulating layers and word line layers, there being at least three insulating layers and at least two word line layers, the oxygen ion capturing capability of at least one word line layer being greater than or equal to a first preset value, and the oxygen ion capturing capability of at least one word line layer being less than the first preset value; a channel penetrating through the insulating layers and the word line layers; and, located on a side wall of the channel, a storage layer, a selection layer and a bit line layer, the selection layer being located on the side of the storage layer away from the side wall of the channel, and the bit line layer being located on the side of the selection layer away from the channel. In the present application, the word line layers having different oxygen ion capturing capabilities are provided, among which the word line layer having a strong oxygen ion capturing capability exhibits a non-volatile property, and the word line layer having a weak oxygen ion capturing capacity exhibits a dynamic property, thereby achieving a three-dimensional memristor array having different properties.

Description

A three-dimensional vertical memristor and its preparation method

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on November 28, 2023, with application number 202311605656.1 and invention name “A three-dimensional vertical memristor and its preparation method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology, and in particular to a three-dimensional vertical memristor and a preparation method thereof. Background Art

[0003] Humans can efficiently and flexibly perceive the external physical world through diverse senses, including vision, touch, hearing, smell, and taste. Neural networks in our brains aggregate and process information collected by these senses, enabling us to explore, understand, and learn. Specifically, sensory neurons in our multisensory neural networks (such as taste neurons) receive physical stimuli from the outside world and convert them into pulse signals, which are then transmitted to the cerebral cortex for further processing.

[0004] In recent years, with the development of wearable devices and the Internet of Things (IoT), the types and number of sensor nodes have increased dramatically, generating a massive amount of sensor data that requires efficient, real-time processing. However, unlike the efficient human perception systems, traditional sensor systems suffer from high energy consumption and low efficiency in data collection and processing. Consequently, a growing number of research efforts are attempting to mimic the way humans perceive the world, creating hardware-based systems that can efficiently process a variety of physical signals.

[0005] Inspired by biology, scientists have developed neuromorphic perception systems that promise to effectively process multisensory signals from the physical world. Such systems require combining sensors with artificial synapses and neurons. However, hardware capable of efficiently sensing and pulse encoding these diverse physical signals remains lacking.

[0006] Among emerging devices, memristors, with their rich ionic dynamics, are being used to mimic the functions of synapses and neurons. By combining memristors with sensors, researchers have demonstrated that such neuromorphic sensing systems can process sensory information such as touch, vision, and nociception.

[0007] However, these artificial neurons can currently only process single physical signals. For example, the Convolutional Neural Network (CNN) using non-volatile memristors (NVM) is widely used for static information recognition, such as image recognition and target detection, and can only be used to simulate the human eye. The Delay Feedback Reservoir (DFR) using dynamic memristors can process time-related information, such as speech recognition, and can only be used to simulate the human ear.

[0008] Non-volatile memristors and dynamic memristors are separate arrays, with one array possessing only non-volatile or only dynamic characteristics. To date, no research has been able to integrate these two devices into a single three-dimensional array, enabling different layers of devices to exhibit distinct characteristics.

[0009] Therefore, how to realize three-dimensional memristor arrays with different characteristics to meet the high-density, miniaturization, and multi-functional requirements of hardware systems put forward by the rapid development of the Internet of Things is a technical problem that needs to be solved in this field.

[0010] Summary of the Invention

[0011] In view of this, this Summary of the Invention section is provided to briefly introduce the concepts that will be described in detail in the Detailed Description of the Invention section below. This Summary of the Invention section is not intended to identify key features or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0012] The purpose of this application is to provide a three-dimensional vertical memristor and a preparation method thereof, which can realize a three-dimensional memristor array with different characteristics to meet the high-density, miniaturization and multi-functional requirements of the hardware system put forward by the rapid development of the Internet of Things.

[0013] To achieve the above objectives, this application has the following technical solutions:

[0014] In a first aspect, an embodiment of the present application provides a three-dimensional vertical memristor, comprising:

[0015] substrate;

[0016] Insulating layers and word line layers are alternately stacked on the substrate; the insulating layers include at least three layers; the word line layers include at least two layers; the ability of at least one word line layer to capture oxygen ions is greater than or equal to a first preset value; and the ability of at least one word line layer to capture oxygen ions is less than the first preset value;

[0017] a channel penetrating the insulating layer and the word line layer;

[0018] The storage layer, the selection layer and the bit line layer are located on the sidewall of the channel; the selection layer is located on the side of the storage layer away from the sidewall of the channel; the bit line layer is located on the side of the selection layer away from the sidewall of the channel.

[0019] In a possible implementation, the material of at least one word line layer includes TiN or Ru; the material of at least one word line layer includes W;

[0020] The ability of the TiN or Ru to capture oxygen ions is less than the first preset value;

[0021] The ability of W to capture oxygen ions is greater than or equal to the first preset value.

[0022] In one possible implementation, the material of the word line layer includes TiN, Ru, W, TaN, Mo, Ta, Al, Ir, Pd, Pt, Cu, Ti, Co, Mo, Ni, Nb or IrO2.

[0023] In a possible implementation, the material of the insulating layer includes SiN, SiO, SiON, SiO 2 , C-doped SiO 2 , P-doped SiO 2 , or F-doped SiO 2 .

[0024] In a possible implementation, the material of the storage layer includes HfO x , TaO x , HZO or ZrO x ; The material of the selection layer includes TiO2 or Al2O3; the material of the bit line layer includes TiN, W, Pt, Ru, TaN, Mo, Ta, Al, Au, Ir, Pd or Pt.

[0025] In a possible implementation, the thickness of one word line layer is [5 nm, 10 nm]; the thickness of one insulating layer is [10 nm, 200 nm]; the thickness of the storage layer is [2 nm, 15 nm]; and the thickness of the selection layer is [5 nm, 20 nm].

[0026] In a second aspect, an embodiment of the present application provides a method for preparing a three-dimensional vertical memristor, comprising:

[0027] providing a substrate;

[0028] Insulating layers and word line layers are alternately stacked on the substrate; the insulating layers include at least three layers; the word line layers include at least two layers; the ability of at least one word line layer to capture oxygen ions is greater than or equal to a first preset value; and the ability of at least one word line layer to capture oxygen ions is less than the first preset value;

[0029] Etching the insulating layer and the word line layer to form a channel penetrating the insulating layer and the word line layer;

[0030] A storage layer, a selection layer and a bit line layer are sequentially formed on the sidewalls of the channel.

[0031] In a possible implementation, the word line layer is formed by chemical plating, magnetron sputtering, chemical vapor deposition, physical vapor deposition, pulsed laser, atomic layer deposition, or electron beam evaporation.

[0032] In a possible implementation, the etching includes ion beam etching, dry etching, or wet etching.

[0033] In a possible implementation manner, the insulating layer is formed by sputtering or chemical vapor deposition.

[0034] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0035] The embodiments of the present application provide a three-dimensional vertical memristor and a method for preparing the same. The three-dimensional vertical memristor comprises: a substrate; an insulating layer and a wordline layer alternately stacked on the substrate; the insulating layer comprises at least three layers; the wordline layer comprises at least two layers; at least one wordline layer has an oxygen ion capture capability greater than or equal to a first preset value; at least one wordline layer has an oxygen ion capture capability less than a first preset value; a channel running through the insulating layer and the wordline layer; a storage layer, a selection layer, and a bitline layer located on the sidewalls of the channel; the selection layer is located on the side of the storage layer away from the sidewalls of the channel; and the bitline layer is located on the side of the selection layer away from the channel. The present application achieves a three-dimensional memristor array with different characteristics by providing wordline layers with different oxygen ion capture capabilities. The wordline layers with strong oxygen ion capture capabilities exhibit non-volatile characteristics, while the wordline layers with weak oxygen ion capture capabilities exhibit dynamic characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0037] The above and other features, advantages, and aspects of the various embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and that the originals and elements are not necessarily drawn to scale.

[0038] FIG1 shows a schematic cross-sectional view of a three-dimensional vertical memristor structure provided in an embodiment of the present application;

[0039] FIG2 shows a schematic diagram of a reserve pool calculation provided by an embodiment of the present application;

[0040] FIG3 shows a schematic diagram of a convolutional neural network provided in an embodiment of the present application;

[0041] FIG4 shows a schematic diagram of an echo state network provided in an embodiment of the present application;

[0042] FIG5 shows a line scan diagram from a first word line layer to an oxide layer of a first-layer device provided by an embodiment of the present application;

[0043] FIG6 shows a line scan diagram from the second word line layer to the oxide layer of a second layer device provided by an embodiment of the present application;

[0044] FIG7 shows a line scan diagram from the third word line layer to the oxide layer of a third-layer device provided by an embodiment of the present application;

[0045] FIG8 shows a voltage-current curve diagram of a first-layer device provided in an embodiment of the present application;

[0046] FIG9 shows a dynamic characteristic diagram of a first layer device under pulses provided by an embodiment of the present application;

[0047] FIG10 shows a voltage-current curve diagram of a second-layer device provided in an embodiment of the present application;

[0048] FIG11 shows a dynamic characteristic diagram of a second layer device under pulses provided by an embodiment of the present application;

[0049] FIG12 shows a voltage-current curve diagram of a third-layer device provided in an embodiment of the present application;

[0050] FIG13 shows a diagram showing the retention characteristics of multiple states of a second-layer device provided by an embodiment of the present application;

[0051] FIG14 shows a flow chart of a method for preparing a three-dimensional vertical memristor provided in an embodiment of the present application. DETAILED DESCRIPTION

[0052] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below with reference to the accompanying drawings.

[0053] In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0054] As described in the background technology, the applicant has found that humans can perceive the external physical world efficiently and flexibly through different senses such as vision, touch, hearing, smell and taste. The neural network in our brain collects and processes the information collected by these senses, enabling us to explore, recognize and learn. Specifically, the sensory neurons (such as taste sensory neurons) in the human multi-sensory neural network will convert the physical information into pulse signals after receiving external physical stimuli, and then transmit them to the cerebral cortex for further processing.

[0055] In recent years, with the development of wearable devices and the Internet of Things (IoT), the types and number of sensor nodes have increased dramatically, generating a massive amount of sensor data that requires efficient, real-time processing. However, unlike the efficient human perception systems, traditional sensor systems suffer from high energy consumption and low efficiency in data collection and processing. Consequently, a growing number of research efforts are attempting to mimic the way humans perceive the world, creating hardware-based systems that can efficiently process a variety of physical signals.

[0056] Inspired by biology, scientists have developed neuromorphic perception systems that promise to effectively process multisensory signals from the physical world. Such systems require combining sensors with artificial synapses and neurons. However, hardware capable of efficiently sensing and pulse encoding these diverse physical signals remains lacking.

[0057] Among emerging devices, memristors, with their rich ionic dynamics, are being used to mimic the functions of synapses and neurons. By combining memristors with sensors, researchers have demonstrated that such neuromorphic sensing systems can process sensory information such as touch, vision, and nociception.

[0058] However, these artificial neurons can currently only process single physical signals. For example, the Convolutional Neural Network (CNN) using non-volatile memristors (NVM) is widely used for static information recognition, such as image recognition and target detection, and can only be used to simulate the human eye. The Delay Feedback Reservoir (DFR) using dynamic memristors can process time-related information, such as speech recognition, and can only be used to simulate the human ear.

[0059] Non-volatile memristors and dynamic memristors are separate arrays, with one array possessing only non-volatile or only dynamic characteristics. To date, no research has been able to integrate these two devices into a single three-dimensional array, enabling different layers of devices to exhibit distinct characteristics.

[0060] Therefore, how to realize three-dimensional memristor arrays with different characteristics to meet the high-density, miniaturization, and multi-functional requirements of hardware systems put forward by the rapid development of the Internet of Things is a technical problem that needs to be solved in this field.

[0061] To solve the above technical problems, an embodiment of the present application provides a three-dimensional vertical memristor and a method for preparing the same. The three-dimensional vertical memristor comprises: a substrate; an insulating layer and a wordline layer alternately stacked on the substrate; the insulating layer comprises at least three layers; the wordline layer comprises at least two layers; at least one wordline layer has an oxygen ion capture capability greater than or equal to a first preset value; at least one wordline layer has an oxygen ion capture capability less than a first preset value; a channel running through the insulating layer and the wordline layer; a storage layer, a selection layer, and a bitline layer located on the sidewalls of the channel; the selection layer is located on the side of the storage layer away from the sidewall of the channel; and the bitline layer is located on the side of the selection layer away from the channel. The present application achieves a three-dimensional memristor array with different characteristics by providing wordline layers with different oxygen ion capture capabilities, whereby wordline layers with strong oxygen ion capture capabilities exhibit non-volatile characteristics, and wordline layers with weak oxygen ion capture capabilities exhibit dynamic characteristics.

[0062] Exemplary devices

[0063] 1 , which is a schematic cross-sectional view of a three-dimensional vertical memristor structure provided in an embodiment of the present application, includes:

[0064] A substrate 1; insulating layers 2 and word line layers 3 (WL) alternately stacked on the substrate 1; the insulating layers 2 include at least three layers; the word line layers 3 include at least two layers; that is, each word line layer 3 is provided with insulating layers 2 on both sides; at least one word line layer 3 has an oxygen ion capture capability greater than or equal to a first preset value; and at least one word line layer 3 has an oxygen ion capture capability less than the first preset value.

[0065] A channel 4 passes through the insulating layer 2 and the word line layer 3; a storage layer 5, a selection layer 6 and a bit line layer 7 (BL) are located on the sidewalls of the channel 4; the selection layer 6 is located on the side of the storage layer 5 away from the sidewall of the channel 4; and the bit line layer 7 is located on the side of the selection layer 6 away from the sidewall of the channel 4.

[0066] Specifically, the substrate 1 provided in the embodiment of the present application may include a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon on Insulator), or a GOI (Germanium on Insulator). In other embodiments, the semiconductor substrate may also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, or may be a stacked structure such as Si / SiGe, or may be another epitaxial structure such as SGOI (Silicon Germanium on Insulator). In this embodiment, the substrate 1 is a bulk silicon substrate.

[0067] Optionally, the material of the insulating layer 2 provided in the embodiment of the present application may include SiN, SiO, SiON, SiO2, C-doped SiO2, P-doped SiO2, or F-doped SiO2. Optionally, the material of the word line layer 3 provided in the embodiment of the present application may include TiN, Ru, W, TaN, Mo, Ta, Al, Ir, Pd, Pt, Cu, Ti, Co, Mo, Ni, Nb, or IrO2.

[0068] In the embodiment of the present application, because the ability of at least one wordline layer 3 to capture oxygen ions is greater than or equal to a first preset value, the oxygen ions can be better captured, resulting in the device in this layer exhibiting non-volatile characteristics. At the same time, because the ability of at least one wordline layer 3 to capture oxygen ions is less than the first preset value, the oxygen ions spontaneously diffuse and relax, resulting in the device in this layer exhibiting volatile characteristics, i.e., dynamic characteristics.

[0069] It should be noted that the embodiment of the present application does not specifically limit the size of the first preset value, and it can be set by those skilled in the art according to actual conditions.

[0070] Therefore, the embodiments of the present application can use layer devices exhibiting dynamic characteristics to simulate the cell bodies of neurons, imitate the firing behavior of neurons, and construct neuromorphic computing systems based on dynamic memristors, such as spiking neural networks (SNNs) and reservoir computing systems (RCs) (not limited to SNNs and RCs), for processing speech signals, making time series predictions, etc. See Figure 2, which is a schematic diagram of a reservoir computing provided by an embodiment of the present application, in which reservoir computing is performed through input and output.

[0071] At the same time, the embodiments of the present application can use layer devices that exhibit non-volatile properties to construct neuromorphic computing networks such as convolutional neural networks (CNN), recurrent neural networks (RNN), and echo state networks (ESN) based on non-volatile memristors (which should not be limited to CNN, RNN, and ESN) for processing static information, such as image recognition. See Figure 3, which is a schematic diagram of a convolutional neural network provided in an embodiment of the present application. See Figure 4, which is a schematic diagram of an echo state network provided in an embodiment of the present application, including an input layer (Input Layer), a dynamic memory reservoir (Dynamic Reservoir), and an output layer (Output Layer). The input layer can input fixed weights and output trained weights (Trained weights) to the output layer.

[0072] Optionally, the material of the storage layer 5 provided in the embodiment of the present application may include HfO x , TaO x , HZO or ZrO x ; The material of the selection layer 6 may include TiO2 or Al2O3; the material of the bit line layer 7 may include TiN, W, Pt, Ru, TaN, Mo, Ta, Al, Au, Ir, Pd or Pt.

[0073] In the embodiment of the present application, the height of the Schottky barrier can be adjusted by controlling the ion concentration of the storage layer 5 , the selection layer 6 can be used to suppress interlayer leakage, and the bit line layer 7 serves as a conductive connection for the device.

[0074] Optionally, the thickness of a word line layer 3 provided in an embodiment of the present application may be [5nm, 10nm]; the thickness of a insulating layer 2 may be [10nm, 200nm]; the thickness of the storage layer 5 may be [2nm, 15nm]; and the thickness of the selection layer 6 may be [5nm, 20nm].

[0075] In one possible implementation, as shown in FIG1 , the material of at least one word line layer 3 in the embodiment of the present application may include TiN or Ru; the material of at least one word line layer 3 includes W; the ability of TiN or Ru to capture oxygen ions is less than a first preset value; and the ability of W to capture oxygen ions is greater than or equal to the first preset value.

[0076] Specifically, as shown in FIG. 1 , the word line layer 3 may include a first word line layer 31 , a second word line layer 32 and a third word line layer 33 . The material of the first word line layer 31 may be TiN, the material of the second word line layer 32 may be Ru, and the material of the third word line layer 33 may be W.

[0077] The electron affinity of an element reflects how easily its atoms acquire electrons. The greater the electron affinity, the more difficult it is to acquire electrons. The electron affinity of Ti is 8.4 kJ / mol, that of W is 79 kJ / mol, and that of Ru is 101 kJ / mol.

[0078] The work function refers to the minimum energy required to move an electron from the inside of a solid to the surface of the object. The work function of material Ti is 4.33eV, the work function of material W is 4.55eV, and the work function of material Ru is 4.71eV.

[0079] Ti has the smallest electron affinity and the lowest work function, so it oxidizes naturally in the air at room temperature. The first layer device with TiN as the material of the first word line layer 31 forms the thickest oxide layer (TiN). x O y N z :7.4nm), followed by an oxide layer (WO 3) formed by the third layer device with W as the material of the third word line layer 33. x : 5.2nm), the thinnest is the oxide layer (RuO x :1nm).

[0080] See Figure 5, which is a schematic line scan diagram of the connection from the first word line layer 31 to the oxide layer of a first-tier device according to an embodiment of the present application. See Figure 6, which is a schematic line scan diagram of the connection from the second word line layer 32 to the oxide layer of a second-tier device according to an embodiment of the present application. See Figure 7, which is a schematic line scan diagram of the connection from the third word line layer 33 to the oxide layer of a third-tier device according to an embodiment of the present application.

[0081] Figures 5-7 provide the Energy Dispersive Spectrometer line (EDS line), where the horizontal axis represents position and the vertical axis represents intensity. x In comparison, it can be seen that 7.4nm TiON oxygen-rich (O-rich TiON) exhibits volatile characteristics, and 1nm RuO x Ultra-thin RuOx exhibits volatile properties, 5.2nm WO x Oxygen deficiency exhibits non-volatile properties.

[0082] Specifically, Ti with sufficient oxygen content x O y N z (1st layer) and too thin RuO x (Layer 2) can only introduce shallow defects, so after the voltage is removed, the oxygen ions spontaneously diffuse and relax, so the devices in Layer 1 and Layer 2 show volatile characteristics; while the WO in the oxygen-deficient state x It can better capture oxygen ions and exhibit non-volatile properties.

[0083] See Figure 8, which is a voltage-current curve diagram of a first-layer device provided in an embodiment of the present application. See Figure 9, which is a dynamic characteristic diagram of a first-layer device under pulses provided in an embodiment of the present application.

[0084] As shown in FIG8 , the horizontal axis is voltage (Voltage (V)), the vertical axis is (Current (A)), and the device of the first layer is continuously applied with three positive voltage scans (1 st sweep, 2 nd sweep and 3 rd In the case of pulses, the device exhibits a "memory loss" as shown in Figure 8; the gradual change of the conductance state can be more intuitively observed.

[0085] As shown in Figure 9, the horizontal axis is time (Time (us)) and the vertical axis is (Read Current (nA)). When a 2V pulse is applied, the conductivity of the device gradually increases. After the 2V programming voltage is removed, the conductivity of the device cannot be maintained at a read voltage of 0.5V and gradually decreases to the initial state. This is because the Ti in the first layer device x O y N z The conductivity is in an "oxygen-rich" state and has a weaker ability to capture oxygen ions. This gradual change in conductivity can be described by the formula Fitting, where That is, the characteristic time constant of the relaxation characteristics of the first layer device is 1.66us.

[0086] Similarly, see Figure 10, which is a voltage-current curve diagram of a second-layer device provided in an embodiment of the present application. See Figure 11, which is a dynamic characteristic diagram of a second-layer device under pulses provided in an embodiment of the present application.

[0087] The device of the second layer was subjected to three consecutive positive voltage sweeps. As shown in FIG10 , the device showed a more obvious “memory loss” compared with the first layer device 9. This is because the oxide layer RuO x (1nm) than the first layer Tix O y N z Because the second-layer device is thinner (7.4 nm), oxygen ions diffuse more easily, so the time constant of the relaxation characteristics of the second-layer device (0.93 μs) is smaller than that of the first-layer device, as shown in FIG11 .

[0088] See Figure 12, which is a voltage-current curve diagram of a third-layer device according to an embodiment of the present application. See Figure 13, which is a retention characteristic diagram of multiple states of a second-layer device according to an embodiment of the present application.

[0089] The voltage-current curve of the third layer device under DC sweep is shown in Figure 12. x The device is in an "oxygen-deficient" state and has a strong ability to capture oxygen ions, so the third-layer device exhibits non-volatile characteristics, has multiple states, and has good retention characteristics, as shown in Figure 13.

[0090] Therefore, the different properties (volatile or non-volatile) exhibited by each layer are related to the electron affinity and work function of each wordline layer material, as well as the thickness of the oxide layer formed by natural oxidation and the oxygen content therein. In addition, the operating voltage of the devices in each layer also varies. Therefore, the above factors should be comprehensively considered and the appropriate wordline material should be selected according to the actual application requirements. The embodiments of this application are not specifically limited here, and the specific material selection can be selected by those skilled in the art based on actual conditions.

[0091] An embodiment of the present application provides a three-dimensional vertical memristor, comprising: a substrate; insulating layers and wordline layers alternately stacked on the substrate; the insulating layers comprising at least three layers; the wordline layers comprising at least two layers; at least one wordline layer having an oxygen ion capture capability greater than or equal to a first preset value; at least one wordline layer having an oxygen ion capture capability less than a first preset value; a channel running through the insulating layers and the wordline layers; a storage layer, a selection layer, and a bitline layer located on the sidewalls of the channel; the selection layer being located on the side of the storage layer away from the sidewalls of the channel; and the bitline layer being located on the side of the selection layer away from the channel. The present application implements a three-dimensional memristor array with different oxygen ion capture capabilities by providing wordline layers with different oxygen ion capture capabilities, whereby wordline layers with strong oxygen ion capture capabilities exhibit non-volatile characteristics, and wordline layers with weak oxygen ion capture capabilities exhibit dynamic characteristics.

[0092] Exemplary Methods

[0093] FIG14 is a flow chart of a method for preparing a three-dimensional vertical memristor according to an embodiment of the present application, comprising:

[0094] S101: providing a substrate.

[0095] S102: Alternating insulating layers and word line layers are formed on the substrate; the insulating layers include at least three layers; the word line layers include at least two layers; the ability of at least one word line layer to capture oxygen ions is greater than or equal to a first preset value; the ability of at least one word line layer to capture oxygen ions is less than the first preset value.

[0096] S103: etching the insulating layer and the word line layer to form a channel penetrating the insulating layer and the word line layer.

[0097] S104: forming a storage layer, a selection layer and a bit line layer in sequence on the sidewalls of the channel.

[0098] In a possible implementation, the word line layer is formed by chemical plating, magnetron sputtering, chemical vapor deposition, physical vapor deposition, pulsed laser, atomic layer deposition, or electron beam evaporation.

[0099] In a possible implementation, the etching includes ion beam etching, dry etching, or wet etching.

[0100] Specifically, taking SiO2 as an insulating layer as an example, the embodiment of the present application can use positive photoresist, negative photoresist or metal as a mask, and use ion beam etching, dry etching or wet etching to etch to the bottom SiO2 layer in one step, wherein in this embodiment:

[0101] The insulating layer SiO2 (30nm) was dry-etched under the following conditions: 20sccm of octafluoropropane, 2sccm of sulfur hexafluoride, 50W / 500W power, and 9s. The metal W (20nm) was dry-etched under the following conditions: 10sccm of argon, 10sccm of sulfur hexafluoride, 20W / 300W power, and 15s. The metal Ru (20nm) was etched using ion beam etching with an etching time of 1min30s and an ion energy of 500eV. The TiN (20nm) was dry-etched under the following conditions: 20sccm of octafluoropropane, 2sccm of sulfur hexafluoride, 50W / 500W power, and 12s. The SiO2 layer at the bottom was etched to form a groove for separating the planar electrodes.

[0102] In one possible implementation, the insulating layer is formed by sputtering or chemical vapor deposition. In one possible implementation, various storage layers are grown using methods such as atomic layer deposition, magnetron sputtering, or ion beam sputtering. In one possible implementation, a self-aligned selective layer is grown using methods such as atomic layer deposition of metal or oxygen plasma. In one possible implementation, the deposited bitline layer can be prepared using any of electron beam evaporation, magnetron sputtering, ion beam sputtering, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, and electroplating.

[0103] The embodiment of the present application provides a method for preparing a three-dimensional vertical memristor. The three-dimensional vertical memristor formed by this method includes: a substrate; an insulating layer and a wordline layer alternately stacked on the substrate; the insulating layer includes at least three layers; the wordline layer includes at least two layers; the ability of at least one wordline layer to capture oxygen ions is greater than or equal to a first preset value; the ability of at least one wordline layer to capture oxygen ions is less than the first preset value; a channel running through the insulating layer and the wordline layer; a storage layer, a selection layer, and a bitline layer located on the sidewalls of the channel; the selection layer is located on the side of the storage layer away from the sidewall of the channel; and the bitline layer is located on the side of the selection layer away from the channel. The present application realizes a three-dimensional memristor array with different characteristics by providing wordline layers with different oxygen ion capture abilities. The wordline layers with strong oxygen ion capture abilities exhibit non-volatile characteristics, while the wordline layers with weak oxygen ion capture abilities exhibit dynamic characteristics.

[0104] The various embodiments in this specification are described in a progressive manner. Similar portions between the various embodiments can be referenced to each other. Each embodiment focuses on the differences from the other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the device embodiments. For relevant portions, refer to the description of the method embodiments.

[0105] The above is only a preferred embodiment of the present application. Although the present application has been disclosed as a preferred embodiment, it is not intended to limit the present application. Any technician familiar with the art can use the above-disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present application without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of protection of the technical solution of the present application.

Claims

1. A three-dimensional vertical memristor, characterized in that, comprising: a substrate; an insulating layer and a word line layer alternately stacked on the substrate; the insulating layer includes at least three layers; the word line layer includes at least two layers; the oxygen ion capturing ability of at least one layer of the word line layer is greater than or equal to a first preset value; the oxygen ion capturing ability of at least one layer of the word line layer is less than the first preset value; a channel penetrating the insulating layer and the word line layer; a storage layer, a selection layer and a bit line layer located on the side wall of the channel; the selection layer is located on one side of the side wall of the storage layer away from the channel; the bit line layer is located on one side of the side wall of the selection layer away from the channel.

2. The three-dimensional vertical memristor according to claim 1, characterized in that, the material of at least one layer of the word line layer includes TiN or Ru; the material of at least one layer of the word line layer includes W; the oxygen ion capturing ability of the TiN or the Ru is less than the first preset value; the oxygen ion capturing ability of the W is greater than or equal to the first preset value.

3. The three-dimensional vertical memristor according to claim 1, characterized in that, The materials of the word line layer include TiN, Ru, W, TaN, Mo, Ta, Al, Ir, Pd, Pt, Cu, Ti, Co, Mo, Ni, Nb or IrO 2 .

4. The three-dimensional vertical memristor according to claim 1, characterized in that, The materials of the insulating layer include SiN, SiO, SiON, SiO 2 , C-doped SiO 2 , P-doped SiO 2 or F-doped SiO 2 .

5. The three-dimensional vertical memristor according to claim 1, characterized in that, The materials of the storage layer include HfO x , TaO x , HZO or ZrO x ; The materials of the selection layer include TiO 2 or Al 2 O 3 ; The materials of the bit line layer include TiN, W, Pt, Ru, TaN, Mo, Ta, Al, Au, Ir, Pd or Pt.

6. The three-dimensional vertical memristor according to claim 1, characterized in that, the thickness of one layer of the word line layer is [5 nm, 10 nm]; the thickness of one layer of the insulating layer is [10 nm, 200 nm]; the thickness of the storage layer is [2 nm, 15 nm]; the thickness of the selection layer is [5 nm, 20 nm].

7. A preparation method of a three-dimensional vertical memristor, characterized in that, comprising: providing a substrate; forming an insulating layer and a word line layer alternately stacked on the substrate; the insulating layer includes at least three layers; the word line layer includes at least two layers; the oxygen ion capturing ability of at least one layer of the word line layer is greater than or equal to a first preset value; the oxygen ion capturing ability of at least one layer of the word line layer is less than the first preset value; etching the insulating layer and the word line layer to form a channel penetrating the insulating layer and the word line layer; forming a storage layer, a selection layer and a bit line layer in sequence on the side wall of the channel.

8. The preparation method according to claim 7, characterized in that, the word line layer is formed by a method of electroless plating, magnetron sputtering, chemical vapor deposition, physical vapor deposition, pulsed laser, atomic layer deposition or electron beam evaporation.

9. The preparation method according to claim 7, characterized in that, the etching includes ion beam etching, dry etching or wet etching.

10. The preparation method according to claim 7, characterized in that, the insulating layer is formed by sputtering or chemical vapor deposition.

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