Pixel circuit and driving method therefor, and display apparatus

Abstract

A pixel circuit and a driving method therefor, and a display apparatus. In a pixel circuit (10), a driving circuit (100) controls the magnitude of a driving current, which flows through a first end (100a) and a second end (100b); a first end (200a) of a data writing circuit (200) is electrically connected to the second end (100b) of the driving circuit (100), a second end (200b) of the data writing circuit (200) receives a data signal (Vdata), and the data writing circuit (200) writes, in response to a data scanning signal (G1), the data signal (Vdata) into the second end (100b) of the driving circuit (100) at a data writing stage; a control end (800m) of a first compensation circuit (800) is configured to receive a first compensation control signal (G4), a first end (800a) of the first compensation circuit (800) is electrically connected to the first end (100a) of the driving circuit (100), a second end (800b) of the first compensation circuit (800) is electrically connected to a control end (100m) of the driving circuit (100), and the first compensation circuit (800) is configured to control, in response to the first compensation control signal (G4), the control end (100m) of the driving circuit (100) and the first end (100a) of the driving circuit (100) to be connected or not to be connected by means of the first compensation circuit (800); and a second compensation circuit (900) comprises a compensation capacitor (C1), wherein a first electrode plate of the compensation capacitor (C1) is electrically connected to the control end (100m) of the driving circuit (100).

Description

Pixel circuit, driving method thereof, and display device Technical Field

[0001] At least one embodiment of the present disclosure relates to a pixel circuit, a driving method thereof, and a display device. Background Art

[0002] With the continuous development of display technology, pixel circuits using low-temperature polycrystalline silicon-oxide (LTPO) are increasingly being used in display devices. LTPO-based pixel circuits offer high refresh rates, low leakage current, and uniform brightness across the display panel. Furthermore, internal compensation circuits are widely used due to their low requirements for driver integrated circuits (ICs), low cost, and simple control algorithms.

[0003] Summary of the Invention

[0004] At least one embodiment of the present disclosure provides a pixel circuit, comprising: a driving circuit, a data writing circuit, a first compensation circuit, and a second compensation circuit. The driving circuit comprises a control terminal, a first terminal, and a second terminal, and is configured to control the magnitude of a driving current flowing through the first terminal and the second terminal; the first terminal of the data writing circuit is electrically connected to the second terminal of the driving circuit, the second terminal of the data writing circuit is configured to receive a data signal, and the data writing circuit is configured to write the data signal to the second terminal of the driving circuit in response to a data scanning signal during a data writing phase; the first compensation circuit comprises a control terminal, a first terminal, and a second terminal, the control terminal of the first compensation circuit is configured to receive a first compensation control signal, the first terminal of the first compensation circuit is electrically connected to the first terminal of the driving circuit, the second terminal of the first compensation circuit is electrically connected to the control terminal of the driving circuit, and the first compensation circuit is configured to control whether the control terminal of the driving circuit and the first terminal of the driving circuit are connected via the first compensation circuit in response to the first compensation control signal; the second compensation circuit comprises a compensation capacitor, the first plate of the compensation capacitor is electrically connected to the control terminal of the driving circuit.

[0005] For example, in the pixel circuit provided by at least one embodiment of the present disclosure, the first compensation circuit and the second compensation circuit are configured to allow the potential of the control end of the driving circuit to change in response to the change of the potential of the second end of the driving circuit during the data writing phase, and are configured to maintain the potential of the control end of the driving circuit in the compensation phase after the data writing phase, and not allow the potential of the control end of the driving circuit to change in response to the change of the potential of the second end of the driving circuit.

[0006] For example, in the pixel circuit provided by at least one embodiment of the present disclosure, the driving circuit includes a driving transistor, the gate of the driving transistor serves as the control end of the driving circuit, the first electrode of the driving transistor serves as the first end of the driving circuit, the second electrode of the driving transistor serves as the second end of the driving circuit, and the first end of the driving circuit is electrically connected to the first power supply voltage end to receive the first power supply voltage; the pixel circuit also includes a light-emitting element, the light-emitting element is configured to emit light under the drive of the driving current, the second end of the driving circuit is electrically connected to the first electrode of the light-emitting element, and the driving circuit is configured to control the magnitude of the driving current flowing through the light-emitting element; the first compensation circuit includes a first compensation transistor, the gate of the first compensation transistor receives the first compensation control signal, the first electrode of the first compensation transistor is electrically connected to the first electrode of the driving transistor, and the second electrode of the first compensation transistor is electrically connected to the gate of the driving transistor.

[0007] For example, in the pixel circuit provided by at least one embodiment of the present disclosure, the second compensation circuit also includes a second compensation transistor, the gate of the second compensation transistor receives a second compensation control signal, the first electrode of the second compensation transistor is electrically connected to the gate of the driving transistor, the second electrode of the second compensation transistor is electrically connected to the first plate of the compensation capacitor so that the first plate of the compensation capacitor is electrically connected to the gate of the driving transistor through the second compensation transistor, and the second plate of the compensation capacitor is electrically connected to the second electrode of the driving transistor.

[0008] For example, in the pixel circuit provided by at least one embodiment of the present disclosure, the first plate of the compensation capacitor is electrically connected to the gate of the driving transistor, and the second plate of the compensation capacitor is electrically connected to the first electrode of the light-emitting element.

[0009] For example, in the pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit also includes a first reset circuit, the control end of the first reset circuit is configured to receive a first reset control signal, the first end of the first reset circuit is electrically connected to the second end of the driving circuit, the second end of the first reset circuit is electrically connected to the first reset signal end to receive the first reset signal, and the first reset circuit is configured to write the first reset signal to the second end of the driving circuit in response to the first reset control signal.

[0010] For example, in the pixel circuit provided by at least one embodiment of the present disclosure, the first reset circuit includes a first reset transistor, the gate of the first reset transistor is electrically connected to the first reset control terminal to receive the first reset control signal, the first electrode of the first reset transistor is electrically connected to the second terminal of the driving circuit, and the second electrode of the first reset transistor is electrically connected to the first reset signal terminal to receive the first reset signal; the data write circuit includes a data write transistor, the gate of the data write transistor is configured to receive the data scan signal, the first electrode of the data write transistor is electrically connected to the second terminal of the driving circuit, and the second electrode of the data write transistor is electrically connected to the data signal terminal to receive the data signal; the data write transistor and the first reset transistor are different transistors independent of each other, and the data signal terminal and the first reset signal terminal are different signal terminals independent of each other; or, the data write transistor is reused as the first reset transistor, the data scan signal is reused as the first reset control signal, and the data signal terminal is reused as the first reset signal terminal, and is configured to receive the data signal and the first reset signal respectively in different time periods.

[0011] For example, in the pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit also includes an auxiliary capacitor, the first plate of the auxiliary capacitor is electrically connected to the second end of the driving circuit, and the second plate of the auxiliary capacitor is electrically connected to the first reset voltage end.

[0012] For example, in the pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit also includes a light-emitting element, which is configured to emit light under the drive of the driving current, and the second end of the driving circuit is electrically connected to the first electrode of the light-emitting element, and the driving circuit is configured to control the magnitude of the driving current flowing through the light-emitting element; the pixel circuit also includes a second reset circuit, the control end of the second reset circuit is configured to receive a second reset control signal, the first end of the second reset circuit is electrically connected to the first electrode of the light-emitting element, the second end of the second reset circuit is electrically connected to the second reset signal end to receive a second reset signal, and the second reset circuit is configured to apply the second reset signal to the first electrode of the light-emitting element and / or the second plate of the compensation capacitor in response to the second reset control signal.

[0013] For example, in the pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit also includes a second reset circuit, the control end of the second reset circuit is configured to receive a second reset control signal, the first end of the second reset circuit is electrically connected to the second end of the driving circuit, the second end of the second reset circuit is electrically connected to the second reset signal end to receive the second reset signal, and the second reset circuit is configured to apply the second reset signal to the second end of the driving circuit and / or the second plate of the compensation capacitor in response to the second reset control signal.

[0014] For example, in a pixel circuit provided by at least one embodiment of the present disclosure, the first reset circuit includes a first reset transistor, the gate of the first reset transistor is electrically connected to the first reset control terminal to receive the first reset control signal, the first electrode of the first reset transistor is electrically connected to the second terminal of the drive circuit, and the second electrode of the first reset transistor is electrically connected to the first reset signal terminal to receive the first reset signal; the second reset circuit includes a second reset transistor, the gate of the second reset transistor is electrically connected to the second reset control terminal to receive the second reset control signal, the first electrode of the second reset transistor is electrically connected to the second terminal of the drive circuit, and the second electrode of the second reset transistor is electrically connected to the second reset signal terminal to receive the second reset signal; the first reset transistor is multiplexed as the second reset transistor, the first reset control signal is multiplexed as the second reset control signal, and the first reset signal terminal is multiplexed as the second reset signal terminal, and is configured to receive the first reset signal and the second reset signal, respectively, in different time periods; or, the second reset transistor and the first reset transistor are different transistors independent of each other, and the first reset signal terminal and the second reset signal terminal are different signal terminals independent of each other.

[0015] For example, in the pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit also includes a third reset circuit, the control end of the third reset circuit is configured to receive a third reset control signal, the first end of the third reset circuit is electrically connected to the first end of the driving circuit, the second end of the third reset circuit is electrically connected to the third reset signal end to receive the third reset signal, and the third reset circuit is configured to apply the third reset signal to the first end of the driving circuit in response to the third reset control signal.

[0016] For example, in the pixel circuit provided by at least one embodiment of the present disclosure, the third reset circuit includes a third reset transistor, the gate of the third reset transistor is configured to receive a third reset control signal, the first electrode of the third reset transistor is electrically connected to the first electrode of the first compensation transistor and the first end of the driving circuit, and the first electrode of the third reset transistor is electrically connected to the third reset signal end to receive the third reset signal.

[0017] For example, in the pixel circuit provided by at least one embodiment of the present disclosure, the first compensation circuit includes a first compensation transistor, the first electrode of the first compensation transistor is electrically connected to the first end of the driving circuit, and the second electrode of the first compensation transistor is electrically connected to the driving end of the driving circuit; the second reset circuit includes a second reset transistor, the gate of the second reset transistor is electrically connected to the second reset control end to receive the second reset control signal, the first electrode of the second reset transistor is electrically connected to the second end of the driving circuit, and the second electrode of the second reset transistor is electrically connected to the second reset signal end to receive the second reset signal; the gate of the first compensation transistor and the gate of the second reset transistor are connected to the same gate line, and the second reset control signal and the first compensation control signal are the same gate scan signal.

[0018] For example, in the pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit also includes a first light-emitting control circuit and a second light-emitting control circuit; the control end of the first light-emitting control circuit is configured to receive a first light-emitting control signal, the first end of the first light-emitting control circuit is electrically connected to the first end of the driving circuit, the second end of the first light-emitting control circuit is electrically connected to the first voltage end to receive a first power supply voltage, and the first light-emitting control circuit is configured to apply the first power supply voltage to the first end of the driving circuit in response to the first light-emitting control signal; the control end of the second light-emitting control circuit is configured to receive a second light-emitting control signal, the second light-emitting control signal is different from the first light-emitting control signal, the first end of the second light-emitting control circuit is electrically connected to the second end of the driving circuit, the second end of the second light-emitting control circuit is electrically connected to the first electrode of the light-emitting element, the second electrode of the light-emitting element is electrically connected to the second voltage end to receive the second power supply voltage, and the second light-emitting control circuit is configured to apply the driving current to the light-emitting element in response to the second light-emitting control signal.

[0019] At least one embodiment of the present disclosure further provides a display device, which includes any pixel circuit provided by the embodiments of the present disclosure.

[0020] At least one embodiment of the present disclosure provides a driving method for a pixel circuit, which is applicable to any pixel circuit provided by the embodiments of the present disclosure, and the driving method includes: in a data writing stage, setting the data scanning signal to a turn-on signal to turn on the data writing circuit, and writing the data signal to the second end of the driving circuit through the data writing circuit, and controlling the first compensation circuit and the second compensation circuit so that the potential of the control end of the driving circuit changes in response to the change of the potential of the second end of the driving circuit; and in a compensation stage after the data writing stage, controlling the first compensation circuit and the second compensation circuit to maintain the potential of the control end of the driving circuit, and not allowing the potential of the control end of the driving circuit to change in response to the change of the potential of the second end of the driving circuit.

[0021] For example, in the driving method of the pixel circuit provided by at least one embodiment of the present disclosure, in the data writing stage, the first compensation control signal is set to an on signal so that the first compensation circuit is turned on in response to the first compensation control signal, and the control end of the driving circuit and the first end of the driving circuit are turned on via the first compensation circuit, and the first end and the second end of the driving circuit are turned on to generate a compensation current between the control end of the driving circuit and the second end of the driving circuit, and the compensation current flows through the first compensation circuit and the driving circuit, so that the potential of the control end of the driving circuit changes in response to the change of the potential of the second end of the driving circuit; in the compensation stage, at least the first compensation control signal is set to an off signal to turn off the first compensation circuit, so that no current is allowed to be generated between the control end of the driving circuit and the second end of the driving circuit, the potential of the control end of the driving circuit is kept unchanged, and the potential of the control end of the driving circuit is not allowed to change in response to the change of the potential of the second end of the driving circuit.

[0022] For example, in a driving method for a pixel circuit provided in at least one embodiment of the present disclosure, the driving circuit includes a driving transistor, the gate of the driving transistor serves as a control terminal of the driving circuit, the first electrode of the driving transistor serves as a first terminal of the driving circuit, and the second electrode of the driving transistor serves as a second terminal of the driving circuit; the first compensation circuit includes a first compensation transistor, the gate of the first compensation transistor receives the first compensation control signal, the first electrode of the first compensation transistor is electrically connected to the first electrode of the driving transistor, and the second electrode of the first compensation transistor is electrically connected to the gate of the driving transistor; the second compensation circuit also includes a second compensation transistor, the gate of the second compensation transistor receives the second compensation control signal, the first electrode of the second compensation transistor is electrically connected to the gate of the driving transistor, and the second electrode of the second compensation transistor is electrically connected to the first plate of the compensation capacitor so that the first plate of the compensation capacitor is electrically connected to the gate of the driving transistor through the second compensation transistor, and the second plate of the compensation capacitor is electrically connected to the second electrode of the driving transistor; the pixel circuit also includes a light-emitting element, the light-emitting element is configured to emit light under the drive current, wherein the second terminal of the driving circuit is electrically connected to the first electrode of the light-emitting element, and the driving circuit is configured to control the magnitude of the driving current flowing through the light-emitting element. The driving method of the pixel circuit includes: in the data writing stage, setting the first compensation control signal and the second compensation control signal to both be turn-on signals, so that the first compensation transistor and the second compensation transistor are both turned on to generate the compensation current; and in the compensation stage, setting the first compensation transistor and the second compensation transistor to both be turned off to keep the potential of the control end of the driving circuit unchanged.

[0023] For example, in the driving method of the pixel circuit provided by at least one embodiment of the present disclosure, the control method of the pixel circuit further includes: in the initial stage, setting the second compensation control signal to a turn-on signal to turn on the second compensation transistor.

[0024] For example, in the driving method of the pixel circuit provided by at least one embodiment of the present disclosure, the driving circuit includes a driving transistor, the gate of the driving transistor serves as the control end of the driving circuit, the first electrode of the driving transistor serves as the first end of the driving circuit, and the second electrode of the driving transistor serves as the second end of the driving circuit; the first compensation circuit includes a first compensation transistor, the gate of the first compensation transistor receives the first compensation control signal, the first electrode of the first compensation transistor is electrically connected to the first electrode of the driving transistor, and the second electrode of the first compensation transistor is electrically connected to the gate of the driving transistor; the pixel circuit also includes a light-emitting element, which is configured to emit light under the drive current, wherein the second end of the driving circuit is electrically connected to the first electrode of the light-emitting element, and the driving circuit is configured to control the magnitude of the driving current flowing through the light-emitting element; the first plate of the compensation capacitor is electrically connected to the gate of the driving transistor, and the second plate of the compensation capacitor is electrically connected to the first electrode of the light-emitting element. The driving method includes: in the data writing stage, setting the first compensation control signal to an on signal to turn on the first compensation transistor to generate the compensation current; in the compensation stage, setting the first compensation control signal to an off signal to turn off the first compensation transistor to keep the potential of the control end of the driving circuit unchanged.

[0025] For example, in the driving method of the pixel circuit provided by at least one embodiment of the present disclosure, in the data writing stage, the potential of the control end of the driving circuit changes in response to the change of the potential of the second end of the driving circuit until the driving transistor is turned off, and at the end of the data writing stage, the potential VG of the control end of the driving circuit satisfies VG=Vdata+Vth.

[0026] For example, in the driving method of the pixel circuit provided by at least one embodiment of the present disclosure, the first end of the driving circuit is connected to the first power supply voltage end to receive the first power supply voltage; the driving method also includes: in the initial stage before the data writing stage, the first compensation control signal is set to be a turn-on signal to turn on the first compensation circuit, and the first power supply voltage is applied to the driving end of the driving circuit in sequence through the first end of the driving circuit and the first compensation circuit to turn on one end and the second end of the driving circuit.

[0027] For example, in a driving method for a pixel circuit provided in at least one embodiment of the present disclosure, the pixel circuit further comprises a first reset circuit, a control terminal of the first reset circuit being configured to receive a first reset control signal, a first terminal of the first reset circuit being electrically connected to a second terminal of the driving circuit, a second terminal of the first reset circuit being electrically connected to a first reset signal terminal to receive a first reset signal, and the first reset circuit being configured to write the first reset signal to the second terminal of the driving circuit in response to the first reset control signal; the pixel circuit further comprises a second reset circuit, a control terminal of the second reset circuit being configured to receive a second reset control signal, a first terminal of the second reset circuit being electrically connected to a first electrode of the light-emitting element, a second terminal of the second reset circuit being electrically connected to a second reset signal terminal to receive a second reset signal, and the second reset circuit being configured to apply the second reset signal to the first electrode of the light-emitting element and the second plate of the compensation capacitor in response to the second reset control signal. The driving method comprises: in an initial stage, setting the first reset control signal, the second reset control signal, and the first compensation control signal to all be on signals, so that the first reset circuit is turned on to apply the first reset signal to the second terminal of the driving circuit, and the second reset circuit is turned on to apply the second reset signal to the first electrode of the light-emitting element.

[0028] For example, in the driving method of the pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit also includes a first light-emitting control circuit and a second light-emitting control circuit; the control end of the first light-emitting control circuit is configured to receive a first light-emitting control signal, the first end of the first light-emitting control circuit is electrically connected to the first end of the driving circuit, and the second end of the first light-emitting control circuit is electrically connected to the first voltage end to receive a first power supply voltage; the control end of the second light-emitting control circuit is configured to receive a second light-emitting control signal, the second light-emitting control signal is different from the first light-emitting control signal, and the first end of the second light-emitting control circuit is electrically connected to the second end of the driving circuit; the second compensation circuit also includes a second compensation transistor, the gate of the second compensation transistor receives the second compensation control signal, the first electrode of the second compensation transistor is electrically connected to the gate of the driving transistor, and the second electrode of the second compensation transistor is electrically connected to the first plate of the compensation capacitor so that the first plate of the compensation capacitor is electrically connected to the gate of the driving transistor through the second compensation transistor, and the second plate of the compensation capacitor is electrically connected to the second electrode of the driving transistor. The driving method includes: in the compensation stage, setting the second light-emitting control signal and the second reset control signal to be both on signals, and the first light-emitting control signal to be an off signal, so that the second light-emitting control circuit and the second reset circuit are both turned on, and the second reset signal is written into the second end of the driving circuit via the second light-emitting control circuit so that the potential VN3 of the second end of the driving circuit satisfies VN3=Vini; and, in the compensation stage, the potential of the control end of the driving circuit is maintained at the potential at the end of the data writing stage.

[0029] For example, in the driving method of the pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit also includes a first light-emitting control circuit and a second light-emitting control circuit; the control end of the first light-emitting control circuit is configured to receive a first light-emitting control signal, the first end of the first light-emitting control circuit is electrically connected to the first end of the driving circuit, and the second end of the first light-emitting control circuit is electrically connected to the first voltage end to receive a first power supply voltage; the control end of the second light-emitting control circuit is configured to receive a second light-emitting control signal, the second light-emitting control signal is different from the first light-emitting control signal, and the first end of the second light-emitting control circuit is electrically connected to the second end of the driving circuit; the pixel circuit also includes a light-emitting element, the light-emitting element is configured to emit light under the drive of the driving current, the second end of the driving circuit is electrically connected to the first electrode of the light-emitting element, and the driving circuit is configured to control the magnitude of the driving current flowing through the light-emitting element; the first plate of the compensation capacitor is electrically connected to the gate of the driving transistor, and the second plate of the compensation capacitor is electrically connected to the first electrode of the light-emitting element. The driving method includes: in the compensation stage, setting the second reset control signal to an on signal and the first light-emitting control signal to an off signal, and writing the second reset signal to the first electrode of the light-emitting element via the second reset circuit so that the potential VN4 of the first electrode of the light-emitting element satisfies VN4=Vini; and, in the compensation stage, maintaining the potential of the control end of the driving circuit at the potential at the end of the data writing stage.

[0030] For example, in the driving method of the pixel circuit provided by at least one embodiment of the present disclosure, in the initial stage, the first light-emitting control signal is a turn-on signal to turn on the first light-emitting control circuit, and the first power supply voltage is written to the first end of the driving circuit through the first light-emitting control circuit; and in the data writing stage, the first light-emitting control signal and the second light-emitting control signal are both turn-off signals.

[0031] For example, in the driving method of the pixel circuit provided by at least one embodiment of the present disclosure, the data signal is a data voltage, and the first power supply voltage written in the initial stage is higher than the data voltage written in the data writing stage.

[0032] For example, in the driving method of the pixel circuit provided in at least one embodiment of the present disclosure, the second reset control signal and the first compensation control signal are the same gate scanning signal.

[0033] For example, in the driving method of the pixel circuit provided by at least one embodiment of the present disclosure, the driving method of the pixel circuit also includes: in the light-emitting stage after the compensation stage, the first light-emitting control signal and the second light-emitting control signal are set as turn-on signals, and the data scanning signal, the first reset control signal, the second reset control signal and the first compensation control signal are all turn-off signals, so that the first light-emitting control circuit and the second light-emitting control circuit are both turned on, and the data writing circuit, the first reset circuit, the second reset circuit and the first compensation circuit are all turned off, forming the driving current flowing through the first light-emitting control circuit, the driving circuit, the second light-emitting control circuit and the light-emitting element.

[0034] For example, in the driving method of the pixel circuit provided by at least one embodiment of the present disclosure, when the second compensation circuit also includes a second compensation transistor, the gate of the second compensation transistor receives a second compensation control signal, the first electrode of the second compensation transistor is electrically connected to the gate of the driving transistor, and the second electrode of the second compensation transistor is electrically connected to the first plate of the compensation capacitor so that the first plate of the compensation capacitor is electrically connected to the gate of the driving transistor through the second compensation transistor, and the second plate of the compensation capacitor is electrically connected to the second electrode of the driving transistor, the driving method of the pixel circuit also includes: in the light-emitting stage after the compensation stage, setting the second compensation control signal to a turn-on signal to turn on the second compensation control transistor.

[0035] For example, in the driving method of a pixel circuit provided in at least one embodiment of the present disclosure, the pixel circuit further includes a third reset circuit, a control terminal of the third reset circuit being configured to receive a third reset control signal, a first terminal of the third reset circuit being electrically connected to the first terminal of the driving circuit, and a second terminal of the third reset circuit being electrically connected to a third reset signal terminal to receive a third reset signal. The driving method of the pixel circuit further includes: in the initial stage, making the third reset control signal a turn-on signal so as to turn on the third reset circuit, and applying the third reset signal to the first terminal of the driving circuit through the third reset circuit.

[0036] For example, in the driving method of the pixel circuit provided in at least one embodiment of the present disclosure, the first end of the driving circuit is connected to the first power supply voltage end to receive the first power supply voltage; the third reset signal is a reset voltage, and the reset voltage is lower than the first power supply voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0038] FIG1 is a schematic block diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0039] FIG2 is a circuit diagram of a specific example of the pixel circuit shown in FIG1 ;

[0040] FIG3 is a signal timing diagram of a driving method for the pixel circuit shown in FIG1 and FIG2 according to at least one embodiment of the present disclosure;

[0041] FIG4A is a schematic diagram of the working state of the pixel circuit shown in FIG2 in the initial stage;

[0042] FIG4B is a schematic diagram of the working state of the pixel circuit shown in FIG2 during the data writing phase;

[0043] FIG4C is a schematic diagram of the working state of the pixel circuit shown in FIG2 during the light emitting stage;

[0044] FIG4D is a schematic diagram of the working state of the pixel circuit shown in FIG2 during the compensation phase;

[0045] FIG5 is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure;

[0046] FIG6 is a circuit diagram of a specific example of the pixel circuit shown in FIG5 ;

[0047] FIG7 is a signal timing diagram of a driving method for the pixel circuits shown in FIG5 and FIG6 according to at least one embodiment of the present disclosure;

[0048] FIG8 is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure;

[0049] FIG9 is a circuit diagram of a specific example of the pixel circuit shown in FIG8 ;

[0050] FIG10 is a signal timing diagram of a driving method for the pixel circuits shown in FIG8 and FIG9 according to at least one embodiment of the present disclosure;

[0051] FIG11 is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure;

[0052] FIG12 is a circuit diagram of a specific example of the pixel circuit shown in FIG11 ;

[0053] FIG13 is a signal timing diagram of a driving method for the pixel circuits shown in FIG11 and FIG12 according to at least one embodiment of the present disclosure;

[0054] FIG14 is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure;

[0055] FIG15 is a circuit diagram of a specific example of the pixel circuit shown in FIG14 ;

[0056] FIG16 is a signal timing diagram of a driving method for the pixel circuits shown in FIG14 and FIG15 according to at least one embodiment of the present disclosure;

[0057] FIG17 is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure;

[0058] FIG18 is a circuit diagram of a specific example of the pixel circuit shown in FIG17 ;

[0059] FIG19 is a signal timing diagram of a driving method for the pixel circuits shown in FIG17 and FIG18 according to at least one embodiment of the present disclosure;

[0060] FIG20 is a circuit diagram of another pixel circuit provided by at least one embodiment of the present disclosure;

[0061] FIG21 is a signal timing diagram of a driving method for the pixel circuit shown in FIG20 according to at least one embodiment of the present disclosure;

[0062] FIG22 is a circuit diagram of another specific example of the pixel circuit shown in FIG1 ;

[0063] FIG23 is a signal timing diagram of a driving method for the pixel circuit shown in FIG22 ;

[0064] FIG24 is a circuit diagram of another specific example of the pixel circuit shown in FIG17 ;

[0065] FIG25 is a schematic block diagram of a display device provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0066] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. The embodiments described below are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0067] Unless otherwise defined, the technical or scientific terms used herein should have the usual meanings understood by persons of ordinary skill in the field to which the invention belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0068] The features "perpendicular," "parallel," and "identical" used in the embodiments of the present disclosure include the features "perpendicular," "parallel," and "identical" in the strict sense, as well as "approximately perpendicular," "approximately parallel," and "approximately identical" that include certain errors, taking into account the errors associated with the measurement of specific quantities (i.e., the limitations of the measurement system), and represent within the acceptable deviation range for the specific value determined by ordinary technicians in this field. The "center" in the embodiments of the present disclosure can include a position strictly at the geometric center and a position approximately at the center of a small area around the geometric center.

[0069] In pixel circuits, the threshold voltage of the driver transistor affects display brightness. When the threshold voltage is unstable, it can lead to uneven brightness. To address this issue, the threshold voltage of the driver transistor needs to be compensated. Compensating the threshold voltage of the driver transistor can solve the problem of uneven display brightness on display panels.

[0070] At least one embodiment of the present disclosure provides a pixel circuit, comprising: a driving circuit, a data writing circuit, a first compensation circuit, and a second compensation circuit. The driving circuit comprises a control terminal, a first terminal, and a second terminal, and is configured to control the magnitude of a driving current flowing through the first terminal and the second terminal; the first terminal of the data writing circuit is electrically connected to the second terminal of the driving circuit, the second terminal of the data writing circuit is configured to receive a data signal, and the data writing circuit is configured to write the data signal to the second terminal of the driving circuit in response to a data scanning signal during a data writing phase; the first compensation circuit comprises a control terminal, a first terminal, and a second terminal, the control terminal of the first compensation circuit is configured to receive a first compensation control signal, the first terminal of the first compensation circuit is electrically connected to the first terminal of the driving circuit, the second terminal of the first compensation circuit is electrically connected to the control terminal of the driving circuit, and the first compensation circuit is configured to control whether the control terminal of the driving circuit and the first terminal of the driving circuit are connected via the first compensation circuit in response to the first compensation control signal; the second compensation circuit comprises a compensation capacitor, the first plate of the compensation capacitor is electrically connected to the control terminal of the driving circuit.

[0071] At least one embodiment of the present disclosure further provides a display device, which includes any pixel circuit provided by the embodiments of the present disclosure.

[0072] At least one embodiment of the present disclosure provides a driving method for a pixel circuit, which is applicable to any pixel circuit provided by the embodiments of the present disclosure, and the driving method includes: in a data writing stage, setting the data scanning signal to a turn-on signal to turn on the data writing circuit, and writing the data signal to the second end of the driving circuit through the data writing circuit, and controlling the first compensation circuit and the second compensation circuit so that the potential of the control end of the driving circuit changes in response to the change of the potential of the second end of the driving circuit; and in a compensation stage after the data writing stage, controlling the first compensation circuit and the second compensation circuit to maintain the potential of the control end of the driving circuit, and not allowing the potential of the control end of the driving circuit to change in response to the change of the potential of the second end of the driving circuit.

[0073] It should be noted that, in this application, "direct connection between A and B" means that there is no other switching element between A and B, for example, the connection is only electrically connected via a wire. The switching element can be any switching element such as a transistor that can be controlled to turn on and off as needed. A and B respectively represent elements or electrodes that can be electrically connected.

[0074] For example, FIG1 is a schematic block diagram of a pixel circuit provided by an embodiment of the present disclosure. Referring to FIG1 , the pixel circuit 10 provided by an embodiment of the present disclosure includes: a driving circuit 100, a data writing circuit 200, a first compensation circuit 800, and a second compensation circuit 900. The driving circuit 100 includes a control terminal 100m, a first terminal 100a, and a second terminal 100b, and is configured to control the magnitude of the driving current flowing through the first terminal 100a and the second terminal 100b, that is, to control the magnitude of the driving current flowing through the light-emitting element 400EL electrically connected to the driving circuit 100; the first terminal 200a of the data writing circuit 200 is electrically connected to the second terminal 100b of the driving circuit 100, and the second terminal 200b of the data writing circuit 200 is configured to receive a data signal Vdata, and the data writing circuit 200 is configured to write the data signal Vdata into the second terminal 100b of the driving circuit 100 in response to the data scanning signal G1 during the data writing phase; the first compensation circuit 800 has a control terminal 800m. m, a first end 800a and a second end 800b, the control end 800m of the first compensation circuit 800 is configured to receive a first compensation control signal G4, the first end 800a of the first compensation circuit 800 is electrically connected to the first end 100a of the drive circuit 100, the second end 800b of the first compensation circuit 800 is electrically connected to the control end 100m of the drive circuit 100, and the first compensation circuit 800 is configured to control whether the control end 100m of the drive circuit 100 and the first end 100a of the drive circuit 100 are conducted via the first compensation circuit 800 in response to the first compensation control signal G4; the second compensation circuit 900 includes a compensation capacitor, and a first plate of the compensation capacitor C1 is electrically connected to the control end 100m of the drive circuit 100.

[0075] The pixel circuit 10 provided by the embodiment of the present disclosure can realize that in the data writing stage, the data signal Vdata is written into the second terminal 100b of the driving circuit 100 through the data writing circuit 200, and the potential of the control terminal 100m of the driving circuit 100 changes in response to the change of the potential of the second terminal 100b of the driving circuit 100 by controlling the first compensation circuit 800 and the second compensation circuit 900 including the compensation capacitor, thereby participating in the regulation of the potential of the control terminal 100m of the driving circuit 100 by the data signal Vdata written into the second terminal 100b of the pixel circuit 10, thereby participating in the regulation of the potential of the control terminal 100m of the driving circuit 100, thereby participating in the regulation of the potential of the driving circuit 100 Furthermore, the pixel circuit 10 can implement, during a compensation phase after the data writing phase, a compensation phase by controlling the operating states of the first compensation circuit 800 and the second compensation circuit 900 to maintain the potential of the control terminal 100m of the driver circuit 100 at the end of the data writing phase, and not allowing the potential of the control terminal 100m of the driver circuit 100 to change in response to a change in the potential of the second terminal 100b of the driver circuit 100, so that the potential participates in the compensation calculation of the threshold voltage of the driver circuit 100. That is, the first compensation circuit 800 and the second compensation circuit 900 are configured to allow the potential of the control terminal 100m of the driver circuit 100 to change in response to a change in the potential of the second terminal 100b of the driver circuit 100 during the data writing phase, and to maintain the potential of the control terminal 100m of the driver circuit 100 during the compensation phase after the data writing phase, and not allowing the potential of the control terminal 100m of the driver circuit 100 to change in response to a change in the potential of the second terminal 100b of the driver circuit 100. Moreover, during the light-emitting stage, the potential of the control terminal 100m of the driving circuit 100 can be changed through the compensation capacitor of the second compensation circuit 900, so that the threshold voltage of the driving circuit 100 can be compensated during the light-emitting stage, and the driving current is independent of the threshold voltage of the driving circuit 100, thereby improving the light-emitting uniformity of the pixel driven by the pixel circuit 10.

[0076] For example, referring to FIG1 , a first terminal 100 a of the driver circuit 100 is electrically connected to a first power supply voltage terminal ELVDD to receive a first power supply voltage VDD. For example, the pixel circuit 10 further includes a light-emitting element 400, which is configured to emit light under the drive current. A second terminal 100 b of the driver circuit 100 is electrically connected to a first electrode of the light-emitting element 400, and the driver circuit 100 is configured to control the magnitude of the drive current flowing through the light-emitting element 400. A second electrode 400 b of the light-emitting element 400 is electrically connected to a second voltage terminal ELVSS to receive a second power supply voltage VSS. For example, the first power supply voltage VDD is at a high level, and the second power supply voltage VSS is at a low level. For example, the second voltage terminal ELVSS can be grounded, i.e., the second power supply voltage VSS can be 0V. For example, the second power supply voltage VSS can be a negative voltage. For example, the light-emitting element can be implemented as a light-emitting diode (LED), such as an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED) or an inorganic light-emitting diode, such as a micro light-emitting diode (Micro LED) or a micro OLED. The embodiments of the present disclosure do not limit the type of the light-emitting element.

[0077] For example, as shown in FIG1 , the pixel circuit 10 further includes a first reset circuit 300. A control terminal 300m of the first reset circuit 300 is configured to receive a first reset control signal G2. A first terminal 300a of the first reset circuit 300 is electrically connected to the second terminal 100b of the driver circuit 100. A second terminal 300b of the first reset circuit 300 is electrically connected to the first reset signal terminal Vref1 to receive the first reset signal Vref1. The first reset circuit 300 is configured to write the first reset signal Vref1 to the second terminal 100b of the driver circuit 100 in response to the first reset control signal G2. Thus, for example, the first reset signal Vref1 is a relatively low reference voltage, which can reset the second terminal 100b of the driver circuit 100 in the initial stage, so that the voltage at the second terminal 100b of the driver circuit 100 is the relatively low reference voltage, thereby preparing for subsequent compensation of the threshold voltage of the driver transistor DT.

[0078] For example, as shown in FIG1 , the pixel circuit further includes a second reset circuit 500, wherein a control terminal 500m of the second reset circuit 500 is configured to receive a second reset control signal G3, a first terminal 500a of the second reset circuit 500 is electrically connected to the first electrode 400a of the light-emitting element 400, and a second terminal 500b of the second reset circuit 500 is electrically connected to the second reset signal terminal Vini to receive the second reset signal Vini. The second reset circuit 500 is configured to apply the second reset signal Vini to the first electrode 400a of the light-emitting element 400 and / or the second plate of the compensation capacitor C1 in response to the second reset control signal G3. Thus, for example, in the initial stage, the second reset signal Vini can be applied to the first electrode 400a of the light-emitting element 400 to reset the voltage of the first electrode 400a of the light-emitting element 400. For example, during the compensation stage, the first electrode 400a of the light-emitting element 400 can be electrically connected to the second electrode of the driving transistor DT, so that the second reset signal Vini is applied to the second electrode of the driving transistor DT. Since the second plate of the compensation capacitor C1 is electrically connected to the second electrode of the driving transistor DT, the second reset signal Vini is applied to the second plate of the compensation capacitor C1, so as to cooperate with the control of the potential of the control end of the driving circuit 100 and the potential of the second end 100b of the driving circuit in other working periods to achieve compensation for the threshold voltage of the driving transistor.

[0079] For example, as shown in FIG1 , the pixel circuit 10 further includes a first light-emitting control circuit 600. A control terminal 600m of the first light-emitting control circuit 600 is configured to receive a first light-emitting control signal EM1. A first terminal 600a of the first light-emitting control circuit 600 is electrically connected to the first terminal 100a of the driver circuit 100. A second terminal 600b of the first light-emitting control circuit 600 is electrically connected to the first voltage terminal ELVDD to receive a first power supply voltage VDD. The first light-emitting control circuit 600 is configured to apply the first power supply voltage VDD to the first terminal 100a of the driver circuit 100 in response to the first light-emitting control signal EM1. For example, in an initial stage, the first light-emitting control circuit 600 may be turned on in response to the first light-emitting control signal EM1, thereby applying the first power supply voltage VDD to the first terminal 100a of the driver circuit 100. For example, during the light-emitting phase, the first light-emitting control circuit 600 may also be turned on in response to the first light-emitting control signal EM1, thereby applying the second power supply voltage VDD to the first terminal 100a of the driver circuit 100. When the driver circuit 100 is turned on, the second power supply voltage VDD is written to the second terminal 100b of the driver circuit 100. The second terminal 400b of the light-emitting element 400 receives the second power supply voltage VSS, and the light-emitting element 400 emits light under the influence of the first power supply voltage VDD and the second power supply voltage VSS.

[0080] For example, as shown in FIG1 , the pixel circuit 10 further includes a second light-emission control circuit 700. A control terminal 700m of the second light-emission control circuit 700 is configured to receive a second light-emission control signal EM2, which is different from the first light-emission control signal EM1. A first terminal 700a of the second light-emission control circuit 700 is electrically connected to a second terminal 100b of the driver circuit 100, and a second terminal 700b of the second light-emission control circuit 700 is electrically connected to a first electrode 400a of the light-emitting element 400. The second light-emission control circuit 700 is configured to apply a drive current to the light-emitting element 400 in response to the second light-emission control signal EM2 and to allow a second reset signal Vini to be applied to the second terminal 100b of the driver circuit 100 via the second light-emission control circuit 700. For example, during a light-emission phase, the second light-emission control circuit 700 can be turned on in response to the second light-emission control signal EM2, so that the driver circuit 100 can apply a drive current to the light-emitting element 400 via the second light-emission control circuit 700 to cause the light-emitting element 400 to emit light. For example, in the compensation stage, the second light-emitting control circuit 700 can also be turned on in response to the second light-emitting control signal EM2, so that the first electrode 400a of the light-emitting element 400 and the second electrode of the driving transistor DT are electrically connected through the second light-emitting control circuit 700, thereby applying the second reset signal Vini to the second electrode of the driving transistor DT and the second plate of the compensation capacitor C1, so as to cooperate with the control of the potential of the control end of the driving circuit 100 and the potential of the second end 100b of the driving circuit in other working periods to achieve compensation for the threshold voltage of the driving transistor.

[0081] In the pixel circuit 10 of FIG1 , the first end 600a of the first light emitting control circuit 600, the first end 100a of the driving circuit 100, and the second end 800b of the first compensation circuit 800 are electrically connected to the first node N1; the control end 100m of the driving circuit 100, the first end 800a of the first compensation circuit 800, and the first end 900a of the second compensation circuit 900 are electrically connected to the second node N2. For example, the first plate of the compensation capacitor of the second compensation circuit 900 is electrically connected to the second node N2. The first plate of the compensation capacitor and the second node N2 can be directly connected, that is, there is no switching element between the two. The two nodes N2 can also be electrically connected through switching elements such as transistors; the second end 100b of the driving circuit 100, the second end 900b of the second compensation circuit 900 and the first end 700a of the second light-emitting control circuit 700 are electrically connected to the third node N3, for example, the second plate of the compensation capacitor of the second compensation circuit 900 is electrically connected to the third node N3, for example, the second plate of the compensation capacitor is directly electrically connected to the third node N3, that is, there is no switching element between the two; the first electrode 400a of the light-emitting element 400, the second end 700b of the second light-emitting control circuit 700, and the first end 500a of the second reset circuit are electrically connected to the fourth node N4.

[0082] FIG2 is a circuit diagram of a specific example of the pixel circuit shown in FIG1 . As shown in FIG2 , the pixel circuit 10 includes: a driving transistor DT, a data writing transistor T1, a first compensation transistor T3, a second compensation transistor T7, a first reset transistor T4, a second reset transistor T6, a first emission control transistor T2, a second emission control transistor T5, a compensation capacitor C1, and a light-emitting element 400. For example, the light-emitting element 400 may be an organic light-emitting diode (OLED). For example, the data writing transistor T1, the first compensation transistor T3, the second compensation transistor T7, the first reset transistor T4, the second reset transistor T6, the first emission control transistor T2, and the second emission control transistor T5 may function as switching transistors. For example, the embodiments of the present disclosure are described using an OLED as an example, but are not limited to this. For example, the light-emitting element may also be other light-emitting devices, and the embodiments of the present disclosure are not limited to this. For example, when the light-emitting element is an OLED, the light-emitting element may be of various types, such as top-emitting or bottom-emitting, and may emit red, green, blue, or white light, and the embodiments of the present disclosure are not limited to this.

[0083] For example, as shown in Figures 1 and 2, the driving circuit 100 includes a driving transistor DT, the gate of the driving transistor DT serves as the control terminal 100m of the driving circuit 100, the first electrode of the driving transistor DT serves as the first terminal 100a of the driving circuit 100, and the second electrode of the driving transistor DT serves as the second terminal 100b of the driving circuit 100. The first terminal 100a of the driving circuit 100 is electrically connected to the first power supply voltage terminal ELVDD to receive the first power supply voltage VDD.

[0084] For example, as shown in Figures 1 and 2, the data write circuit 200 includes a data write transistor T1. The gate of the data write transistor T1 is configured to be connected to the data scan signal terminal to receive the data scan signal G1. The first electrode of the data write transistor T1 is electrically connected to the second terminal 100b of the driving circuit 100, that is, electrically connected to the second electrode of the driving transistor DT. The second electrode of the data write transistor T1 is electrically connected to the data signal Vdata terminal to receive the data signal Vdata. The data write transistor T1 is configured to write the data signal Vdata to the second electrode of the driving transistor DT in response to the data scan signal G1 during the data write phase.

[0085] For example, as shown in Figures 1 and 2, the first compensation circuit 800 includes a first compensation transistor T3, the gate of which receives a first compensation control signal G4. The first electrode of the first compensation transistor T3 is electrically connected to the first electrode of the driving transistor DT, and the second electrode of the first compensation transistor T3 is electrically connected to the gate of the driving transistor DT. Thus, by controlling the on / off state of the first compensation transistor T3 via the first compensation control signal G4, it is possible to control whether the control terminal 100m of the driving circuit 100 is conductively connected to the first terminal 100a of the driving circuit 100.

[0086] For example, as shown in Figures 1 and 2, the first reset circuit 300 includes a first reset transistor T4, the gate of which is electrically connected to the first reset control terminal to receive the first reset control signal G2, the first electrode of which is electrically connected to the second terminal 100b of the driving circuit 100, that is, the second electrode of the driving transistor DT, and the second electrode of the first reset transistor T4 is electrically connected to the first reset signal terminal Vref1 to receive the first reset signal Vref1. The first reset transistor T4 is configured to write the first reset signal Vref1 to the second electrode of the driving transistor DT in response to the first reset control signal G2.

[0087] For example, in the pixel circuit shown in FIG2 , the data writing transistor T1 and the first reset transistor T4 are different transistors independent of each other, and the data signal terminal Vdata and the first reset signal terminal Vref1 are different signal terminals independent of each other.

[0088] For example, as shown in Figures 1 and 2, the second reset circuit 500 includes a second reset transistor T6. The gate of the second reset transistor T6 is electrically connected to the second reset control terminal to receive the second reset control signal G3. The first electrode of the second reset transistor T6 is electrically connected to the second terminal 100b of the driving circuit 100, for example, the first electrode of the second reset transistor T6 is electrically connected to the second electrode of the driving transistor DT. The second electrode of the second reset transistor T6 is electrically connected to the second reset signal terminal Vini to receive the second reset signal Vini. For example, the first electrode of the second reset transistor T6 is electrically connected to the second terminal 100b of the driving circuit 100 via the second light-emitting control circuit 700. Alternatively, in other embodiments, the first electrode of the second reset transistor T6 can be directly electrically connected to the second terminal 100b of the driving circuit 100.

[0089] For example, in the pixel circuit 10 shown in FIG. 2 , the second reset transistor T6 and the first reset transistor T4 are different transistors independent of each other, and the first reset signal terminal Vref1 and the second reset signal terminal Vini are different signal terminals independent of each other.

[0090] For example, as shown in Figures 1 and 2, the second compensation circuit 900 further includes a second compensation transistor T7, the gate of which receives a second compensation control signal G5. The first electrode of the second compensation transistor T7 is electrically connected to the gate of the driving transistor DT, and the second electrode of the second compensation transistor T7 is electrically connected to the first plate of the compensation capacitor C1, so that the first plate of the compensation capacitor C1 is electrically connected to the gate of the driving transistor DT through the second compensation transistor T7, and the second plate of the compensation capacitor C1 is electrically connected to the second electrode of the driving transistor DT. In this way, the second compensation control signal G5 can be used to control the on and off of the second compensation transistor T7, so that the second compensation transistor T7 can be turned on during a specific operating period so that the compensation capacitor C1 can play a bootstrap role to adjust the potential of the gate of the driving transistor DT. Alternatively, the second compensation transistor T7 can be turned off during a specific operating period so that the potential of the gate of the driving transistor DT is maintained and is not changed by changes in the potential applied to the second plate of the compensation capacitor C1, that is, it is not changed by changes in the potential of the second electrode of the driving transistor DT, so as to achieve threshold voltage compensation.

[0091] For example, the second plate of the compensation capacitor C1 is directly connected to the second electrode of the second compensation transistor T7, i.e., no other switching element is present between the two, thereby achieving compensation for the threshold voltage of the driving circuit using the simplest structure. Of course, this is not limited to this embodiment. The switching element here can be, for example, any switching element such as a transistor that can be controlled to turn on and off as needed.

[0092] For example, as shown in Figures 1 and 2, the first light-emitting control circuit 600 includes a first light-emitting control transistor T2, a gate of the first light-emitting control transistor T2 is electrically connected to the first light-emitting control terminal EM1 to receive the first light-emitting control signal EM1, a first electrode of the first light-emitting control transistor T2 is electrically connected to the first terminal 100a of the driving circuit 100, that is, electrically connected to the first electrode of the driving transistor DT, and a second electrode of the first light-emitting control transistor T2 is electrically connected to the first voltage terminal ELVDD to receive the first power supply voltage VDD.

[0093] For example, as shown in Figures 1 and 2, the second light-emission control circuit 700 includes a second light-emission control transistor T5. The gate of the second light-emission control transistor T5 is electrically connected to the second light-emission control terminal EM2 to receive the second light-emission control signal EM2. The first electrode of the second light-emission control transistor T5 is electrically connected to the second terminal 100b of the driving circuit 100, that is, the second electrode of the driving transistor DT. The second electrode of the second light-emission control transistor T5 is electrically connected to the first electrode of the light-emitting element 400. For example, the first electrode of the second reset transistor T6 is electrically connected to the second electrode of the second light-emission control transistor T5, and thus can be electrically connected to the second terminal 100b of the driving circuit 100 through the second light-emission control transistor T5.

[0094] In the pixel circuit 10 shown in Figure 2, the first electrode of the first compensation transistor T3, the first electrode of the driving transistor DT and the first electrode of the first light-emitting control transistor T2 are connected to the first node N1; the gate of the driving transistor DT, the second electrode of the first compensation transistor T3 and the first electrode of the second compensation transistor T7 are connected to the second node N2; the second electrode of the driving transistor DT, the second plate of the compensation capacitor C1 and the first electrode of the second light-emitting control transistor T5, the first electrode of the data writing transistor T1 and the first electrode of the first reset transistor T4 are electrically connected to the third node N3; the first electrode of the second reset transistor T6, the second electrode of the second light-emitting control transistor T5 and the first electrode of the light-emitting element 400 are electrically connected to the fourth node N4.

[0095] It should be noted that in various embodiments of the present disclosure, the first node N1 , the second node N2 , the third node N3 and the fourth node N4 do not necessarily represent actual components, but represent junction points of related circuit connections in a circuit diagram. In the description of the embodiments of the present disclosure, the symbol Vdata can represent both the data signal terminal and the data signal; similarly, the symbol Vref1 can represent both the first reset control signal terminal and the first reset control signal; the symbol Vini can represent both the second reset signal terminal and the second reset signal; the symbol Vref2 can represent both the third reset signal terminal and the third reset signal; the symbol EM1 can represent both the first light-emitting control terminal and the first light-emitting control signal; the symbol EM2 can represent both the second light-emitting control terminal and the second light-emitting control signal; the symbol G1 can represent both the data scan signal terminal and the data scan signal, the symbol G2 can represent both the first reset control terminal and the first reset control signal, the symbol G3 can represent both the second reset control terminal and the second reset control signal, the symbol G4 can represent both the second reset control terminal and the second reset control signal, the symbol G5 can represent both the second compensation control terminal and the second compensation control signal, and the symbol G6 can represent both the third reset control signal terminal and the third reset control signal.

[0096] It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics. The embodiments of the present disclosure are described using thin film transistors as examples. The source and drain of the transistors used here may be symmetrical in structure, so the source and drain may be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one pole is directly described as the first pole and the other pole is directly described as the second pole.

[0097] In addition, transistors can be divided into N-type and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (for example, 5V, 10V, or other suitable voltages); when the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (for example, 5V, 10V, or other suitable voltages), and the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V, or other suitable voltages). However, the embodiments of the present disclosure do not limit the type of transistor. When the type of transistor changes, the connection relationship in the circuit can be adjusted accordingly.

[0098] The following describes the operation of the pixel circuit 10 shown in FIG2 in conjunction with the signal timing diagram shown in FIG3 and FIG4A-4D. As shown in FIG3, the display process of each frame of image includes four stages, namely, the initial stage P1, the data writing stage P2, the compensation stage P3, and the light emitting stage P4.

[0099] FIG4A is a schematic diagram of the pixel circuit 10 shown in FIG2 in the initial stage; FIG4B is a schematic diagram of the pixel circuit 10 shown in FIG2 in the data writing stage; FIG4C is a schematic diagram of the pixel circuit 10 shown in FIG2 in the compensation stage; and FIG4D is a schematic diagram of the pixel circuit 10 shown in FIG2 in the light emitting stage. Furthermore, transistors marked with dashed lines in FIG4A-4D are in the off state (i.e., disconnected state) during the corresponding stage, and transistors not marked with dashed lines are in the on state (i.e., conductive state) during the corresponding stage.

[0100] For example, in the pixel circuit 10 shown in FIG2 , the driving transistor DT, the data writing transistor T1, the first compensation transistor T3, the second compensation transistor T7, the first reset transistor T4, the second reset transistor T6, the first light emission control transistor T2, and the second light emission control transistor T5 are all N-type transistors, that is, each transistor is turned on when a high-level signal is connected to its gate and is turned off when a low-level signal is connected. Of course, in other embodiments, these transistors can also all be P-type transistors, or some can be P-type transistors and the other can be N-type transistors, as long as the designed on-signal or off-signal is controlled to be supplied to each transistor at the corresponding stage during the operation of the pixel circuit.

[0101] As shown in Figures 1 and 3, an embodiment of the present disclosure provides a driving method for a pixel circuit, which is applicable to the pixel circuit provided by the embodiment of the present disclosure. The driving method of the pixel circuit includes: in the data writing phase P2, the data scanning signal G1 is set to a start signal to turn on the data writing circuit 200, and the data signal Vdata is written to the second end 100b of the driving circuit 100 through the data writing circuit 200, and the potential of the control end 100m of the driving circuit 100 changes in response to the change of the potential of the second end 100b of the driving circuit 100 by controlling the first compensation circuit 800 and the second compensation circuit 900; and in the compensation phase after the data writing phase P2, the potential of the control end 100m of the driving circuit 100 is maintained by controlling the first compensation circuit 800 and the second compensation circuit 900, and the potential of the control end 100m of the driving circuit 100 is not allowed to change in response to the change of the potential of the second end 100b of the driving circuit 100.

[0102] For example, the driving method of the pixel circuit further includes: in the initial stage P1, the first compensation circuit 800 is turned on, and the first power supply voltage VDD is sequentially applied to the driving end of the driving circuit 100 through the first end 100a of the driving circuit 100 and the first compensation circuit 800 so that the driving circuit 100 is turned on, that is, the first end 100a and the second end 100b of the driving circuit 100 are turned on.

[0103] For example, the driving method of the pixel circuit further includes: in the initial stage P1, the first light control signal EM1 is an on signal to turn on the first light control circuit 600, and the first power supply voltage VDD is written to the first terminal 100a of the driving circuit 100 through the first light control circuit 600.

[0104] For example, the driving method of the pixel circuit further includes: in an initial stage P1, setting the first reset control signal G2, the second reset control signal G3, and the first compensation control signal G4 to all be on signals, so that the first reset circuit 300 is turned on, thereby applying the first reset signal Vref1 to the second terminal 100b of the driving circuit 100 via the first reset circuit 300, and turning on the second reset circuit 500, thereby applying the second reset signal Vini to the first electrode 400a of the light-emitting element 400 via the second reset circuit 500, thereby completing the reset of each position. Furthermore, applying the second reset signal Vini to the first electrode 400a of the light-emitting element 400 in the initial stage P1 eliminates the need to turn on the second reset circuit again during the subsequent data writing stage and compensation stage, that is, it is unnecessary to write the second reset signal Vini. This ensures that the potential of the first electrode 400a of the light-emitting element 400 remains at Vini during the subsequent data writing stage and compensation stage to meet the calculation of the compensation threshold voltage, thereby simplifying the driving method.

[0105] For example, the driving method of the pixel circuit further includes: in the data writing phase P2, setting the first compensation control signal G4 as a start signal, so that the first compensation circuit 800 is turned on in response to the first compensation control signal G4, and the control terminal 100m of the driving circuit 100 and the first terminal 100a of the driving circuit 100 are turned on via the first compensation circuit 800, and the potential of the first power supply voltage VDD input to the control terminal 100m of the driving circuit 100 in the initial phase P1 is higher than the potential of the data signal Vdata written to the third node N3 in the data writing phase P2, thereby During phase P2, the control terminal 100m of the driver circuit 100 is discharged to the third node N3 through the first compensation circuit 800 and the driver circuit 100, thereby generating a compensation current between the control terminal 100m of the driver circuit 100 and the second terminal 100b of the driver circuit 100. The compensation current flows through the first compensation circuit 800 and the driver circuit 100, thereby causing the potential of the control terminal 100m of the driver circuit 100 to change in response to changes in the potential of the second terminal 100b of the driver circuit 100, until the potential of the second terminal 100b of the driver circuit 100 reaches a level that disconnects the driver circuit 100. In other words, the potential of the control terminal 100m of the driver circuit 100 changes in response to changes in the potential of the second terminal 100b of the driver circuit 100 until the driver circuit 100 is disconnected, for example, until the driver transistor DT is turned off. At the end of the data writing phase P2, the potential of the control terminal 100m of the driver circuit 100 is V G Meet V G =Vdata+Vth.

[0106] For example, the control method of the pixel circuit also includes: in the compensation stage P3, at least setting the first compensation control signal G4 to a shutdown signal to turn off the first compensation circuit 800, thereby not allowing current to be generated between the control terminal 100m of the driving circuit 100 and the second terminal 100b of the driving circuit 100, keeping the potential of the control terminal 100m of the driving circuit 100 unchanged, and not allowing the potential of the control terminal 100m of the driving circuit 100 to change in response to changes in the potential of the second terminal 100b of the driving circuit 100.

[0107] For example, the driving method of the pixel circuit further includes: in a light-emitting phase P4 following the compensation phase P3, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are set to on signals, and the data scanning signal G1, the first reset control signal G2, the second reset control signal G3, and the first compensation control signal G4 are all set to off signals, so that the first light-emitting control circuit 600 and the second light-emitting control circuit 700 are both turned on, and the data writing circuit 200, the first reset circuit 300, the second reset circuit 500, and the first compensation circuit 800 are all turned off, thereby forming a driving current flowing through the first light-emitting control circuit 600, the driving circuit 100, the second light-emitting control circuit 700, and the light-emitting element 400. After the above four phases, the threshold voltage of the driving circuit 100 (i.e., the threshold voltage of the driving transistor DT of the driving circuit 100) is compensated during the light-emitting phase. The driving current is independent of the threshold voltage of the driving circuit 100, and the problem of uneven brightness of pixels using the pixel circuit due to unstable threshold voltage is eliminated, thereby improving the uniformity of light emission of the pixels driven by the pixel circuit 10.

[0108] Specifically, the driving method of the pixel circuit of FIG. 2 and the compensation principle for the threshold voltage shown in FIG. 4A-4D are taken as an example for description.

[0109] 4A and 3 , the pixel circuit control method further includes the following steps in an initial stage P1. In the initial stage P1, the first light-emitting control signal EM1, the first reset control signal G2, the second reset control signal G3, the first compensation control signal G4, and the second compensation control signal G5 are all on signals, for example, at a high voltage, so that the first light-emitting control transistor T2, the first reset transistor T4, the second reset transistor T6, the first compensation transistor T3, and the second compensation transistor T7 are turned on. Furthermore, the second light-emitting control signal EM2 and the data scanning signal G1 are both off signals, for example, at a low voltage, so that the second light-emitting control transistor T5 and the data writing transistor T1 are turned off. Therefore, in the initial stage P1, the first power supply voltage VDD is written into the gate G of the driving transistor DT via the first light-emitting control transistor T2 and the first compensation transistor T3 in sequence, so that the driving transistor DT is turned on, so that the first power supply voltage VDD is written into the first node N1 via the first light-emitting control transistor T2 and the driving transistor DT in sequence, and the first reset voltage Vref1 is written into the third node N3 via the first reset transistor T4, and the second reset voltage Vini is written into the fourth node N4 via the second reset transistor T6, thereby completing the setting of the potential of the required node.

[0110] 4B and FIG. 3 , the method for controlling the pixel circuit further includes the following steps in the data writing phase P2 . In the data writing phase P2, the data scanning signal G1 is an on signal, for example, a high potential signal, so that the data writing transistor T1 is turned on; and the first compensation control signal G4 and the second compensation control signal G5 are both on signals, for example, high potential signals, so that the first compensation transistor T3 and the second compensation transistor T7 remain turned on; the potential of the first power supply voltage VDD written to the gate G of the driving transistor DT in the initial phase P1 is higher than the potential of the data signal Vdata written to the third node N3 in the data writing phase P2. Therefore, in the data writing phase P2, the gate G of the driving transistor DT is discharged to the third node N3 through the first compensation transistor T3 and the driving transistor DT in sequence, so as to generate a compensation current between the driving transistor DT and the second electrode of the driving transistor DT. The compensation current flows through the first compensation transistor T3 and the driving transistor DT. That is, the potential of the gate G of the driving transistor DT changes in response to the change in the potential of the second electrode of the driving transistor DT until the driving transistor DT is turned off (shut down), for example, until it is just turned off, so that the gate-source voltage V GS =Vth, that is, V G -V N3 =Vth, since V N3 =Vdata, therefore, V G =Vdata+Vth. Therefore, at the end of the data writing phase P2, the potential V of the gate G of the driving transistor DT is G Meet V G =Vdata+Vth, V G Participating in the compensation calculation, in conjunction with the control of the potential of the control terminal of the driver circuit 100 and the potential of the second terminal 100b of the driver circuit during other working periods, compensates for the threshold voltage of the driver transistor. Furthermore, during the above-described process of the data writing phase P2, since the second compensation transistor T7 and the compensation capacitor C1 are provided and the second compensation transistor T7 is turned on, information such as the threshold voltage Vth of the driver transistor DT is stored in the compensation capacitor C1, thereby completing the data writing process.

[0111] For example, the data signal Vdata is a data voltage, and the first power supply voltage VDD written in the initial stage P1 is higher than the data voltage written in the data writing stage P2, so that the gate G of the driving transistor DT can be discharged to the third node N3 in sequence through the first compensation transistor T3 and the driving transistor DT in the data writing stage P2.

[0112] For example, in the embodiment shown in Figure 3, in the data writing stage P2, the second reset control signal G3 is also an on signal, for example, a high potential signal, so that the second reset transistor T6 is turned on and continues to write the second reset signal Vini to the fourth node N4; or, in other embodiments, for the pixel circuit 10 shown in Figure 2, in the data writing stage P2, the second reset control signal G3 can also be an off signal, stopping writing the second reset signal Vini to the fourth node N4, because at this time the second light-emitting control transistor T5 is turned off, and the signal of the fourth node N4 will not affect the potential of the second electrode of the driving transistor DT and the potential of the gate G of the driving transistor DT.

[0113] 4C and 3 , the pixel circuit control method further includes the following steps in the compensation phase P3. In the compensation phase P3, the first compensation control signal G4 and the second compensation control signal G5 are both off signals, for example, both at a low potential, so that the first compensation transistor T3 and the second compensation transistor T7 are both turned off. As a result, the gate G of the driving transistor DT cannot be discharged through the first compensation transistor T3 or the second compensation transistor T7, thereby maintaining the potential of the control terminal 100m of the driving circuit 100 unchanged. In other words, the potential of the gate G of the driving transistor DT remains unchanged, and the potential of the control terminal 100m of the driving circuit 100 remains at the potential at the end of the data writing phase P2. For example, in the compensation phase P3, the first light-emitting control signal EM1, the data scanning signal G1, and the first reset control signal G2 are all off signals, for example, low-voltage signals, so that the first light-emitting control transistor T2, the data transistor T1, and the first reset transistor T4 are all turned off; and, in the compensation phase P3, the second light-emitting control signal EM2 and the second reset control signal G3 are both on signals, for example, high-voltage signals, so that the second light-emitting control circuit 700 is turned on and the second reset circuit 500 is turned on, that is, the second reset signal Vini is written into the second terminal 100b of the driving circuit 100 via the second light-emitting control circuit 700 so that the potential V N3 Meet V N3 =Vini, and the potential of the gate G of the driving transistor DT is maintained at the potential at the end of the data writing phase P2. Specifically, the second light-emitting control transistor T5 and the second reset transistor T6 are both turned on, so that the second reset signal Vini is written into the second electrode of the driving transistor DT via the second light-emitting control transistor T5 so that the potential V N3 becomes V N3 =Vini, that is, the potential of the second plate of the compensation capacitor C1 becomes Vini, that is, the potential of the third node N3 becomes V N3 Meet V N3=Vini, and the potential of the gate G of the driving transistor DT is maintained at the potential at the end of the data writing phase P2, thereby utilizing the potential of the third node N3 at this moment and the potential of the gate G of the driving transistor DT to participate in the compensation calculation of the threshold voltage of the driving transistor DT. Of course, for example, in other embodiments, during the compensation phase, the second reset control signal G3 may also be a shutdown signal, because the second reset signal Vini has been written to the fourth node N4 during the initial phase P1. Therefore, during the compensation phase, when the second light-emitting control transistor T5 is turned on, even if the second reset signal Vini is not rewritten, the potential of the third node N3 can be V N 3 Satisfy V N3 =Vini.

[0114] 4D and 3 , the pixel circuit control method further includes the following steps in a light-emitting phase P4 following the compensation phase P3. During the light-emitting phase P4, the second compensation control signal G5 is set to an on-state signal, such as a high-voltage signal, to turn on the second compensation control transistor T7. This allows the compensation capacitor C1 to function as a bootstrap, changing the potentials of the gate G of the drive transistor DT, which is electrically connected to the first plate of the compensation capacitor C1, and the third node N3, which is electrically connected to the second plate of the compensation capacitor C1, by the same amount, thereby compensating for the threshold voltage of the drive transistor DT. For example, for the pixel circuit 10 shown in Figure 2, in the light-emitting stage P4, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are also turn-on signals, for example, high-voltage signals, so that the first light-emitting control transistor T2 and the second light-emitting control transistor T5 are turned on, and the data scanning signal G1, the first reset control signal G2, the second reset control signal G3 and the first compensation control signal G4 are all turn-off signals, for example, they are all low-voltage signals, so that the data writing transistor T1, the first reset transistor T4, the second reset transistor T6 and the first compensation transistor T3 are all turned off, and finally the driving transistor DT is turned on, the first power supply voltage VDD is applied to the first electrode of the driving transistor DT, and the driving current is applied to the light-emitting element 400 via the second light-emitting control transistor T5 to make it emit light.

[0115] In the light-emitting stage P4, since the light-emitting element 400 is in the light-emitting state, the voltage value of the first electrode of the light-emitting element 400 (i.e., the voltage value of the fourth node N4) and the voltage value of the second electrode of the driving transistor DT both correspond to the voltage value Voled when the light-emitting element 400 emits light, that is, the voltage value of the first electrode of the light-emitting element 400 (i.e., the fourth node N4) is Voled; since the second light-emitting control circuit 700 is turned on, the voltage value of the second plate of the compensation capacitor C1 is also Voled at this moment. Therefore, the change in the voltage value of the second plate of the compensation capacitor C1 △V N3=Voled-Vini. Accordingly, the compensation capacitor C1 plays a self-bootstrapping role, so that the first plate of the compensation capacitor C1 also has a variation ΔV N3 =Voled-Vini, thereby making the voltage value of the gate G of the driving transistor DT (the voltage value of the second node N2) have a change amount ΔV N3 The voltage value of the gate G of the driving transistor DT is V G Representative, then V G =Vdata+Vth+Voled-Vini. The driving transistor DT is in the on state, and the gate-source voltage of the driving transistor DT is V GS Representative, then V GS =V G -V N3 =(Vdata+Vth+Voled-Vini)-Voled=Vdata+Vth-Vini.

[0116] The value of the driving current I flowing through the light-emitting element can be obtained according to the following formula:

[0117] I=K×(V GS -Vth) 2 , K is the conductivity coefficient of the driving transistor DT. That is: I=K*(Vdata-Vini) 2

[0118] According to the above formula, the value I of the driving current flowing through the light-emitting element is no longer related to the threshold voltage Vth of the driving transistor DT. This can compensate for the pixel circuit, solve the problem of threshold voltage Vth drift of the driving transistor DT due to process technology and long-term operation, and eliminate its influence on the driving current, thereby improving the display effect of the display device using this pixel circuit.

[0119] Figure 5 is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure; Figure 6 is a circuit diagram of a specific example of the pixel circuit shown in Figure 5; and Figure 7 is a signal timing diagram of a driving method for the pixel circuit shown in Figures 5-6, provided by at least one embodiment of the present disclosure. The structure and driving method of the pixel circuit shown in Figures 5-7 differ from the pixel circuit shown in Figures 1-3 in the following ways.

[0120] Referring to Figure 5, the data write circuit 200 is reused as the first reset circuit 300. For example, referring to Figure 6, the data write transistor T1 is reused as the first reset transistor; the data scan signal G1 is reused as the first reset control signal, and the data signal terminal Vdata is reused as the first reset signal terminal Vref1, and is configured to receive the data signal Vdata and the first reset signal Vref1 respectively in different time periods.

[0121] For example, in the initial stage P1 and the data writing stage P2, the data scanning signal G1 is an on signal to turn on the data writing circuit 200, for example, to keep the data writing transistor T1 turned on, and the data signal terminal Vdata receives the first reset signal Vref1 in the initial stage P1 and receives the data signal Vdata in the data writing stage P2.

[0122] Specifically, referring to Figures 5 and 7, in the initial stage P1, the data scan signal G1 is an on signal to turn on the data write circuit 200. The data write circuit 200 functions as the first reset circuit 300. The data signal terminal Vdata receives the first reset signal Vref1, and the first reset signal Vref1 is applied to the second terminal 100b of the driving circuit 100 via the data write circuit 200. For example, for the pixel circuit shown in Figure 6, in the initial stage P1, the data scan signal G1 is an on signal to turn on the data write transistor T1. The data write transistor T1 functions as the first reset transistor. The data signal terminal Vref1 receives the first reset signal Vref1, and the first reset signal Vref1 is applied to the second electrode of the driving transistor DT, that is, to the third node N3, via the data write transistor T1.

[0123] 5 and 7 , in the data writing phase P2, the data scanning signal G1 is an on signal to turn on the data writing circuit 200, the data signal terminal Vref1 receives the data signal Vdata, and the data signal Vdata is written into the second terminal 100b of the driving circuit 100 via the data writing circuit 200. For example, for the pixel circuit shown in FIG6 , in the data writing phase P2, the data scanning signal G1 is an on signal to turn on the data writing transistor T1, the data signal terminal Vdata receives the data signal Vdata, and the data signal Vdata is written into the second electrode of the driving transistor DT, that is, into the third node N3, via the data writing transistor T1.

[0124] The other signals and operating processes during the initialization phase P1 and the data writing phase P2 are identical to those of the pixel circuits shown in Figures 1-3 . The operating processes during the subsequent compensation phase and the light-emitting phase are also identical to those of the pixel circuits shown in Figures 1-3 . The pixel circuits and their driving methods shown in Figures 5-7 , as well as the other unmentioned structures, operating processes in each phase, and compensation principles, are identical to those of the pixel circuits shown in Figures 1-3 . Please refer to the previous descriptions and will not be repeated here.

[0125] Figure 8 is a schematic block diagram of another pixel circuit provided in at least one embodiment of the present disclosure; Figure 9 is a circuit diagram of a specific example of the pixel circuit shown in Figure 8; and Figure 10 is a signal timing diagram of a driving method for the pixel circuit shown in Figures 8-10, provided in at least one embodiment of the present disclosure. The structure and driving method of the pixel circuit shown in Figures 8-10 differ from the pixel circuit shown in Figures 1-3 in the following ways.

[0126] Compared with the pixel circuit shown in FIG. 1-FIG . 2 , the first reset circuit 300 is removed from the pixel circuit 10 shown in FIG. 8-FIG . 9 .

[0127] For the pixel circuit 10 and its driving method shown in Figures 8-9, the method for resetting the third node N3 during the initial phase P1 differs from that shown in Figures 1-3. Referring to Figures 8 and 9, during the initial phase P1, the second light-emission control signal EM2 is an on signal, thereby turning on the second light-emission control circuit 700. Furthermore, the second reset control signal G3 is an on signal, thereby turning on the second reset circuit 500. Consequently, the second reset signal Vini is applied to the first electrode 400a of the light-emitting element 400, i.e., the fourth node N4, via the second reset circuit 500. Furthermore, the second reset signal Vini is applied to the second terminal 100b of the driving circuit 100, i.e., the third node N3, via the second light-emission control circuit 700, thereby resetting various locations. For example, for the pixel circuit 10 shown in Figure 9, during the initial phase P1, the second reset signal Vini is applied to the second electrode of the driving transistor DT, i.e., the third node N3, via the turned-on second light-emission control circuit 700. The pixel circuit shown in FIG1-2 can achieve the same or similar technical effects. During the operation of the pixel circuit, the characteristic that the voltage of the first plate and the second plate of the compensation capacitor C1 cannot suddenly change can be utilized to better maintain the potential of the third node N3 at the second reset voltage Vini in the initial stage P1, and prevent the voltage of the third node N3 from jumping during the operation of the pixel circuit, thereby avoiding the adverse effects of the potential jump of the third node N3 on the display uniformity and stability. Specifically, for example, at the end of the initial stage P1, the potential of the third node N3 is the second reset voltage Vini. When entering the data writing stage P2, when the data signal Vdata is written to the third node N3 through the data writing circuit 200, the compensation capacitor C1 can be used to avoid the potential jump of the third node N3. Moreover, at the end of the data writing stage P2, the data writing transistor T1 is turned off, and the auxiliary storage capacitor C2 can also be used to avoid the potential jump of the third node N3. Thus, it is possible to at least avoid the potential jumps at the third node N3 at these time points that are very likely to cause the potential of the third node N3 to jump, thereby preventing the potential of the third node N3 from jumping, and improving the uniformity and stability of the light emission of the pixel driven by the pixel circuit 10. The pixel circuit and its driving method shown in Figures 8 and 9, as well as other unmentioned structures, other working processes at various stages, and compensation principles, are the same as those of the pixel circuit shown in Figures 1 to 3. Please refer to the previous description and will not be repeated here.

[0128] Figure 11 is a schematic block diagram of another pixel circuit according to at least one embodiment of the present disclosure; Figure 12 is a circuit diagram of a specific example of the pixel circuit shown in Figure 11; and Figure 13 is a signal timing diagram of a driving method for the pixel circuits shown in Figures 11 and 12 according to at least one embodiment of the present disclosure. The structure and driving method of the pixel circuits shown in Figures 11-13 differ from those shown in Figures 8-9 in the following ways.

[0129] 11 , for example, pixel circuit 10 further includes an auxiliary storage circuit 001. A first terminal 001a of auxiliary storage circuit 001 is electrically connected to a second terminal 100b of driver circuit 100. A second terminal 100b of auxiliary storage circuit 001 is electrically connected to a first reset signal terminal Vref1 to receive the first reset signal Vref1. Auxiliary storage circuit 001 is configured to maintain the potential of second terminal 100b of driver circuit 100. Referring to 8-9 , auxiliary storage circuit 001 includes an auxiliary storage capacitor C2. A first plate of auxiliary storage capacitor C2 is electrically connected to second terminal 100b of driver circuit 100, and a second plate of auxiliary storage capacitor C2 is electrically connected to first reset signal terminal Vref1.

[0130] With reference to Figures 11 and 12, for example, the auxiliary storage circuit 001 includes an auxiliary storage capacitor C2. The first plate of the auxiliary storage capacitor C2 is electrically connected to the second electrode of the drive transistor DT, that is, to the third node N3. The second plate of the auxiliary storage capacitor C2 is electrically connected to the first reset signal terminal Vref1. In this way, the auxiliary storage capacitor C can be used to prevent potential jumps at the third node N3, thereby preventing the adverse effects of potential jumps at the third node N3 on display uniformity and stability.

[0131] As shown in FIG13 , the driving method and timing of the pixel circuit can be the same as the driving method and timing of the pixel circuit shown in FIG8-FIG10 above. Referring to FIG11 and FIG13 , in the initial stage P1, the second light-emitting control signal EM2 is an on signal, so that the second light-emitting control circuit 700 is turned on, and the second reset control signal G3 is an on signal, so that the second reset circuit 500 is turned on. As a result, the second reset signal Vini is applied to the first electrode 400a of the light-emitting element 400, i.e., the fourth node N4, through the second reset circuit 500. The second reset signal Vini is then applied to the second terminal 100b of the driving circuit 100, i.e., the third node N3, through the second light-emitting control circuit 700, thereby resetting each position. For example, for the pixel circuit 10 shown in FIG12 , in the initial stage P1, the second reset signal Vini is applied to the second electrode of the driving transistor DT, i.e., the third node N3, through the turned-on second light-emitting control circuit 700. During the operation of the pixel circuit 10, the voltage of the first and second plates of the auxiliary storage capacitor C2 cannot suddenly change, which can effectively maintain the potential of the third node N3 at the second reset voltage Vini during the initial phase P1. This prevents the voltage of the third node N3 from jumping during the operation of the pixel circuit, thereby avoiding the adverse effects of the third node N3 potential jump on display uniformity and stability. Specifically, for example, at the end of the initial phase P1, the potential of the third node N3 is at the second reset voltage Vini. When entering the data writing phase P2 and writing the data signal Vdata to the third node N3 via the data writing circuit 200, the auxiliary storage capacitor C2 can be used to prevent the third node N3 potential from jumping. Furthermore, at the end of the data writing phase P2, the data writing transistor T1 is turned off, and the auxiliary storage capacitor C2 can also be used to prevent the third node N3 potential from jumping. Thus, at least at these time points that are particularly prone to causing the third node N3 potential jump, the third node N3 potential jump can be prevented, thereby improving the uniformity and stability of the light emission of the pixel driven by the pixel circuit 10.

[0132] The pixel circuits and driving methods shown in Figures 11-13 and other unmentioned structures, other working processes in various stages, and compensation principles are the same as those of the pixel circuits shown in Figures 8-10. Please refer to the previous description and will not repeat them here.

[0133] Figure 14 is a schematic block diagram of another pixel circuit according to at least one embodiment of the present disclosure; Figure 15 is a circuit diagram of a specific example of the pixel circuit shown in Figure 14; and Figure 16 is a signal timing diagram of a driving method for the pixel circuits shown in Figures 14 and 15 according to at least one embodiment of the present disclosure. The structures and driving methods of the pixel circuits shown in Figures 14-16 differ from those shown in Figures 1-3 in the following ways.

[0134] 14 and 16 , the first reset circuit 300 is reused as the second reset circuit 500, and the first reset signal terminal Vref1 is reused as the second reset signal terminal Vini, that is, the two are the same common signal terminal, and the common signal terminal is configured to receive the first reset signal Vref1 and the second reset signal Vini respectively at different time periods, so as to write the first reset signal Vref1 and the second reset signal Vini to specific locations respectively at different specific time periods. For example, in the initial stage P1, the first reset control signal G2 is a turn-on signal and the second light-emitting control signal EM2 is also a turn-on signal, for example, a high-voltage signal, so that the first reset circuit 300 and the second light-emitting control circuit 700 are both turned on, and the first reset signal terminal Vref1 (that is, the above-mentioned common signal terminal) receives the first reset signal Vref1. The first reset signal Vref1 is written into the second terminal 100b (the third node N3) of the driving circuit 100 through the first reset circuit 300, and is written into the first electrode 400a (the fourth node N4) of the light-emitting element 400 through the second light-emitting control circuit 700, so as to use the first reset signal Vref1 to complete the resetting of the second terminal 100b of the driving circuit 100 and the first electrode 400a of the light-emitting element 400.

[0135] In the data writing stage P2, the first reset signal G2 and the second light-emitting control signal EM2 are both shut-off signals, for example, low-voltage signals, so that the first reset circuit 300 and the second light-emitting control circuit 700 are turned off, and the data signal Vdata is written into the third node N3. The writing process of the data signal Vdata is the same as that of the embodiment shown in Figures 1-3.

[0136] In the compensation phase P3, the first reset signal G2 and the second light-emitting control signal EM2 are both on signals, so as to turn on the first reset circuit 300 and the second light-emitting control circuit 700 again. The first reset signal terminal Vref1 (i.e., the common signal terminal) receives the second reset signal Vini, and the second reset signal Vini is written into the second terminal 100b (the third node N3) of the driving circuit 100 through the first reset circuit 300. In this way, the potential V N3 Meet V N3 =Vini, the potential of the gate G of the driving transistor DT is maintained at the potential at the end of the data writing phase P2, so that the potential of the third node N3 at this moment and the potential of the gate G of the driving transistor DT are used to participate in the compensation calculation of the threshold voltage of the driving transistor DT.

[0137] In the light emitting phase P4 , the first reset signal G2 is a turn-off signal, and the operation process and compensation principle of the pixel circuit are the same as those of the embodiment shown in FIG. 1-3 .

[0138] Specifically, in the pixel circuit 10 shown in FIG15 , the first reset transistor T4 is multiplexed as the second reset transistor T6, the first reset control signal G2 is multiplexed as the second reset control signal G3, and the first reset signal terminal Vref1 is multiplexed as the second reset signal terminal Vini. In the initial stage P1, the first reset control signal G2 is an on-state signal, and the second light-emission control signal EM2 is an on-state signal, for example, a high-voltage signal, so that the first reset transistor T4 and the second light-emission control transistor T5 are both turned on. The first reset signal terminal Vref1 (i.e., the common signal terminal) receives the first reset signal Vref1. The first reset signal Vref1 is written into the second electrode (third node N3) of the driving transistor DT through the first reset circuit 300 and into the first electrode 400a (fourth node N4) of the light-emitting element 400 through the second light-emission control transistor T5, thereby resetting the second electrode of the driving transistor DT and the first electrode 400a of the light-emitting element 400 using the first reset signal Vref1.

[0139] In the data writing stage P2, the first reset signal G2 and the second light-emitting control signal EM2 are both shut-off signals, for example, low-voltage signals, so that the first reset transistor T4 and the second light-emitting control transistor T5 are turned off, and the data signal Vdata is written into the third node N3. The writing process of the data signal Vdata is the same as that of the embodiment shown in Figures 1-3.

[0140] In the compensation phase P3, the first reset signal G2 and the second light-emitting control signal EM2 are both on signals, so as to turn on the first reset transistor T4 and the second light-emitting control transistor T5 again. The first reset signal terminal Vref1 (i.e., the common signal terminal) receives the second reset signal Vini, and the second reset signal Vini is written into the second electrode (third node N3) of the driving transistor DT through the first reset transistor T4. In this way, the potential V N3 Meet V N3 =Vini, that is, the potential of the second plate of the compensation capacitor C1 becomes Vini, and the potential of the gate G of the driving transistor DT is maintained at the potential at the end of the data writing phase P2, so that the potential of the third node N3 and the potential of the gate G of the driving transistor DT at this moment are used to participate in the compensation calculation of the threshold voltage of the driving transistor DT.

[0141] In the light emitting phase P4, the first reset signal G2 is a shutdown signal to turn off the first reset transistor T4. Other control signals, working states of other transistors, and the working process and compensation principle of the pixel circuit are the same as those of the embodiments shown in Figures 1 to 3.

[0142] The pixel circuits shown in Figures 14 to 16 and the driving methods thereof, other unmentioned structures, other working processes at various stages, compensation principles for threshold voltage, and corresponding technical effects are the same as those of the pixel circuits shown in Figures 1 to 3. Please refer to the previous description and will not repeat them here.

[0143] Figure 17 is a schematic block diagram of another pixel circuit according to at least one embodiment of the present disclosure; Figure 18 is a circuit diagram of a specific example of the pixel circuit shown in Figure 17; and Figure 19 is a signal timing diagram of a driving method for the pixel circuit shown in Figures 17 and 18 according to at least one embodiment of the present disclosure. The structure and driving method of the pixel circuit shown in Figures 17 to 19 differ from those of the pixel circuit shown in Figures 1 to 3 in the following ways.

[0144] 14 and 17 , based on the pixel circuit shown in FIG1 , the pixel circuit 10 further includes a third reset circuit 002, the control end of the third reset circuit 002 being configured to receive a third reset control signal G6, the first end of the third reset circuit 002 being electrically connected to the first end 100 a of the driving circuit 100, the second end of the third reset circuit 002 being electrically connected to the third reset signal end Vref2 to receive the third reset signal Vref2, and the third reset circuit 002 being configured to apply the third reset signal Vref2 to the first end 100 a of the driving circuit 100 in response to the third reset control signal G6.

[0145] Based on the driving method of the pixel circuit shown in Figures 1-3, with reference to Figures 17 and 19, the driving method of the pixel circuit further includes: in an initial stage P1, the third reset control signal G6 is set to an on signal to turn on the third reset circuit 002, and the third reset signal Vref2 is applied to the first terminal 100a of the driving circuit 100 through the third reset circuit 002. In this way, in the initial stage P1, the third reset signal Vref2 is used to reset the first node N1 and the control terminal 100m of the driving circuit 100.

[0146] Referring to Figures 17 and 19 , the pixel circuit driving method further includes: in an initial phase P1, setting the first light-emitting control signal EM1 to an off signal to shut down the first light-emitting control circuit 600, thereby preventing the first power supply voltage VDD from being written to the first node N1 and the control terminal 100m of the driver circuit 100. For example, the third reset signal is a reset voltage Vref2, which is lower than the first power supply voltage VDD. That is, the voltage value of the third reset signal Vref2 can be lower than the voltage value of the first power supply voltage VDD. For example, the voltage value of the third reset signal Vref2 is higher than the data voltage Vdata. Thus, similar to the data writing phase P2 shown in Figures 1-3 , in the subsequent data writing phase P2, the control terminal 100m of the driver circuit 100 discharges to the third node N3 through the first compensation circuit 800 and the driver circuit 100. Thus, by providing the third reset circuit 002, during the initial phase P1, the third reset signal Vref2 is used to reset the first node N1 and the control terminal 100m of the driver circuit 100. This facilitates discharge of the control terminal 100m of the driver circuit 100 to the third node N3 via the first compensation circuit 800 and the driver circuit 100 during the subsequent data writing phase P2, thereby improving the reliability of the pixel circuit in achieving the designed operating process and producing a more ideal driving effect. For example, if the first power supply voltage VDD is 10V, the third reset signal Vref2 can be 4V, 5V, 6V, etc. Of course, the specific voltage values ​​of the two are not limited to the values ​​listed here, and are merely examples.

[0147] The driving method of the pixel circuit also includes: making the third reset control signal G6 an off signal in other stages (data writing stage P2, compensation stage P3 and light emitting stage P4) so ​​that the third reset circuit 002 is turned off. As a result, the third reset circuit 002 will not affect the normal operation of the pixel circuit in other stages.

[0148] As shown in Figure 18, for example, the third reset circuit 002 includes a third reset transistor T8, the gate of the third reset transistor T8 is configured to receive the third reset control signal G6, the first electrode of the third reset transistor T8 is electrically connected to the first electrode of the first compensation transistor T3 and the first electrode of the driving transistor DT, and the first electrode of the third reset transistor T8 is electrically connected to the third reset signal terminal Vref2 to receive the third reset signal Vref2.

[0149] 18 and 19 , the driving method of the pixel circuit further includes: in an initial stage P1, setting the third reset control signal G6 to an on signal to turn on the third reset circuit 002, and applying the third reset signal Vref2 to the first electrode of the driving transistor DT via the third reset circuit 002. Thus, in the initial stage P1, the first node N1 and the gate G of the driving transistor are reset using the third reset signal Vref2.

[0150] For example, referring to Figures 18 and 19 , the driving method of the pixel circuit further includes: during the initial phase P1, setting the first emission control signal EM1 to an off signal, thereby turning off the first emission control transistor T2, thereby preventing the first power supply voltage VDD from being written to the first node N1 and the gate G of the driving transistor. The driving method of the pixel circuit further includes: during the initial phase P1, setting the first emission control signal EM1 to an off signal, thereby turning off the first emission control transistor T2, thereby preventing the first power supply voltage VDD from being written to the first node N1 and the gate G of the driving transistor DT. For example, the third reset signal Vref2 can be lower than the first power supply voltage VDD. Thus, by providing the third reset circuit 002, the first node N1 and the gate G of the driving transistor DT are reset using the third reset signal Vref2 during the initial phase P1. This facilitates discharge of the gate G of the driving transistor DT to the third node N3 via the first compensation transistor T3 and the driving transistor DT during the subsequent data writing phase P2, thereby improving the reliability of the pixel circuit in implementing the designed operation process and producing a more ideal driving effect.

[0151] The driving method of the pixel circuit shown in Figure 18 also includes: making the third reset control signal G6 an off signal in other stages (data writing stage P2, compensation stage P3 and light-emitting stage P4) so ​​that the third reset circuit 002 is turned off. Therefore, the third reset circuit 002 will not affect the normal operation of the pixel circuit in other stages.

[0152] The other structures and driving methods not mentioned in the pixel circuit shown in Figure 18, the compensation principle for the threshold voltage and the corresponding technical effects are the same as those of the pixel circuit shown in Figures 1 to 3. Please refer to the previous description and will not be repeated here.

[0153] Figure 20 is a circuit diagram of another pixel circuit provided in at least one embodiment of the present disclosure; Figure 21 is a signal timing diagram of a driving method for the pixel circuit shown in Figure 20 provided in at least one embodiment of the present disclosure. The structures and driving methods of the pixel circuits shown in Figures 20 and 21 differ from those shown in Figures 2 and 3 in the following ways.

[0154] Referring to FIG. 20 , for example, the gate of the first compensation transistor T3 and the gate of the second reset transistor T6 are connected to the same gate line, i.e., the first compensation transistor T3 and the second reset transistor T6 share a gate, and the second reset control signal G3 and the first compensation control signal G4 are the same gate scan signal. For example, the first compensation transistor T3 and the second reset transistor T6 are of the same type, and both are N-type transistors. Of course, in other embodiments, both can also be P-type transistors. The types of the on and off signals can be adjusted accordingly to ensure the operating states (on or off) of the two transistors in the following process.

[0155] Referring to FIG21 , in the compensation phase P3, the first compensation control signal G4 needs to be an off signal, so that the second reset control signal G3 is also an off signal; at this time, the first reset signal G2 and the second light-emitting control signal EM2 are both on signals, so that the first reset transistor T4 and the second light-emitting control transistor T5 are turned on, and the first reset signal terminal Vref1 (i.e., the above-mentioned common signal terminal) receives the second reset signal Vini, and the second reset signal Vini is written into the second electrode (third node N3) of the driving transistor DT through the first reset transistor T4. In this way, the potential V N3 Meet V N3 =Vini, that is, the potential of the second plate of the compensation capacitor C1 becomes Vini, and the potential of the gate G of the driving transistor DT is maintained at the potential at the end of the data writing phase P2, so that the potential of the third node N3 and the potential of the gate G of the driving transistor DT at this moment are used to participate in the compensation calculation of the threshold voltage of the driving transistor DT.

[0156] The other unmentioned structures and driving methods, threshold voltage compensation principles and corresponding technical effects of the pixel circuits shown in Figures 20 and 21 are the same as those of the pixel circuits shown in Figures 1 and 2. Please refer to the previous description and will not be repeated here.

[0157] Figure 22 is a circuit diagram of another specific example of the pixel circuit shown in Figure 1 ; Figure 23 is a signal timing diagram of a driving method for the pixel circuit shown in Figure 22 . The structure and driving method of the pixel circuit shown in Figure 22 differ from those shown in Figures 2-3 in the following ways.

[0158] 22 , the second compensation circuit 900 includes a compensation capacitor C1, a first plate of the compensation capacitor C1 being electrically connected to the gate of the driving transistor DT, and a second plate of the compensation capacitor C1 being electrically connected to the first electrode of the light emitting element 400. For example, the second compensation circuit 900 does not include a transistor.

[0159] For example, the first plate of the compensation capacitor C1 is electrically connected to the gate of the driving transistor DT, that is, there is no other switching element between the second plate of the compensation capacitor C1 and the first electrode of the light-emitting element 400; for example, the second plate of the compensation capacitor C1 is directly electrically connected to the first electrode of the light-emitting element 400, that is, there is no other switching element between the first plate of the compensation capacitor C1 and the gate of the driving transistor DT.

[0160] For example, the driving method and operation process of the pixel circuit shown in FIG22 are different from those shown in FIG1-3 in the following ways.

[0161] During the operation of the pixel circuit shown in FIG22 , there is no second compensation control signal.

[0162] 22 and 23 , the control signals other than the second compensation control signal and the related driving steps and the working processes of the initial phase P1 and the data writing phase P2 are the same as those shown in FIG. 1-3 .

[0163] 22 and 23 , in the compensation phase P3, the second reset control signal G3 is set to be an on signal, and the first light-emitting control signal EM1 is set to be an off signal. The second reset signal Vini is written to the first electrode 400a of the light-emitting element 400 via the second reset circuit 500 (e.g., via the second reset transistor T6), that is, the second reset signal Vini is written to the fourth node N4, that is, the second reset signal Vini is written to the second plate of the compensation capacitor C1, so that the potential V of the first electrode of the light-emitting element 400 is lowered to 0. N4 Meet V N4 =Vini; and, in the compensation phase P3, the compensation capacitor C1 can be used to maintain the potential of the control terminal 100m of the driving circuit 100 at the potential at the end of the data writing phase P2. Since the second plate of the compensation capacitor C1 is directly electrically connected to the fourth node N4, as long as V N4 =Vini, the threshold voltage can be compensated later, without having to write the second reset signal Vini to the third node N3 during the compensation phase P3. Therefore, during the compensation phase P3, the second light-emitting control signal EM2 can be an off signal (as shown in FIG22), and the second reset signal Vini is not written to the third node N3 during the compensation phase P3. This still does not affect the threshold voltage compensation and can simplify the driving method of the pixel circuit. Alternatively, in other embodiments, the second light-emitting control signal EM2 can also be an on signal to turn on the second light-emitting control circuit 700, so that the second reset signal Vini is written to the third node N3 via the second light-emitting control circuit 700. For example, the second light-emitting control signal EM2 is an on signal to turn on the second light-emitting control transistor T5, and the second reset signal Vini is written to the third node N3 via the second light-emitting control transistor T5.

[0164] For example, for the pixel circuit 10 shown in Figure 22, in the light-emitting stage P4, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are both turn-on signals, for example, high-voltage signals, so that the first light-emitting control transistor T2 and the second light-emitting control transistor T5 are turned on, and the data scanning signal G1, the first reset control signal G2, the second reset control signal G3 and the first compensation control signal G4 are all turn-off signals, for example, low-voltage signals, so that the data writing transistor T1, the first reset transistor T4, the second reset transistor T6 and the first compensation transistor T3 are all turned off, and finally the driving transistor DT is turned on, the first power supply voltage VDD is applied to the first electrode of the driving transistor DT, and the driving current is applied to the light-emitting element 400 via the second light-emitting control transistor T5 to make it emit light.

[0165] In the light-emitting stage P4, the compensation capacitor C1 can play a self-bootstrapping role and change the potential of the gate G of the driving transistor DT electrically connected to the first plate of the compensation capacitor C1 and the fourth node N4 electrically connected to the second plate of the compensation capacitor C1 by the same amount, thereby achieving compensation for the threshold voltage of the driving transistor DT. Specifically, in the light-emitting stage P4, since the light-emitting element 400 is in the light-emitting state, the voltage value of the first electrode of the light-emitting element 400 (that is, the voltage value of the fourth node N4) and the voltage value of the second electrode of the driving transistor DT both correspond to the voltage value Voled when the light-emitting element 400 emits light, that is, the voltage value of the first electrode of the light-emitting element 400 (that is, the fourth node N4) is Voled; since the second light-emitting control circuit 700 is turned on, the voltage value of the second plate of the compensation capacitor C1 is also Voled at this moment, so the change in the voltage value of the second plate of the compensation capacitor C1 △V N4 =Voled-Vini. Accordingly, the compensation capacitor C1 plays a self-bootstrapping role, so that the first plate of the compensation capacitor C1 also has a variation ΔV N4 =Voled-Vini, thereby making the voltage value of the gate G of the driving transistor DT (the voltage value of the second node N2) have a change amount ΔV N4 The voltage value of the gate G of the driving transistor DT is V G represents, then V G =Vdata+Vth+Voled-Vini. The driving transistor DT is in the on state, and the gate-source voltage of the driving transistor DT is V GS Representative, then V GS =V G -V N4 =(Vdata+Vth+Voled-Vini)-Voled=Vdata+Vth-Vini.

[0166] The value of the driving current I flowing through the light-emitting element can be obtained according to the following formula:

[0167] I=K×(V GS -Vth) 2 , K is the conductivity coefficient of the driving transistor DT. That is: I=K*(Vdata-Vini) 2

[0168] According to the above formula, the value I of the driving current flowing through the light-emitting element is no longer related to the threshold voltage Vth of the driving transistor DT. This can compensate for the pixel circuit, solve the problem of threshold voltage Vth drift of the driving transistor DT due to process technology and long-term operation, and eliminate its influence on the driving current, thereby improving the display effect of the display device using this pixel circuit.

[0169] The other unmentioned structures and driving methods, threshold voltage compensation principles and corresponding technical effects of the pixel circuits shown in Figures 22-23 are the same as those of the pixel circuits shown in Figures 1-3. Please refer to the previous description and will not be repeated here.

[0170] FIG24 is a circuit diagram of another specific example of the pixel circuit shown in FIG17 . The pixel circuit shown in FIG24 differs from the pixel circuit shown in FIG23 in the following ways: In addition to the pixel circuit shown in FIG22 , the pixel circuit shown in FIG24 further includes the aforementioned third reset circuit, which includes a third reset transistor T8 , the gate of which is configured to receive a third reset control signal G6 , a first electrode of the third reset transistor T8 electrically connected to the first electrode of the first compensation transistor T3 and the first electrode of the drive transistor DT, and a first electrode of the third reset transistor T8 electrically connected to a third reset signal terminal Vref2 to receive the third reset signal Vref2 .

[0171] The application method of the third reset control signal G6, the operation process of the third reset transistor T8, and the function thereof are the same as those shown in FIG18 , and reference is made to the previous description. The driving method of the pixel circuit shown in FIG24 is the same as that of the pixel circuit shown in FIG22 above, with the addition of the operation process of the third reset transistor T8, and will not be repeated here.

[0172] The other structures and driving methods not mentioned in the pixel circuit shown in Figure 24, the compensation principle for the threshold voltage and the corresponding technical effects are the same as those of the pixel circuit shown in Figures 22 and 23. Please refer to the previous description and will not be repeated here.

[0173] For example, when the second compensation circuit 900 includes the compensation capacitor C1 shown in FIG. 22 , it can be combined with non-contradictory features in other embodiments to obtain a new embodiment.

[0174] At least one embodiment of the present disclosure further provides a display device, which includes any pixel circuit provided by the embodiments of the present disclosure.

[0175] Figure 25 is a schematic block diagram of a display device provided by at least one embodiment of the present disclosure. As shown in Figure 25, a display device 1000 includes any of the pixel circuits 10 provided by the embodiments of the present disclosure. The display device 1000 may be, for example, an organic light-emitting diode display device, a quantum dot light-emitting diode display device, or other device with display functionality. The embodiments of the present disclosure are not limited thereto.

[0176] The other structures and functions of the display device 1000 provided in the embodiment of the present disclosure can be implemented with reference to conventional technologies, and the embodiment of the present disclosure does not limit this. The technical effects of the display device 01 provided in the embodiment of the present disclosure can refer to the above description of the technical effects of the pixel circuit provided in the embodiment of the present disclosure, and will not be repeated here.

[0177] For example, the display device 1000 provided in at least one embodiment of the present disclosure may be any product or component with a display function, such as a display panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator, and the embodiments of the present disclosure are not limited thereto.

[0178] There are a few points to note:

[0179] (1) The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can refer to general designs.

[0180] (2) In the absence of conflict, features in the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0181] The foregoing description is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. The scope of protection of the present disclosure is determined by the scope defined in the claims.

Claims

1. A pixel circuit, comprising: a driving circuit including a control terminal, a first terminal, and a second terminal, and configured to control a magnitude of a driving current flowing through the first terminal and the second terminal; a data writing circuit, wherein a first terminal of the data writing circuit is electrically connected to the second terminal of the driving circuit, a second terminal of the data writing circuit is configured to receive a data signal, and the data writing circuit is configured to write the data signal into the second terminal of the driving circuit in response to a data scanning signal during a data writing stage; a first compensation circuit having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first compensation circuit is configured to receive a first compensation control signal, the first terminal of the first compensation circuit is electrically connected to the first terminal of the driving circuit, the second terminal of the first compensation circuit is electrically connected to the control terminal of the driving circuit, and the first compensation circuit is configured to control whether the control terminal of the driving circuit and the first terminal of the driving circuit are conducted through the first compensation circuit in response to the first compensation control signal; and a second compensation circuit including a compensation capacitor, wherein a first electrode plate of the compensation capacitor is electrically connected to the control terminal of the driving circuit.

2. The pixel circuit according to claim 1, wherein the first compensation circuit and the second compensation circuit are configured to allow a potential of the control terminal of the driving circuit to change in response to a change in a potential of the second terminal of the driving circuit during the data writing stage, and are configured to maintain the potential of the control terminal of the driving circuit during a compensation stage after the data writing stage and not allow the potential of the control terminal of the driving circuit to change in response to a change in the potential of the second terminal of the driving circuit.

3. The pixel circuit according to claim 1 or 2, wherein the driving circuit includes a driving transistor, a gate of the driving transistor serves as the control terminal of the driving circuit, a first pole of the driving transistor serves as the first terminal of the driving circuit, a second pole of the driving transistor serves as the second terminal of the driving circuit, and the first terminal of the driving circuit is electrically connected to a first power supply voltage terminal to receive a first power supply voltage; the pixel circuit further includes a light emitting element configured to emit light under the drive of the driving current, the second terminal of the driving circuit is electrically connected to a first electrode of the light emitting element, the driving circuit is configured to control a magnitude of the driving current flowing through the light emitting element; the first compensation circuit includes a first compensation transistor, a gate of the first compensation transistor receives the first compensation control signal, a first pole of the first compensation transistor is electrically connected to the first pole of the driving transistor, and a second pole of the first compensation transistor is electrically connected to the gate of the driving transistor.

4. The pixel circuit according to claim 3, wherein The second compensation circuit further includes a second compensation transistor. The gate of the second compensation transistor receives a second compensation control signal. A first pole of the second compensation transistor is electrically connected to the gate of the driving transistor. A second pole of the second compensation transistor is electrically connected to a first plate of the compensation capacitor, such that the first plate of the compensation capacitor is electrically connected to the gate of the driving transistor through the second compensation transistor. A second plate of the compensation capacitor is electrically connected to a second pole of the driving transistor.

5. The pixel circuit according to claim 3, wherein, the first plate of the compensation capacitor is electrically connected to the gate of the driving transistor, and the second plate of the compensation capacitor is electrically connected to a first electrode of the light-emitting element.

6. The pixel circuit according to any one of claims 1-5, wherein, the pixel circuit further includes a first reset circuit. A control end of the first reset circuit is configured to receive a first reset control signal. A first end of the first reset circuit is electrically connected to a second end of the driving circuit. A second end of the first reset circuit is electrically connected to a first reset signal terminal to receive a first reset signal. The first reset circuit is configured to write the first reset signal to the second end of the driving circuit in response to the first reset control signal.

7. The pixel circuit according to claim 6, wherein, the first reset circuit includes a first reset transistor. The gate of the first reset transistor is electrically connected to the first reset control end to receive the first reset control signal. A first pole of the first reset transistor is electrically connected to the second end of the driving circuit. A second pole of the first reset transistor is electrically connected to the first reset signal terminal to receive the first reset signal; the data writing circuit includes a data writing transistor. The gate of the data writing transistor is configured to receive the data scanning signal. A first pole of the data writing transistor is electrically connected to the second end of the driving circuit. A second pole of the data writing transistor is electrically connected to a data signal terminal to receive the data signal; the data writing transistor and the first reset transistor are different transistors independent of each other, and the data signal terminal and the first reset signal terminal are different signal terminals independent of each other; or, the data writing transistor is reused as the first reset transistor, the data scanning signal is reused as the first reset control signal, the data signal terminal is reused as the first reset signal terminal, and is configured to receive the data signal and the first reset signal respectively in different time periods.

8. The pixel circuit according to any one of claims 1-7, wherein, the pixel circuit further includes an auxiliary capacitor. A first plate of the auxiliary capacitor is electrically connected to the second end of the driving circuit. A second plate of the auxiliary capacitor is electrically connected to a first reset voltage terminal.

9. The pixel circuit according to any one of claims 1-8, wherein, The pixel circuit further includes a light-emitting element configured to emit light under the drive of the drive current. The second end of the drive circuit is electrically connected to the first electrode of the light-emitting element, and the drive circuit is configured to control the magnitude of the drive current flowing through the light-emitting element; The pixel circuit further includes a second reset circuit. The control end of the second reset circuit is configured to receive a second reset control signal. The first end of the second reset circuit is electrically connected to the first electrode of the light-emitting element. The second end of the second reset circuit is electrically connected to a second reset signal terminal to receive a second reset signal. The second reset circuit is configured to apply the second reset signal to the first electrode of the light-emitting element and / or the second plate of the compensation capacitor in response to the second reset control signal.

10. The pixel circuit according to any one of claims 1-8, wherein, The pixel circuit further includes a second reset circuit. The control end of the second reset circuit is configured to receive a second reset control signal. The first end of the second reset circuit is electrically connected to the second end of the drive circuit. The second end of the second reset circuit is electrically connected to a second reset signal terminal to receive a second reset signal. The second reset circuit is configured to apply the second reset signal to the second end of the drive circuit and / or the second plate of the compensation capacitor in response to the second reset control signal.

11. The pixel circuit according to claim 10, wherein, The first reset circuit includes a first reset transistor. The gate of the first reset transistor is electrically connected to the first reset control end to receive the first reset control signal. The first pole of the first reset transistor is electrically connected to the second end of the drive circuit. The second pole of the first reset transistor is electrically connected to the first reset signal terminal to receive the first reset signal; The second reset circuit includes a second reset transistor. The gate of the second reset transistor is electrically connected to the second reset control end to receive the second reset control signal. The first pole of the second reset transistor is electrically connected to the second end of the drive circuit. The second pole of the second reset transistor is electrically connected to the second reset signal terminal to receive the second reset signal; The first reset transistor is reused as the second reset transistor, the first reset control signal is reused as the second reset control signal, and the first reset signal terminal is reused as the second reset signal terminal and is configured to receive the first reset signal and the second reset signal respectively in different time periods; or, The second reset transistor and the first reset transistor are different transistors independent of each other, and the first reset signal terminal and the second reset signal terminal are different signal terminals independent of each other.

12. The pixel circuit according to any one of claims 1-11, wherein, The pixel circuit further includes a third reset circuit. A control end of the third reset circuit is configured to receive a third reset control signal. A first end of the third reset circuit is electrically connected to a first end of the driving circuit. A second end of the third reset circuit is electrically connected to a third reset signal terminal to receive a third reset signal. The third reset circuit is configured to apply the third reset signal to the first end of the driving circuit in response to the third reset control signal.

13. The pixel circuit according to claim 12, wherein, the third reset circuit includes a third reset transistor. A gate of the third reset transistor is configured to receive the third reset control signal. A first pole of the third reset transistor is electrically connected to a first pole of the first compensation transistor and the first end of the driving circuit. The first pole of the third reset transistor is electrically connected to the third reset signal terminal to receive the third reset signal.

14. The pixel circuit according to any one of claims 10-13, wherein, the first compensation circuit includes a first compensation transistor. A first pole of the first compensation transistor is electrically connected to the first end of the driving circuit. A second pole of the first compensation transistor is electrically connected to a driving end of the driving circuit; the second reset circuit includes a second reset transistor. A gate of the second reset transistor is electrically connected to a second reset control end to receive the second reset control signal. A first pole of the second reset transistor is electrically connected to a second end of the driving circuit. The second pole of the second reset transistor is electrically connected to the second reset signal terminal to receive the second reset signal; the gate of the first compensation transistor and the gate of the second reset transistor are connected to the same gate line. The second reset control signal and the first compensation control signal are the same gate scanning signal.

15. The pixel circuit according to any one of claims 10-13, wherein, the pixel circuit further includes a first light emission control circuit and a second light emission control circuit; a control end of the first light emission control circuit is configured to receive a first light emission control signal. A first end of the first light emission control circuit is electrically connected to the first end of the driving circuit. A second end of the first light emission control circuit is electrically connected to a first voltage terminal to receive a first power supply voltage. The first light emission control circuit is configured to apply the first power supply voltage to the first end of the driving circuit in response to the first light emission control signal; a control end of the second light emission control circuit is configured to receive a second light emission control signal, the second light emission control signal being different from the first light emission control signal. A first end of the second light emission control circuit is electrically connected to the second end of the driving circuit. A second end of the second light emission control circuit is electrically connected to a first electrode of the light emitting element. A second electrode of the light emitting element is electrically connected to a second voltage terminal to receive a second power supply voltage. The second light emission control circuit is configured to apply the driving current to the light emitting element in response to the second light emission control signal.

16. A display device includes the pixel circuit according to any one of claims 1-15.

17. A driving method for a pixel circuit, applicable to the pixel circuit according to any one of claims 1-15, the driving method comprises: In the data writing stage, making the data scanning signal an enabling signal to turn on the data writing circuit, and writing the data signal into the second end of the driving circuit through the data writing circuit. Moreover, by controlling the first compensation circuit and the second compensation circuit, the potential of the control end of the driving circuit changes in response to the change in the potential of the second end of the driving circuit; and In the compensation stage after the data writing stage, by controlling the first compensation circuit and the second compensation circuit to maintain the potential of the control end of the driving circuit, and not allowing the potential of the control end of the driving circuit to change in response to the change in the potential of the second end of the driving circuit.

18. The driving method for a pixel circuit according to claim 17, wherein, In the data writing stage, making the first compensation control signal an enabling signal so that the first compensation circuit conducts in response to the first compensation control signal. The control end of the driving circuit is conducted to the first end of the driving circuit via the first compensation circuit. Moreover, making the first end and the second end of the driving circuit conduct to generate a compensation current between the control end of the driving circuit and the second end of the driving circuit. The compensation current flows through the first compensation circuit and the driving circuit, so that the potential of the control end of the driving circuit changes in response to the change in the potential of the second end of the driving circuit; In the compensation stage, at least making the first compensation control signal a disabling signal to turn off the first compensation circuit, thereby not allowing a current to be generated between the control end of the driving circuit and the second end of the driving circuit, keeping the potential of the control end of the driving circuit unchanged, and not allowing the potential of the control end of the driving circuit to change in response to the change in the potential of the second end of the driving circuit.

19. The driving method for a pixel circuit according to claim 18, wherein, The driving circuit includes a driving transistor, the gate of the driving transistor serves as the control end of the driving circuit, the first pole of the driving transistor serves as the first end of the driving circuit, and the second pole of the driving transistor serves as the second end of the driving circuit; The first compensation circuit includes a first compensation transistor, the gate of the first compensation transistor receives the first compensation control signal, the first pole of the first compensation transistor is electrically connected to the first pole of the driving transistor, and the second pole of the first compensation transistor is electrically connected to the gate of the driving transistor; The second compensation circuit further includes a second compensation transistor, the gate of the second compensation transistor receives a second compensation control signal, a first pole of the second compensation transistor is electrically connected to the gate of the driving transistor, a second pole of the second compensation transistor is electrically connected to a first plate of the compensation capacitor such that the first plate of the compensation capacitor is electrically connected to the gate of the driving transistor through the second compensation transistor, and a second plate of the compensation capacitor is electrically connected to a second pole of the driving transistor; The pixel circuit further includes a light-emitting element configured to emit light under the drive of the drive current. Wherein, a second end of the drive circuit is electrically connected to a first electrode of the light-emitting element, and the drive circuit is configured to control the magnitude of the drive current flowing through the light-emitting element; A driving method of the pixel circuit includes: In the data writing stage, making both the first compensation control signal and the second compensation control signal be enabling signals so that the first compensation transistor and the second compensation transistor are both turned on to generate the compensation current; and In the compensation stage, turning off both the first compensation transistor and the second compensation transistor, to keep the potential of the control end of the drive circuit unchanged.

20. According to the driving method of the pixel circuit as claimed in claim 19, wherein, The control method of the pixel circuit further includes: In the initial stage, making the second compensation control signal be an enabling signal so that the second compensation transistor is turned on.

21. According to the driving method of the pixel circuit as claimed in claim 18, wherein, The drive circuit includes a driving transistor, the gate of the driving transistor serves as the control end of the drive circuit, a first pole of the driving transistor serves as the first end of the drive circuit, and a second pole of the driving transistor serves as the second end of the drive circuit; The first compensation circuit includes a first compensation transistor, the gate of the first compensation transistor receives the first compensation control signal, a first pole of the first compensation transistor is electrically connected to the first pole of the driving transistor, and a second pole of the first compensation transistor is electrically connected to the gate of the driving transistor; The pixel circuit further includes a light-emitting element configured to emit light under the drive of the drive current. Wherein, a second end of the drive circuit is electrically connected to a first electrode of the light-emitting element, and the drive circuit is configured to control the magnitude of the drive current flowing through the light-emitting element; A first plate of the compensation capacitor is electrically connected to the gate of the driving transistor, and a second plate of the compensation capacitor is electrically connected to a first electrode of the light-emitting element; The driving method includes: In the data writing stage, making the first compensation control signal be an enabling signal to turn on the first compensation transistor to generate the compensation current; and In the compensation stage, making the first compensation control signal be a disabling signal to turn off the first compensation transistor to keep the potential of the control end of the drive circuit unchanged.

22. According to the driving method of the pixel circuit as claimed in any one of claims 19-21, wherein, In the data writing phase, the potential of the control terminal of the driving circuit changes in response to the change of the potential of the second terminal of the driving circuit until the driving transistor is turned off. At the end of the data writing phase, the potential V G Meet V G =Vdata+Vth.

23. The driving method of the pixel circuit according to any one of claims 19-22, wherein, the first end of the driving circuit is connected to the first power supply voltage terminal to receive the first power supply voltage; the driving method further includes: in an initial stage before the data writing stage, making the first compensation control signal an enabling signal so that the first compensation circuit is turned on, and the first power supply voltage is applied to the driving end of the driving circuit through the first end of the driving circuit and the first compensation circuit in sequence to make one end and the second end of the driving circuit conduct.

24. The driving method of the pixel circuit according to claim 22, wherein, the pixel circuit further includes a first reset circuit, the control end of the first reset circuit is configured to receive a first reset control signal, the first end of the first reset circuit is electrically connected to the second end of the driving circuit, the second end of the first reset circuit is electrically connected to the first reset signal terminal to receive a first reset signal, and the first reset circuit is configured to write the first reset signal into the second end of the driving circuit in response to the first reset control signal; the pixel circuit further includes a second reset circuit, the control end of the second reset circuit is configured to receive a second reset control signal, the first end of the second reset circuit is electrically connected to the first electrode of the light-emitting element, the second end of the second reset circuit is electrically connected to the second reset signal terminal to receive a second reset signal, and the second reset circuit is configured to apply the second reset signal to the first electrode of the light-emitting element and the second plate of the compensation capacitor in response to the second reset control signal; the driving method includes: in the initial stage, making the first reset control signal, the second reset control signal, and the first compensation control signal all enabling signals, so that the first reset circuit is turned on to apply the first reset signal to the second end of the driving circuit, and the second reset circuit is turned on to apply the second reset signal to the first electrode of the light-emitting element.

25. The driving method of the pixel circuit according to claim 24, wherein, the pixel circuit further includes a first light-emitting control circuit and a second light-emitting control circuit; the control end of the first light-emitting control circuit is configured to receive a first light-emitting control signal, the first end of the first light-emitting control circuit is electrically connected to the first end of the driving circuit, and the second end of the first light-emitting control circuit is electrically connected to the first voltage terminal to receive the first power supply voltage; the control end of the second light-emitting control circuit is configured to receive a second light-emitting control signal, the second light-emitting control signal is different from the first light-emitting control signal, and the first end of the second light-emitting control circuit is electrically connected to the second end of the driving circuit; The second compensation circuit further includes a second compensation transistor. The gate of the second compensation transistor receives a second compensation control signal. The first pole of the second compensation transistor is electrically connected to the gate of the driving transistor. The second pole of the second compensation transistor is electrically connected to the first plate of the compensation capacitor, so that the first plate of the compensation capacitor is electrically connected to the gate of the driving transistor through the second compensation transistor. The second plate of the compensation capacitor is electrically connected to the second pole of the driving transistor; The driving method includes: In the compensation stage, the second light-emitting control signal and the second reset control signal are both turn-on signals, and the first light-emitting control signal is a turn-off signal, so that the second light-emitting control circuit and the second reset circuit are both turned on. The second reset signal is written into the second end of the driving circuit through the second light-emitting control circuit, so that the potential VN3 at the second end of the driving circuit satisfies VN3 = Vini. Wherein, in the compensation stage, the potential at the control end of the driving circuit remains the potential at the end of the data writing stage.

26. The driving method of the pixel circuit according to claim 24, wherein, The pixel circuit further includes a first light-emitting control circuit and a second light-emitting control circuit; the control end of the first light-emitting control circuit is configured to receive a first light-emitting control signal. The first end of the first light-emitting control circuit is electrically connected to the first end of the driving circuit. The second end of the first light-emitting control circuit is electrically connected to a first voltage terminal to receive a first power supply voltage; the control end of the second light-emitting control circuit is configured to receive a second light-emitting control signal, and the second light-emitting control signal is different from the first light-emitting control signal. The first end of the second light-emitting control circuit is electrically connected to the second end of the driving circuit; The pixel circuit further includes a light-emitting element configured to emit light under the drive of the drive current. The second end of the driving circuit is electrically connected to the first electrode of the light-emitting element. The driving circuit is configured to control the magnitude of the drive current flowing through the light-emitting element; The first plate of the compensation capacitor is electrically connected to the gate of the driving transistor, and the second plate of the compensation capacitor is electrically connected to the first electrode of the light-emitting element; The driving method includes: In the compensation stage, the second reset control signal is set to an enabling signal, and the first light-emitting control signal is a disabling signal. The second reset signal is written into the first electrode of the light-emitting element via the second reset circuit, so that the potential V of the first electrode of the light-emitting element N4 satisfies V N4 = Vini, where In the compensation stage, the potential at the control end of the driving circuit remains the potential at the end of the data writing stage.

27. The driving method of the pixel circuit according to claim 25 or 26, wherein, In the initial stage, the first light-emitting control signal is a turn-on signal to turn on the first light-emitting control circuit. The first power supply voltage is written into the first end of the driving circuit through the first light-emitting control circuit; and, In the data writing stage, both the first light-emitting control signal and the second light-emitting control signal are turn-off signals.

28. The driving method of the pixel circuit according to any one of claims 23-27, wherein, The data signal is a data voltage, and the first power supply voltage written in the initial stage is higher than the data voltage written in the data writing stage.

29. The driving method of the pixel circuit according to claim 24, wherein, the second reset control signal and the first compensation control signal are the same gate scanning signal.

30. The driving method of the pixel circuit according to any one of claims 25-27, wherein, the driving method of the pixel circuit further includes: In the light emitting stage after the compensation stage, making the first light emitting control signal and the second light emitting control signal be on signals, and the data scanning signal, the first reset control signal, the second reset control signal, and the first compensation control signal be off signals, so that the first light emitting control circuit and the second light emitting control circuit are both turned on, and the data writing circuit, the first reset circuit, the second reset circuit, and the first compensation circuit are all turned off, forming a driving current flowing through the first light emitting control circuit, the driving circuit, the second light emitting control circuit, and the light emitting element.

31. The driving method of the pixel circuit according to claim 30, wherein, when the second compensation circuit further includes a second compensation transistor, the gate of the second compensation transistor receives a second compensation control signal, the first pole of the second compensation transistor is electrically connected to the gate of the driving transistor, and the second pole of the second compensation transistor is electrically connected to the first electrode plate of the compensation capacitor so that the first electrode plate of the compensation capacitor is electrically connected to the gate of the driving transistor through the second compensation transistor, and the second electrode plate of the compensation capacitor is electrically connected to the second pole of the driving transistor, the driving method of the pixel circuit further includes: in the light emitting stage after the compensation stage, making the second compensation control signal be an on signal so that the second compensation control transistor is turned on.

32. The driving method of the pixel circuit according to any one of claims 17-31, wherein, the pixel circuit further includes a third reset circuit, the control end of the third reset circuit is configured to receive a third reset control signal, the first end of the third reset circuit is electrically connected to the first end of the driving circuit, and the second end of the third reset circuit is electrically connected to a third reset signal terminal to receive a third reset signal; the driving method of the pixel circuit further includes: In the initial stage, making the third reset control signal be an on signal so that the third reset circuit is turned on, and the third reset signal is applied to the first end of the driving circuit through the third reset circuit.

33. The driving method of the pixel circuit according to claim 32, wherein, the first end of the driving circuit is connected to a first power supply voltage terminal to receive a first power supply voltage; the third reset signal is a reset voltage, and the reset voltage is lower than the first power supply voltage.

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