Pixel driving circuit and display panel

Abstract

A pixel driving circuit and a display panel. The pixel driving circuit (101) comprises: a light-emitting element; a driving transistor (T1); a data writing transistor (T3) used for transmitting a data signal (VDATA) to the driving transistor (T1) in response to a second write control signal (WR2); an internal compensation transistor (T2) electrically connected between the gate of the driving transistor (T1) and the drain of the driving transistor (T1) and used for compensating for a threshold voltage of the driving transistor (T1) in response to a first write control signal (WR1); and an external compensation transistor (T4) electrically connected to the source of a light-emitting control transistor (T5) and the drain of the driving transistor (T1) and used for, in response to a read-write control signal (RD), reading an electric signal of the drain of the driving transistor (T1) and compensating for the threshold voltage of the driving transistor (T1), wherein the first write control signal (WR1) is different from the second write control signal (WR2).

Description

Pixel driving circuit and display panel Technical Field

[0001] The present application relates to the field of display technology, and in particular to a pixel driving circuit and a display panel. Background Art

[0002] OLED (Organic Light-Emitting Diode) display panels are widely used due to their flexibility and other characteristics.

[0003] The pixel driving circuit of the OLED display panel has high requirements for its timing design in order to realize the functions of the display panel at different time periods and to improve the reliability of the display panel. SUMMARY OF THE INVENTION

[0004] The purpose of the present application is to provide a display panel and a compensation method thereof, as well as a device for generating a compensated grayscale, so as to improve the technical problem of a boundary sense phenomenon in the display screen of a display terminal with an existing three-gate driving architecture.

[0005] The present application provides a pixel driving circuit and a display panel to improve the functional reliability of the display panel at different time periods.

[0006] The embodiment of the present application provides a pixel driving circuit, including:

[0007] Light-emitting element;

[0008] a driving transistor, configured to generate a driving current according to a data signal to drive the light-emitting element to emit light;

[0009] a data writing transistor, configured to transmit the data signal to the driving transistor in response to a second writing control signal;

[0010] a storage capacitor, electrically connected to the driving transistor, for storing the data signal;

[0011] an internal compensation transistor electrically connected between the gate of the driving transistor and the drain of the driving transistor, and configured to compensate for a threshold voltage of the driving transistor in response to a first write control signal, the first write control signal being different from the second write control signal; Beneficial effects

[0012] An external compensation transistor is electrically connected to the source of the light emitting control transistor and the driving transistor, and is used to respond to a read / write control signal to read the electrical signal at the source of the driving transistor and compensate for the threshold voltage of the driving transistor.

[0013] The present application provides a pixel driving circuit and a display panel, which are based on a light-emitting element, a driving transistor for generating a driving current according to a data signal to drive the light-emitting element to emit light, a data writing transistor for responding to a second write control signal to transmit a data signal to the driving transistor, a storage capacitor for storing the data signal, an internal compensation transistor for responding to a first write control signal to compensate for the threshold voltage of the driving transistor, and an external compensation transistor (electrically connected to the light-emitting control transistor and the source of the driving transistor) for responding to a read / write control signal to read the electrical signal at the source of the driving transistor. The first write control signal is set to be different from the second write control signal, so that during the data writing period of each frame, the data signal is transmitted to one end of the storage capacitor to turn on the driving transistor, and the gate and drain of the driving transistor are electrically disconnected, thereby improving the reliability of data signal writing and the accuracy of the driving current. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0015] FIG1 is a schematic structural diagram of a display panel provided in an embodiment of the present application.

[0016] FIG2 is a schematic structural diagram of a pixel driving circuit provided in an embodiment of the present application.

[0017] 3 , 5 , 8 , 10 , and 12 are waveform diagrams of some signals in the pixel driving circuit provided in embodiments of the present application, respectively.

[0018] 4 , 7 , 9 , 11 , 13 to 18 are schematic diagrams of signal flows in some stages of the pixel driving circuit provided by the embodiments of the present application.

[0019] FIG6 is a diagram showing the potential V of the third node B of the pixel driving circuit. B Change curve at t1. Modes for Carrying Out the Invention

[0020] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0021] In the description of this application, the terms "first", "second", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In this article, no distinction is made between the source and drain of the transistor, and the two can be set interchangeably. In addition, it should be noted that the drawings only provide structures that are closely related to this application, and some details that are not closely related to the application are omitted. The purpose is to simplify the drawings so that the application points are clear at a glance, rather than to indicate that the actual device is exactly the same as the drawings, and it is not a limitation of the actual device.

[0022] References to "embodiments" herein mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase at various times in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0023] The present application provides a pixel driving circuit and a display panel including the pixel circuit. The display panel and the pixel driving circuit include but are not limited to the following embodiments and combinations of the following embodiments.

[0024] In some embodiments, as shown in FIG1 , a display panel 100 includes: a panel body 10 including a pixel driving circuit 101 as described below; and a driver chip 20 electrically connected to the pixel driving circuit 101 to drive the pixel driving circuit 101. It can be understood that the driver chip 20 stores multiple instructions and multiple data. The multiple instructions can control the transmission of multiple data to control the communication within the driver chip 20 and between the driver chip 20 and the panel body 10, thereby realizing the display of the image.

[0025] Specifically, as shown in Figure 1, the panel body 10 also includes a multi-stage gate driving circuit (included in the gate driving module 102) arranged in cascade, and the driving chip 20 includes: a timing controller 201, each of the gate driving circuits is electrically connected between the timing controller 201 and the corresponding plurality of pixel driving circuits 101, and is used to respond to the first control signal output by the timing controller 201 to output a gate signal (including the first light-emitting control signal EM1, the second light-emitting control signal EM2, the first write control signal WR1 or the second write control signal WR2 below); at least one source driver 202, electrically connected between the timing controller 201 and the corresponding plurality of pixel driving circuits 101, and is used to respond to the second control signal output by the timing controller 201 to output the data signal VDATA.

[0026] For ease of description, an example is given herein where a plurality of pixel driving circuits 101 are arranged in an array of n rows and m columns (n ​​and m are both positive integers). The gate driving module 102 may include at least n levels of gate driving circuits, as shown in FIG1 . Each gate driving circuit outputs a corresponding gate signal according to a first control signal. The n-level gate signals are transmitted to n rows of pixel driving circuits 101 through n gate lines (GL1 to GLn). The first control signal controls the gate driving module 102 so that the effective gate pulses in the n-level gate signals for turning on the pixel driving circuits 101 can be arranged sequentially on the time axis, thereby turning on multiple rows of pixel driving circuits 101 in sequence. The source driver 202 can transmit the corresponding gate signals to the multiple columns of pixel driving circuits 101 through m data lines (DL1 to DLm). Multiple groups of data signals VDATA, each group of data signals VDATA may include multiple data signals VDATA corresponding to multiple pixel driving circuits 101 in the same column. The second control signal controls the source driver 202 so that when each row of pixel driving circuits 101 is turned on, the multiple data lines respectively receive multiple data voltages of the multiple pixel driving circuits 101 located in the row, so that the multiple data voltages act on the multiple pixel driving circuits 101 in the row to realize the light emission of the multiple light-emitting elements in the multiple pixel driving circuits 101 in the row. Similarly, the light emission of the light-emitting elements in all rows can be controlled in sequence to present a complete picture.

[0027] In some embodiments, as shown in Figure 2, the pixel driving circuit 101 includes: a light-emitting element (including a light-emitting element body and a light-emitting element capacitor Coled connected in parallel therewith, and the light-emitting referred to subsequently can be understood as light-emitting by the "light-emitting element body"); a driving transistor T1, used to generate a driving current according to a data signal VDATA to drive the light-emitting element to emit light; a data writing transistor T3, used to respond to a second write control signal WR2 to transmit the data signal VDATA to the driving transistor T1; a storage capacitor Cs, electrically connected to the driving transistor T1, used to store the data signal VDATA; an internal compensation transistor T2, electrically connected between the gate of the driving transistor T1 and the drain of the driving transistor T1, used to respond to the first write control signal WR1 to compensate for the threshold voltage of the driving transistor T1.

[0028] Furthermore, as shown in FIG2 , the pixel driving circuit 101 further includes an external compensation transistor T4 electrically connected to the light-emitting control transistor T5 and the source of the driving transistor T1. The external compensation transistor T4 is configured to respond to a read / write control signal RD to read the electrical signal at the source of the driving transistor T1 and to compensate for the threshold voltage of the driving transistor T1. Specifically, the gate of the external compensation transistor T4 is loaded with the read / write control signal RD, the source of the external compensation transistor T4 can be connected to the drain of the driving transistor T1, and the drain of the external compensation transistor T4 can be loaded with the fourth signal VMON.

[0029] When the driving transistor T1 is in the off state, the potential of the source of the driving transistor T1 is detected, and the drain of the external compensation transistor T4 can be connected to the external compensation module. The external compensation module can combine the measured potential of the source of the driving transistor T1 and the magnitude of the second signal ELVDD loaded on the source of the driving transistor T1 to calculate the threshold voltage of the driving transistor T1 and perform a corresponding compensation value to react to the pixel driving circuit 101 to compensate for the threshold voltage of the driving transistor T1.

[0030] The light-emitting element may be an electroluminescent element, and the electroluminescent element includes at least one of an OLED and an LED (Light-Emitting Diode). The types of the multiple transistors in the pixel driving circuit 101 may be the same or different. For example, all of them may be P-type transistors (whose constituent materials may be, but are not limited to, LTPS (Low Temperature Poly-Silicon)), all of them may be N-type transistors (whose constituent materials may be, but are not limited to, IGZO (Indium Gallium Zinc Oxide)), or some (such as the driving transistor T1 and the light-emitting control transistor T5) may be P-type transistors, and the other part (such as the internal compensation transistor T2, the data writing transistor T3, the external compensation transistor T4, and the reset transistor T6) may be N-type transistors. It should be noted that the type of each transistor in this application is not limited, but is intended to illustrate that it has a corresponding function, and the signal acting on it can be set according to the type of transistor and functional requirements.

[0031] Furthermore, as shown in FIG2 , the pixel driving circuit 101 further includes: a light emitting control transistor T5 electrically connected between the light emitting element and the driving transistor T1, and configured to transmit the driving current to the light emitting element in response to a first light emitting control signal EM1; a reset transistor T6 electrically connected to the storage capacitor Cs and the data writing transistor T3, and configured to transmit a first signal VREF to one end of the storage capacitor Cs in response to a second light emitting control signal EM2, wherein the first signal VREF is different from a second signal ELVDD loaded to the source of the driving transistor T1;

[0032] As shown in Figure 3, the pixel driving circuit 101 has a data writing period S2 in each frame. In the data writing period S2, the first write control signal WR1 is different from the second write control signal WR2; in the data writing period S2, the data writing transistor T3 is used to respond to the second write control signal WR2 to transmit the data signal VDATA to one end of the storage capacitor Cs to turn on the driving transistor T1, and the internal compensation transistor T2 is used to respond to the first write control signal WR1 to electrically disconnect the gate of the driving transistor T1 and the drain of the driving transistor T1.

[0033] Specifically, as shown in Figure 2, the source of the data write transistor T3 can be loaded with the data signal VDATA, the source of the reset transistor T6 can be loaded with the first signal VREF, the gate of the data write transistor T3 is loaded with the second write control signal WR2, the gate of the reset transistor T6 is loaded with the second light-emitting control signal EM2, the drain of the data write transistor T3 and the drain of the reset transistor T6 can be connected to the first end of the storage capacitor Cs through the first node N, the gate of the drive transistor T1 and the drain of the internal compensation transistor T2 can be connected to the second end of the storage capacitor Cs through the second node Q; the gate of the internal compensation transistor T2 is loaded with the first write control signal WR1; the source of the drive transistor T1 is loaded with the second signal ELVDD, the gate of the light-emitting control transistor T5 is loaded with the first light-emitting control signal EM1, the source of the light-emitting control transistor T5 is connected to the drain of the drive transistor T1 and the source of the internal compensation transistor T2 through the third node B, the drain of the light-emitting control transistor T5 can be connected to the anode of the light-emitting element, and the cathode of the light-emitting element can be grounded (that is, loaded with the ground voltage ELVSS).

[0034] Among them, the reset transistor T6 can be used to reset the potential VN of the first node N, the data write transistor T3 can be used to transmit the data signal VDATA to the storage capacitor Cs, the internal compensation transistor T2 can be used to store the threshold voltage of the driving transistor T1 in the storage capacitor Cs, the driving transistor T1 can generate a driving current under the action of the data signal VDATA, and the light-emitting control transistor T5 is used to turn on to transmit the driving current to the light-emitting element to control the light-emitting element to emit light.

[0035] To better illustrate the above-mentioned functions of the pixel driving circuit 101 of the present application, it is assumed here that all transistors in the pixel driving circuit 101 are P-type transistors (it can be considered that the signal loaded on their gates can be used to control their on-state if it is at a corresponding low potential, and can be used to control their off-state if it is at a corresponding high potential, and the high potentials of multiple signals can be equal or different, and the low potentials of multiple signals can be equal or different), and the values ​​of the first signal VREF, the second signal ELVDD, the third signal VGMP and the fourth signal VMON can also be represented by VREF, ELVDD, VGMP, and VMON, respectively, and VREF, ELVDD, and VGMP are high potentials (used to control the P-type transistors to be turned off), and VMON is low potential (used to control the P-type transistors to be turned on) as an example. The working period of the pixel driving circuit 101 is described as follows.

[0036] (1) Threshold voltage external detection period t1: As shown in Figures 4 and 5, the first light-emitting control signal EM1 and the second write control signal WR2 are both corresponding high potentials to control the light-emitting control transistor T5 and the data write transistor T3 to be turned off. The first write control signal WR1, the second light-emitting control signal EM2, and the read-write control signal RD are all corresponding low potentials to control the internal compensation transistor T2, the reset transistor T6, and the external compensation transistor T4 to be turned on. The first signal VREF is transmitted to the first node N through the reset transistor T6 to maintain the potential VN of the first node N. Before that, the second node Q can be reset to a low potential (for example, the fourth signal VMON with a low potential can be transmitted to the second node Q by turning on the internal compensation transistor T2 and the external compensation transistor T4). Therefore, it can be considered that the driving transistor The transistor T1 is turned on, and the second signal ELVDD is transmitted to the second node Q through the driving transistor T1 and the internal compensation transistor T2 to charge the storage capacitor Cs. The potential VQ of the second node Q gradually rises until the difference between the potential VQ of the second node Q and the potential of the source of the driving transistor T1 (equal to ELVDD) is equal to the first threshold voltage Vth1 of the driving transistor T1, that is, "VQ-ELVDD=Vth1". The driving transistor T1 is turned off, so the potential VQ of the second node Q can gradually approach ELVDD+Vth1 (Vth1<0) from its initial potential (which can be close to VMON). As shown in Figure 6, it can represent the change curve of the potential VB of the third node B during this period. Since the internal compensation transistor T2 is turned on, the external compensation module can obtain VB, that is, VQ, through the external compensation transistor T4.

[0037] Furthermore, the threshold voltage external detection period t1 can be divided into a first sub-period t11 and a second sub-period t12 located after the first sub-period t11. As shown in Figure 6, the first sub-period t11 can be understood as a period in which VQ changes greatly. At this time, the driving transistor T1 is still far from reaching the cut-off state. The second sub-period t12 is understood as a period in which VQ is relatively stable (close to ELVDD-|Vth1|). Therefore, the duration of the first write control signal WR1 being a corresponding low potential (unknown, and can be set based on multiple experimental values ​​or empirical values) needs to be long enough to ensure that it can reach the second sub-period t12. In order to reduce the power consumption of the external compensation module when detecting Vth1, the read-write control signal RD can be set to a corresponding low potential only in the second sub-period t12 to turn on the external compensation transistor T4 to enable the external compensation module to work.

[0038] It can be seen that a first write control pulse p1 in the first write control signal WR1 is overlapped with a read / write control pulse p2 in the read / write control signal RD, and the starting point of the first write control pulse p1 is earlier than the starting point of the corresponding read / write control pulse p2; for example, as shown in Figure 5, in the threshold voltage external detection period t1, the first write control pulse p1 can cover the first sub-period t11, but the read / write control pulse p2 can only cover the second sub-period t12.

[0039] Specifically, the pixel driving circuit 101 has the above-mentioned threshold voltage external detection period t1 before the first frame (which can be understood as the first frame displayed after the display panel 100 is turned on). In combination with the above discussion, during the threshold voltage external detection period t1, the first light-emitting control signal EM1 is different from the first write control signal WR1. Specifically, the reset transistor T6 is configured to respond to the second light-emitting control signal EM2 to transmit the first signal VREF to one end of the storage capacitor Cs, and the data write transistor T3 is configured to respond to the second write control signal WR2 to transmit the third signal VGMP to one end of the storage capacitor Cs. The internal compensation transistor T2 is configured to respond to the first write control signal WR1 to transmit the second signal ELVDD to one end of the storage capacitor Cs. The external compensation transistor T4 is configured to respond to the read / write control signal RD to read the threshold voltage of the driving transistor T1 (the above-mentioned first threshold voltage Vth1). The light-emitting control transistor T5 is configured to respond to the first light-emitting control signal EM1 to be electrically disconnected from the driving transistor T1.

[0040] It can be understood that Figures 4 and 5 only use the reset transistor T6 responding to the second light-emitting control signal EM2 to transmit the first signal VREF to one end of the storage capacitor Cs (the first node N, i.e., the first end of the storage capacitor Cs) as an example. Its function is to maintain the potential of the first end of the storage capacitor Cs so that the storage capacitor Cs can be charged to achieve stability. Similarly, the method in Figures 4 and 5 can be replaced by setting the second write control signal WR2 to a corresponding low potential to transmit the third signal VGMP to the first end of the storage capacitor Cs.

[0041] Therefore, during this period, any one of the second write control signal WR2 and the second light-emitting control signal EM2 can be set to a corresponding low potential; but it should be satisfied that the first light-emitting control signal EM1 is different from the first write control signal WR1, for example, the former is set to a corresponding high potential to turn off the light-emitting control transistor T5 to prevent the light-emitting element from emitting light, and the latter is set to a corresponding low potential to turn on the internal compensation transistor T2 to charge the second node Q.

[0042] Specifically, the threshold voltage external detection period t1 after the i1th (i1 is a positive integer) power-on can be detected by the above method to obtain the i1th VQ (called VQ1, close to ELVDD-|Vth1|), and the threshold voltage external detection period t1 after the i2th (i2 is a positive integer greater than i1) power-on can be detected by the above method to obtain the i2th VQ (called VQ2, close to ELVDD-|Vth2|), Vth2 is the driving crystal at the i2th power-on. The threshold voltage of the transistor T1 is referred to as the second threshold voltage Vth2. Compared with the i1st power-on, the absolute value of the offset ∆Vth of the threshold voltage of the driving transistor T1 during the i2th power-on is approximately equal to |VQ1-VQ2|. Compared with the i1st power-on, the absolute value of the compensation value ∆VDATA of the data signal VDATA during the i2th power-on is positively correlated with ∆Vth. Taking into account the influence of detection accuracy and other factors, the absolute value of ∆VDATA can be equal to k1×|∆Vth|, where k1 is greater than 0.

[0043] It should be noted that, in order to improve the consistency of the detection standard, VQ can be measured at the moment when VQ is relatively stable in the threshold voltage external detection period t1 after the i1th and i2th power-ons.

[0044] (2) External luminous detection period t2: As shown in Figures 7 and 8, the first write control signal WR1 and the second luminous control signal EM2 are both corresponding high potentials to control the internal compensation transistor T2 and the reset transistor T6 to be turned off. The second write control signal WR2, the first luminous control signal EM1, and the read / write control signal RD are all corresponding low potentials to control the reset transistor T6, the luminous control transistor T5, and the external compensation transistor T4 to be turned on. Since the corresponding ∆VDATA can be determined after the threshold voltage external detection period t1 after this (second and subsequent) power-on, in order to avoid the influence of the offset of the threshold voltage of the driving transistor T1 on the luminous brightness of the luminous element, a new data voltage "VDATA+∆V The new data voltage "DATA" is loaded into the source of the data write transistor T3 for transmission to the first node N through the data write transistor T3, causing the potential VN of the first node N to change by "(VDATA+∆VDATA)-VREF". Due to the coupling effect of the storage capacitor Cs, the potential of the second node Q also changes by the same amount, causing the potential of the second node Q "ELVDD-|Vth2|+(VDATA+∆VDATA)-VREF" to also be related to the new data voltage. At this time, the driving transistor T1 is also turned on and can be considered to be operating in the saturation region. After the light-emitting control transistor T5 is turned on, the new driving current (related to the new data voltage) generated by the driving transistor T1 flows into the light-emitting element. At this time, the potential of the third node B can be detected by the external compensation module.

[0045] Specifically, it can be understood here that the pixel driving circuit 101 has a light-emitting external detection period t2 located after the threshold voltage external detection period t1 before the first frame. In the light-emitting external detection period t2, combined with the above discussion, the first write control signal WR1 is different from the second write control signal WR2, and the first light-emitting control signal EM1 is different from the second light-emitting control signal EM2. Specifically, the data write transistor T3 is used to respond to the second write control signal WR2 to transmit the target data signal VDATA (that is, "VDATA+∆VDATA") to the storage capacitor Cs to turn on the driving transistor T1, and the light-emitting control transistor T3 is used to respond to the second write control signal WR2 to transmit the target data signal VDATA (that is, "VDATA+∆VDATA") to the storage capacitor Cs to turn on the driving transistor T1. The transistor T5 is configured to respond to the first light-emitting control signal EM1 to electrically connect the light-emitting element and the driving transistor T1. The external compensation transistor T4 is configured to respond to the read / write control signal RD to read the electrical signal of the light-emitting element (i.e., the potential of the third node B). The target data signal VDATA is determined based on the data signal VDATA and the threshold voltage. The internal compensation transistor T2 is configured to respond to the first write control signal WR1 to electrically disconnect the gate of the driving transistor T1 from the output terminal of the driving transistor T1. The reset transistor T6 is configured to respond to the second light-emitting control signal EM2 to electrically disconnect the reset transistor T6 from the storage capacitor Cs.

[0046] During this period, turning off the reset transistor T6 can prevent the first signal VREF from being transmitted to the first node N and affecting its potential. Turning off the internal compensation transistor T2 can prevent the potential of the second node Q from affecting the potential of the third node B.

[0047] It can be seen that a second write control pulse p3 in the second write control signal WR2 and a second light-emitting control pulse p4 in the second light-emitting control signal EM2 that is close to the corresponding second write control pulse p3 are staggered; for example, as shown in Figure 5, the second light-emitting control pulse p4 covers the threshold voltage external detection period t1, and the second write control pulse p3 is not set in the threshold voltage external detection period t1; for example, as shown in Figure 8, the second write control pulse p3 covers the light-emitting external detection period t2, and the second light-emitting control pulse p4 is not set in the light-emitting external detection period t2; or, for example, as shown in Figure 9, the second light-emitting control pulse p4 covers the light-emitting external detection period t2, and the second write control pulse p3 is not set in the light-emitting external detection period t2.

[0048] Specifically, in this embodiment, the j1-th (j1 is a positive integer) external light detection period t2 (which must be preceded by the corresponding threshold voltage external detection period t1) can be used to detect and obtain the j1-th VB (called VB1, which is close to the anode potential of the light-emitting element when it emits light for the j1th time), and the j2-th (j2 is a positive integer greater than j1) external light detection period t2 (which must be preceded by the corresponding threshold voltage external detection period t1) can be used to detect and obtain the j2-th VB (called VB2, which is close to the anode potential of the light-emitting element when it emits light for the j2th time). j1 and j1 can be respectively j2 and j3 may be the same or different, that is, the corresponding threshold voltage external detection period t1 must exist before the light-emitting external detection period t2 of this embodiment, but not every threshold voltage external detection period t1 must have a corresponding light-emitting external detection period t2, that is, the frequency of light-emitting external detection may be lower than the frequency of threshold voltage external detection; then, compared with the j1st power-on, the absolute value of the change in the anode potential of the light-emitting element when emitting light under the same "VDATA+∆VDATA" during the j2nd power-on may be positively correlated with the absolute value of the VB offset ∆VB. If other factors are not considered, the two may be considered equal.

[0049] It should be noted that due to the leakage current of the internal compensation transistor T2, the brightness of the light-emitting element will continue to decrease during the process of the external compensation module detecting the potential of the third node B, and the detected potential of the third node B will also continue to decrease. Based on this, the internal compensation transistor T2 can be set to include two transistors connected in series, and the gates of the two transistors are short-circuited to serve as the gate of the internal compensation transistor T2, wherein the drain of one transistor is connected to the second node Q, and the source of the other transistor is connected to the third node B. Similarly, to improve the consistency of the detection standard, VB can be measured at the time corresponding to the same VB leakage level in the external light-emitting detection period t2 after the j1th and j2th power-ups.

[0050] Of course, in other embodiments, as shown in combination with FIG9 and FIG10, the pixel driving circuit 101 may also have a light-emitting external detection period t2 before the first frame (the above-mentioned threshold voltage external detection period t1 may not be set before it). During the light-emitting external detection period, the first write control signal WR1 is different from the second write control signal WR2, and the first light-emitting control signal EM1 is different from the second light-emitting control signal EM2. Specifically, the data writing transistor T3 is used to respond to the second write control signal WR2 to transmit the third signal VGMP to one end of the storage capacitor Cs (i.e., the first node N) to turn off the driving transistor T1, and the external compensation transistor T4 is used to respond to the read-write control signal RD to transmit the first The fourth signal VMON is transmitted to the light-emitting control transistor T5, and the light-emitting control transistor T5 is used to respond to the first light-emitting control signal EM1 to electrically connect the light-emitting element and the driving transistor T1, so that the fourth signal VMON is transmitted to the light-emitting element. The external compensation transistor T4 is also used to respond to the read-write control signal RD to read the threshold voltage of the light-emitting element and compensate for the threshold voltage of the driving transistor T1; wherein, the internal compensation transistor T2 is used to respond to the first write control signal WR1 to electrically disconnect the gate of the driving transistor T1 and the output end of the driving transistor T1, and the reset transistor T6 is used to respond to the second light-emitting control signal EM2 to electrically disconnect from the storage capacitor Cs.

[0051] The difference between this embodiment and the light-emitting external detection period t2 in the previous embodiment is that here, the third signal VGMP with a high potential is transmitted to the first node N through the turned-on data writing transistor T3 instead of the data signal VDATA. Similarly, the change in the potential VN of the first node N at this time is "VGMP-VREF". Due to the coupling effect of the storage capacitor Cs, the potential of the second node Q also changes by the same amount, so that the potential of the second node Q is higher at this time, causing the driving transistor T1 to be turned off, making the driving current close to zero. At this time, the external detection module can transmit the fourth signal VMON to the anode of the light-emitting element through the turned-on external compensation transistor T4 and the light-emitting control transistor T5. It can be considered that the potential of the fourth signal VMON is still higher than the ground voltage ELVSS, so that the light-emitting element is still turned on, and the external detection module can still measure the anode potential of the light-emitting element when it is emitting light.

[0052] In this embodiment, turning off the reset transistor T6 can prevent the first signal VREF from being transmitted to the first node N and affecting its potential. Turning off the internal compensation transistor T2 can prevent the potential of the second node Q from affecting the potential of the third node B.

[0053] In this embodiment, the change in the anode potential of the light-emitting element when emitting light under the same fourth signal VMON can be measured by referring to the absolute value of the change in the anode potential of the light-emitting element when emitting light under the same "VDATA+∆VDATA" in the previous embodiment.

[0054] It can be seen that a first light-emitting control pulse p5 in the first light-emitting control signal EM1 is overlapped with a read-write control pulse p2 in the read-write control signal RD, and is staggered with a first write control pulse p1 in the first write control signal WR1 that is close to the corresponding first light-emitting control pulse p5; for example, as shown in Figures 8 and 10, the first light-emitting control pulse p5 and the read-write control pulse p2 both cover the light-emitting external detection period t2, and the first write control pulse p1 is not set in the light-emitting external detection period t2.

[0055] It should be noted that the pixel driving circuits 101 located in the same row can be driven by the same read / write control signal RD. Each read / write control signal RD can control the on / off of corresponding multiple external compensation transistors T4, which is positively correlated with the row scanning period. In this case, if the above-mentioned threshold voltage external detection period t1 and light emission external detection period t2 are also set before multiple frames (other than the first frame), in order to improve the detection accuracy of the external detection module in at least one of the above-mentioned threshold voltage external detection period t1 and light emission external detection period t2, the period of the read / write control signal RD can be set to be longer, which can be achieved by frequency reduction.

[0056] (3) First reset period t3 (including the first sub-period S0-1 and the second sub-period S0-2): As shown in FIG11 and FIG12, in the first sub-period S0-1, the second light-emitting control signal EM2, the first write control signal WR1, and the read-write control signal RD are all at corresponding high potentials to control the reset transistor T6, the internal compensation transistor T2, and the external compensation transistor T4 to be turned off, and the first light-emitting control signal EM1 and the second write control signal WR2 are at corresponding low potentials to control the internal compensation transistor T2 and the data write transistor T3 to be turned on. For the convenience of description, the discussion here is based on the embodiment described in FIG7. At this time, the third signal VGMP is transmitted to the first node N through the data write transistor T3. When the potential VN of the first node N changes by "VGMP-(VDATA+∆VDATA)", due to the coupling effect of the storage capacitor Cs, the potential of the second node Q also changes by the same amount, so that the potential of the second node Q becomes "ELVDD-|Vth2|+(VDATA+∆VDATA)-VREF+VGMP-(VDATA+∆VDATA)", that is, "ELVDD-|Vth2|-VREF+VGMP". The second signal ELVDD and the third signal VGMP are high, so the potential of the gate of the driving transistor T1 can be considered to be close to the dark state voltage. The driving transistor T1 is close to the off state. At this time, there is a very small dark state current flowing through the light-emitting element;

[0057] In the second sub-period S0-2, in combination with Figures 13 and 12, the second light-emitting control signal EM2, the first write control signal WR1, and the second write control signal WR2 are all corresponding high potentials to control the reset transistor T6, the internal compensation transistor T2, and the data write transistor T3 to be turned off, and the first light-emitting control signal EM1 and the read-write control signal RD are all corresponding low potentials to control the internal compensation transistor T2 and the external compensation transistor T4 to be turned on. At this time, the first node N and the second node Q can be maintained at their previous potentials, respectively, and the driving transistor T1 is still turned off. The low-potential fourth signal VMON is transmitted to the anode of the light-emitting element (i.e., the fourth node C) through the turned-on external compensation transistor T4 and the light-emitting control transistor T5 to reset the potential.

[0058] 11 and 12 , it can be understood that the pixel driving circuit 101 has the above-mentioned first reset period t3 in each frame. In the first sub-period S0-1 in the first reset period t3, the data write transistor T3 is used to respond to the second write control signal WR2 to transmit the third signal VGMP to one end of the storage capacitor Cs, and the reset transistor T6 is used to respond to the second light-emitting control signal EM2 to transmit the first signal VREF to one end of the storage capacitor Cs. At least one of the two functions is realized to turn off the driving transistor T1, and the internal compensation transistor T2 is used to respond to the first write control signal WR1 to electrically disconnect the gate of the driving transistor T1 and the output end of the driving transistor T1.

[0059] During this phase, the third signal VGMP, which is at a high potential, is applied to the driving transistor T1 to control its shutdown, thereby preventing the generation of a large driving current. Furthermore, the internal compensation transistor T2 disconnects the gate and drain of the driving transistor T1 to prevent the potentials of the third node B and the fourth node C from being affected by the potential of the second node Q. As discussed above, unlike the embodiment shown in FIG11 , the reset transistor T6 can also be turned on to transmit the first signal VREF, which is at a high potential, to the first node N. In other words, at least one of the data writing transistor T3 and the reset transistor T6 can be turned on, and both can raise the potential of the second node Q to a higher level to turn off the driving transistor T1.

[0060] Following the first sub-period S0-1, in combination with Figures 13 and 12, in the second sub-period S0-2 of the first reset period t3, in the first reset period, the first light-emitting control signal EM1 is different from the first write control signal WR1; specifically, the external compensation transistor T4 is used to respond to the read-write control signal RD to transmit the fourth signal VMON to the light-emitting control transistor T5, the light-emitting control transistor T5 is used to respond to the first light-emitting control signal EM1 to transmit the second signal ELVDD to the light-emitting element to reset the light-emitting element, and the internal compensation transistor T2 is used to respond to the first write control signal WR1 to electrically disconnect the gate of the driving transistor T1 and the output end of the driving transistor T1.

[0061] In this stage, the fourth node C (i.e., the anode of the light-emitting element) is reset by transmitting the fourth signal VMON with a low potential to it. Similarly, the data writing transistor T3, the reset transistor T6 and the internal compensation transistor T2 are all turned off to avoid affecting the resetting of the potential of the fourth node C.

[0062] It can be seen that a second write control pulse p3 in the second write control signal WR2 is staggered with a read / write control pulse p2 in the read / write control signal RD that is close to the corresponding second write control pulse p3, and the second write control pulse p3 is located before the corresponding read / write control pulse p2; for example, as shown in Figure 12, the second write control pulse p3 is located in the first sub-period S0-1 in the first reset period t3, and the read / write control pulse p2 is located in the first sub-period S0-1 in the corresponding first reset period t3.

[0063] Moreover, a first light-emitting control pulse p5 in the first light-emitting control signal EM1 is overlapped with a second write control pulse p3 in the second write control signal WR2, and the starting point of the first light-emitting control pulse p5 is earlier than or equal to the starting point of the corresponding second write control pulse p3, and the end point of the first light-emitting control pulse p5 is later than the end point of the corresponding second write control valid pulse p3; for example, as shown in Figure 12, the second write control pulse p3 is located in the first sub-period S0-1 in the first reset period t3, and the first light-emitting control pulse p5 covers the entire first reset period t3.

[0064] (4) Second reset period S0-3: As shown in FIG14 and FIG12, the first light-emitting control signal EM1 and the second write control signal WR2 are both corresponding high potentials to control the light-emitting control transistor T5 and the data write transistor T3 to be turned off, and the second light-emitting control signal EM2, the first write control signal WR1, and the read-write control signal RD are all corresponding low potentials to control the reset transistor T6, the internal compensation transistor T2, and the external compensation transistor T4 to be turned on. At this time, the fourth signal VMON with a low potential is transmitted to the second node Q through the turned-on external compensation transistor T4 and the internal compensation transistor T2, and the driving transistor T1 is turned on. At the same time, the first signal VREF with a high potential is transmitted to the first node N through the turned-on reset transistor T6 to maintain the potential of the first end of the storage capacitor Cs, which is beneficial to the charging of the storage capacitor Cs, so that the potential of the second end (the second node Q) of the storage capacitor Cs can be charged to reach stability, thereby achieving reset.

[0065] Here, it can be understood that the pixel driving circuit 101 has the above-mentioned second reset period S0-3 in each frame (which can be located after the corresponding first reset period t3). In the second reset period S0-3, the first light-emitting control signal EM1 is different from the first write control signal WR1; in the second reset period S0-3, the reset transistor T6 is used to respond to the second light-emitting control signal EM2 to transmit the first signal VREF to one end of the storage capacitor Cs (Figure 14 is only used as an example), and the data write transistor T3 is used to respond to the second write control signal WR2 to transmit the third signal VGMP to the storage One end of the capacitor Cs (not shown in FIG14 ) is configured to implement at least one of the two functions: the external compensation transistor T4 is configured to respond to the read / write control signal RD to transmit the fourth signal VMON to the source of the driving transistor T1; the internal compensation transistor T2 is configured to respond to the first write control signal WR1 to electrically connect the gate of the driving transistor T1 and the source of the driving transistor T1, so that the fourth signal VMON is transmitted to the gate of the driving transistor T1 to reset the driving transistor T1; and the light-emitting control transistor T5 is configured to respond to the first light-emitting control signal EM1 to be electrically disconnected from the driving transistor T1.

[0066] In this stage, the second node Q is reset by transmitting the fourth signal VMON to the second node Q, and one of the reset transistor T6 and the data writing transistor T3 needs to be turned on to maintain the potential of the first node N, which is beneficial to resetting the potential of the second node Q.

[0067] In particular, the third signal VGMP discussed throughout the text can be understood as another signal independent of the data signal VDATA; it can also be understood as a partial signal belonging to the first signal VREF, that is, the source of the data write transistor T3 can always be loaded with the first signal VREF, and as shown in Figures 3 and 12, the first signal VREF is equal to the third signal VGMP in the corresponding time period. Combined with the circuit diagrams of S0-1, S0-2, and S0-3 above and the timing diagram of Figure 12, it can be seen that since the sources of the data transistors in S0-1 and S0-2 need to be loaded with the third signal VGMP, the first signal VREF can be set to a value equal to the third signal VGMP in S0-1 and S0-2, and the data write transistor T3 can be turned off in S0-3. Therefore, the specific value of the first signal VREF is not limited. For example, it can be equal to the value of the first signal VREF at this time. Combined with the above discussion, the first signal VREF can be set to be equal to the third signal VGMP or a valid data signal in t1.

[0068] (5) Threshold voltage internal detection period S1: As shown in FIG15 and FIG12, the first light-emitting control signal EM1, the second write control signal WR2, and the read-write control signal RD are all at corresponding high potentials to control the light-emitting control transistor T5, the data write transistor T3, and the external compensation transistor T4 to be turned off. The second light-emitting control signal EM2 and the first write control signal WR1 are at corresponding low potentials to control the reset transistor T6 and the internal compensation transistor T2 to be turned on. At this time, the first signal VREF at a high potential is transmitted to the first node N through the turned-on reset transistor T6, driving the transistor T4. The transistor T1 is maintained turned on, and the second signal ELVDD with a high potential charges the second node Q through the driving transistor T1 and the turned-on internal compensation transistor T2. When the potential VQ of the second node Q gradually rises to a point where the difference between the potential VQ of the second node Q and the potential of the source of the driving transistor T1 (equal to ELVDD) is equal to the third threshold voltage Vth3 (which may be equal to Vth2) of the driving transistor T1 at this time, that is, "VQ-ELVDD=Vth3", the driving transistor T1 is turned off, so the potential VQ of the second node Q gradually approaches ELVDD+Vth3 (Vth3<0).

[0069] Among them, unlike T1, S1 only stores the third threshold voltage Vth3 of the driving transistor T1 at this time at the second node Q, and does not turn on the external compensation transistor T4 to detect it; each frame can include the above-mentioned S0-1, S0-2, and S0-3, and S1 can be performed after S0-3 of each frame to "detect" the threshold voltage of the driving transistor T1 in this frame.

[0070] It can be seen that the second light-emitting control pulse p4 in the second light-emitting control signal EM2 and the first write control pulse p1 in the first write control signal WR1 are overlapped; for example, as shown in Figure 12, the second light-emitting control pulse p4 and the first write control pulse p1 both cover the threshold voltage internal detection period S1.

[0071] (6) Data writing period S2: As shown in FIG16 and FIG12, the first light-emitting control signal EM1, the second light-emitting control signal EM2, the first write control signal WR1, and the read-write control signal RD are all corresponding high potentials to control the light-emitting control transistor T5, the reset transistor T6, the internal compensation transistor T2, and the external compensation transistor T4 to be turned off. The second write control signal WR2 corresponds to a low potential to control the data writing transistor T3 to be turned on. At this time, the data signal VDATA (the valid data signal VDATA at this time) with a low potential is transmitted to the first node N through the turned-on data writing transistor T3, so that the change in the potential VN of the first node N is "VDATA-VREF". Due to the coupling effect of the storage capacitor Cs, the potential of the second node Q will also have the same change. Therefore, the potential VQ of the second node Q is "ELVDD-|Vth3|+VDATA-VREF". It can be seen that the potential of the second node Q includes the valid data signal VDATA in the data signal VDATA and the third threshold voltage of the driving transistor T1 at this time. At this time, the driving transistor T1 is turned on.

[0072] Specifically, as discussed above, in the data writing period S2, the first write control signal WR1 is different from the second write control signal WR2; specifically, the data writing transistor T3 is used to respond to the second write control signal WR2 to transmit the data signal VDATA to one end of the storage capacitor Cs to turn on the driving transistor T1, and the internal compensation transistor T2 is used to respond to the first write control signal WR1 to electrically disconnect the gate of the driving transistor T1 and the drain of the driving transistor T1, thereby preventing the high-potential second signal ELVDD from charging the second node Q through the driving transistor T1 and the internal transistor, resulting in the potential of the second node Q being unable to store the data signal VDATA and the third threshold voltage of the driving transistor T1 at this time.

[0073] It can be seen that a second write control pulse p3 in the second write control signal WR2 is interleaved with a first write control pulse p1 in the first write control signal WR1 that is close to the corresponding second write control pulse p3, and the first write control pulse p1 is located before the corresponding second write control pulse p3; for example, as shown in Figure 12, the second write control pulse p3 can be located in the data writing period S2, but the first write control pulse p1 is not set in the data writing period S2.

[0074] (7) Light-emitting period S3: As shown in FIG17 and FIG12, the second light-emitting control signal EM2, the first write control signal WR1, the read-write control signal RD, and the second write control signal WR2 are all at corresponding high potentials to control the reset transistor T6, the internal compensation transistor T2, the external compensation transistor T4, and the data write transistor T3 to be turned off. The first light-emitting control signal EM1 is at a corresponding low potential to control the light-emitting control transistor T5 to be turned on. At this time, the storage capacitor Cs maintains the potentials of the first node N and the second node Q at both ends thereof unchanged. The driving current generated by turning on the driving transistor T1 is transmitted to the light-emitting element through the turned-on light-emitting control transistor T5, and the light-emitting element emits light.

[0075] In the embodiment shown in FIG17 , the potential VQ of the second node Q is maintained at "ELVDD-|Vth3|+VDATA-VREF." Therefore, the voltage difference between the gate and source of the driving transistor T1 is "VQ-ELVDD," and the driving current is equal to k2×((VQ-ELVDD)-Vth3)2. Substituting this into the expression for VQ, the driving current is equal to k2×(VDATA-VREF)2. Therefore, through the above-mentioned S1 and S2, the threshold voltage of the driving transistor T1 in this frame is compensated by internal compensation.

[0076] It can be seen that a first light-emitting control pulse p5 in the first light-emitting control signal EM1 is staggered with the first write control pulse p1 close to the corresponding first light-emitting control pulse p5 in the first write control signal WR1, and is staggered with the read-write control pulse p2 close to the corresponding first light-emitting control pulse p5 in the read-write control signal RD, and the first light-emitting control pulse p5 is located after the corresponding first write control pulse p1 and the corresponding read-write control pulse p2; for example, as shown in Figure 12, the first light-emitting control pulse p5 covers the light-emitting period S3, but the first write control pulse p1 and the read-write control pulse p2 are not set in the light-emitting period S3, and the first write control pulse p1 and the read-write control pulse p2 are both located before the light-emitting period S3.

[0077] Of course, in the embodiment shown in FIG. 18, different from the timing diagram of S3 shown in FIG. 12, the second light emission control potential at this time can also be the corresponding low potential to turn on the reset transistor T6. At this time, the first signal VREF is transmitted to the first node N, that is, VN in S3 is equal to VREF, while VN in S2 is "VREF+(VDATA - VREF)", that is, equal to VDATA. Therefore, the change amount of the potential of the first node N in S3 is "VREF - VDATA". Correspondingly, the potential of the second node Q also has the same change amount. However, in this case, it needs to be considered that VQ in S1 gradually approaches "ELVDD + Vth3" but is not equal. It can be considered that VQ in S1 is equal to a×(ELVDD + Vth3), where 0 < a < 1; in S2, it needs to be considered all the capacitances CN coupled between the first node N and other signals and all the capacitances CQ coupled between the second node Q and other signals. Therefore, there is an equation of "∆VN×CN = ∆VQ×CQ". Thus, VQ in S2 is equal to "(CN / CQ)×(VDATA - VREF)+a×(ELVDD + Vth3)". Let "CN / CQ" be equal to b, then VQ in S2 is equal to a×(ELVDD + Vth3)+b×(VDATA - VREF); in S3, VQ is equal to the sum of VQ in S2 and "VREF - VDATA", that is, equal to a×(ELVDD + Vth3)+(b - 1)×(VDATA - VREF). And the drive current is equal to k2×((VQ - ELVDD)-Vth3)2. Substituting the expression of VQ, the drive current is equal to k2×((a - 1)×(ELVDD + Vth3)+(b - 1)×(VDATA - VREF))2.

[0078] Of course, different from the embodiments shown in FIGS. 17 and 18, different from the timing diagram of S3 shown in FIG. 12, the second write control signal potential at this time can also be the corresponding low potential to turn on the data write transistor T3 to still write VDATA to the first node N. Since the potential of the first node N in S3 is the same as that of the first node N in S2, the potential VQ of the second node Q is maintained as "ELVDD - |Vth3|+VDATA - VREF" as in the embodiment shown in FIG. 17 above, and the drive current is also equal to k2×(VDATA - VREF)2.

[0079] It should be noted that if a threshold voltage external detection period t1 is performed before the first frame after this or at least one previous power-on to determine the compensation value ∆VDATA of the data signal VDATA, the data signal VDATA loaded in the data writing period S2 can be the new data signal VDATA after the superposition of ∆VDATA. That is, the change in VN in S2 can be "VDATA + ∆VDATA - VREF", and VQ is "ELVDD - |Vth3| + VDATA + ∆VDATA - VREF". Correspondingly, the drive current in S3 is equal to k2 × (VDATA + ∆VDATA - VREF)2.

[0080] Therefore, in the present application, an external detection period t1 of the threshold voltage can be set after two power-ons to obtain the ∆Vth of the driving transistor T1 at the last power-on, so as to obtain the compensation value ∆VDATA1 of the data voltage corresponding to the entire screen display after the last power-on, so that in the data writing period S2 of each frame, the driving transistor T1 is turned on according to the voltage related to the ∆VDATA1, thereby realizing external compensation of the threshold voltage. At the same time, the internal compensation of the threshold voltage can be realized through the above-mentioned timing setting in the internal detection period S1 of the threshold voltage, the data writing period S2, and the light-emitting period S3 of each frame.

[0081] Similarly, the present application can also set an external light-emitting detection period t2 after two power-ons to obtain the anode potential offset of ∆Vth of the light-emitting element at the last power-on, and can also obtain the compensation value ∆VDATA2 of the data voltage corresponding to the entire screen display after the last power-on based on the corresponding algorithm, so that in the data writing period S2 of each frame, the driving transistor T1 is turned on according to the voltage related to ∆VDATA2 to achieve external compensation of the light-emitting element. At the same time, in the threshold voltage internal detection period S1, data writing period S2, and light-emitting period S3 of each frame, the internal compensation of the threshold voltage can be achieved through the above-mentioned timing setting.

[0082] The light emitting external detection period t2 may be set corresponding to the threshold voltage external detection period t1, or only the light emitting external detection period t2 or only the threshold voltage external detection period t1 may be set. For details, please refer to the above discussion.

[0083] The present application provides a pixel driving circuit and a display panel, which are based on a light-emitting element, a driving transistor for generating a driving current according to a data signal to drive the light-emitting element to emit light, a storage capacitor for storing the data signal, an internal compensation transistor for responding to a first write control signal to compensate for the threshold voltage of the driving transistor, and an external compensation transistor for responding to a read / write control signal to read the electrical signal at the source of the driving transistor, and compensating for the threshold voltage of the driving transistor (electrically connected to the light-emitting control transistor and the source of the driving transistor). The first write control signal is set to be different from the second write control signal, so that during the data writing period of each frame, the data signal is transmitted to one end of the storage capacitor to turn on the driving transistor, and the gate and drain of the driving transistor are electrically disconnected, thereby improving the reliability of data signal writing and the accuracy of the driving current.

[0084] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for technical personnel in this field, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A pixel driving circuit, in, include: Light emitting element; A driving transistor, used for generating a driving current according to a data signal to drive the light emitting element to emit light; a data writing transistor, configured to transmit the data signal to the driving transistor in response to a second writing control signal; A storage capacitor, electrically connected to the driving transistor, for storing the data signal; an internal compensation transistor electrically connected between the gate of the driving transistor and the drain of the driving transistor, for compensating for a threshold voltage of the driving transistor in response to a first write control signal, the first write control signal being different from the second write control signal; An external compensation transistor is electrically connected to the source of the light emitting control transistor and the driving transistor, and is used to respond to a read / write control signal to read the electrical signal at the source of the driving transistor and to compensate for the threshold voltage of the driving transistor.

2. The pixel driving circuit according to claim 1, in, Also includes: a light emitting control transistor, electrically connected between the light emitting element and the driving transistor, and configured to transmit the driving current to the light emitting element in response to a first light emitting control signal; A reset transistor is electrically connected to the storage capacitor and the data writing transistor, and is used to respond to a second light emitting control signal to transmit a first signal to one end of the storage capacitor, wherein the first signal is different from a second signal loaded on the source of the driving transistor.

3. The pixel driving circuit according to claim 2, in, The pixel driving circuit has a data writing period in each frame, and in the data writing period, the first writing control signal is different from the second writing control signal; During the data writing period, the data writing transistor is used to respond to the second writing control signal to transmit the data signal to one end of the storage capacitor to turn on the driving transistor, and the internal compensation transistor is used to respond to the first writing control signal to electrically disconnect the gate of the driving transistor and the drain of the driving transistor.

4. The pixel driving circuit according to claim 3, in, The pixel driving circuit has a light-emitting period in each frame, during which the first light-emitting control signal is different from the second light-emitting control signal, and the first write control signal is the same as the second write control signal; During the light-emitting period, the reset transistor is used to respond to the second light-emitting control signal, and the data write transistor is used to respond to the second write control signal to jointly maintain the voltage at one end of the storage capacitor as the voltage corresponding to the data signal. The internal compensation transistor is used to respond to the first write control signal to maintain the voltage at the other end of the storage capacitor as the voltage during the data write period to keep the drive transistor turned on. The light-emitting control transistor is used to respond to the first light-emitting control signal to electrically connect the light-emitting element and the drive transistor to transmit the drive current to the light-emitting element.

5. The pixel driving circuit according to claim 2, in, The pixel driving circuit has a first reset period in each frame, and in the first reset period, the first write control signal is different from the second write control signal; During the first reset period, the data write transistor is used to respond to the second write control signal to transmit a third signal to one end of the storage capacitor, and the reset transistor is used to respond to the second light-emitting control signal to transmit the first signal to one end of the storage capacitor to realize at least one of the two functions to turn off the driving transistor, and the internal compensation transistor is used to respond to the first write control signal to electrically disconnect the gate of the driving transistor and the output end of the driving transistor.

6. The pixel driving circuit according to claim 5, in, During the first reset period, the first light emission control signal is different from the first write control signal; During the first reset period, the external compensation transistor is used to respond to the read-write control signal to transmit a fourth signal to the light-emitting control transistor, the light-emitting control transistor is used to respond to the first light-emitting control signal to transmit the second signal to the light-emitting element to reset the light-emitting element, and the internal compensation transistor is used to respond to the first write control signal to electrically disconnect the gate of the driving transistor and the output end of the driving transistor.

7. The pixel driving circuit according to claim 2, in, The pixel driving circuit has a second reset period in each frame, and in the second reset period, the first light emitting control signal is different from the first writing control signal; In the second reset period, the reset transistor is used to respond to the second light emitting control signal to transmit the first signal to one end of the storage capacitor, and the data writing transistor is used to respond to the second writing control signal to transmit the third signal to one end of the storage capacitor. At least one of the two functions is realized, the external compensation transistor is used to respond to the read-write control signal to transmit the fourth signal to the source of the driving transistor, and the internal compensation transistor is used to respond to the first writing control signal to electrically connect the gate of the driving transistor and the source of the driving transistor so that the fourth signal is transmitted to the gate of the driving transistor to reset the driving transistor; The light emitting control transistor is used to respond to the first light emitting control signal to be electrically disconnected from the driving transistor.

8. The pixel driving circuit according to claim 2, in, The pixel driving circuit has a threshold voltage external detection period before the first frame, and in the threshold voltage external detection period, the first light emitting control signal is different from the first writing control signal; During the threshold voltage external detection period, the reset transistor is used to respond to the second light-emitting control signal to transmit the first signal to one end of the storage capacitor, and the data writing transistor is used to respond to the second writing control signal to transmit the third signal to one end of the storage capacitor to achieve at least one of the two functions, the internal compensation transistor is used to respond to the first writing control signal to transmit the second signal to one end of the storage capacitor, and the external compensation transistor is used to respond to the read-write control signal to read the threshold voltage of the driving transistor; The light emitting control transistor is used to respond to the first light emitting control signal to be electrically disconnected from the driving transistor.

9. The pixel driving circuit according to claim 8, in, The pixel driving circuit has a light-emitting external detection period after the threshold voltage external detection period before the first frame, and in the light-emitting external detection period, the first write control signal is different from the second write control signal, and the first light-emitting control signal is different from the second light-emitting control signal; During the light-emitting external detection period, the data writing transistor is used to respond to the second writing control signal to transmit the target data signal to the storage capacitor to turn on the driving transistor, the light-emitting control transistor is used to respond to the first light-emitting control signal to electrically connect the light-emitting element and the driving transistor, the external compensation transistor is used to respond to the read-write control signal to read the electrical signal of the light-emitting element, and the target data signal is determined according to the data signal and the threshold voltage; The internal compensation transistor is used to respond to the first write control signal to electrically disconnect the gate of the driving transistor and the output end of the driving transistor, and the reset transistor is used to respond to the second light emitting control signal to electrically disconnect from the storage capacitor.

10. The pixel driving circuit according to claim 2, in, The pixel driving circuit has a light-emitting external detection period before the first frame, during which the first write control signal is different from the second write control signal, and the first light-emitting control signal is different from the second light-emitting control signal; During the light-emitting external detection period, the data writing transistor is used to respond to the second writing control signal to transmit a third signal to one end of the storage capacitor to turn off the driving transistor, the external compensation transistor is used to respond to the read-write control signal to transmit a fourth signal to the light-emitting control transistor, the light-emitting control transistor is used to respond to the first light-emitting control signal to electrically connect the light-emitting element and the driving transistor so that the fourth signal is transmitted to the light-emitting element, and the external compensation transistor is also used to respond to the read-write control signal to read the threshold voltage of the light-emitting element and compensate the threshold voltage of the driving transistor; The internal compensation transistor is used to respond to the first write control signal to electrically disconnect the gate of the driving transistor and the output end of the driving transistor, and the reset transistor is used to respond to the second light emitting control signal to electrically disconnect from the storage capacitor.

11. The pixel driving circuit according to claim 2, in, The first write control pulse of the first write control signal is used to turn on the internal compensation transistor, and the read / write control pulse of the read / write control signal is used to turn on the external compensation transistor; The first write control pulse in the first write control signal is overlapped with the read / write control pulse in the read / write control signal, and the starting point of the first write control pulse is earlier than the starting point of the corresponding read / write control pulse.

12. The pixel driving circuit according to claim 2, in, The second write control pulse of the second write control signal is used to turn on the data write transistor, and the second light emission control pulse of the second light emission control signal is used to turn on the reset transistor; Among them, a second write control pulse in the second write control signal and a second light-emitting control pulse in the second light-emitting control signal close to the corresponding second write control pulse are staggered.

13. The pixel driving circuit according to claim 2, in, The first light-emitting control pulse of the first light-emitting control signal is used to turn on the light-emitting control transistor, the read-write control pulse of the read-write control signal is used to turn on the external compensation transistor, and the first write control pulse of the first write control signal is used to turn on the internal compensation transistor; Among them, the first light-emitting control pulse in the first light-emitting control signal is overlapped with the read-write control pulse in the read-write control signal, and is staggered with the first write control pulse in the first write control signal that is close to the corresponding first light-emitting control pulse.

14. The pixel driving circuit according to claim 2, in, The second write control pulse of the second write control signal is used to turn on the data write transistor, and the read and write control pulse of the read and write control signal is used to turn on the external compensation transistor; Among them, a second write control pulse in the second write control signal and a read / write control pulse in the read / write control signal close to the corresponding second write control pulse are staggered, and the second write control pulse is located before the corresponding read / write control pulse.

15. The pixel driving circuit according to claim 14, in, The first light emitting control pulse of the first light emitting control signal is used to turn on the light emitting control transistor; Among them, the first light-emitting control pulse in the first light-emitting control signal and the second write control pulse in the second write control signal are overlapped, and the starting point of the first light-emitting control pulse is earlier than or equal to the starting point of the corresponding second write control pulse, and the end point of the first light-emitting control pulse is later than the end point of the corresponding second write control pulse.

16. The pixel driving circuit according to claim 2, in, The second light-emitting control pulse of the second light-emitting control signal is used to turn on the reset transistor, the first write control pulse of the first write control signal is used to turn on the internal compensation transistor, and the read-write control pulse of the read-write control signal is used to turn on the external compensation transistor; The second light-emitting control pulse in the second light-emitting control signal is overlapped with the first write control pulse in the first write control signal.

17. The pixel driving circuit according to claim 2, in, The second write control pulse of the second write control signal is used to turn on the data write transistor, and the first write control pulse of the first write control signal is used to turn on the internal compensation transistor; The second write control pulse in the second write control signal is alternately arranged with the first write control pulse in the first write control signal that is close to the corresponding second write control pulse, and the first write control pulse is located before the corresponding second write control pulse.

18. The pixel driving circuit according to claim 2, in, The first light-emitting control pulse of the first light-emitting control signal is used to turn on the light-emitting control transistor, the first write control pulse of the first write control signal is used to turn on the internal compensation transistor, and the read-write control pulse of the read-write control signal is used to turn on the external compensation transistor; Among them, the first light-emitting control pulse in the first light-emitting control signal is staggered with the first write control pulse in the first write control signal that is close to the corresponding first light-emitting control pulse, and is staggered with the read-write control pulse in the read-write control signal that is close to the corresponding first light-emitting control pulse, and the first light-emitting control pulse is located after the corresponding first write control pulse and the corresponding read-write control pulse.

19. A display panel, in, include: A panel body, comprising a pixel driving circuit as claimed in any one of claims 2 to 18; The driving chip is electrically connected to the pixel driving circuit to drive the pixel driving circuit to work.

20. The display panel according to claim 19, in, The panel body also includes a multi-stage gate driving circuit arranged in cascade; The driver chip comprises: a timing controller, wherein each gate driving circuit is electrically connected between the timing controller and the corresponding plurality of pixel driving circuits, and is configured to respond to a first control signal output by the timing controller to output the first light-emitting control signal, the second light-emitting control signal, the first write control signal, or the second write control signal; At least one source driver is electrically connected between the timing controller and the corresponding plurality of pixel driving circuits, and is used for responding to a second control signal output by the timing controller to output the data signal.

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