Display panel and display apparatus

Abstract

Provided are a display panel and a display apparatus. A first physical part is connected to a data line and a signal wire, and a first gap is provided between the first physical part and a first dummy part. The display panel comprises a first metal layer and a second metal layer which are stacked; the first physical part comprises a first portion located on the first metal layer, and the first dummy part comprises a third portion located on the first metal layer; the first portion comprises a first end of the first physical part, and the third portion comprises a first end of the first dummy part.

Description

Display panel and display device Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Compared with liquid crystal displays, organic light-emitting diode (OLED) display panels have the advantages of being thinner and lighter, having better display effects, higher resolution, wider color gamut, lower power consumption, and flexible display. As a result, they have developed rapidly in recent years and have become the preferred display panel type for mobile terminals.

[0003] Currently, to achieve a narrow bezel effect, a display architecture in which signal routing is in the display area (full name: Fanout in Active Area, abbreviated as FIAA) is adopted. The FIAA routing in the display area is used to connect data lines and signal routing (such as fan-out routing (also known as fanout routing, but it may not have a fan-shaped planar form)), usually including horizontal connecting lines and vertical connecting lines. Currently, in order to reduce the production cost of display panels and simplify the process flow, the display panel is simplified from three source and drain metal layers to two source and drain metal layers, and the horizontal connecting lines and the vertical connecting lines are arranged in the two source and drain metal layers, which shortens the vertical distance between the horizontal connecting lines, the vertical connecting lines and the anode.

[0004] Due to the layout design requirements of the display area, the horizontal and vertical connecting lines should be arranged in different metal film layers, and each horizontal and vertical connecting line is electrically connected to only one data line. This requires a break (or gap, in which the horizontal connecting line is divided into two parts) to be formed on each horizontal connecting line, and a break to be formed on each vertical connecting line. The breaks on each of the horizontal and vertical connecting lines are arranged linearly, and because the breaks are located in the display area, the display panel will produce linear moiré (full English name: mura) when the screen is off, causing the problem of screen-off mura, which needs to be solved urgently. SUMMARY OF THE INVENTION

[0005] The present application provides a display panel and a display device, which can effectively solve the problem of off-screen mura existing in the existing FIAA architecture OLED display panel.

[0006] In the first aspect, the present application provides a display panel, which has a display area and a non-display area, the display area is provided with multiple data lines and multiple first connection lines, the data lines and the first connection lines are cross-arranged, and the non-display area is provided with multiple signal lines; wherein, each of the first connection lines includes a first physical portion and a first dummy portion arranged at intervals, the first physical portion is electrically connected to the data line and the signal line, the first dummy portion is electrically insulated from the first physical portion, and a first gap is provided between the first end of the first physical portion and the first end of the first dummy portion; wherein, the display panel includes a substrate and a first metal layer and a second metal layer stacked in sequence on the substrate, the display panel also includes multiple thin film transistors, at least one of the source and the drain of the thin film transistor is located in the second metal layer; wherein, the first physical portion includes a first part located in the first metal layer, the first dummy portion includes a third part located in the first metal layer, and the first part includes the first end of the first physical portion, and the third part includes the first end of the first dummy portion.

[0007] In a second aspect, the present application provides a display device, comprising a housing and a display panel as described above, wherein the housing has an accommodating space, and the display panel is disposed in the accommodating space. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0009] FIG1 is a schematic plan view of a display panel provided in Embodiment 1 of the present application.

[0010] FIG2 is a partial enlarged view of the A1 area in FIG1 .

[0011] FIG3 is a partial enlarged view of FIG2 .

[0012] FIG4 is a schematic diagram showing the position distribution of multiple pixel areas provided in Example 1 of the present application.

[0013] FIG5 is a plan view of a reset signal line and a reset signal connection line provided in the first embodiment of the present application.

[0014] FIG6 is a schematic cross-sectional view of a display panel provided in the first embodiment of the present application.

[0015] FIG. 7 is another partial enlarged view of the A1 area in FIG. 1 .

[0016] Description of reference numerals:

[0017] Display panel 10; display area 11; non-display area 12; pixel area 13; data line Ma; signal trace Mb; first connecting line Mc; first solid portion Mc1; first end Mc10 of the first solid portion; first part Mc11; first sub-portion Mc111; second part Mc12; second sub-portion Mc121; first dummy portion Mc2; first end Mc20 of the first dummy portion; third part Mc21; third sub-portion Mc211; fourth part Mc22; fourth sub-portion Mc221; first gap Mc3; second connecting line Md; second solid portion Md1; first end Md10 of the second solid portion; second dummy portion Md2; first end Md20 of the second dummy portion; second gap Md3; reset signal connecting line Mvic; gate reset signal connecting line Mvi c1; anode reset signal connection line Mvic2; reset signal line Mvi; gate reset signal line Mvi1; anode reset signal line Mvi2; power signal line Me; fifth part Me1; fifth sub-part Me11; sixth part Me2; substrate 20; first substrate layer 21; first barrier layer 22; second substrate layer 23; first metal layer 30; second metal layer 40; third metal layer 50; anode layer 60; fourth metal layer 70; first barrier layer 81; second barrier layer 82; buffer layer 83; active layer 84; first gate insulating layer 85; second gate insulating layer 86; interlayer dielectric layer 87; first planarization layer 88; second planarization layer 89; pixel definition layer 90; pad layer 91; first gate GE1; second gate GE2; source S1; drain D1; Modes for Carrying Out the Invention

[0018] In the first aspect, the present application provides a display panel, which has a display area and a non-display area, the display area is provided with multiple data lines and multiple first connection lines, the data lines and the first connection lines are cross-arranged, and the non-display area is provided with multiple signal lines; wherein, each of the first connection lines includes a first physical portion and a first dummy portion arranged at intervals, the first physical portion is electrically connected to the data line and the signal line, the first dummy portion is electrically insulated from the first physical portion, and a first gap is provided between the first end of the first physical portion and the first end of the first dummy portion; wherein, the display panel includes a substrate and a first metal layer and a second metal layer stacked in sequence on the substrate, the display panel also includes multiple thin film transistors, at least one of the source and the drain of the thin film transistor is located in the second metal layer; wherein, the first physical portion includes a first part located in the first metal layer, the first dummy portion includes a third part located in the first metal layer, and the first part includes the first end of the first physical portion, and the third part includes the first end of the first dummy portion.

[0019] Optionally, the first entity portion further includes a second portion located in the second metal layer, the second portion is electrically connected to the first portion through a via connection, and the resistivity of the first metal layer is greater than the resistivity of the second metal layer.

[0020] Optionally, one of the gate electrodes of the thin film transistor is located in the first metal layer.

[0021] Optionally, the display area is further provided with a plurality of reset signal connection lines, and the reset signal connection lines are arranged to cross the first connection lines; wherein, the reset signal connection lines are located in the second metal layer, the first part includes at least one first sub-part, and the second part includes at least one second sub-part, and in the extension direction of the first physical part, the first sub-part and the second sub-part are alternately arranged in sequence; wherein, the reset signal connection line spans a plurality of the first connection lines, and in the direction perpendicular to the substrate, the part where the first physical part overlaps with the reset signal connection line is the first sub-part.

[0022] Optionally, the first dummy part includes a fourth part located in the second metal layer, the fourth part is electrically connected to the third part through a via connection, the third part includes at least one third sub-part, and the fourth part includes at least one fourth sub-part, and in the extension direction of the first dummy part, the third sub-part and the fourth sub-part are alternately arranged in sequence; wherein, in the direction perpendicular to the substrate, the part of the first dummy part that overlaps with the reset signal connection line is the third sub-part.

[0023] Optionally, the display area is further provided with a plurality of second connecting lines, which are arranged to cross the first connecting lines, and each of the second connecting lines includes a second solid portion and a second dummy portion arranged at intervals, the first solid portion is electrically connected to the signal line through the second solid portion, the second dummy portion is electrically insulated from the second solid portion, and a second gap is provided between the first end of the second solid portion and the first end of the second dummy portion; wherein, the display panel also includes a third metal layer, the third metal layer is provided on the side of the second metal layer away from the substrate, the second connecting line and the data line are both located in the third metal layer, and in the direction perpendicular to the substrate, the second gap overlaps with the reset signal connecting line.

[0024] Optionally, the reset signal connection line and the second connection line extend in the same direction, and in a direction perpendicular to the substrate, an overlapping area of ​​the second connection line and the reset signal connection line accounts for more than 50% of a total area of ​​the second connection line.

[0025] Optionally, the display area is also provided with a plurality of reset signal lines, the reset signal lines and the first connecting lines extending in the same direction, and being located in the first metal layer, and the reset signal lines and the first connecting lines not overlapping in a direction perpendicular to the substrate; wherein the reset signal lines and the reset signal connecting lines are cross-arranged to form a grid structure arranged in an array.

[0026] Optionally, the multiple reset signal lines include alternately arranged gate reset signal lines and anode reset signal lines, and the multiple reset signal connection lines include alternately arranged gate reset signal connection lines and anode reset signal connection lines; wherein the gate reset signal line is electrically connected to the gate reset signal connection line, and the anode reset signal line is electrically connected to the anode reset signal connection line.

[0027] Optionally, the display area is further provided with a power signal line, and the power signal line includes a fifth part and a sixth part, and the extension direction of the fifth part and the extension direction of the sixth part are the same as the extension direction of the data line. In the direction perpendicular to the substrate, the fifth part does not overlap with the data line and the second connecting line, and the sixth part does not overlap with the data line and the second connecting line; wherein, the fifth part is located in the second metal layer, and the fifth part includes a plurality of fifth sub-parts arranged at intervals, and two adjacent fifth sub-parts are spaced apart by the second sub-part or the fourth sub-part; wherein, the sixth part is located in the third metal layer, and the sixth part is continuously arranged and connected in parallel with the fifth part.

[0028] Optionally, a line connecting three adjacent first gaps is a curve.

[0029] Optionally, a line connecting three adjacent second gaps is a curve.

[0030] Optionally, the display panel further includes an anode layer, which is arranged on a side of the second metal layer facing away from the substrate, wherein an orthographic projection of the anode layer on the substrate covers an orthographic projection of the first gap on the substrate.

[0031] Optionally, the display panel further includes an anode layer, which is arranged on a side of the third metal layer facing away from the substrate, wherein an orthographic projection of the anode layer on the substrate covers an orthographic projection of the second gap on the substrate.

[0032] In a second aspect, the present application provides a display device, comprising a housing and a display panel as described above, wherein the housing has an accommodating space, and the display panel is disposed in the accommodating space.

[0033] The present application provides a display panel and a display device, wherein the display panel has a display area and a non-display area, the display area is provided with a plurality of data lines and a plurality of first connection lines, the data lines and the first connection lines are arranged crosswise, and the non-display area is provided with a plurality of signal traces; wherein each of the first connection lines includes a first solid portion and a first dummy portion arranged at intervals, the first solid portion is electrically connected to the data line and the signal trace, the first dummy portion is electrically insulated from the first solid portion, and a first gap is provided between the first end of the first solid portion and the first end of the first dummy portion; wherein the display panel includes a substrate and a first metal layer and a second metal layer stacked in sequence on the substrate, the display panel also includes a plurality of thin film transistors, at least one of the source and the drain of the thin film transistor is located at The second metal layer; wherein, the first solid part includes a first part located in the first metal layer, the first dummy part includes a third part located in the first metal layer, and the first part includes a first end of the first solid part, and the third part includes a first end of the first dummy part. In the display panel provided in the present application, due to the first connecting line located in the display area, a first gap is provided between the first end of the first solid part and the first end of the first dummy part, and the first end of the first solid part and the first end of the first dummy part are both located in the first metal layer with a lower film layer position relative to the second metal layer, so that the first gap has less influence on the film layer flatness of the pixel area in the display area, thereby improving the screen-off mura problem and improving the appearance characteristics of the display panel in the screen-off state.

[0034] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0035] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed. In addition, examples of various specific processes and materials are provided in the present application, but a person of ordinary skill in the art will recognize the application of other processes and / or the use of other materials. Each of the following is described in detail. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0036] Figure 1 is a schematic plan view of a display panel provided in Example 1 of the present application; Figure 2 is a partial enlarged view of area A1 in Figure 1; Figure 3 is a partial enlarged view of Figure 2; Figure 4 is a schematic diagram of the position distribution of multiple pixel areas provided in Example 1 of the present application; Figure 5 is a schematic plan view of a reset signal line and a reset signal connection line provided in Example 1 of the present application; and Figure 6 is a schematic cross-sectional view of a display panel provided in Example 1 of the present application. In conjunction with Figures 1-6, in a first aspect, Example 1 of the present application provides a display panel, which may be an OLED display panel.

[0037] Specifically, the display panel 10 has a display area 11 and a non-display area 12, the display area 11 is provided with a plurality of data lines Ma and a plurality of first connecting lines Mc, the data lines Ma and the first connecting lines Mc are arranged to cross each other, and the non-display area 12 is provided with a plurality of signal lines Mb, wherein each of the first connecting lines Mc includes a first solid portion Mc1 and a first dummy portion Mc2 arranged at intervals, the first solid portion Mc1 is electrically connected to the data line Ma and the signal line Mb, the first dummy portion Mc2 is electrically insulated from the first solid portion Mc1, and a first gap is provided between a first end Mc10 of the first solid portion Mc1 and a first end Mc20 of the first dummy portion Mc2. Mc3; wherein, the display panel 10 includes a substrate 20 and a first metal layer 30 and a second metal layer 40 stacked in sequence on the substrate 20, and the display panel 10 also includes a plurality of thin film transistors, at least one of the source S1 and the drain D1 of the thin film transistor is located in the second metal layer 40; wherein, the first physical part Mc1 includes a first part Mc11 located in the first metal layer 30, the first virtual part Mc2 includes a third part Mc21 located in the first metal layer 30, and the first part Mc11 includes the first end Mc10 of the first physical part Mc1, and the third part Mc21 includes the first end Mc20 of the first virtual part Mc2.

[0038] In the display panel 10 provided in the present application, the signal trace Mb is a fan-out trace, which may not have a fan-shaped planar shape. The first connecting line Mc is arranged to intersect with the data line Ma. The first solid portion Mc1 of the first connecting line Mc electrically connects the data line Ma and the signal trace Mb. The first dummy portion Mc2 of the first connecting line Mc is electrically insulated from the first solid portion Mc1. That is, the first dummy portion Mc2 is a FIAA horizontal connecting line provided in the display area 11, and the first dummy portion Mc2 is a dummy trace provided in the display area 11 corresponding to the FIAA horizontal connecting line.

[0039] Because the display area 11 includes multiple pixel areas 13 (or effective light-emitting areas) arranged in an array, and the first connecting line Mc is located in the display area 11, the first gap Mc3 between the first end Mc10 of the first solid portion Mc1 and the first end Mc20 of the first dummy portion Mc2 can easily affect the flatness of the film layer in the pixel area 13, for example, the flatness of the anode in the pixel area 13. When the first gaps Mc3 are arranged linearly, the flatness of the anodes in the corresponding pixel areas 13 is reduced, causing each anode to form a linear depression in the area corresponding to the first gaps Mc3. This, in turn, causes linear mura in the display panel 10 when the screen is off, affecting the appearance of the display panel 10 when the screen is off.

[0040] In the display panel 10 provided in the present application, since a first gap Mc3 is provided between the first end Mc10 of the first solid part Mc1 and the first end Mc20 of the first dummy part Mc2 in the first connecting line Mc located in the display area 11, and the first end Mc10 of the first solid part Mc1 and the first end Mc20 of the first dummy part Mc2 are both located in the first metal layer 30 having a lower film layer position relative to the second metal layer 40, so that the first gap Mc3 has less influence on the film layer flatness of the pixel area 13 in the display area 11, thereby improving the screen-off mura problem and improving the appearance characteristics of the display panel 10 in the screen-off state.

[0041] In some embodiments of the present application, the display panel 10 further includes an anode layer 60, which is disposed on a side of the second metal layer 40 away from the substrate 20, and the anode layer 60 includes a plurality of anodes, which are correspondingly disposed within the pixel area 13, wherein the orthographic projection of the anode layer 60 on the substrate 20 covers the orthographic projection of the first gap Mc3 on the substrate 20.

[0042] In the display panel 10 provided in the present application, since the orthographic projection of the anode layer 60 on the substrate 20 covers the orthographic projection of the first gap Mc3 on the substrate 20, and the first end Mc10 of the first solid part Mc1 and the first end Mc20 of the first virtual part Mc2 on both sides of the first gap Mc3 are both located in the first metal layer 30 whose film layer position is lower than that of the second metal layer 40, the influence of the first gap Mc3 on the flatness of each anode can be weakened, and the problem of each anode forming a linearly arranged depression in the area corresponding to the first gap Mc3 when the first gaps Mc3 are linearly arranged is improved, thereby improving the appearance characteristics of the display panel 10 when the screen is off.

[0043] In some embodiments of the present application, the first physical portion Mc1 also includes a second portion Mc12 located in the second metal layer 40, the second portion Mc12 is electrically connected to the first portion Mc11 through a via connection, and the resistivity of the first metal layer 30 is greater than the resistivity of the second metal layer 40.

[0044] In the display panel 10 provided in the present application, because the resistivity of the first metal layer 30 is greater than that of the second metal layer 40, when the first solid portion Mc1 is entirely located in the first metal layer 30, the resistance of the first solid portion Mc1 will be greatly increased, affecting the transmission of data signals and, in turn, the display quality of the display panel 10. To overcome the aforementioned problem of increased resistance of the first solid portion Mc1, the present application locates the first portion Mc11 of the first solid portion Mc1 in the first metal layer 30, while the second portion Mc12 of the first solid portion Mc1 is located in the second metal layer 40, which has a lower resistivity than the first metal layer 30. This reduces the resistance of the first solid portion Mc1, improves the transmission quality of the data signals of the first solid portion Mc1, and thus improves the display quality of the display panel 10.

[0045] In some embodiments of the present application, one of the gates of the thin film transistor is located in the first metal layer 30. That is, the first portion Mc11 of the first solid portion Mc1 is disposed in the same layer as one of the gates of the thin film transistor, and the material of the one of the gates is different from the material of at least one of the source S1 and the drain D1.

[0046] In some embodiments of the present application, the display area 11 is further provided with a plurality of reset signal connection lines Mvic, and the reset signal connection line Mvic is arranged to cross the first connection line Mc; wherein, the reset signal connection line Mvic is located in the second metal layer 40, the first part Mc11 includes at least one first sub-part Mc111, and the second part Mc12 includes at least one second sub-part Mc121, and in the extension direction of the first physical part Mc1, the first sub-part Mc111 and the second sub-part Mc121 are alternately arranged in sequence; wherein, the reset signal connection line Mvic spans a plurality of the first connection lines Mc, and in the direction perpendicular to the substrate 20, the part where the first physical part Mc1 overlaps with the reset signal connection line Mvic is the first sub-part Mc111.

[0047] In the display panel 10 provided in the present application, since the reset signal connection line Mvic and the first connection line Mc are arranged to intersect each other, the reset signal connection line Mvic and the first connection line Mc located in the same film layer will affect each other, that is, the reset signal connection line Mvic and the first physical portion Mc1 of the first connection line Mc cannot be arranged in the same layer at the intersection position.

[0048] First, the present application arranges the reset signal connection line Mvic in the second metal layer 40 having a lower resistivity, thereby improving the conduction efficiency of the multiple reset signal lines Mvi connected in parallel through the reset signal connection line Mvic; secondly, since the first portion Mc11 includes at least one first sub-portion Mc111, and the second portion Mc12 includes at least one second sub-portion Mc121, in the extension direction of the first physical portion Mc1, the first sub-portion Mc111 and the second portion Mc121 are alternately arranged in sequence, and in the direction perpendicular to the substrate 20, The portion where the first physical portion Mc1 overlaps with the reset signal connection line Mvic is the first sub-portion Mc111 which is on a different layer from the reset signal connection line Mvic. Therefore, while increasing the portion of the first connection line Mc located in the second metal layer 40 having a lower resistivity as much as possible, the bridge design of the first sub-portion Mc111 ensures that the reset signal connection line Mvic spanning multiple first connection lines Mc and the first physical portion Mc1 in the first connection line Mc do not interfere with each other at the intersection, thereby optimizing the circuit layout of the display panel 10.

[0049] In some embodiments of the present application, the first dummy portion Mc2 includes a fourth portion Mc22 located in the second metal layer 40, the fourth portion Mc22 is electrically connected to the third portion Mc21 through a via connection, the third portion Mc21 includes at least one third sub-portion Mc211, and the fourth portion Mc22 includes at least one fourth sub-portion Mc221. In the extension direction of the first dummy portion Mc2, the third sub-portion Mc211 and the fourth sub-portion Mc221 are alternately arranged in sequence; wherein, in the direction perpendicular to the substrate 20, the portion of the first dummy portion Mc2 that overlaps with the reset signal connection line Mvic is the third sub-portion Mc211.

[0050] Similarly, in the display panel 10 provided in the present application, since the reset signal connection line Mvic and the first connection line Mc are arranged to cross each other, the reset signal connection line Mvic and the first connection line Mc located in the same film layer will affect each other, that is, the reset signal connection line Mvic and the first dummy portion Mc2 in the first connection line Mc cannot be arranged on the same layer at the crossing position.

[0051] First, the present application arranges the first dummy portion Mc2 into a form in which the third sub-portion Mc211 and the fourth sub-portion Mc221 are alternately arranged in sequence, so that the circuit structure of the first dummy portion Mc2 is similar to that of the first physical portion Mc1, thereby making the first connecting lines Mc of the display area 11 have a more uniform pattern design, thereby improving the appearance characteristics of the display panel 10; secondly, the present application arranges the overlapping part of the first dummy portion Mc2 and the reset signal connecting line Mvic in a direction perpendicular to the substrate 20 to be the third sub-portion Mc211 of a different layer from the reset signal connecting line Mvic, so that the reset signal connecting line Mvic spanning multiple first connecting lines Mc will not interfere with the first dummy portion Mc2 in the first connecting line Mc at the intersection position, thereby making the circuit layout of the display panel 10 better.

[0052] In some embodiments of the present application, the third sub-portion Mc211 and the first sub-portion Mc111 have the same shape, and the fourth sub-portion Mc221 and the second sub-portion Mc121 have the same shape, so that the first connecting lines Mc in the display area 11 have a more uniform pattern design.

[0053] In some embodiments of the present application, the display area 11 is further provided with a plurality of second connecting lines Md, which are arranged to cross the first connecting lines Mc, and each of the second connecting lines Md includes a second physical portion Md1 and a second virtual portion Md2 arranged at intervals, the first physical portion Mc1 is electrically connected to the signal trace Mb through the second physical portion Md1, the second virtual portion Md2 is electrically insulated from the second physical portion Md1, and a second gap Md3 is provided between the first end Md10 of the second physical portion Md1 and the first end Md20 of the second virtual portion Md2; wherein, the display panel 10 also includes a third metal layer 50, the third metal layer 50 is provided on the side of the second metal layer 40 away from the substrate 20, the second connecting line Md and the data line Ma are both located in the third metal layer 50, and in the direction perpendicular to the substrate 20, the second gap Md3 overlaps with the reset signal connecting line Mvic.

[0054] Because the display area 11 includes multiple pixel areas 13 (or effective light-emitting areas) arranged in an array, and the second connecting line Md is located in the display area 11, the second gap Md3 between the first end Md10 of the second solid portion Md1 and the first end Md20 of the second dummy portion Md2 can easily affect the film flatness of the pixel areas 13, for example, the flatness of the anodes in the pixel areas 13. When the second gaps Md3 are arranged linearly, the flatness of the anodes in the corresponding pixel areas 13 is reduced, causing linear depressions in the anodes corresponding to the second gaps Md3. This, in turn, causes linear mura in the display panel 10 when the screen is off, affecting its appearance. Furthermore, because the second connecting line Md located in the display area 11 must meet design requirements on a different layer than the first connecting line Mc and must be disposed in the relatively higher third metal layer 50 along with the data line Ma, the second gap Md3 has a greater impact on the appearance of the display panel 10 when the screen is off.

[0055] The present application utilizes the reset signal connection line Mvic already existing in the display architecture so that the second gap Md3 overlaps with the reset signal connection line Mvic in a direction perpendicular to the substrate 20, thereby utilizing the reset signal connection line Mvic to support the second gap Md3, thereby reducing the probability of the anode layer 60 having a flattening problem at the second gap Md3; and weakening the light diffraction effect at each of the linearly arranged second gaps Md3, thereby improving the off-screen mura problem at the second gap Md3.

[0056] In some embodiments of the present application, the second metal layer 40 and the third metal layer 50 are made of the same material, so that the reset signal connection line Mvic and the second connection line Md have the same visual effect, further weakening the light diffraction effect at each of the linearly arranged second gaps Md3.

[0057] In some embodiments of the present application, the anode layer 60 is disposed on a side of the third metal layer 50 facing away from the substrate 20 , wherein the orthographic projection of the anode layer 60 on the substrate 20 covers the orthographic projection of the second gap Md3 on the substrate 20 .

[0058] In the display panel 10 provided in the present application, since the orthographic projection of the anode layer 60 on the substrate 20 covers the orthographic projection of the second gap Md3 on the substrate 20, and in the direction perpendicular to the substrate 20, the second gap Md3 overlaps with the reset signal connection line Mvic, the influence of the second gap Md3 on the flatness of each anode can be weakened, thereby improving the problem of each anode forming a linearly arranged depression in the area corresponding to the second gap Md3 when the second gaps Md3 are linearly arranged, thereby improving the appearance characteristics of the display panel 10 when the screen is off.

[0059] In some embodiments of the present application, each of the reset signal connection lines Mvic is continuously arranged in the display area 11.

[0060] In some embodiments of the present application, the reset signal connection line Mvic and the second connection line Md have the same extension direction, and in the direction perpendicular to the substrate 20, the overlapping area of ​​the second connection line Md and the reset signal connection line Mvic accounts for more than 50% of the total area of ​​the second connection line Md.

[0061] In the display panel 10 provided in the present application, since the reset signal connection line Mvic is a layout design that already exists in the display architecture, the present application makes the overlapping area of ​​the second connection line Md and the reset signal connection line Mvic account for more than 50% of the total area of ​​the second connection line Md, so that the second connection line Md and the reset signal connection line Mvic can overlap as much as possible in the direction perpendicular to the substrate 20, thereby enabling when the display panel 10 has an under-screen fingerprint sensing module (full name: Fingerprint on Display, abbreviated: FOD), to improve the transmittance of the under-screen fingerprint sensing module and improve the fingerprint sensing accuracy.

[0062] In some embodiments of the present application, the display area 11 is further provided with a plurality of reset signal lines Mvi, the reset signal lines Mvi and the first connecting lines Mc extending in the same direction, and being located in the first metal layer 30, and in a direction perpendicular to the substrate 20, the reset signal lines Mvi and the first connecting lines Mc do not overlap; wherein, the reset signal lines Mvi and the reset signal connecting lines Mvic are cross-arranged to form a grid structure arranged in an array.

[0063] In the display panel 10 provided in the present application, since the reset signal line Mvi and the first connection line Mc extend in the same direction and are located in the first metal layer 30, the reset signal line Mvi will not interfere with the reset signal connection line Mvic located in the second metal layer 40, the data line Ma located in the third metal layer 50, and the second connection line Md. Moreover, since the reset signal line Mvi and the first connection line Mc do not overlap in the direction perpendicular to the substrate 20, the reset signal line Mvi will not interfere with the first connection line Mc, thereby effectively reducing the difficulty of layout design. In addition, since the reset signal line Mvi and the reset signal connection line Mvic are arranged in an intersecting manner and form a grid structure arranged in an array, the patterned structure of each area can be regularized, thereby improving the display uniformity of the display panel 10.

[0064] In some embodiments of the present application, the multiple reset signal lines Mvi include alternately arranged gate reset signal lines Mvi1 and anode reset signal lines Mvi2, and the multiple reset signal connection lines Mvic include alternately arranged gate reset signal connection lines Mvic1 and anode reset signal connection lines Mvic2; wherein, the gate reset signal line Mvi1 is electrically connected to the gate reset signal connection line Mvic1, and the anode reset signal line Mvi2 is electrically connected to the anode reset signal connection line Mvic2.

[0065] In the display panel 10 provided in the present application, the multiple reset signal lines Mvi include alternately arranged gate reset signal lines Mvi1 and anode reset signal lines Mvi2, and the multiple reset signal connection lines Mvic include alternately arranged gate reset signal connection lines Mvic1 and anode reset signal connection lines Mvic2. Therefore, the display panel 10 can achieve gate reset and anode reset, increase the types of reset signals of the display panel 10, and improve the display quality of the display panel 10.

[0066] In some embodiments of the present application, the display area 11 is further provided with a power signal line Me, and the power signal line Me includes a fifth part Me1 and a sixth part Me2. The extension direction of the fifth part Me1 and the extension direction of the sixth part Me2 are the same as the extension direction of the data line Ma. In the direction perpendicular to the substrate 20, the fifth part Me1 does not overlap with the data line Ma and the second connecting line Md, and the sixth part Me2 does not overlap with the data line Ma and the second connecting line Md; wherein, the fifth part Me1 is located in the second metal layer 40, and the fifth part Me1 includes a plurality of fifth sub-parts Me11 arranged at intervals, and two adjacent fifth sub-parts Me11 are spaced apart by the second sub-part Mc121 or the fourth sub-part Mc221; wherein, the sixth part Me2 is located in the third metal layer 50, and the sixth part Me2 is continuously arranged and connected in parallel with the fifth part Me1.

[0067] In the display panel 10 provided in the present application, the power signal line Me can be a VDD signal line. Since the extension direction of the fifth part Me1 and the extension direction of the sixth part Me2 are the same as the extension direction of the data line Ma, and in the direction perpendicular to the substrate 20, the fifth part Me1 does not overlap with the data line Ma and the second connecting line Md, and the sixth part Me2 does not overlap with the data line Ma and the second connecting line Md, the power signal line Me will not interfere with the data line Ma and the second connecting line Md, which can effectively reduce the difficulty of layout design.

[0068] Moreover, since the fifth part Me1 is located in the second metal layer 40, the fifth part Me1 includes a plurality of fifth sub-parts Me11 arranged at intervals, and two adjacent fifth sub-parts Me11 are spaced apart by the second sub-part Mc121 or the fourth sub-part Mc221, that is, the two adjacent fifth sub-parts Me11 are disconnected at the second part Mc121 or the fourth sub-part Mc221 arranged in the same layer, thereby avoiding interference between the fifth part Me1 in the power signal line Me and the second part Mc12 or the fourth sub-part Mc221 in the first connecting line Mc, and effectively reducing the difficulty of layout design.

[0069] In addition, since the sixth portion Me2 is located in the third metal layer 50, the sixth portion Me2 is continuously arranged and connected in parallel with the fifth portion Me1. Therefore, by connecting the fifth portion Me1 and the sixth portion Me2 in parallel, the resistance of the power signal line Me can be reduced, the resistance-capacitance delay can be reduced, and the display uniformity of the display panel 10 can be improved.

[0070] In some embodiments of the present application, the display panel 10 includes a thin film transistor, which includes a first gate electrode GE1, a second gate electrode GE2, a source electrode S1, and a drain electrode D1. The second gate electrode GE2 is located in the first metal layer 30, and the source electrode S1 and the drain electrode D1 are located in the second metal layer 40. The display panel 10 also includes a fourth metal layer 70 disposed on a side of the first metal layer 30 close to the substrate 20, and the first gate electrode GE1 is located in the fourth metal layer 70. Of course, the present application does not limit the positions of the first gate electrode, the second gate electrode, and the fourth metal layer. In other embodiments of the present application, the fourth metal layer may be disposed between the first metal layer 30 and the second metal layer 40, the first gate electrode may be located in the first metal layer 30, and the second gate electrode may be located in the fourth metal layer.

[0071] In some embodiments of the present application, at least one of the material and film structure of the first metal layer 30 is different from the material and film structure of the second metal layer 40 , and the material and film structure of the second metal layer 40 are the same as the material and film structure of the third metal layer 50 .

[0072] In some embodiments of the present application, a reset signal line Mvi is provided between two adjacent first connection lines Mc, and a reset signal line Mvic is provided between two adjacent second connection lines Md. Furthermore, a line connecting three adjacent first gaps Mc3 is a straight line, and a line connecting three adjacent second gaps Md3 is a straight line.

[0073] In some embodiments of the present application, the substrate 20 includes a first substrate layer 21, a first barrier layer 22, and a second substrate layer 23. Of course, in other embodiments of the present application, the substrate 20 may include only the first substrate layer 21.

[0074] In some embodiments of the present application, the display panel 10 further includes a first barrier layer 81, a second barrier layer 82, a buffer layer 83, an active layer 84, a first gate insulating layer 85, a second gate insulating layer 86, an interlayer dielectric layer 87, a first flat layer 88, a second flat layer 89, a pixel definition layer 90 and a pad layer 91 stacked sequentially on the substrate 20, wherein the fourth metal layer 70 is arranged on the side of the first gate insulating layer 85 away from the substrate 20, and the second gate insulating layer 86 is arranged on the fourth metal layer 70 and the first metal layer 81. The interlayer dielectric layer 87 is arranged between the first metal layer 30 and the second metal layer 40, the first flat layer 88 is arranged between the second metal layer 40 and the third metal layer 50, the second flat layer 89 is arranged on the side of the third metal layer 50 away from the substrate 20, the anode layer 60 is arranged on the side of the second flat layer 89 away from the substrate 20, the pixel definition layer 90 is arranged on the side of the anode layer 60 away from the substrate 20, and the pixel definition layer 90 and the pad layer 91 are formed as one piece.

[0075] In a second aspect, a first embodiment of the present application provides a display device, comprising a housing and a display panel 10 as described above, wherein the housing has an accommodating space, and the display panel 10 is disposed in the accommodating space.

[0076] Example 2

[0077] FIG7 is another partial enlarged view of the A1 area in FIG1. ​​In combination with FIG1, FIG6 and FIG7, a second embodiment of the present application provides a display panel 10 and a display device, wherein the display panel 10 has a display area 11 and a non-display area 12, wherein the display area 11 is provided with a plurality of data lines Ma and a plurality of first connection lines Mc, wherein the data lines Ma and the first connection lines Mc are arranged crosswise, and the non-display area 12 is provided with a plurality of signal traces Mb, wherein each of the first connection lines Mc includes a first physical portion Mc1 and a first dummy portion Mc2 arranged at intervals, wherein the first physical portion Mc1 is electrically connected to the data line Ma and the signal trace Mb, the first dummy portion Mc2 is electrically insulated from the first physical portion Mc1, and the first end Mc10 of the first physical portion Mc1 and the first dummy portion Mc2 are electrically insulated. A first gap Mc3 is provided between the first end Mc20; wherein the display panel 10 includes a substrate 20 and a first metal layer 30 and a second metal layer 40 sequentially stacked on the substrate 20; the display panel 10 also includes a plurality of thin film transistors, at least one of the source S1 and the drain D1 of the thin film transistor being located in the second metal layer 40; wherein the first solid portion Mc1 includes a first portion Mc11 located in the first metal layer 30, and the first dummy portion Mc2 includes a third portion Mc21 located in the first metal layer 30, wherein the first portion Mc11 includes the first end Mc10 of the first solid portion Mc1, and the third portion Mc21 includes the first end Mc20 of the first dummy portion Mc2. The display device includes a housing and the display panel 10, the housing having a housing space, and the display panel 10 is disposed in the housing space.

[0078] It should be noted that the structure of the display panel 10 and the display device provided in the second embodiment of the present application is similar to the structure of the display panel 10 and the display device provided in the first embodiment of the present application, and the same parts will not be repeated in the second embodiment of the present application.

[0079] In some embodiments of the present application, a line connecting three adjacent first gaps Mc3 is a curve.

[0080] In the display panel 10 provided in the present application, since the line connecting the three adjacent first gaps Mc3 is a curve, the linear mura problem caused by the linear arrangement of multiple first gaps Mc3 can be further improved, and the appearance characteristics of the display panel 10 in the off state can be further improved.

[0081] In some embodiments of the present application, a line connecting three adjacent second gaps Md3 is a curve.

[0082] In the display panel 10 provided in the present application, since the line connecting the three adjacent first gaps is a curve, it is possible to further improve the linear mura problem caused by the linear arrangement of multiple first gaps, and further improve the appearance characteristics of the display panel 10 in the off state.

[0083] Specifically, referring to FIG7 , the distance between two adjacent first connecting lines Mc among the three adjacent first connecting lines Mc can be made different from the distance between the other two adjacent first connecting lines Mc, so that the line connecting the three adjacent first gaps Mc3 and the line connecting the three adjacent second gaps Md3 can be made into a curve. Of course, in other embodiments of the present application, the distance between two adjacent second connecting lines Md among the three adjacent second connecting lines Md can be made different from the distance between the other two adjacent second connecting lines Md, so that the line connecting the three adjacent first gaps Mc3 and the line connecting the three adjacent second gaps Md3 can be made into a curve.

[0084] In summary, the present application provides a display panel and a display device, wherein the display panel has a display area and a non-display area, the display area is provided with a plurality of data lines and a plurality of first connecting lines, the data lines and the first connecting lines are arranged to cross each other, and the non-display area is provided with a plurality of signal traces; wherein each of the first connecting lines includes a first solid portion and a first dummy portion arranged at intervals, the first solid portion is electrically connected to the data line and the signal trace, the first dummy portion is electrically insulated from the first solid portion, and a first gap is provided between a first end of the first solid portion and a first end of the first dummy portion; wherein the display panel includes a substrate and a first metal layer and a second metal layer stacked in sequence on the substrate, the display panel also includes a plurality of thin film transistors, at least one of the source and the drain of the thin film transistor is in the second metal layer; wherein, the first solid part includes a first part located in the first metal layer, the first dummy part includes a third part located in the first metal layer, and the first part includes a first end of the first solid part, and the third part includes a first end of the first dummy part. In the display panel provided by the present application, due to the first connecting line located in the display area, a first gap is provided between the first end of the first solid part and the first end of the first dummy part, and the first end of the first solid part and the first end of the first dummy part are both located in the first metal layer with a lower film layer position relative to the second metal layer, so that the first gap has less influence on the film layer flatness of the pixel area in the display area, thereby improving the screen-off mura problem and improving the appearance characteristics of the display panel in the screen-off state.

[0085] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific regulations are applied herein to explain the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, wherein, the display panel has a display area and a non-display area. The display area is provided with a plurality of data lines and a plurality of first connection lines, the data lines and the first connection lines are arranged in a cross manner, and the non-display area is provided with a plurality of signal traces; wherein, each of the first connection lines includes a first solid portion and a first dummy portion arranged at intervals. The first solid portion is electrically connected to the data line and the signal trace, the first dummy portion is electrically insulated from the first solid portion, and a first gap is provided between the first end of the first solid portion and the first end of the first dummy portion; wherein, the display panel includes a substrate and a first metal layer and a second metal layer sequentially stacked on the substrate. The display panel further includes a plurality of thin film transistors, and at least one of the source and drain of the thin film transistor is located in the second metal layer; wherein, the first solid portion includes a first part located in the first metal layer, the first dummy portion includes a third part located in the first metal layer, and the first part includes the first end of the first solid portion, and the third part includes the first end of the first dummy portion.

2. The display panel according to claim 1, wherein, the first solid portion further includes a second part located in the second metal layer. The second part is electrically connected to the first part by means of via connection, and the resistivity of the first metal layer is greater than the resistivity of the second metal layer.

3. The display panel according to claim 2, wherein, one of the gates of the thin film transistors is located in the first metal layer.

4. The display panel according to claim 2, wherein, the display area is further provided with a plurality of reset signal connection lines, and the reset signal connection lines are arranged in a cross manner with the first connection lines; wherein, the reset signal connection lines are located in the second metal layer. The first part includes at least one first sub-part, the second part includes at least one second sub-part, and in the extending direction of the first solid portion, the first sub-part and the second sub-part are alternately arranged in sequence; wherein, the reset signal connection lines straddle a plurality of the first connection lines, and in the direction perpendicular to the substrate, the overlapping part of the first solid portion and the reset signal connection line is the first sub-part.

5. The display panel according to claim 4, wherein, the first dummy portion includes a fourth part located in the second metal layer. The fourth part is electrically connected to the third part by means of via connection. The third part includes at least one third sub-part, the fourth part includes at least one fourth sub-part, and in the extending direction of the first dummy portion, the third sub-part and the fourth sub-part are alternately arranged in sequence; wherein, in the direction perpendicular to the substrate, the overlapping part of the first dummy portion and the reset signal connection line is the third sub-part.

6. The display panel according to claim 5, wherein, The display area is further provided with a plurality of second connection lines, the second connection lines are arranged to cross the first connection lines, each of the second connection lines includes a second solid portion and a second dummy portion arranged at intervals, the first solid portion is electrically connected to the signal trace through the second solid portion, the second dummy portion is electrically insulated from the second solid portion, and a second gap is provided between a first end of the second solid portion and a first end of the second dummy portion; The display panel further comprises a third metal layer, the third metal layer is arranged on a side of the second metal layer away from the substrate, the second connection line and the data line are both located in the third metal layer, and in a direction perpendicular to the substrate, the second gap overlaps with the reset signal connection line.

7. The display panel according to claim 6, in, The reset signal connection line and the second connection line extend in the same direction, and in a direction perpendicular to the substrate, an overlapping area of ​​the second connection line and the reset signal connection line accounts for more than 50% of a total area of ​​the second connection line.

8. The display panel according to claim 7, in, The display area is further provided with a plurality of reset signal lines, the reset signal lines and the first connecting lines extend in the same direction and are located in the first metal layer, and in a direction perpendicular to the substrate, the reset signal lines and the first connecting lines do not overlap; The reset signal lines and the reset signal connection lines are arranged crosswise to form a grid structure arranged in an array.

9. The display panel according to claim 8, in, The multiple reset signal lines include alternately arranged gate reset signal lines and anode reset signal lines, and the multiple reset signal connection lines include alternately arranged gate reset signal connection lines and anode reset signal connection lines; wherein the gate reset signal lines are electrically connected to the gate reset signal connection lines, and the anode reset signal lines are electrically connected to the anode reset signal connection lines.

10. The display panel according to claim 6, in, The display area is further provided with a power signal line, the power signal line includes a fifth portion and a sixth portion, the extension direction of the fifth portion and the extension direction of the sixth portion are the same as the extension direction of the data line, and in a direction perpendicular to the substrate, the fifth portion does not overlap with the data line and the second connecting line, and the sixth portion does not overlap with the data line and the second connecting line; The fifth portion is located in the second metal layer, and includes a plurality of fifth sub-portions arranged at intervals, and two adjacent fifth sub-portions are spaced apart by the second sub-portion or the fourth sub-portion; Wherein, the sixth part is located in the third metal layer, the sixth part is continuously arranged, and is connected in parallel with the fifth part.

11. The display panel according to claim 1, in, A line connecting three adjacent first gaps is a curve.

12. The display panel according to claim 6, in, A line connecting three adjacent second gaps is a curve.

13. The display panel according to claim 1, in, The display panel further includes an anode layer disposed on a side of the second metal layer away from the substrate, wherein a positive projection of the anode layer on the substrate covers a positive projection of the first gap on the substrate.

14. The display panel according to claim 6, wherein, The display panel further includes an anode layer disposed on a side of the third metal layer away from the substrate, wherein a positive projection of the anode layer on the substrate covers a positive projection of the second gap on the substrate.

15. A display device, wherein, The display device includes a housing and a display panel. The housing has a receiving space, and the display panel is disposed in the receiving space. The display panel has a display area and a non-display area. The display area is provided with a plurality of data lines and a plurality of first connection lines, and the data lines and the first connection lines are arranged in a crosswise manner. The non-display area is provided with a plurality of signal traces; wherein each of the first connection lines includes a first solid portion and a first dummy portion arranged at intervals. The first solid portion is electrically connected to the data line and the signal trace, the first dummy portion is electrically insulated from the first solid portion, and a first gap is provided between a first end of the first solid portion and a first end of the first dummy portion; wherein the display panel includes a substrate and a first metal layer and a second metal layer sequentially stacked on the substrate. The display panel further includes a plurality of thin film transistors, and at least one of a source electrode and a drain electrode of the thin film transistor is located in the second metal layer; wherein the first solid portion includes a first part located in the first metal layer, the first dummy portion includes a third part located in the first metal layer, and the first part includes the first end of the first solid portion, and the third part includes the first end of the first dummy portion.

16. The display device according to claim 15, wherein, The first solid portion further includes a second part located in the second metal layer. The second part is electrically connected to the first part by means of a via connection, and a resistivity of the first metal layer is greater than a resistivity of the second metal layer.

17. The display device according to claim 16, wherein, One of the gate electrodes of the thin film transistor is located in the first metal layer.

18. The display device according to claim 16, wherein, The display area is further provided with a plurality of reset signal connection lines, and the reset signal connection lines are arranged in a crosswise manner with the first connection lines; wherein the reset signal connection lines are located in the second metal layer, the first part includes at least one first sub-part, the second part includes at least one second sub-part, and in an extending direction of the first solid portion, the first sub-part and the second sub-part are alternately arranged in sequence; wherein the reset signal connection lines straddle a plurality of the first connection lines, and in a direction perpendicular to the substrate, a portion of the first solid portion overlapping with the reset signal connection line is the first sub-part.

19. The display device according to claim 15, wherein, A connection line of three adjacent ones of the first gaps is a curve.

20. The display device according to claim 15, wherein, the display panel further includes an anode layer disposed on a side of the second metal layer away from the substrate, wherein a positive projection of the anode layer on the substrate covers a positive projection of the first gap on the substrate.

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