Chip configuration method and apparatus for chip board, server, electronic device, and medium

Abstract

The present application provides a chip configuration method and apparatus for a chip board, a server, an electronic device, and a medium. The chip board comprises N chips which are connected in series. The method comprises: on the basis of the order in which N chips of a chip board are connected in series, determining a configuration order of the N chips; and on the basis of the configuration order of the N chips, configuring the N chips of the chip board one by one, wherein the configuration process of an nth chip comprises: setting a chip identifier for the nth chip; on the basis of the chip identifier, indicating that the pulse width of a communication signal passing through the nth chip is compensated for in the nth chip; and on the basis of the chip identifier, indicating whether to invert a clock signal in the nth chip, wherein the value range of n is [1, N], and N is a positive integer that is at least 2. By configuring chips one by one, the clock signal and communication signal of each chip can be kept normal.

Description

Chip configuration method, device, server, electronic device and medium for chip board

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 1, 2023, with application number 2023116324175 and application name “Chip configuration method, device, server, electronic device and medium”. The entire contents of the application are incorporated by reference into this application. Technical Field

[0002] The present application belongs to the field of chip technology, and in particular relates to a chip configuration method, device, server, electronic device and medium for a chip board. Background Art

[0003] Blockchain technology involves a distributed infrastructure and computing approach. Specifically, it utilizes a block-chain data structure to verify and store data, a distributed node consensus algorithm to generate and update data, cryptography to ensure secure data transmission and access, and smart contracts composed of automated script code to program and manipulate data. A blockchain network is a decentralized, peer-to-peer (P2P) network. There are no centralized services or hierarchical structures in a blockchain network; each node is a peer, collectively providing network services. Nodes in a blockchain network act as both clients and servers.

[0004] The chipboard included in a blockchain server typically consists of multiple chips connected in series. The signal transmission paths within the chipboard have a corresponding series structure. In some scenarios, each time a signal (such as a clock signal or communication signal) passes through a chip, the upper pulse width ratio (i.e., the ratio of the high-level signal in a signal cycle to the total duration of that signal cycle) may change (widen or narrow). This can cause the signal quality to deteriorate with each chip it passes through. In some cases, after passing through multiple chips, subsequent chips receiving the signal may not be able to properly recognize the signal.

[0005] Summary of the Invention

[0006] The present application proposes a chip configuration method, device, server, electronic device and medium for a chip board.

[0007] The technical solution of this application is as follows:

[0008] A chip configuration method for a chip board, wherein the chip board includes N chips connected in series; the method comprises:

[0009] Determining a configuration order of the N chips based on a series connection order of the N chips in the chip board;

[0010] Based on the configuration order of the N chips, the N chips in the chip board are configured one by one, wherein the configuration process of the nth chip includes:

[0011] Setting a chip identifier for the nth chip;

[0012] Based on the chip identification, it is indicated that the nth chip has passed the nth

[0013] The chip's communication signal compensation pulse width;

[0014] Indicating, based on the chip identifier, whether to flip a clock signal in the nth chip;

[0015] The value range of n is [1, N], and N is a positive integer of at least 2.

[0016] A chip configuration device for a chip board, wherein the chip board includes N chips connected in series; the device includes:

[0017] A determination module, configured to determine a configuration order of the N chips based on a series connection order of the N chips in the chip board;

[0018] A configuration module is configured to configure the N chips in the chip board one by one based on the configuration order of the N chips, wherein the configuration process of the nth chip includes:

[0019] Setting a chip identifier for the nth chip;

[0020] Based on the chip identification, it is indicated that the nth chip has passed the nth

[0021] The chip's communication signal compensation pulse width;

[0022] Indicating, based on the chip identifier, whether to flip a clock signal in the nth chip;

[0023] The value range of n is [1, N], and N is a positive integer of at least 2.

[0024] An electronic device, comprising:

[0025] Memory;

[0026] processor;

[0027] The memory stores an application program executable by the processor, which is used to enable the processor to execute the chip configuration method of the chip board as described above.

[0028] A blockchain server, comprising:

[0029] Chipboard, containing multiple chips;

[0030] A control board comprising: a memory and a processor; wherein the memory stores an application program executable by the processor, for causing the processor to execute the chip configuration method of the chip board as described above;

[0031] The chip board has a signal connection with the control board through a signal connection interface, and the chip board has a power connection with the power supply through a power connection interface.

[0032] A computer-readable storage medium stores computer-readable instructions for executing the chip configuration method of the chip board as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] FIG1 is an exemplary structural diagram of a chip board according to an embodiment of the present application.

[0034] FIG2 is an exemplary flow chart of a chip configuration method for a chip board according to an embodiment of the present application.

[0035] FIG3 is an exemplary structural diagram of a chip configuration device of a chip board according to an embodiment of the present application.

[0036] FIG4 is a diagram showing an exemplary structure of an electronic device according to an embodiment of the present application.

[0037] FIG5 is an exemplary structural diagram of a blockchain server according to an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the objectives, technical solutions and advantages of this application clearer, this application is further described in detail below with reference to the accompanying drawings.

[0039] For the sake of brevity and intuitiveness in description, the solution of the present application is explained below by describing several representative implementation methods. A large number of details in the implementation methods are only used to help understand the solution of the present application. However, it is obvious that the technical solution of the present application may not be limited to these details when implemented. In order to avoid unnecessarily blurring the solution of the present application, some implementation methods are not described in detail, but only a framework is given. Hereinafter, "including" means "including but not limited to", and "according to..." means "at least according to..., but not limited to only according to...". Due to the language habits of Chinese, when the number of a component is not specifically specified below, it means that the component can be one or more, or can be understood as at least one.

[0040] Figure 1 is an exemplary structural diagram of a chip board. A chip board is a circuit board configured with multiple chips, such as a computing power board. In Figure 1, the chip board includes a substrate, and mounted on the substrate: (1) a positive power terminal; (2) a negative power terminal; (3) a communication interface; (4) chips 1, chip 2, chip 3, ..., chip N connected in series, where N is a positive integer of at least 2; and (5) a clock signal generator.

[0041] The positive power terminal and the negative power terminal are adapted to be connected in series with another chip board. The communication interface can receive communication signals from components outside the chip board (e.g., the control board) and can also send communication signals to components outside the chip board (e.g., the control board). The signal transmission path of chip 1, chip 2, chip 3...chip N connected in series has a chain structure (shown by the dotted line). When the communication interface receives a communication signal from the control board, the transmission path of the communication signal is: chip 1 (the signal receiving starting point in the chip board, that is, the chip where the signal transmitted by the communication interface first reaches) → chip 2 → chip 3 → chip 4 → chip 5 → chip 6 → chip 7 → chip 8 → ... chip N-5 → chip N-4 → chip N-3 → chip N-2 → chip N-1 → chip N. When a communication signal is sent to the control board through the communication interface, the transmission path of the communication signal is: chip N → chip N-1 → chip N-2 → chip N-3 → chip N-4 → chip N-5...chip 8 → chip 7 → chip 6 → chip 5 → chip 4 → chip 3 → chip 2 → chip 1 (the signal in the chip board is sent from chip 1 to the communication interface).

[0042] In addition, a clock signal generator (e.g., a crystal oscillator) generates a clock signal, which is first transmitted to chip 1. The clock signal transmission path in the chip board is: chip 1 (the signal receiving starting point in the chip board) → chip 2 → chip 3 → chip 4 → chip 5 → chip 6 → chip 7 → chip 8 → ... chip N-5 → chip N-4 → chip N-3 → chip N-2 → chip N-1 → chip N.

[0043] Every time a signal (including clock signals and communication signals) passes through a chip, the upper pulse width ratio of the signal (the ratio of the upper pulse width to the total signal duration) may change (become wider or narrower), resulting in worse signal quality the more chips it passes through. Even after passing through multiple chips, the subsequent chips that receive the signal may not be able to recognize the signal normally. Among them, the upper pulse width is the duration of the high level in a signal cycle. The lower pulse width is the duration of the low level in a signal cycle. The upper pulse width ratio is the ratio of the high-level signal in a signal cycle to the total duration of the signal cycle (that is, the proportion of the time the high-level signal lasts in the signal cycle). The lower pulse width ratio is the ratio of the low-level signal in a signal cycle to the total duration of the signal cycle (that is, the proportion of the time the low-level signal lasts in the signal cycle).

[0044] In some embodiments, with respect to the change in the upper pulse width of the clock signal, the clock signal is corrected in a manner that includes performing a flip of the clock signal every time it passes through a predetermined number (eg, 3) of chips.

[0045] Flipping a clock signal means reversing the level of the clock signal (including high and low levels). This specifically involves changing the high level of the clock signal to a low level and the low level of the clock signal to a high level. Compared to the clock signal before flipping, the upper pulse width and lower pulse width percentages of the flipped clock signal are swapped. For example, the upper pulse width percentage of the clock signal before flipping is A%, and the lower pulse width percentage is B%. After flipping, the upper pulse width percentage of the clock signal after flipping is B%, and the lower pulse width percentage is A%, where A + B = 100. Assuming that after passing through m chips, the upper pulse width percentage of the clock signal exceeds a predetermined threshold (e.g., 55%), the clock signal is flipped, and the lower pulse width becomes wider. After passing through m more chips, the clock signal flips again. For example, assuming the predetermined number is 3, the clock signal in Figure 1 passes through chip 1, chip 2, and chip 3 in sequence. The clock signal output by chip 3 to chip 4 is flipped. Then, the flipped clock signal passes through chip 4, chip 5, and chip 6 in sequence, and the clock signal output by chip 6 to chip 7 is flipped again. By analogy, the clock signal is flipped in the transmission path of the clock signal in the chip board, thereby solving the signal quality problem caused by the change of the upper pulse width of the clock signal.

[0046] The applicant discovered that it is necessary to issue a clock flip command to a specific chip in the chip board (for example, chip 3 and chip 6 in the above example) to flip the clock signal at the appropriate position. In order to distinguish a specific chip in the chip board, it is necessary to assign a unique identifier to each chip. However, every time the communication signal carrying the clock flip command or the identifier assignment command passes through a chip, the upper pulse width ratio of the communication signal may also change, resulting in the signal quality becoming worse the more chips it passes through. Even after passing through multiple chips, the subsequent chip that receives the signal cannot normally identify the communication signal, making it impossible to assign identifiers to all chips and send a clock flip command to a specific chip, resulting in the clock signal at the specific chip being unable to be flipped.

[0047] Taking Figure 1 as an example, in order to flip the clock signal for a specific chip (assuming chip 15) in the chip board to maintain the correctness of the clock signal, it is necessary to set a separate identifier for each chip. Chip 1 receives a communication signal carrying a configuration command (used to instruct each chip to turn on the chip identifier allocation function) via the communication interface and transmits the communication signal in the chip board. During the transmission process, the quality of the communication signal gradually deteriorates due to the change in the upper pulse width. Assuming that the communication signal cannot be recognized at chip 12, the subsequent chips of chip 12 cannot receive the communication signal and cannot assign an identifier, so chip 15 cannot assign an identifier and cannot flip the clock signal at chip 15.

[0048] It can be seen that the chip board can only work normally when the clock signal and communication signal in the chip board are normal at the same time.

[0049] Because communication signals carry various commands, flipping the communication signal similar to flipping a clock signal in an attempt to address the issue of upper pulse width variations can cause communication signal errors. The applicant has also discovered that a signal compensation mechanism can be implemented on the communication signal to address the issue of upper pulse width variations. For example, assuming that after passing through K chips, the upper pulse width of the communication signal will widen by a certain amount T, then this fixed amount of compensation (i.e., T / K) can be distributed to each of the K chips, thereby addressing the signal quality issues caused by the upper pulse width variations of the communication signal.

[0050] The above disclosure details the technical defects in the related art, the causes of these defects, and the analytical process for overcoming them. In reality, the understanding of these technical defects is not common knowledge in the field, but rather a novel discovery made by the applicant during their research. Furthermore, the tracing of the causes of these defects and the analytical process for overcoming them are the result of gradual analysis conducted by the applicant during their actual research and are not common knowledge in the field.

[0051] FIG2 is an exemplary flow chart of a chip configuration method for a chip board according to an embodiment of the present application. The chip configuration method shown in FIG2 can be executed, for example, in an electronic device. The electronic device is, for example, a blockchain server. Here, the blockchain server may include, for example, a chip board and a control board. The chip board includes N chips connected in series. The control board includes: a memory and a processor; wherein the memory stores an application program executable by the processor, for causing the processor to execute the chip configuration method for the chip board. The method includes:

[0052] Step 201: Determine the configuration order of the N chips based on the serial connection order of the N chips in the chip board.

[0053] For example, in the series connection sequence of N chips, the chip connected to the communication interface is ranked first, the next chip in series with the first chip is ranked second, the next chip in series with the second is ranked third, the next chip in series with the third is ranked fourth, and so on. The order of each chip is determined sequentially. Referring to Figure 1, Chip 1, Chip 2, Chip 3, ..., and Chip N are connected in series, with Chip 1 being the chip connected to the communication interface. Therefore, the order of the N chips is: Chip 1, Chip 2, Chip 3, ..., and Chip N.

[0054] Step 202: Based on the configuration order of the N chips, configure the N chips one by one, wherein the configuration process of the nth chip includes: setting a chip identifier for the nth chip; based on the chip identifier, indicating in the nth chip to compensate for the pulse width of the communication signal passing through the nth chip; based on the chip identifier, indicating whether to flip the clock signal in the nth chip; wherein the value range of n is [1, N], and N is a positive integer of at least 2. In some embodiments, for a situation where the communication signal passing through a chip changes, if the situation is that the proportion of high-level pulse width increases, thereby deteriorating the quality of the communication signal, then the pulse width compensation may be to reduce the proportion of high-level pulse width and increase the proportion of low-level pulse width. Correspondingly, if the situation is that the proportion of high-level pulse width decreases, thereby deteriorating the quality of the communication signal, then the pulse width compensation may be to increase the proportion of high-level pulse width and reduce the proportion of low-level pulse width.

[0055] It can be seen that the embodiment of the present application configures each chip one by one based on the configuration order of N chips. During the configuration process of each chip, based on the chip identifier assigned to the chip, it is indicated in the chip to compensate for the pulse width of the communication signal passing through the chip (that is, it is indicated by the chip to compensate for the pulse width (including upper pulse width and lower pulse width) of the communication signal transmitted from the chip to the next level chip), thereby providing compensation for the pulse width change of the communication signal in the chip, so that the upper pulse width ratio and the lower pulse width ratio that have changed can be corrected, thereby ensuring the correctness of the communication signal and thus improving the working stability of the chip board. Moreover, during the configuration process of each chip, it is also possible to indicate whether to flip the clock signal in the chip based on the chip identifier, thereby ensuring the correctness of the clock signal and further improving the working stability of the chip board.

[0056] Before the chip board is initialized, the N chips in the chip board have the same initial identification. In one embodiment, the configuration process of the nth chip includes:

[0057] A first configuration command is sent to the chip connected to the communication interface on the chip board. The first configuration command is used to instruct each chip to enable the chip ID assignment function. The first configuration command is transmitted on the chip board based on the serial connection order of the N chips, that is, the first configuration command is transmitted sequentially to the N chips in the series connection. Here, the chip connected to the communication interface is the first chip in the N chips in the series connection to receive the first configuration command, for example, chip 1.

[0058] A second configuration command is sent to a chip connected to the communication interface in the chip board. The second configuration command is used to instruct the nth chip with the initial identifier to be assigned a chip identifier associated with n. In other words, the second configuration command instructs the nth chip to be assigned a chip identifier associated with its configuration order. The second configuration command is transmitted in the chip board based on the serial order of the N chips until the second configuration command stops at the nth chip.

[0059] A third configuration command is sent to a chip connected to a communication interface on the chip board. The third configuration command is used to instruct the chip assigned a chip identifier associated with n to compensate for the pulse width of the communication signal, wherein the third configuration command is transmitted on the chip board based on the serial connection order of the N chips. Here, compensating for the pulse width of the communication signal refers to adjusting the pulse width of the communication signal passing through the chip with the chip identifier associated with n (i.e., the nth chip). Because the high-level pulse width of the communication signal may change (e.g., increase or decrease) during transmission, pulse width adjustment is to correct for the change in pulse width (i.e., deviation).

[0060] A fourth configuration command is sent to the chip board, where the fourth configuration command is used to instruct whether to flip the clock signal in the chip assigned with the chip identifier associated with n, wherein the fourth configuration command is transmitted in the chip board based on the serial order of the N chips.

[0061] It can be seen that through the coordinated cooperation of the first configuration command, the second configuration command, the third configuration command and the fourth configuration command, the configuration of each chip is realized, ensuring that the clock signal and communication signal at each chip are normal, thereby helping to ensure the working stability of the chip board.

[0062] In one embodiment, the chip identifier associated with n includes one of the following:

[0063] (1) Chip ID equal to n.

[0064] For example: if n is 1, the chip ID is 1; if n is 2, the chip ID is 2... and so on. The chip ID of the nth chip is n.

[0065] (2) A chip identifier equal to the sum of n and a predetermined increment value.

[0066] For example, assuming the increment is k, if n is 1, the chip ID is 1+k; if n is 2, the chip ID is 2+k, and so on. The chip ID of the nth chip is n+k, where k is a positive integer.

[0067] (3) A chip identifier equal to the product of n and a predetermined multiple.

[0068] For example, assume the multiple is P. If n is 1, the chip ID is 1*P; if n is 2, the chip ID is 2*P... and so on. The chip ID of the nth chip is n*P.

[0069] The above exemplary descriptions are typical examples of chip identifiers associated with n. Those skilled in the art will appreciate that this description process is merely exemplary and is not intended to limit the scope of protection of the embodiments of the present application.

[0070] Considering that during the configuration process of each chip, errors such as configuration command loss or unsuccessful execution may occur, by redundantly executing the configuration process multiple times (for example, configuring a chip multiple times), it can be ensured that each chip is successfully configured. In multiple redundant configurations, the chip identifier associated with n in the second configuration command of each configuration process is incremented. In one embodiment, M configuration processes are executed for the chip board to complete the configuration of N chips, where M is greater than or equal to N. For example, M can be twice N, and so on.

[0071] The configuration process of the embodiment of the present application is described in detail below with reference to FIG1 .

[0072] Assume that chips 1 to N all have the same initial identifier, for example, Kabc.

[0073] First, the configuration process of chip 1 is performed. Specifically:

[0074] (1): When n is equal to 1, the configuration process of chip 1 includes:

[0075] First, chip 1 receives a communication signal carrying a first configuration command from the control board via a communication interface. The first configuration command is used to instruct each chip to enable the chip identification allocation function. Chip 1 transmits the first configuration command along the transmission path of the communication signal. During the transmission process, the quality of the communication signal will deteriorate (for example, the proportion of high-level pulse width increases). Assuming that the pulse width is not compensated, the communication signal cannot be recognized after passing through 7 chips, that is, the communication signal cannot be recognized at chip 8, then only chips 1 to 7 actually obtain the first configuration command, and only chips 1 to 7 enable the chip identification allocation function.

[0076] Then, chip 1 receives a communication signal carrying a second configuration command from the control board via the communication interface. The second configuration command instructs the chip with the initial identifier Kabc to be assigned a chip identifier associated with n (=1), for example, chip identifier 1. After receiving the second configuration command, chip 1 determines that its initial identifier Kabc matches the second configuration command and therefore sets its chip identifier to 1. Furthermore, chip 1 does not transmit the second configuration command.

[0077] Next, chip 1 receives a communication signal carrying a third configuration command from the control board via the communication interface. The third configuration command is used to instruct the chip with chip identification 1 to compensate the pulse width of the communication signal passing through chip 1. After receiving the third configuration command, chip 1 determines that its own chip identification (1) meets the third configuration command, and therefore executes the third configuration command. Specifically, the compensation amount for compensating the pulse width can be: the total pulse width change of the communication signal of chip 1 to chip 7 is distributed to the average value of these 7 chips, that is, the average value of the pulse width change of the 7 chips. Chip 1 transmits the third configuration command. Since the subsequent chips of chip 1 do not meet the chip identification 1, they do not execute the third configuration command.

[0078] Furthermore, chip 1 receives a communication signal carrying a fourth configuration command from the control board via the communication interface. The fourth configuration command is used to instruct whether to invert the clock signal in the chip with chip ID 1. Chip 1 executes the fourth configuration command and, based on the fourth configuration command, determines whether to invert the clock signal. Chip 1 transmits the fourth configuration command. Subsequent chips of chip 1 do not satisfy the chip ID 1 and therefore do not execute the fourth configuration command.

[0079] At this point, the configuration process of chip 1 is completed. Next, the configuration process of chip 2 is performed.

[0080] (2): When n is equal to 2, the configuration process of chip 2 includes:

[0081] First, chip 1 receives a communication signal carrying a first configuration command from the control board via a communication interface. The first configuration command is used to instruct each chip to turn on the chip identification allocation function. Chip 1 transmits the first configuration command along the transmission path of the communication signal. During the transmission process, the quality of the communication signal will deteriorate. Since the communication signal has been pulse-width compensated during the configuration process of chip 1 (equivalent to no pulse-width change for the communication signal in chip 1), the communication signal has deteriorated in quality in chips 2-8 and has not been pulse-width compensated. Therefore, the first configuration command cannot be identified from the received communication signal at chip 9. Only chips 1 to 8 actually obtain the first configuration command carried in the communication signal and turn on the chip identification allocation function of chips 1 to 8.

[0082] Then, chip 1 receives a communication signal carrying a second configuration command from the control board via the communication interface. The second configuration command is used to instruct the chip with the initial identifier Kabc to be assigned a chip identifier associated with n (=2), for example, the chip identifier is 2. After receiving the second configuration command, chip 1 determines that its own identifier (1) does not conform to the second configuration command, and therefore does not execute the second configuration command, and passes the second configuration command to chip 2. After receiving the second configuration command, chip 2 determines that its own initial identifier Kabc conforms to the second configuration command, and therefore sets the chip identifier of chip 2 to 2. Moreover, chip 2 does not pass the second configuration command.

[0083] Next, chip 1 receives a communication signal carrying a third configuration command from the control board via the communication interface. The third configuration command is used to instruct the chip with the chip identifier 2 to compensate for the pulse width of the communication signal. After receiving the third configuration command, chip 1 determines that its own identifier (1) does not meet the third configuration command, and therefore does not execute the third configuration command, and passes the third configuration command to chip 2. After receiving the third configuration command, chip 2 determines that its own chip identifier (2) meets the third configuration command, and therefore executes the third configuration command. Similarly, the compensation amount for the communication signal in the chip with the chip identifier 2 is equal to the compensation amount in the configuration process of chip 1. Chip 2 passes the third configuration command. Since the subsequent chips of chip 2 do not meet the chip identifier 2, they will not execute the third configuration command.

[0084] Moreover, chip 1 receives a communication signal carrying a fourth configuration command from the control board via a communication interface. The fourth configuration command is used to indicate whether to flip the clock signal in the chip with a chip identifier of 2. After receiving the fourth configuration command, chip 1 determines that its own identifier (1) does not meet the fourth configuration command, and therefore does not execute the fourth configuration command, and passes the fourth configuration command to chip 2. After receiving the fourth configuration command, chip 2 determines that its own chip identifier (2) meets the fourth configuration command, and therefore executes the fourth configuration command and determines whether to flip the clock signal based on the fourth configuration command. Chip 2 passes the fourth configuration command. Since the subsequent chips of chip 2 do not meet the chip identifier of 2, they will not execute the fourth configuration command.

[0085] At this point, the configuration process of chip 2 is completed. Next, the configuration process of chip 3 is executed.

[0086] (3): When n is equal to 3, the configuration process of chip 3 includes:

[0087] First, chip 1 receives a communication signal carrying a first configuration command from the control board via a communication interface. The first configuration command is used to instruct each chip to enable the chip identification allocation function. Chip 1 transmits the first configuration command along the transmission path of the communication signal. During the transmission process, the quality of the communication signal will deteriorate. Since the communication signal has been pulse-width compensated during the configuration process of chip 1 and chip 2 (equivalent to no pulse width change for the communication signal in chip 1 and chip 2), the quality of the communication signal deteriorates in chips 3-9 and is not pulse-width compensated. Therefore, the communication signal cannot be identified at chip 10 at this time. Only chips 1 to 9 actually receive the communication signal and enable the chip identification allocation function of chips 1 to 9.

[0088] Then, chip 1 receives a communication signal carrying a second configuration command from the control board via the communication interface. The second configuration command is used to instruct the chip with the initial identifier Kabc to be assigned a chip identifier associated with n (=3), for example, the chip identifier is 3. After receiving the second configuration command, chip 1 determines that its own identifier (1) does not conform to the second configuration command, so it does not execute the second configuration command and passes the second configuration command to chip 2. After receiving the second configuration command, chip 2 determines that its own identifier (2) does not conform to the second configuration command, so it does not execute the second configuration command and passes the second configuration command to chip 3. After receiving the second configuration command, chip 3 determines that its own initial identifier Kabc conforms to the second configuration command, so it sets the chip identifier of chip 3 to 3. Moreover, chip 3 does not pass the second configuration command.

[0089] Next, chip 1 receives a communication signal carrying a third configuration command from the control board via the communication interface. The third configuration command is used to instruct the chip with the chip identifier 3 to compensate for the pulse width of the communication signal. After receiving the third configuration command, chip 1 determines that its own identifier (1) does not conform to the third configuration command, and therefore does not execute the third configuration command, and passes the third configuration command to chip 2. After receiving the third configuration command, chip 2 determines that its own identifier (2) does not conform to the third configuration command, and therefore does not execute the third configuration command, and passes the third configuration command to chip 3. After receiving the third configuration command, chip 3 determines that its own chip identifier (3) conforms to the third configuration command, and therefore executes the third configuration command. Similarly, the compensation amount for the communication signal in the chip with the chip identifier 3 is equal to the compensation amount in the configuration process of chip 1. Chip 3 passes the third configuration command. Since the subsequent chips of chip 3 do not meet the chip identifier 3, they will not execute the third configuration command.

[0090] Moreover, chip 1 receives a communication signal carrying a fourth configuration command from the control board via a communication interface. The fourth configuration command is used to indicate whether to flip the clock signal in the chip with a chip identifier of 3. After receiving the fourth configuration command, chip 1 determines that its own identifier (1) does not conform to the fourth configuration command, and therefore does not execute the fourth configuration command, and passes the fourth configuration command to chip 2. After receiving the fourth configuration command, chip 2 determines that its own identifier (2) does not conform to the fourth configuration command, and therefore does not execute the fourth configuration command, and passes the fourth configuration command to chip 3. After receiving the fourth configuration command, chip 3 determines that its own chip identifier (3) conforms to the fourth configuration command, and therefore executes the fourth configuration command and determines whether to flip the clock signal based on the fourth configuration command. Chip 3 passes the fourth configuration command. Since the subsequent chips of chip 3 do not meet the chip identifier of 3, they will not execute the fourth configuration command.

[0091] At this point, the configuration process of chip 3 is completed.

[0092] The same process continues, completing the configuration process for all N chips on the chip board. As can be seen, during the configuration process for each chip, instructions are given to compensate for the pulse width of the communication signal passing through that chip, thereby compensating for variations in the pulse width of the communication signal within that chip. Furthermore, during the configuration process, each chip is assigned a chip ID, which can be used to indicate whether to flip the clock signal within that chip based on the chip ID, thereby ensuring the correctness of the clock signal. As a result, the clock signal and communication signal for each chip on the chip board can be maintained in a normal state simultaneously.

[0093] During the configuration process of all N chips in the chip board, errors such as configuration command loss or unsuccessful execution of configuration command may occur. The configuration process can be executed redundantly (for example, one chip is configured multiple times) to ensure that each chip is successfully configured. For example, assume that during the configuration process of chip 6, the second configuration command (for example, specifying to set the chip identifier to 6) cannot be executed correctly, resulting in the chip identifier of chip 6 not being successfully set, that is, the configuration process of setting the chip identifier to 6 fails. At this time, continue to execute the configuration process of setting the chip identifier to 7. During the configuration process of setting the chip identifier to 7, chip 6 continues to try to set the chip identifier of chip 6 to 7. When the chip identifier of chip 6 is successfully set to 7, the configuration process of chip 6 can be completed. In other words, when the configuration process of setting the chip identifier to 6 fails to successfully configure chip 6, the identifier of chip 6 still remains the initial identifier. Therefore, in the next configuration process of setting the chip identifier to 7, chip 6 can continue to be attempted to be configured until chip 6 is successfully configured.

[0094] When there are no errors in the configuration process of N chips, executing the above N configuration processes can successfully complete the configuration of N chips. To address possible configuration errors, the configuration process can be redundantly executed M times for N chips (M is greater than N) to provide fault tolerance for errors, where the larger M is, the greater the fault tolerance. For example, assuming that the chip board has 100 chips, the above configuration process can be executed 200 times for the chip board in sequence, where the chip identifier associated with n in the second configuration command of each configuration process is incremented, so that 100 configuration errors can be accommodated.

[0095] Based on the above description, the embodiment of the present application also proposes a chip configuration device. Figure 3 is an exemplary structural diagram of the chip configuration device of the chip board of the embodiment of the present application. The chip board includes N chips connected in series; the chip configuration device 300 of the chip board includes: a determination module 301, which is used to determine the configuration order of the N chips based on the series order of the N chips in the chip board; a configuration module 302, which is used to configure the N chips in the chip board one by one based on the configuration order of the N chips, wherein the configuration process of the nth chip includes: setting a chip identifier for the nth chip; based on the chip identifier, indicating that the pulse width of the communication signal passing through the nth chip is compensated in the nth chip; based on the chip identifier, indicating whether to flip the clock signal in the nth chip; wherein the value range of n is [1, N], and N is a positive integer of at least 2.

[0096] In one embodiment, N chips have the same initial identifier; a configuration module is used to execute a configuration process for the nth chip, wherein the configuration process for the nth chip includes: sending a first configuration command to a chip connected to a communication interface in a chip board, the first configuration command being used to instruct each chip to enable a chip identifier allocation function, wherein the first configuration command is transmitted in the chip board based on the serial order of the N chips; sending a second configuration command to a chip connected to the communication interface in the chip board, the second configuration command being used to assign a chip identifier associated with n to the chip having the initial identifier, wherein the second configuration command is transmitted in the chip board based on the serial order of the N chips until the transmission stops at the nth chip; sending a third configuration command to a chip connected to the communication interface in the chip board, the third configuration command being used to instruct the chip assigned the chip identifier associated with n to compensate for the pulse width of the communication signal, wherein the third configuration command is transmitted in the chip board based on the serial order of the N chips; and sending a fourth configuration command to the chip board, the fourth configuration command being used to instruct the chip assigned the chip identifier associated with n whether to flip the clock signal, wherein the fourth configuration command is transmitted in the chip board based on the serial order of the N chips.

[0097] In one embodiment, the chip identification associated with n includes one of the following: a chip identification equal to n; a chip identification equal to the sum of n and a predetermined increase value; a chip identification equal to the product of n and a predetermined multiple, and so on.

[0098] The present application also provides an electronic device. Figure 4 is an exemplary structural diagram of an electronic device according to an embodiment of the present application. Electronic device 400 includes a processor 401 and a memory 402. Memory 402 stores an application program executable by processor 401, which is configured to cause processor 401 to execute the chip configuration method for a chip board according to the above embodiment.

[0099] Specifically, the memory 402 may be implemented as various storage media such as an electrically erasable programmable read-only memory (EEPROM), flash memory, or programmable read-only memory (PROM). The processor 401 may be implemented as including one or more central processing units (CPUs) or one or more field programmable gate arrays (FPGAs), wherein the FPGAs integrate one or more CPU cores. Specifically, the CPU or CPU core may be implemented as a CPU, an MCU, or a digital signal processor (DSP).

[0100] The present application also proposes a blockchain server. Figure 5 is an exemplary structural diagram of a blockchain server according to the present application. As shown in Figure 5, the blockchain server 500 includes: a chip board 501, wherein the chip board 501 includes multiple chips; a control board 502, which includes: a memory and a processor; wherein the memory stores an application program executable by the processor, which is used to enable the processor to execute the chip configuration method of the chip board as described in any of the above items; wherein the chip board 501 forms a signal connection with the control board 502 via a signal connection interface, and the chip board 501 forms an electrical connection with the power supply 503 via a power connection interface.

[0101] It should be noted that not all steps and modules in the above processes and structure diagrams are required, and certain steps or modules can be omitted based on actual needs. The execution order of the steps is not fixed and can be adjusted as needed. The division of the modules is merely for the convenience of describing the functional division adopted. In actual implementation, a module can be implemented by multiple modules, and the functions of multiple modules can be implemented by the same module. These modules can be located in the same device or in different devices.

[0102] The hardware modules in each embodiment can be implemented mechanically or electronically. For example, a hardware module may include a specially designed permanent circuit or logic device (such as a dedicated processor, such as an FPGA or ASIC) for performing a specific operation. The hardware module may also include a programmable logic device or circuit (such as a general-purpose processor or other programmable processor) temporarily configured by software to perform a specific operation. As for whether to implement the hardware module mechanically, or using a dedicated permanent circuit, or using a temporarily configured circuit (such as configured by software), it can be decided based on cost and time considerations.

[0103] The present application also provides a machine-readable storage medium, which stores instructions for causing a machine to execute the chip configuration method of the chip board as above. Specifically, a system or device equipped with a storage medium can be provided, on which a software program code for realizing the function of any one of the above-mentioned embodiments is stored, and the computer (or CPU or MPU) of the system or device is made to read out and execute the program code stored in the storage medium. In addition, the operating system etc. operated on the computer can also be made to complete part or all of the actual operations by instructions based on the program code. The program code read out from the storage medium can also be written to a memory provided in an expansion board inserted into the computer or to a memory provided in an expansion unit connected to the computer, and then the CPU etc. installed on the expansion board or expansion unit are made to perform part and all of the actual operations based on the instructions of the program code, thereby realizing the function of any one of the above-mentioned embodiments.

[0104] Examples of storage media for providing program code include floppy disks, hard disks, magneto-optical disks, optical disks (e.g., CD-ROMs, CD-Rs, CD-RWs, DVD-ROMs, DVD-RAMs, DVD-RWs, DVD+RWs), magnetic tapes, non-volatile memory cards, and ROMs. Alternatively, the program code may be downloaded from a server computer or a cloud via a communication network.

[0105] In this document, "schematic" means "serving as an example, instance or illustration", and any diagram or embodiment described as "schematic" in this document should not be interpreted as a more preferred or more advantageous technical solution. In order to keep the drawings concise, each figure only schematically shows the parts related to the present application, and does not represent its actual structure as a product. In addition, in order to keep the drawings concise and easy to understand, in some figures, only one of the components with the same structure or function is schematically drawn, or only one of them is marked. In this document, "one" does not mean that the number of relevant parts of the present application is limited to "only one", and "one" does not mean excluding the situation where the number of relevant parts of the present application is "more than one". In this document, "upper", "lower", "front", "back", "left", "right", "inside", "outside" and the like are only used to indicate the relative positional relationship between the relevant parts, rather than to limit the absolute positions of these relevant parts.

[0106] The above description is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A chip configuration method for a chip board, wherein the chip board comprises N chips connected in series; the method comprising: Determining a configuration order of the N chips based on a series connection order of the N chips in the chip board; Based on the configuration order of the N chips, the N chips are configured one by one, wherein the configuration process of the nth chip includes: Setting a chip identifier for the nth chip; Based on the chip identifier, indicating in the nth chip to compensate for a pulse width of a communication signal passing through the nth chip; Based on the chip identifier, it is indicated whether to flip the clock signal in the nth chip; wherein the value range of n is [1, N], and N is a positive integer of at least 2.

2. According to the method of claim 1, the N chips have the same initial identification; the configuration process of the nth chip further comprises: Sending a first configuration command to a chip connected to the communication interface in the chip board, wherein the first configuration command is used to instruct each chip to enable a chip identification allocation function, wherein the first configuration command is transmitted in the chip board based on the serial connection order of the N chips; Sending a second configuration command to a chip connected to the communication interface in the chip board, the second configuration command being used to instruct the chip with the initial identifier to be assigned a chip identifier associated with n, wherein the second configuration command is transmitted in the chip board based on the serial sequence of the N chips until the transmission stops at the nth chip; Sending a third configuration command to a chip connected to the communication interface in the chip board, the third configuration command being used to instruct to compensate the pulse width for the communication signal in a chip assigned with a chip identifier associated with the n, wherein the third configuration command is transmitted in the chip board based on the serial connection order of the N chips; A fourth configuration command is sent to the chip board, the fourth configuration command being used to indicate whether to flip a clock signal in a chip assigned with a chip identifier associated with the n chips, wherein the fourth configuration command is transmitted in the chip board based on the serial order of the N chips.

3. The method according to claim 2, wherein the chip identifier associated with the n comprises one of the following: A chip identifier equal to said n; a chip identifier that is equal to the sum of the n and a predetermined increase value; A chip identifier that is equal to the product of n and a predetermined multiple.

4. The method according to claim 2, characterized in that: M of the configuration processes are performed on the chip board to complete the configuration of the N chips, where M is greater than or equal to N.

5. A chip configuration device for a chip board, the chip board comprising N chips connected in series; the device comprising: A determination module, configured to determine a configuration order of the N chips based on a series connection order of the N chips in the chip board; A configuration module is used to configure the N chips in the chip board one by one based on the configuration order of the N chips, wherein the configuration process of the nth chip includes: Setting a chip identifier for the nth chip; Based on the chip identifier, indicating in the nth chip to compensate for a pulse width of a communication signal passing through the nth chip; Based on the chip identifier, indicating whether to flip a clock signal in the nth chip; The value range of n is [1, N], and N is a positive integer that is at least 2.

6. The device according to claim 5, wherein the N chips have the same initial identification; The configuration module is used to execute the configuration process of the nth chip, wherein the configuration process of the nth chip includes: A first configuration command is sent to a chip connected to the communication interface in the chip board, the first configuration command is used to instruct each chip to enable a chip identification allocation function, wherein the first configuration command is transmitted in the chip board based on the serial order of the N chips; a second configuration command is sent to a chip connected to the communication interface in the chip board, the second configuration command is used to allocate a chip identification associated with n to the chip having the initial identification, wherein the second configuration command is transmitted in the chip board based on the serial order of the N chips until the transmission stops at the nth chip; a third configuration command is sent to a chip connected to the communication interface in the chip board, the third configuration command is used to instruct to compensate for the pulse width of the communication signal in the chip allocated with the chip identification associated with n, wherein the third configuration command is transmitted in the chip board based on the serial order of the N chips; a fourth configuration command is sent to the chip board, the fourth configuration command is used to instruct that in the chip allocated with the chip identification associated with n, it is No inverts the clock signal, wherein the fourth configuration command is transmitted in the chip board based on the serial sequence of the N chips.

7. The device according to claim 6, wherein the chip identifier associated with n comprises one of the following: A chip identifier equal to said n; a chip identifier that is equal to the sum of the n and a predetermined increase value; A chip identifier that is equal to the product of n and a predetermined multiple.

8. An electronic device comprising: Memory; processor; The memory stores an application program executable by the processor, which is used to enable the processor to execute the chip configuration method of the chip board as described in any one of claims 1 to 4.

9. A blockchain server, comprising: Chipboard, containing multiple chips; A control board, comprising: a memory and a processor; wherein the memory stores an application program executable by the processor, for causing the processor to execute the chip configuration method of the chip board according to any one of claims 1 to 4; The chip board has a signal connection with the control board through a signal connection interface, and the chip board has a power connection with the power supply through a power connection interface. 10 . A computer-readable storage medium storing computer-readable instructions for executing the chip configuration method of a chip board according to claim 1 .

Images