MEMS sensor and preparation method therefor

Abstract

A MEMS sensor and a preparation method therefor. The method comprises: forming a first oxide layer on a substrate wafer, performing patterned etching on the first oxide layer, and performing deposition and doping on the first oxide layer that has undergone the patterned etching, so as to form a first polycrystalline silicon layer; performing patterned etching on the first polycrystalline silicon layer to form a wiring, and depositing a second oxide layer on the first polycrystalline silicon layer; upon performing patterned etching on the second oxide layer, performing deposition and doping to form a second polycrystalline silicon layer; performing patterned etching on the second polycrystalline silicon layer to form bonding anchor points and a capacitive plate having a lower height than the bonding anchor points; bonding a device wafer with the bonding anchor points, and performing patterned etching on the device wafer to generate a movable structure, so as to obtain a device layer; and bonding the side of the device wafer distant from the substrate wafer with a cover layer.

Description

MEMS sensor and preparation method thereof

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on November 28, 2023, with application number 202311605668.4, and invention name “MEMS sensor and its preparation method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the technical field of MEMS devices, and in particular to a MEMS sensor and a preparation method thereof. Background Art

[0003] MEMS (Micro-Electro Mechanical System) technology integrates sensor structures and corresponding electronic circuits within a small housing. Compared to sensors manufactured using traditional processing methods, MEMS sensors, based on integrated circuit and micromachining processes, offer advantages such as small size, light weight, and low power consumption, and have broad potential for dual-use applications in both military and civilian applications.

[0004] MEMS sensors, such as IMU (inertial measurement unit), MEMS gyroscope, MEMS accelerometer, etc., include a cover layer, a device layer and a substrate layer, wherein the device layer includes a device wafer, a movable structure is formed on the device wafer, and the substrate layer includes a capacitor plate, and the movable structure and the capacitor plate cooperate to form a sensing capacitor for sensing the corresponding physical quantity. In the traditional manufacturing method, an oxide layer is set between the capacitor plate and the device wafer. After the device wafer is patterned and etched to form a movable structure, it is necessary to punch a hole in the device wafer to allow the etching gas to pass through, and the etching gas is used to etch and remove at least part of the oxide layer to release the movable structure. This manufacturing method will affect the sensing capacitor used for out-of-plane sensing, and the manufactured MEMS sensor has the disadvantage of low reliability.

[0005] Summary of the Invention

[0006] According to various embodiments of the present application, a MEMS sensor and a method for manufacturing the same are provided.

[0007] A method for preparing a MEMS sensor, comprising:

[0008] Generating a first oxide layer on a substrate wafer, pattern-etching the first oxide layer, and depositing and doping the pattern-etched first oxide layer to form a first polysilicon layer;

[0009] Performing patterned etching on the first polysilicon layer to form wiring, and depositing a second oxide layer on the first polysilicon layer;

[0010] After patterning and etching the second oxide layer, depositing and doping to form a second polysilicon layer;

[0011] performing pattern etching on the second polysilicon layer to form a bonding anchor point and a capacitor plate with a lower height than the bonding anchor point;

[0012] Bonding a device wafer to the bonding anchor point, and pattern-etching the device wafer to generate a movable structure to obtain a device layer;

[0013] The side of the device wafer facing away from the substrate wafer is bonded to the capping layer.

[0014] In one embodiment, patterning and etching the second polysilicon layer to form a bonding anchor point and a capacitor plate with a lower height relative to the bonding anchor point includes:

[0015] performing a planarization process on the second polysilicon layer, and forming a third oxide layer on the planarized second polysilicon layer;

[0016] The third oxide layer and the second polysilicon layer are patterned and etched to form a bonding anchor point and a capacitor plate with a first protrusion, and a portion of the third oxide layer covering the bonding anchor point is retained.

[0017] A MEMS sensor comprises a substrate wafer, a first oxide layer, a first polysilicon layer, a second oxide layer, a second polysilicon layer, a device layer and a cover layer. The MEMS sensor is prepared by the above method.

[0018] The details of one or more embodiments of the present application are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0020] FIG1 is a flow chart of a method for preparing a MEMS sensor according to one embodiment;

[0021] 2 to 31 are schematic structural diagrams of a partial fabrication process of a MEMS sensor according to one embodiment;

[0022] FIG32 is a flow chart of a method for preparing a MEMS sensor according to another embodiment;

[0023] 33 to 35 are schematic structural diagrams of a partial preparation process of a MEMS sensor in one embodiment. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0025] In one embodiment, as shown in FIG1 , a method for preparing a MEMS sensor is provided, comprising:

[0026] Step S101: generating a first oxide layer on a substrate wafer, and pattern-etching the first oxide layer; depositing and doping the pattern-etched first oxide layer to form a first polysilicon layer.

[0027] As shown in Figure 2, a substrate wafer 110 is first provided, which may be a silicon wafer. Global alignment marks (not shown) may also be set on the substrate wafer 110 to facilitate subsequent alignment.

[0028] As shown in Figures 3 and 4, a first oxide layer 120 is generated by performing oxide deposition (for example, thermal oxide deposition) on one side or both sides of the substrate wafer 110, and the first oxide layer 120 on one side is patterned and etched to form an etching groove, exposing a portion of the substrate wafer 110. The first oxide layer 120 can be any dielectric film. In this embodiment, the first oxide layer 120 is a silicon oxide layer. The first oxide layer 120 is used to shield the substrate wafer 110 during subsequent deposition and doping to avoid deposition and doping in undesirable places. As shown in Figure 5, after the patterned etching of the first oxide layer 120 is completed, silicon deposition and doping are performed to form a first polysilicon layer 130. The first polysilicon layer 130 covers the first oxide layer 120 after patterned etching, and fills the etching groove of the first oxide layer 120 to contact the substrate wafer 110.

[0029] Step S102: performing pattern etching on the first polysilicon layer to form wiring, and depositing a second oxide layer on the first polysilicon layer.

[0030] As shown in Figures 6 and 7, after patterning and etching the first polysilicon layer 130 to form wiring, oxide can be deposited using a plasma-enhanced chemical vapor deposition process to form a second oxide layer 140. The second oxide layer 140 can also be formed by vapor deposition using any dielectric material. For example, the second oxide layer 140 can also be a silicon oxide layer.

[0031] Step S103: After patterning and etching the second oxide layer, a second polysilicon layer is formed by deposition and doping.

[0032] Specifically, as shown in Figures 8 and 9, the second oxide layer 140 can be first subjected to chemical mechanical polishing. After the planarization process is completed, the second oxide layer 140 is patterned and etched to remove a portion of the oxide to form an etched groove, thereby exposing a portion of the first polysilicon layer 130. As shown in Figure 10, after the patterned etching of the second oxide layer 140 is completed, silicon deposition and doping are performed to form a second polysilicon layer 150. The second polysilicon layer 150 covers the second oxide layer 140 after the patterned etching, fills the etched groove of the second oxide layer 140, and contacts the first polysilicon layer 130.

[0033] Step S104: performing pattern etching on the second polysilicon layer to form a bonding anchor point and a capacitor plate with a lower height than the bonding anchor point.

[0034] Specifically, in one embodiment, step S104 includes steps 41 and 42 .

[0035] Step 41: Planarize the second polysilicon layer and form a third oxide layer on the planarized second polysilicon layer. As shown in Figures 11 and 12 , the planarization process can be completed by chemical mechanical polishing the second polysilicon layer 150. Then, a plasma-enhanced chemical vapor deposition process is performed on the second polysilicon layer 150 to deposit oxide, forming the third oxide layer 160.

[0036] Step 42: The third oxide layer and the second polysilicon layer are patterned and etched to form bonding anchors and capacitor plates with first protrusions, and the portion of the third oxide layer covering the bonding anchors is retained. Specifically, the patterned etching of the third oxide layer and the second polysilicon layer can be completed in multiple steps. As shown in FIG13 , in the first etching step, the third oxide layer 160 and the second polysilicon layer 150 are patterned and etched at the same time, so that multiple bonding anchors are formed on the second polysilicon layer 150. For the third oxide layer 160, only the portion of the third oxide layer 160 covering the bonding anchors is retained, so that in subsequent steps, the bonding anchors are used to protect the surface of the bonding anchors before bonding. The etching depth of the second polysilicon layer 150 in the first etching step determines the gap between the first protrusion generated subsequently and the device layer. As shown in Figure 14 , the second etching step involves masking off portions of the area etched in the first step and continuing to etch the second polysilicon layer 150. This creates a first protrusion 152 on the second polysilicon layer 150. This first protrusion 152 serves to limit the downward movement of the movable structure in the subsequently formed device layer and provides a restoring force to prevent sticking. As shown in Figure 15 , the third etching step continues to etch the second polysilicon layer 150, forming a capacitor plate 154 with the first protrusion 152.

[0037] In this embodiment, the bonding anchor point, the first protrusion 152 and the capacitor plate 154 are obtained by patterning the etching on the same polysilicon layer (the second polysilicon layer 150), which helps to reduce the process steps and simplify the preparation process. In addition, the capacitor plate 154 and the wiring are arranged in different polysilicon layers. Specifically, the capacitor plate 154 is arranged in the second polysilicon layer 150 and the wiring is arranged in the first polysilicon layer 130. This can make the design of the inductive capacitor and the wiring more flexible. In addition, the first polysilicon layer 130 and the second polysilicon layer 150 are in contact with each other through step S103 to form an electrical connection. This electrical connection method makes the design more compact. The first polysilicon layer 130 and the second polysilicon layer 150 are low-resistance polysilicon. It can be understood that in other embodiments, refractory metals or alloys can also be used.

[0038] At this point, the electrode layer is formed through steps S101 to S104.

[0039] Step S105: bonding the device wafer to the bonding anchor points, and pattern-etching the device wafer to generate a movable structure to obtain a device layer.

[0040] The device wafer can be a silicon wafer. Because a complete wafer, not yet etched with a specific structure and / or pattern, is bonded to the second polysilicon layer 150, there is no need to consider bonding tolerances during bonding, and no specific point-to-point alignment bonding is required. Precise alignment can be performed based on image tolerances rather than bonding tolerances. Furthermore, the bonding anchor points on the second polysilicon layer 150 do not need to be increased in size to account for bonding tolerances; instead, the anchor point size can be reduced, thereby achieving a more compact device structure.

[0041] The device layer manufacturing method of traditional MEMS sensors includes a sacrificial release process. Specifically, an oxide layer is provided between the capacitor plate and the device wafer. After the device wafer is patterned and etched to form a movable structure, the movable structure is locked by the oxide layer. The device wafer needs to be perforated to allow the etching gas to pass through, and the etching gas is used to etch away at least part of the oxide layer to release the movable structure. The sensing capacitor formed by the movable structure and the capacitor plate is used to sense changes in external physical quantities, such as acceleration or angular velocity. Drilling holes in the device wafer will affect the sensing capacitance of the sensor. However, the present application adopts a non-sacrificial release process. The bonding anchor point and the capacitor plate 154 are both formed in the second polysilicon layer 150. After the device wafer is bonded to the bonding anchor point, since the height of the capacitor plate 154 is lower than the bonding anchor point, a cavity is formed between the device wafer and the capacitor plate 154. Therefore, after the device wafer is patterned and etched to generate the movable structure, there is no need to etch holes to release the movable structure. The cavity provides space for the movable structure to move. Compared to the sacrificial release process, since no holes are required to release the movable structure, the sensing capacitance for out-of-plane sensing is higher. In addition, since no holes are required, the Q value of out-of-plane sensing is lower than that of the sacrificial release process - reducing ringing and reducing the impact during shock or drop events. The drift and stability changes caused by shock or drop are lower, and the reliability is higher.

[0042] In one embodiment, as shown in FIG. 16 to FIG. 18 , in order to avoid adverse effects on the capacitor plate 154 during the patterned etching of the device wafer during step S105, and to stop the etching in time after the movable structure is formed to avoid over-etching, an oxide patch protection process is performed after step 42 and before step S105, specifically including:

[0043] Step 43: Generate a fourth oxide layer covering the third oxide layer and the capacitor plate. As shown in FIG16 , after etching to obtain the capacitor plate 154, a plasma-enhanced chemical vapor deposition process is performed to deposit oxide to form a fourth oxide layer 170. The fourth oxide layer 170 covers the capacitor plate 154 and the remaining third oxide layer 160. The material of the fourth oxide layer 170 is not limited. Specifically, the fourth oxide layer 170 can be any dielectric film that can be removed by gaseous hydrogen fluoride, so that the fourth oxide layer 170 can be removed later after the movable structure is generated. In this embodiment, the fourth oxide layer 170 is a silicon oxide layer.

[0044] Step 44: Patterned etching of the third oxide layer and the fourth oxide layer to expose the bonding anchor point. As shown in FIG17 , the fourth oxide layer 170 is first patterned etched to expose the third oxide layer 160 covering the bonding anchor point, and the fourth oxide layer 170 covering the capacitor plate 154 is retained. As shown in FIG18 , the third oxide layer 160 is then patterned etched to remove the third oxide layer 160 covering the bonding anchor point, exposing the bonding anchor point to facilitate subsequent melt bonding. The retained fourth oxide layer 170 is used to protect the capacitor plate 154 from unwanted etching when the movable structure is subsequently manufactured, and to provide endpoint detection for device wafer etching, that is, etching stops when the fourth oxide layer 170 is encountered.

[0045] Specifically, in one embodiment, step S105 includes steps 51 to 55 .

[0046] Step 51: Bonding the device wafer to the bonding anchors. As shown in Figure 19, the device wafer 210 is melt-bonded to the exposed bonding anchors. In steps 41 and 42, the second polysilicon layer is first planarized before forming the bonding anchors. This means that the bonding anchors have a flat surface, which is conducive to melt bonding. Furthermore, melt bonding has no temperature restrictions and can be performed at higher temperatures, resulting in higher bond strength and a secure connection between the electrode layer and the device layer.

[0047] Step 52: Planarizing the device wafer As shown in FIG20 , the device wafer 210 is ground and polished to complete the planarization process.

[0048] Step 54: The device wafer is patterned and etched to generate a movable structure, and the device layer is obtained after the etching is completed. As shown in Figure 23, the device wafer 210 is patterned and etched through the device wafer 210 to generate a movable structure. Specifically, after etching through the device wafer 210, the etching is terminated until the fourth oxide layer 170 is reached. The fourth oxide layer 170 provides endpoint detection for etching to prevent over-etching. The fourth oxide layer 170 covering the capacitor plate 154 provides protection for the capacitor plate 154 to avoid unwanted etching of the capacitor plate 170. The multiple movable structures 212 formed by etching are used to cooperate with the capacitor plate 154 for detection. The first protrusion 152 can limit the maximum downward movement of the movable structure 212 and provide a restoring force for the movable structure 212 to avoid adhesion.

[0049] In addition, the thickness of the movable structure 212 produced in this embodiment is determined by the initial thickness of the device wafer 210 and the thickness of the grinding and polishing. The thickness of the grinding and polishing can be selected according to actual needs. It can be understood that the maximum thickness of the movable structure 212 can be the initial thickness of the device wafer 210. Thus, a thicker movable structure 212 can be produced to achieve higher planar capacitance. Compared to the device layer generated by the traditional thin film deposition process, the present application determines the thickness of the movable structure 212 by grinding and polishing on the basis of the initial device wafer 210, which is more convenient to produce and has higher accuracy.

[0050] Step 55: Removing the fourth oxide layer covering the capacitor plate. As shown in FIG24 , after patterning and etching the device wafer 210 to form the movable structure 212 , the remaining fourth oxide layer 170 can be etched away using gaseous hydrogen fluoride to expose the capacitor plate 154 .

[0051] Step S106: bonding the side of the device wafer facing away from the substrate wafer to the cover layer.

[0052] In one embodiment, the side of the device wafer facing away from the substrate wafer is eutectic bonded to the capping layer.

[0053] Specifically, after executing step 52 and before executing step 54, the method further includes:

[0054] Step 53: Depositing metal on the device wafer to obtain solder joints and a first bonding portion includes: depositing a first bonding metal layer on the device wafer; and patterning and etching the first bonding metal layer to obtain solder joints and a first bonding portion. Specifically, as shown in FIG21 , metal deposition is performed on the device wafer 210 to obtain a first bonding metal layer 220. The material of the first bonding metal layer 220 can be any eutectic metal capable of wire bonding, such as aluminum. As shown in FIG22 , the first bonding metal layer 220 is patterned and etched to form solder joints 222 and a first bonding portion 224. The solder joints 222 are used for electrical connection via wires, and the first bonding portion 224 is used for bonding to the cap layer. In this way, by depositing and etching the first bonding metal layer 220, solder joints 222 for wire bonding and first bonding portions 224 for eutectic bonding can be formed, which helps to reduce process steps and simplify the preparation process.

[0055] The steps for preparing the cover layer include:

[0056] Step 61: Provide a capping wafer. As shown in FIG25 , provide a capping wafer 310 . Capping wafer 310 can also be a silicon wafer. Furthermore, capping wafer 310 can also be provided with global alignment marks (not shown) to facilitate subsequent alignment.

[0057] Step 63: Deposit a second bonding metal layer on the cap layer wafer and pattern-etch the second bonding metal layer to form a second bonding portion. As shown in FIG28 , metal is deposited on the cap layer wafer 310 to form a second bonding metal layer 330. As shown in FIG29 , the second bonding metal layer 330 is pattern-etched to form a second bonding portion 332. The material of the second bonding metal layer 330 can be any eutectic metal, such as germanium or gold.

[0058] In combination with step 53, as well as steps 61 and 63, in step S106, the side of the device wafer 210 facing away from the substrate wafer 110 is eutectic bonded to the cap layer via the first bonding portion 224 and the second bonding portion 332. It is understood that the bonding method can be any type of eutectic bonding, or other types of bonding methods can be used, such as thermal compression bonding, transient liquid phase bonding, solder bonding, glass fusion bonding, etc.

[0059] Furthermore, after executing step 61 and before executing step 63, the method further includes:

[0060] Step 62: A fifth oxide layer is formed on the cap layer wafer and patterned and etched to form a second protrusion. As shown in Figures 26 and 27 , oxide is deposited on one or both sides of the cap layer wafer 310 to form a fifth oxide layer 320. The fifth oxide layer 320 on one side is patterned and etched to form a second protrusion 322. The fifth oxide layer 320 can be any dielectric film. In this embodiment, the fifth oxide layer 320 is a silicon oxide layer.

[0061] Combining step 63 and step S105, it can be seen that the second bonding portion 332 obtained in step 63 is adjacent to the second protrusion 322. The second bonding portion 332 and the second protrusion 322 may be in contact or there may be a gap, and the size of the gap is not fixed. The second protrusion 322 may be set on both sides of the second bonding portion 332, or on one side of the second bonding portion 332. The specific setting method can be adjusted according to actual needs. Specifically, the second bonding portion 332 located at the edge of the cover layer wafer 310 is provided with a second protrusion 322 on the side close to the middle area of ​​the cover layer wafer 310; the second bonding portion 332 located in the middle area of ​​the cover layer wafer 310 is provided with a second protrusion 322 on both sides. When the second bonding portion 332 is subsequently eutectic bonded to the first bonding portion 224, a eutectic fluid will be generated during the bonding process. The function of the second protrusion 322 is to prevent the eutectic fluid from overflowing during bonding.

[0062] Furthermore, the step of preparing the cover layer further includes:

[0063] Step 64: Pattern-etch the cap layer wafer to create a cap layer cavity and a third protrusion disposed within the cap layer cavity. As shown in FIG30 , pattern-etch the cap layer wafer 310 in an area avoiding the second bonding portion 332 and the second protrusion 322 to create a cap layer cavity and a third protrusion 312 disposed within the cap layer cavity. Combined with step S106, after the device wafer 210 is eutectic-bonded to the cap layer via the first bonding portion 224 and the second bonding portion 332 on the side facing away from the substrate wafer 110, the cap layer cavity provides space for movement of the movable structure 212. The third protrusion 312 is used to limit the maximum upward movement of the movable structure 212 and provide a restoring force for the movable structure 212 to prevent adhesion. The third protrusion 312 cooperates with the first protrusion 152 to limit the vertical movement of the movable structure 212. In this embodiment, integrating the third protrusion 322 into the cap layer also improves device compactness.

[0064] Furthermore, the step of preparing the cover layer further includes:

[0065] Step 65: Generate a getter in the cap layer chamber of the cap layer wafer. Specifically, the MEMS sensor is an IMU (Inertial Measurement Unit) that includes a gyroscope and an accelerometer, as shown in Figures 31 and 34 . Region X is used to fabricate the gyroscope, and region Y is used to fabricate the accelerometer. A getter 340 is provided in the cap layer chamber corresponding to region X on the cap layer wafer 310. Getter 340 in the cap layer chamber is used to maintain a vacuum in the gyroscope.

[0066] In one embodiment, as shown in FIG32 , after executing step S106, the method further includes:

[0067] Step S107: Graphically etch the cover layer so that the device layer is partially exposed. Specifically, as shown in Figures 33 to 35, after the bonding is completed, the cover layer wafer 310 is ground and polished to reduce the thickness of the cover layer wafer 310 and improve the flatness of the cover layer wafer 310. The portion of the cover layer wafer 310 that blocks the solder joint 222 is graphically etched to expose the solder joint 222. On the one hand, it is convenient to connect the solder joint 222 after it is exposed. On the other hand, the position of the solder joint 222 is lower than the cover layer wafer 310. After the solder joint 222 is connected to the lead, the height of the lead can be lower than the cover layer wafer 310. In this way, the package size can be reduced when the shell is subsequently packaged.

[0068] It is understandable that the specific thicknesses of the substrate wafer 110 , the first oxide layer 120 , the first polysilicon layer 130 , the second oxide layer 140 and the second polysilicon layer 150 are not unique and can be designed according to actual needs.

[0069] In one embodiment, the thickness of the substrate wafer 110 is 150 microns to 500 microns. The thickness of the substrate wafer 110 can be selected to be 150 microns, 200 microns, 300 microns, 500 microns, etc. By designing a thicker substrate wafer 110, the capacitor plates of the MEMS sensor have better stability.

[0070] In one embodiment, the thickness of the second oxide layer 140 is 1 micron to 5 microns. The thickness of the second oxide layer 140 after planarization can be designed to be 1 micron, 2 microns, 3 microns, 5 microns, etc. The thickness of the second oxide layer 140 between the first polysilicon layer 130 and the second polysilicon layer 150 can be adjusted to control the distance between the vertical wiring and the capacitor plate 154. In this embodiment, by properly selecting the thickness of the second oxide layer 140 between the two polysilicon layers, the parasitic capacitance of the MEMS sensor can be effectively reduced.

[0071] In one embodiment, the thickness of the first oxide layer 120 is 1 micron to 3 microns, and / or the thickness of the second oxide layer 140 is 1 micron to 5 microns, and / or the thickness of the first polysilicon layer 130 is 1 micron to 5 microns, and / or the thickness of the second polysilicon layer 150 is 5 microns to 10 microns. The thickness of the first oxide layer 120 can be designed to be 1 micron, 1.5 microns, 2 microns, 3 microns, etc., and the thickness of the second oxide layer 140 after planarization can be designed to be 1 micron, 2 microns, 3 microns, 5 microns, etc. The thickness of the first polysilicon layer 130 can be designed to be 1 micron, 2 microns, 3 microns, 5 microns, etc., and the thickness of the second polysilicon layer 150 after planarization can be designed to be 5 microns, 6 microns, 8 microns, 10 microns, etc. By adjusting the thickness of at least one of the first polysilicon layer 130, the second polysilicon layer 150, the first oxide layer 120, and the second oxide layer 140, the distance between the substrate wafer 110 and the device wafer 210 can be controlled. In this embodiment, by properly adjusting the thickness of at least one of the first polysilicon layer 130 , the second polysilicon layer 150 , the first oxide layer 120 , and the second oxide layer 140 between the substrate wafer 110 and the device wafer 210 , the parasitic capacitance of the MEMS sensor can be effectively reduced.

[0072] In one embodiment, a MEMS sensor is provided, comprising a substrate wafer, a first oxide layer, a first polysilicon layer, a second oxide layer, a second polysilicon layer, a device layer and a cover layer. The MEMS sensor may further comprise a getter, etc. The MEMS sensor is prepared by the above method.

[0073] In the aforementioned MEMS sensor and its fabrication method, both the bonding anchor and the capacitor plate are formed in the second polysilicon layer. After the device wafer is bonded to the bonding anchor, a cavity is formed between the device wafer and the capacitor plate because the capacitor plate is lower than the bonding anchor. Therefore, after patterning the device wafer to create the movable structure, no holes need to be etched to release the movable structure, resulting in higher capacitance for out-of-plane sensing and greater reliability.

[0074] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0075] The above embodiments merely illustrate several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make various modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A method for preparing a MEMS sensor, characterized in that: include: Generating a first oxide layer on a substrate wafer, and pattern-etching the first oxide layer, and depositing and doping the first oxide layer after pattern-etching to form a first polysilicon layer; Performing patterned etching on the first polysilicon layer to form wiring, and depositing a second oxide layer on the first polysilicon layer; After patterning and etching the second oxide layer, depositing and doping to form a second polysilicon layer; Performing pattern etching on the second polysilicon layer to form a bonding anchor point and a capacitor plate with a lower height than the bonding anchor point; Bonding the device wafer to the bonding anchor point, and pattern-etching the device wafer to generate a movable structure to obtain a device layer; The side of the device wafer facing away from the substrate wafer is bonded to the capping layer.

2. The method according to claim 1, characterized in that The patterning and etching of the second polysilicon layer to form a bonding anchor point and a capacitor plate with a lower height relative to the bonding anchor point includes: performing a planarization process on the second polysilicon layer, and forming a third oxide layer on the second polysilicon layer after the planarization process; The third oxide layer and the second polysilicon layer are pattern-etched to form a bonding anchor point and a capacitor plate with a first protrusion, and a portion of the third oxide layer covering the bonding anchor point is retained.

3. The method according to claim 2, characterized in that After patterning and etching the third oxide layer and the second polysilicon layer to form a bonding anchor point and a capacitor plate with a first protrusion, and retaining a portion of the third oxide layer covering the bonding anchor point, the method further includes: generating a fourth oxide layer covering the third oxide layer and the capacitor plate; The third oxide layer and the fourth oxide layer are pattern-etched to expose the bonding anchor point.

4. The method according to claim 3, characterized in that The device wafer is bonded to the bonding anchor point, and the device wafer is patterned and etched to generate a movable structure to obtain a device layer, including: bonding the device wafer to the bonding anchor point; performing a planarization process on the device wafer; Performing patterned etching on the device wafer to generate a movable structure, and obtaining a device layer after the etching is completed; The fourth oxide layer covering the capacitor plate is removed.

5. The method according to claim 4, characterized in that After the device wafer is planarized, the device wafer is patterned and etched to generate a movable structure, and before the device layer is obtained after the etching is completed, the method further includes: metal deposition is performed on the device wafer to obtain solder joints and a first bonding portion.

6. The method according to any one of claims 1 to 5, characterized in that: After bonding the side of the device wafer facing away from the substrate wafer to the cover layer, the method further includes: patterning and etching the cover layer so that the device layer is partially exposed.

7. The method according to claim 5, characterized in that Before bonding the side of the device wafer facing away from the substrate wafer to the cover layer, the method further comprises: providing a cap layer wafer; A second bonding metal layer is deposited on the cap layer wafer, and the second bonding metal layer is pattern-etched to obtain a second bonding portion.

8. The method according to claim 7, characterized in that After providing the cover layer wafer, depositing the second bonding metal layer on the cover layer wafer and pattern-etching the second bonding metal layer to obtain the second bonding portion, the method further includes: generating a fifth oxide layer on the cover layer wafer and pattern-etching the fifth oxide layer to form a second protrusion.

9. The method according to claim 7, characterized in that: After depositing a second bonding metal layer on the cover layer wafer and pattern-etching the second bonding metal layer to obtain a second bonding portion, the method further includes: pattern-etching the cover layer wafer to generate a cover layer chamber and a third protrusion arranged in the cover layer chamber.

10. The method according to any one of claims 1 to 5, characterized in that: The thickness of the second oxide layer is 1 micrometer to 5 micrometers.

11. The method according to any one of claims 1 to 5, characterized in that: The thickness of the first oxide layer is 1 micrometer to 3 micrometers.

12. The method according to any one of claims 1 to 5, characterized in that: The thickness of the first polysilicon layer is 1 micrometer to 5 micrometers.

13. The method according to any one of claims 1 to 5, characterized in that: The thickness of the second polysilicon layer is 5 micrometers to 10 micrometers.

14. The method according to any one of claims 1 to 5, characterized in that: The thickness of the substrate wafer is 150 microns to 500 microns.

15. A MEMS sensor, characterized in that: The MEMS sensor comprises a substrate wafer, a first oxide layer, a first polysilicon layer, a second oxide layer, a second polysilicon layer, a device layer and a cover layer. The MEMS sensor is prepared by the method according to any one of claims 1 to 14.

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