Storage array and manufacturing method therefor, storage apparatus, and electronic device

Abstract

The present application relates to the technical field of storage, and provides a storage array and a manufacturing method therefor, a storage apparatus, and an electronic device. The storage array comprises: a substrate, a plurality of first signal lines and a plurality of second signal lines disposed on the substrate, and multiple layers of storage cells vertically stacked on the substrate. The direction of extension of the first signal lines is parallel to the substrate, and the direction of extension of the second signal lines is perpendicular to the substrate. Each storage cell comprises a selector and a capacitor that are disposed in a direction parallel to the substrate, and the selector and the capacitor are coupled in series between the corresponding first signal line and second signal line. Each second signal line is coupled to a plurality of storage cells that are stacked, and each first signal line is coupled to a plurality of storage cells that are disposed in a same layer. The costs (such as photolithography costs) of the storage array does not increase accordingly with the increase in the number of storage cell layers, thereby achieving low-cost and high-density three-dimensional storage.

Description

Storage array and manufacturing method thereof, storage device, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on November 30, 2023, with application number 202311636811.6 and invention name “Memory array and its manufacturing method, storage device, electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of storage technology, and in particular to a storage array and a manufacturing method thereof, a storage device, and an electronic device. Background Art

[0003] Dynamic random access memory (DRAM) offers the advantages of fast read / write speeds and high endurance, but it also suffers from limited storage capacity and high power consumption. With the rapid development of the Internet of Things, big data, and artificial intelligence, traditional DRAM is no longer able to meet these demands. Ferroelectric random access memory (FRAM), with its fast read / write speeds, low power consumption, and scalability, has become an ideal alternative to DRAM for providing large-capacity memory.

[0004] Compared to the 1T1C (1 transistor 1 capacitor) structure used in traditional DRAM memory cells, the 1S1C (1 selector 1 capacitor) structure used in FRAM memory cells offers excellent scaling potential and robustness against interference in high-density architectures. Currently, in three-dimensional memory architectures based on the 1S1C structure, the stacked layers of memory cells require independent manufacturing processes (including photolithography), which increases device manufacturing costs and limits their further development.

[0005] Summary of the Invention

[0006] The present application provides a storage array and a manufacturing method thereof, a storage device, and an electronic device, providing a low-cost, high-density three-dimensional storage architecture.

[0007] The present application provides a memory array, which includes a substrate, a plurality of first signal lines, a plurality of second signal lines, and a plurality of memory cells stacked vertically on the substrate. The first signal lines extend in a direction parallel to the substrate, and the second signal lines extend in a direction perpendicular to the substrate. The memory cells include a selector and a capacitor coupled in series between the first signal line and the second signal line, and the selector and the capacitor are arranged in a direction parallel to the substrate. The first signal line is coupled to the plurality of memory cells arranged in the same layer. The second signal line is coupled to the plurality of memory cells arranged in a stacked manner.

[0008] That is to say, the storage array provided in the present application adopts a cross-type structure in the direction perpendicular to the substrate. By arranging the selectors and capacitors in the storage cells in the horizontal direction (i.e., in the direction parallel to the substrate), the selectors and capacitors can be formed by preparing transversely stacked film layers by an isotropic deposition method. The production of multi-layer storage cells can be completed through a single production process, so that the production cost of the storage array (such as the photolithography cost) does not increase accordingly with the increase in the number of storage cell layers, thereby achieving the purpose of reducing production costs and being more conducive to achieving high-density storage.

[0009] In some possible implementations, the number of layers of the multi-layer storage unit may be 64 to 200.

[0010] In some possible implementations, the capacitor includes a ferroelectric capacitor, which has good compatibility with silicon-based semiconductor processes and can be manufactured using mature manufacturing processes without increasing manufacturing costs.

[0011] In some possible implementations, the projections of multiple layers of memory cells on the substrate overlap, that is, multiple memory cells located in the lower layer are aligned one by one with multiple memory cells located in the upper layer, thereby simplifying the manufacturing process and reducing manufacturing costs.

[0012] In some possible implementations, a memory cell includes: a first metal line, a ferroelectric layer, a first metal layer, and a resistive switching layer stacked in sequence parallel to a substrate. A first end of the first metal line is connected to a second signal line, and a second end of the first metal line is connected to the first signal line via the ferroelectric layer, the first metal layer, and the resistive switching layer, which are sequentially arranged. The first metal line and the first signal line are located on the same layer. The first metal line, the ferroelectric layer, and the first metal layer form a capacitor. The first signal line, the resistive switching layer, and the first metal layer form a selector.

[0013] In some possible implementations, the memory array includes a trench whose depth is parallel to the substrate. A resistive switching layer covers the bottom and sidewalls of the trench, and a first signal line is filled inside the resistive switching layer. In this case, the ferroelectric layer and the first metal layer cover the end face and side face of the second end of the first metal line, thereby increasing the capacitance of the capacitor and reducing the relative area of ​​the selector. In this way, when operating the memory cell, the selector can obtain a larger voltage divider at the moment the operating voltage is applied, allowing it to be turned on instantly. The turned-on selector is in a low-resistance state, causing most of the voltage to fall on the ferroelectric capacitor, thereby accelerating the polarization reversal speed of the ferroelectric layer in the ferroelectric capacitor, thereby accelerating the read and write speed of the memory cell.

[0014] In some possible implementations, the memory array includes a hole, the depth of which is parallel to the substrate. A ferroelectric layer and a first metal layer cover the bottom and sidewalls of the hole, with the first metal layer located inside the ferroelectric layer; and a first metal line fills the inside of the first metal layer. In this case, the resistive layer covers the surface of the first signal line near the first metal line and two surfaces perpendicular to the substrate.

[0015] In some possible implementations, a plurality of first signal lines connected to the stacked multi-layer memory cells are stacked in parallel and are manufactured through a same photolithography process.

[0016] In some possible implementations, a plurality of second signal lines connected to the stacked multi-layer memory cells are arranged in parallel and are manufactured through a same photolithography process.

[0017] In some possible implementations, the first metal lines in the multi-layer memory cell are fabricated through a single photolithography process.

[0018] In some possible implementations, the ferroelectric layers in the multi-layer memory cell are fabricated through a single photolithography process.

[0019] In some possible implementations, the resistive switching layers in the multi-layer memory cell are manufactured through a single photolithography process.

[0020] In some possible implementations, the resistive switching layer can switch between a high resistance state and a low resistance state under the control of voltages applied by the first signal line and the second signal line.

[0021] In some possible implementations, the material of the resistive layer includes at least one of silicon or silicon compounds, germanium or germanium compounds, metal oxides, materials with metal-insulator transition properties, mixed ion-electron conductor materials, perovskite-type composite oxides, solid electrolytes, or organic polymers.

[0022] In some possible implementations, the resistive switching layer includes a PNP junction or an NPN junction.

[0023] In some possible implementations, the ferroelectric layer may include a hafnium oxide-based ferroelectric material.

[0024] In some possible implementations, the ferroelectric layer may include aluminum nitride (AlN) doped with scandium (Sc) material.

[0025] The present application also provides a method for manufacturing a memory array, which may include: manufacturing a stacked structure on a substrate; wherein the stacked structure includes a plurality of first insulating layers and a plurality of second insulating layers arranged in sequence and overlapping each other; removing the plurality of first insulating layers in the stacked structure, manufacturing a first signal line, a selector, and a capacitor in the removed region of each first insulating layer, and forming a second signal line perpendicular to the substrate on the side of the stacked structure; wherein the selector and the capacitor are arranged in a direction parallel to the substrate and are used to form a memory cell, and the selector and the capacitor are coupled in series between the first signal line and the second signal line, the second signal line is coupled to the plurality of memory cells arranged in the stack, and the first signal line is coupled to the plurality of memory cells arranged in the same layer.

[0026] This fabrication method allows for the production of multiple layers of memory cells in a single manufacturing process. This ensures that the manufacturing costs of the memory array (such as photolithography costs) do not increase proportionally with the number of memory cell layers, thereby reducing manufacturing costs and facilitating high-density storage. Furthermore, this method enables self-alignment of the selector and capacitor, eliminating the need for photolithography alignment, further reducing photolithography costs and avoiding the potential overlap issues that can occur during photolithography alignment.

[0027] In some possible implementation methods, the above-mentioned production of a stacked structure on a substrate may include: sequentially overlapping and producing multiple first insulating layers and multiple second insulating layers on the substrate, and etching the multiple first insulating layers and the multiple second insulating layers as a whole to form a stacked structure; wherein the stacked structure is comb-shaped, and each film layer in the stacked structure includes a connecting portion and multiple comb-tooth portions connected to the connecting portion.

[0028] In some possible implementations, the above-mentioned removal of multiple first insulating layers in the stacked structure, making a first signal line, a selector, and a capacitor in the removed area of ​​each first insulating layer, and forming a second signal line perpendicular to the substrate on the side of the stacked structure may include: removing multiple first insulating layers in the stacked structure, making a first signal line and a selector in the removed area of ​​the connecting portion in the first insulating layer, making capacitors respectively in the removed areas of multiple comb-tooth portions in the first insulating layer, and forming a second signal line perpendicular to the substrate at the end of the comb-tooth portion.

[0029] In some possible implementations, the above-mentioned removal of multiple first insulating layers in the stacked structure, making a first signal line and a selector in the removed area of ​​the connecting portion in the first insulating layer, making capacitors in the removed areas of the multiple comb-tooth portions in the first insulating layer, and forming a second signal line perpendicular to the substrate at the end of the comb-tooth portion can include: using a first insulating material to fill the gap in the stacked structure to form a filling structure. Removing the connecting portions in the multiple first insulating layers to form multiple grooves on the side of the filling structure. Forming a resistive switching layer and a first signal line in the multiple grooves in sequence, and covering the side where the first signal line is located with a second insulating material. Removing the comb-tooth portions in the multiple first insulating layers to form multiple holes. Forming a first metal layer, a ferroelectric layer, and a first metal line in sequence in the multiple holes, and forming a second signal line connected to the first metal line on the open side of the hole.

[0030] In some possible implementations, removing the plurality of connecting portions in the first insulating layer to form the plurality of trenches on the side of the filling structure may include: etching from the top of the filling structure downward to the substrate on a side near the connecting portion to remove a portion of the connecting portion on a side away from the comb-teeth portion; and removing the remaining connecting portions from the side of the filling structure by etching to form the plurality of trenches.

[0031] In some possible implementations, sequentially forming a first metal layer, a ferroelectric layer, and a first metal wire in the plurality of holes, and forming a second signal wire connected to the first metal wire on the opening side of the hole, may include: depositing a metal material in the plurality of holes to form the first metal layer; depositing a ferroelectric layer in the hole having the first metal layer formed; depositing a metal material in the hole having the ferroelectric layer formed to form the first metal wire in the hole; simultaneously forming a metal film on the surface of the hole opening side, and etching the metal film to form the plurality of second signal wires.

[0032] In some possible implementations, the first insulating material is the same as the insulating material in the second insulating layer.

[0033] In some possible implementations, the second insulating material is the same as the insulating material in the second insulating layer.

[0034] The present application also provides a storage device, which includes a controller and a storage array provided in any of the possible implementation methods described above, wherein the storage array is electrically connected to the controller.

[0035] The present application also provides an electronic device, which includes a circuit board and a storage device provided in any of the possible implementation methods described above, wherein the storage device is electrically connected to the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] FIG1 is a diagram illustrating an electronic device according to an embodiment of the present invention;

[0037] FIG2 is an architectural diagram of a storage device provided in an embodiment of the present application;

[0038] FIG3 is a schematic diagram of a storage array provided in an embodiment of the present application;

[0039] FIG4 is a schematic diagram of the structure of a storage unit in a storage array provided in an embodiment of the present application;

[0040] FIG5 is a schematic cross-sectional view along position AA′ in FIG4 (the substrate is omitted);

[0041] FIG6 is a schematic cross-sectional view along position BB′ of FIG4 (the substrate is omitted);

[0042] FIG7 is a schematic diagram of the structure of a selector provided in the present application;

[0043] FIG8 is a schematic structural diagram of a ferroelectric capacitor provided by the present application;

[0044] FIG9 is a partial cross-sectional schematic diagram of a storage array provided in an embodiment of the present application;

[0045] FIG10 is a flowchart of manufacturing a storage array provided by the present application;

[0046] FIG11 is a schematic diagram of a storage array during manufacturing according to an embodiment of the present application;

[0047] FIG12 is a flowchart of manufacturing a storage array provided by the present application;

[0048] FIG13 is a schematic diagram of a storage array during the manufacturing process provided by the present application;

[0049] FIG14 is a schematic diagram of a storage array during the manufacturing process provided by the present application;

[0050] FIG15 is a schematic diagram of a storage array during the manufacturing process provided by the present application;

[0051] FIG16 is a schematic diagram of a storage array during the manufacturing process provided by the present application;

[0052] FIG17 is a schematic diagram of a storage array provided by the present application during the manufacturing process;

[0053] FIG18 is a top view of a storage array provided in accordance with an embodiment of the present application;

[0054] FIG19 is a side view of a storage array provided in accordance with an embodiment of the present application. DETAILED DESCRIPTION

[0055] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions in this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0056] The terms "first", "second", etc. in the specification, embodiments, claims, and drawings of this application are only used for the purpose of distinguishing descriptions and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one (item)" means one or more, and "multiple" means two or more. "Installation", "connection", "connected", etc. should be understood in a broad sense, for example, it can be an electrical connection or a mechanical connection; it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, an indirect connection through an intermediate medium, or a connection between two elements. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, including a series of steps or units. Methods, systems, products, or devices are not necessarily limited to the steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to the processes, methods, products, or devices. "Up," "down," "left," "right," etc. are used only with respect to the orientation of components in the drawings. These directional terms are relative concepts and are used for relative description and clarification. They may change accordingly depending on the orientation of the components in the drawings.

[0057] An embodiment of the present application provides an electronic device that uses a low-cost, high-density new storage device.

[0058] This application does not limit the configuration of the above-mentioned electronic device. The electronic device can be any electronic product with a storage device, such as consumer electronic products, household electronic products, vehicle-mounted electronic products, financial terminal products, communication electronic products, etc.

[0059] For example, the above-mentioned consumer electronic products may include mobile phones, tablet computers, laptop computers, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smart watches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products may include smart door locks, televisions, smart speakers, refrigerators, robot vacuums, etc. Car-mounted electronic products may include car navigation systems, car displays, etc. Financial terminal products may include automated teller machines (ATMs) and electronic devices for self-service transactions, etc. Communication electronic products may include communication equipment such as servers, storage devices, radars, and base stations.

[0060] According to actual needs, the above-mentioned electronic device may also be provided with other devices electrically connected to the storage device, such as a printed circuit board (PCB; also called a printed circuit board), input and output devices, etc., and this application does not impose any restrictions on this.

[0061] For illustration, the electronic device described above is taken as a mobile phone as an example. Referring to FIG1 , the mobile phone 100 includes a bus 101, and a system on chip (SoC) 110, a second RAM 120, a communication chip 130, and a power management chip 140 connected to the bus 101. The SoC 110 can be used to process data, such as processing application data, processing image data, and caching temporary data. The SoC 110 may include an application processor (AP) 111 for processing applications, a graphics processing unit (GPU) 112 for processing image data, and a first RAM (random access memory) 113 for caching high-speed data. The AP 111, GPU 112, and first RAM 113 may be integrated into a single die or may be separately provided in multiple dies. The first RAM 113 may be a static random access memory (SRAM) or an embedded flash memory (EFlash). The second RAM 120 may be a dynamic random access memory (DRAM). The second RAM 120 may be used to store volatile data, such as temporary data generated by the SoC 110. The storage capacity of the second RAM 120 is typically greater than that of the first RAM 113, but the access speed is typically slower than that of the first RAM 113. The communication chip 130 may be used to process the protocol stack, amplify and filter analog RF signals, or perform the above functions simultaneously. The power management chip 140 may be used to power other chips.

[0062] The first RAM 113 and the second RAM 120 may both adopt the novel storage device provided in the embodiment of the present application.

[0063] The novel storage device provided in the embodiment of the present application may be any device having a storage function. The storage device provided in the embodiment of the present application is further described below.

[0064] Schematically, an embodiment of the present application provides a memory, as shown in FIG2 . The memory (i.e., a storage device) includes one or more memory arrays (also referred to as memory circuits) and a controller, and the controller is electrically connected to the memory arrays so that the memory arrays can be accessed through the controller. The memory adopts a novel three-dimensional storage architecture, the lithography cost of which does not increase with the number of stacked layers, thereby achieving low-cost, high-density storage.

[0065] For illustration, the memory may be a ferroelectric random access memory (FRAM), but is not limited thereto. The following embodiments are described using this as an example.

[0066] The following further describes the novel storage array used in the above-mentioned memory.

[0067] FIG3 is a schematic diagram of a memory array provided in an embodiment of the present application. FIG4 is a schematic diagram of the structure of a memory cell 10 in a memory array provided in an embodiment of the present application. FIG5 is a schematic cross-sectional view taken along position AA' of FIG4 (with the substrate omitted). FIG6 is a schematic cross-sectional view taken along position BB' of FIG4 (with the substrate omitted).

[0068] Schematically, an embodiment of the present application provides a memory array, with reference to FIG3 and as shown, the memory array includes a plurality of memory cells 10 vertically stacked on a substrate 1, and a plurality of first signal lines La and a plurality of second signal lines Lb arranged on the substrate 1. Each layer of memory cells 10 includes a plurality of memory cells 10 distributed parallel to the substrate 1. The first signal line La is parallel to the substrate 1, that is, the extension direction (X direction) of the first signal line La is parallel to the substrate 1. Of course, the first signal line La can also extend along the Y direction. The second signal line Lb is perpendicular to the substrate 1, that is, the extension direction (Z direction) of the second signal line Lb is perpendicular to the substrate 1.

[0069] The number of layers of the stacked multi-layer memory cells 10 can be 64 to 200, but is not limited thereto. For example, in some embodiments, the memory array can have 64 layers of stacked memory cells 10. For another example, in some embodiments, the memory array can have 128 layers of stacked memory cells 10. For another example, in some embodiments, the memory array can have 200 layers of stacked memory cells 10.

[0070] As shown in Figures 3, 4, and 5, the memory cell 10 includes a selector S and a capacitor C (such as a ferroelectric capacitor), and the selector S and capacitor C are stacked in a horizontal direction (i.e., in a direction parallel to the substrate 1) (see Figure 5). That is, the selector S and capacitor C in the memory cell 10 are distributed in the same layer. The selector S and capacitor C are coupled in series between a first signal line La and a second signal line Lb. The first signal line La is coupled to the selectors S in multiple memory cells 10 arranged in the same layer, and the second signal line Lb is coupled to the capacitors C in multiple memory cells 10 arranged in the stack.

[0071] In other words, the memory array adopts a cross-type structure in a direction perpendicular to the substrate 1 (i.e., longitudinal direction), and the memory cell 10 can be located in the intersection region of the first signal line La and the second signal line Lb. The "intersection region" refers to the spatial intersection of the first signal line La and the second signal line Lb, and the two do not actually touch each other.

[0072] Furthermore, in the aforementioned memory array, the plurality of first signal lines La can be located in the same layer as the multiple layers of memory cells 10 in a direction perpendicular to the substrate 1. That is, a first signal line La is provided at a spatial location corresponding to each layer of memory cells 10. In this case, the selectors S in the plurality of memory cells 10 located in a particular layer are coupled to the first signal lines La provided in that layer. Of course, the first signal lines La can also be located in different layers from the memory cells 10, and this is not a limitation in this application.

[0073] Compared to a conventional 1T1C memory cell (i.e., a transistor and a capacitor), the memory cell 10 of the present application employs a 1S1C structure (i.e., a selector transistor S and a capacitor C). The selector transistor S replaces the conventional transistor. The selector S is a two-terminal device with an on / off function, exhibiting a high-resistance or low-resistance state depending on the voltage applied across it. Thus, the memory cell 10 can be turned off by controlling the selector S to be in a high-resistance state, and turned on by controlling the selector S to be in a low-resistance state.

[0074] The following briefly describes the structure and operating principle of the selector S and capacitor C.

[0075] Schematically, referring to FIG7 , the selector S includes a first electrode and a second electrode disposed opposite each other, and a resistive switching layer located between the first electrode and the second electrode. The resistive switching layer has a characteristic of varying resistance, and changes between a high-resistance state and a low-resistance state as the voltage applied to the first electrode and the second electrode changes. That is, as the voltage applied to the first electrode and the second electrode changes, the selector S becomes equivalent to a high-resistance device or a low-resistance device, thereby enabling or blocking current in the path, and thereby enabling or disabling the memory cell 10 in which it resides.

[0076] As an example, let's take capacitor C as a ferroelectric capacitor. Referring to FIG8 , capacitor C includes a third electrode and a fourth electrode disposed opposite to each other, and a ferroelectric layer located between the third electrode and the fourth electrode. The polarization direction of the ferroelectric layer reverses as the electric field between the third electrode and the fourth electrode changes, that is, the polarization direction is reversible, and different polarization directions correspond to different information states. The storage unit 10 uses the polarization direction of the ferroelectric layer in the ferroelectric capacitor C to store information. For example, when the polarization direction of the ferroelectric layer in the ferroelectric capacitor C is positive, the stored information is "0"; when the polarization direction of the ferroelectric layer in the ferroelectric capacitor C is negative, the stored information is "1". For another example, when the polarization direction of the ferroelectric layer in the ferroelectric capacitor C is positive, the stored information is "1"; when the polarization direction of the ferroelectric layer in the ferroelectric capacitor C is negative, the stored information is "0".

[0077] It is understandable that the capacitor C is a ferroelectric capacitor, which has good compatibility with silicon-based semiconductor processes and can be manufactured using mature manufacturing processes without increasing manufacturing costs. The following embodiments are all described using this as an example.

[0078] In traditional 3D memory architectures, the devices (transistors and capacitors) within a memory cell are stacked vertically (perpendicular to the substrate), and the signal lines (word lines, bit lines, etc.) connecting the memory cells are arranged parallel to the substrate. In this case, the multi-layer stacked memory cells require independent manufacturing processes (such as photolithography), resulting in high production costs.

[0079] In contrast, in the memory array provided in the embodiment of the present application, the selector S and the capacitor C in the memory cell 10 are stacked in the horizontal direction (i.e., in the direction parallel to the substrate 1) (Figure 5), and one of the two signal lines (La, Lb) connected to the memory cell 10 is arranged perpendicular to the substrate 1, and the other is arranged parallel to the substrate 1. In this case, the laterally stacked film layers can be prepared by an isotropic deposition method to form the laterally stacked selectors S and capacitors C. In this way, a stacked multi-layer memory cell can be manufactured in a single manufacturing process (the specific manufacturing method can be referred to below), so that the manufacturing cost of the memory array (such as the photolithography cost) does not increase accordingly with the increase in the number of memory cell layers, thereby achieving the purpose of reducing the manufacturing cost, which is more conducive to achieving high-density storage.

[0080] Schematically, in some possible implementations, the projections of the stacked multi-layer storage units 10 on the substrate 1 can overlap, that is, the multiple storage units located on the lower layer are aligned one by one with the multiple storage units located on the upper layer, thereby simplifying the manufacturing process and reducing the manufacturing cost. For details, please refer to the relevant instructions below.

[0081] The stacking manner of the selectors S and capacitors C arranged in the lateral direction in the memory cell 10 is described below.

[0082] 4, 5, and 6, in some possible implementations, the memory cell 10 includes a first metal line 101, a ferroelectric layer 102, a first metal layer 103, and a resistive switching layer 104, which are stacked in sequence along a horizontal direction. One end (right end) of the first metal line 101 is connected to the second signal line Lb, and the other end (left end) of the first metal line 101 is connected to the first signal line La provided in the same layer via the ferroelectric layer 102, the first metal layer 103, and the ferroelectric layer 102, in sequence.

[0083] In this case, as shown in FIG5 , the first signal line La, the first metal layer 103, and the resistive switching layer 104 located therebetween, stacked laterally, can form a selector S. The first signal line La and the first metal layer 103 act as the two electrodes of the selector S. The resistive switching layer 104 can switch between a high-resistance state and a low-resistance state under the control of the voltages applied to the first signal line La and the first metal layer 103. The voltage applied to the first metal layer 103 can be controlled by the second signal line La. The first metal layer 103, the first metal line 101, and the ferroelectric layer 102 located therebetween, stacked laterally, can form a capacitor C. The first metal layer 103 and the first metal line 101 act as the two electrodes of the capacitor C. The polarization direction of the ferroelectric layer 102 reverses as the electric field between the first metal layer 103 and the first metal line 101 changes. The voltage applied to the first metal layer 103 and the first metal line 101 can be controlled by the first signal line La and the second signal line Lb.

[0084] It should be understood that in the above-described memory cell 10, the first metal layer 103 serves as a common electrode for the selector S and the capacitor C, which can simplify the manufacturing process and reduce manufacturing costs. However, the present application is not limited thereto, and in other possible implementations, the selector S and the capacitor C can use different electrode layers.

[0085] In addition, according to the actual needs of the storage unit 10, other film layers can be set in the stack formed by the first signal line La, the resistive layer 104, and the first metal layer 103, and other film layers can be set in the stack formed by the first metal layer 103, the ferroelectric layer 102, and the first metal line 101. This application does not impose any restrictions on this.

[0086] Regarding the configuration of the resistive switching layer 104 and the first signal line La:

[0087] Schematically, in some possible implementations, as shown in FIG5 and FIG9 , when fabricating the resistive switching layer 104 and the first signal line La, a transverse trench 21 with an opening toward the left (i.e., away from the capacitor C) can be first formed (i.e., the depth direction of the trench 21 is parallel to the substrate 1), the resistive switching layer 104 is first deposited on the bottom and sidewalls of the trench 21, and then the first signal line La is filled inside the resistive switching layer 104. In this way, the resistive switching layer 104 can cover the right surface of the first signal line La (i.e., the surface close to the first metal line 101) and the upper and lower surfaces in a direction perpendicular to the substrate 1. The specific fabrication process of the resistive switching layer 104 and the first signal line La can be found below.

[0088] The cross-sectional position of FIG9 is for illustrating the internal structure of the storage unit clearly, and the same is true for other similar figures (such as FIG11, FIG16, and FIG17).

[0089] It should be noted that the "overlap" relationship between two devices in this application refers only to regional coverage and does not restrict whether the two devices are in contact. For example, the resistive switching layer 104 covering the surface of the first signal line La may or may not be in direct contact with the first signal line La, and other layers may be present between the two. This application does not impose any restrictions on this, and in practice, the design can be based on the functional requirements of the device.

[0090] 9 , the resistive switching layer 104 in the multi-layer memory cell 10 can be manufactured through a single manufacturing process, that is, the resistive switching layer 104 in the multi-layer memory cell 10 can be obtained through a single photolithography process. For the specific manufacturing process, please refer to the manufacturing method below.

[0091] 9 , the multi-layer first signal line La connected to the multi-layer storage unit 10 can be manufactured through a single manufacturing process, that is, the multi-layer first signal line La can be obtained through a single photolithography process. The specific manufacturing process can refer to the manufacturing method below.

[0092] Regarding the configuration of the first metal wire 101, the ferroelectric layer 102, and the first metal layer 103:

[0093] In some possible implementations, as shown in Figures 5 and 9, when manufacturing the first metal layer 103, the ferroelectric layer 102, and the first metal wire 101, a transverse hole 22 with its opening facing the right side (i.e., away from the selector S) can be first formed (i.e., the depth direction of the hole is parallel to the substrate 1), and the first metal layer 103 and the ferroelectric layer 102 are sequentially deposited on the bottom and sidewalls of the hole 22. Then, metal is filled inside the ferroelectric layer 102 to form the first metal wire 101. In this way, the ferroelectric layer 102 and the first metal layer 103 can extend from the end face (left end) of the first metal wire 101 to cover the side face of the first metal wire 101, thereby increasing the area of ​​the capacitor C and thereby increasing the capacitance of the capacitor C. The specific manufacturing process of the first metal layer 103, the ferroelectric layer 102, and the first metal wire 101 can be referred to below.

[0094] It can be understood that by increasing the area of ​​capacitor C, the relative area of ​​selector S can be reduced. In this way, when operating the storage unit 10, at the moment the operating voltage is applied, the selector S can obtain a larger voltage divider, so that it can be turned on instantly. The turned-on selector S is in a low-resistance state, so that most of the voltage falls on capacitor C, thereby accelerating the polarization reversal speed of the ferroelectric layer 102 in the ferroelectric capacitor C, and thus accelerating the reading and writing speed of the storage unit.

[0095] Schematically, referring to FIG9 , the first metal line 101 in the multi-layer memory cell 10 can be manufactured through a single manufacturing process, that is, the first metal line 101 in the multi-layer memory cell 10 can be obtained through a single photolithography process. For the specific manufacturing process, please refer to the manufacturing method below.

[0096] 9 , the ferroelectric layer 102 in the multi-layer memory cell 10 can be manufactured through a single manufacturing process, that is, the ferroelectric layer 102 in the multi-layer memory cell 10 can be obtained through a single photolithography process. The specific manufacturing process can be referred to the manufacturing method below.

[0097] Schematically, referring to FIG9 , the first metal layer 103 in the multi-layer storage unit 10 can be manufactured through a single manufacturing process, that is, the first metal layer 103 in the multi-layer storage unit 10 can be obtained through a single photolithography process. The specific manufacturing process can refer to the manufacturing method below.

[0098] This application does not limit the specific materials used for the above-mentioned first signal line La, second signal line Lb, first metal line 101, ferroelectric layer 102, first metal layer 103, and resistive layer 104. In practice, they can be set as needed as long as they can meet the requirements of the storage array.

[0099] Illustratively, the first signal line La, the second signal line Lb, the first metal line 101 and the first metal layer 103 may be made of one or more conductive materials such as metal, metal nitride, metal carbide, conductive metal nitride, and conductive metal oxide.

[0100] For example, in some possible implementations, the first signal line La, the second signal line Lb, the first metal line 101, and the first metal layer 103 can be made of titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), titanium carbonitride (TiCN), tantalum carbonitride (TaCN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), ruthenium oxide (RuO2), niobium nitride (NbN), molybdenum nitride (MoN), iridium oxide (IrO2), silicon (Si), germanium (Ge), silicon germanium (SiGe), or a combination thereof.

[0101] The materials forming the first signal line La, the second signal line Lb, the first metal line 101 and the first metal layer 103 may be the same or different. This application does not impose any limitation on this. In practice, they may be set as needed.

[0102] For illustration, the ferroelectric layer 102 may be made of ferroelectric materials, antiferroelectric materials, and the like.

[0103] For example, in some possible implementations, the ferroelectric layer 102 may be made of a hafnium oxide-based ferroelectric material.

[0104] The above-mentioned hafnium oxide-based material can be a ferroelectric material of the hafnium oxide (HfO) material system, such as zirconium (Zr)-doped hafnium dioxide (HfO2), silicon (Si)-doped HfO2, aluminum (Al)-doped HfO2, lanthanum (La)-doped HfO2, yttrium (Y)-doped HfO2, gadolinium (Gd)-doped HfO2, strontium (Sr)-doped HfO2, etc.

[0105] The hafnium oxide-based material may also be a ferroelectric material of the hafnium zirconium oxide (HZO) material system, such as lanthanum (La)-doped HZO, yttrium (Y)-doped HZO, strontium (Sr)-doped HZO, gadolinium (Gd)-doped HZO, gadolinium-lanthanum (Gd / La) co-doped HZO, etc. The doping element may also be one or more of nitrogen, iron, lutetium, praseodymium, germanium, scandium, cerium, neodymium, magnesium, barium, indium, gallium, calcium, and carbon.

[0106] The hafnium oxide-based material may also be ferroelectric materials such as hafnium silicon oxide, hafnium aluminum oxide, hafnium lanthanum oxide, hafnium zirconium lanthanum oxide, hafnium zirconium cerium oxide, hafnium zirconium yttrium oxide, and hafnium zirconium gadolinium oxide.

[0107] For another example, in some possible implementations, the ferroelectric layer 102 may be made of aluminum nitride (AlN) doped with scandium (Sc) material.

[0108] The resistive switching layer 104 may be made of a material or device having resistive switching properties.

[0109] Illustratively, in some possible implementations, the resistive layer 104 may include one or more materials with resistive properties selected from silicon or silicon compounds, germanium or germanium compounds, metal oxides, materials with metal-insulator transition properties, phase change materials, mixed ion-electron conductor materials, perovskite-type composite oxides, solid electrolytes, or organic polymers.

[0110] For example, in some embodiments, the material forming the resistive layer 104 may include silicon (Si) or a silicon compound, germanium (Ge) or a germanium compound, or any combination thereof. Silicon compounds may include, for example, silicon sulfide, silicon oxide, silicon nitride, silicon carbide, etc., and germanium compounds may include, for example, germanium sulfide, germanium oxide, germanium nitride, germanium carbide, etc.

[0111] For another example, in some embodiments, the material forming the resistive switching layer 104 may include metal oxide.

[0112] Illustratively, the metal oxide may include at least one of tantalum oxide (Ta2O5), niobium oxide (Nb2O5), titanium dioxide (TiO2), hafnium dioxide (HfO2) or indium gallium zinc oxide (IGZO).

[0113] For example, the metal oxides may include lanthanide oxides, i.e., oxides containing lanthanide elements, such as lanthanum oxide (La2O3), praseodymium oxide (Pr6O 11 )wait.

[0114] For another example, in some embodiments, the material forming the resistive switching layer 104 may include a material having a metal-insulator transition characteristic.

[0115] The metal-insulator transition (MIT) described above refers to the physical transition from a metal conductor to a non-conductive insulator (or semiconductor). Alternatively, it refers to the physical transition from an insulator to a conductor. The material of the resistive layer 104 has the characteristic of nonlinearly decreasing resistance as voltage increases. Therefore, the material of the resistive layer 104 in the embodiments of the present application has the characteristic of being an insulator at low voltages and a metal at high voltages.

[0116] Illustratively, the MIT material may include at least one of vanadium dioxide (VO2), niobium dioxide (NbO2), titanium dioxide (TiO2), tungsten dioxide (WO2), and the like.

[0117] For another example, in some embodiments, the material forming the resistive layer 104 may include a phase change material, which has a low resistance property in a crystalline state and a high resistance property in an amorphous state.

[0118] For another example, in some embodiments, the material forming the resistive switching layer 104 may include a mixed ionic-electronic conductor (MIEC) material.

[0119] MIEC materials are a type of conductor that exhibits both ionic and electronic conductivity. MIEC materials, also known as mixed conductor materials, are a type of solid material that lies between ionic and electronic conductors, possessing both ionic and electronic conductivity.

[0120] For another example, in some embodiments, the material forming the resistive layer 104 may include a perovskite-type composite oxide.

[0121] The general formula of the above-mentioned perovskite-type composite oxide is ABO3. Perovskite-type composite oxide is a new type of inorganic non-metallic material with unique physical and chemical properties. The A position is generally a rare earth or alkaline earth element ion, and the B position is a transition element ion. Both the A position and the B position can be partially replaced by other metal ions with similar radii while keeping their crystal structure basically unchanged.

[0122] Illustratively, the perovskite-type composite oxide may include at least one of doped strontium titanate (SrTiO 3 ), barium titanate (BaTiO 3 ), lanthanum manganate (LaMnO 3 ), and the like.

[0123] For another example, in some embodiments, the material forming the resistive layer 104 includes a solid electrolyte, which is a type of object that exhibits ionic conductivity in a solid state (ie, below the melting point).

[0124] Schematically, the solid electrolyte can be germanium sulfide (Ge x S y ), silver sulfide (Ag2S), copper sulfide (Cu2S) and other sulfides, silver iodide (AgI), rubidium silver iodide (RbAg4I5) and other iodides, germanium selenide (Ge x Se y ) and other selenides, germanium telluride (Ge x Te y ), antimony telluride (Sbx Te y ), germanium antimony telluride (GeSbTe), silver indium antimony telluride (AgInSbTe), and other tellurides.

[0125] For another example, in some embodiments, the material forming the resistive switching layer 104 may include an organic polymer.

[0126] For example, the organic polymer may include polyethyl methacrylate (PEMA), polyazomethine (PAM), polytriphenylamine (PTPA), or poly[2,7-(9,9-dihexylfluorene)]-block-polypendentisoindigo (PFPA). 14 -b-Piso n ) and other materials.

[0127] In other possible implementations, the resistive layer 104 can be a component with resistive switching characteristics (i.e., a resistive switching element). The resistive layer 104 can be in a high-resistance state or a low-resistance state depending on the magnitude of the applied voltage or current. For example, when the voltage applied to the resistive layer 104 exceeds a threshold voltage (e.g., 1 / 2 Vcc), the resistive layer 104 is in a low-resistance state. When the voltage applied to the resistive layer 104 is less than the threshold voltage, the resistive layer 104 is in a high-resistance state.

[0128] Illustratively, the resistive switching element in the resistive switching layer 104 may be a PNP junction, an NPN junction, a back-to-back Schottky junction, an ovonic threshold switch (OST), or the like.

[0129] For example, in some embodiments, the resistive layer 104 may be a bidirectional threshold switch (OST) element and include a chalcogenide-based material, such as arsenic telluride (As2Te3), arsenic (As2) or arsenic selenide (As2Se3), or include TiO2, titanium dioxide (Ti4O7), tantalum dioxide (TaO2), tantalum pentoxide (Ta2O5), nickel peroxide (NiO2), HfO2, Ge, Sb, Te, etc.

[0130] In addition, the above-mentioned first signal line La, second signal line Lb, first metal line 101, ferroelectric layer 102, first metal layer 103, and resistive layer 104 can be a single-layer structure or a multi-layer structure. This application does not impose any restrictions on this, and they can be set as needed in practice.

[0131] The following further describes the storage array provided by the present application in conjunction with a method for manufacturing the storage array.

[0132] Schematically, an embodiment of the present application provides a method for manufacturing a memory array, as shown in FIG10 , and the manufacturing method may include:

[0133] Step 10: Referring to (a) and (b) of FIG11 , a stacked structure 12 is fabricated on the substrate 1. The stacked structure 12 includes a plurality of first insulating layers A1 and a plurality of second insulating layers A2 that are sequentially overlapped.

[0134] Schematically, in some possible implementations, the laminated structure 12 may be comb-shaped, and each film layer in the laminated structure 12 is comb-shaped, including a connecting portion a and a plurality of comb-tooth portions b connected to the connecting portion a.

[0135] The present application does not impose any restrictions on the materials used for the first insulating layer A1 and the second insulating layer A2, as long as the first insulating layer A1 and the second insulating layer A2 are made of different insulating materials and can meet the requirements of the selective etching of the first insulating layer A1 in the subsequent step 20. For example, the first insulating layer A1 can be made of silicon nitride Si3N4, and the second insulating layer A2 can be made of silicon oxide SiO2.

[0136] Schematically, in some possible implementations, step 10 may include: referring to FIG11(a), using Si3N4 and SiO2, alternately growing on a substrate 1 a plurality of Si3N4 layers (A1) and a plurality of SiO2 layers (A2) to form an initial stacked structure 11. Then, referring to FIG11(b), using a photolithography mask and a dry etching process, the initial stacked structure 11 is etched to the substrate 1, thereby forming a comb-shaped stacked structure 12.

[0137] Step 20, referring to FIG. 11( c ), remove the multiple first insulating layers A1 from the stacked structure 12. A first signal line La, a selector S, and a capacitor C are fabricated in each removed region of the first insulating layer. A second signal line Lb, perpendicular to the substrate 1, is formed on the side of the stacked structure 12. The selector S and the capacitor C are arranged parallel to the substrate 1 and are used to form a memory cell 10. The selector S and the capacitor C are coupled in series between the first signal line La and the second signal line Lb. The second signal line Lb is coupled to the multiple memory cells 10 stacked together, and the first signal line La is coupled to the multiple memory cells 10 located on the same layer.

[0138] Illustratively, in the case where the stacked structure 12 is in a comb-shaped form, the above-mentioned step 20 may include: removing multiple first insulating layers A1 in the comb-shaped stacked structure 12, and making a first signal line La and a selector S stacked in a direction parallel to the substrate 1 in the removed area of ​​the connecting portion a in the first insulating layer A1, and making a capacitor C stacked in a direction parallel to the substrate 1 and the selector S in a direction parallel to the substrate 1 in the removed area of ​​multiple comb-tooth portions b in the first insulating layer A1, and making a second signal line Lb perpendicular to the substrate 1 at the end of the comb-tooth portion b.

[0139] It should be understood that in the present application, by removing the first insulating layer A1 (including the connecting portion and the comb-tooth portion) of the stacked structure 12, a selector S is made in the removed area of ​​the connecting portion a, and a capacitor C is made in the removed area of ​​the comb-tooth portion b. In this way, the selector S and the capacitor C can be self-aligned without the need for photolithography alignment, further saving photolithography costs and avoiding the overlap problem that may occur in the photolithography alignment process.

[0140] In the above step 20 , the first insulating layer A1 is removed to manufacture the storage unit 10 and the first signal line La and the second signal line Lb connected thereto. An appropriate manufacturing process may be selected according to actual needs, and this application does not impose any limitation thereto.

[0141] Schematically, referring to FIG12 , in some possible implementations, based on forming the comb-shaped laminated structure 12 in step 10, the above-mentioned step 20 may include steps 201, 202, 203, 204, and 205, as follows:

[0142] Step 201 , referring to (a) to (b) in FIG. 13 , a first insulating material K1 is used to fill the gaps in the stacked structure 12 to form a filling structure 13 .

[0143] The first insulating material K1 may be the same as the insulating material used in the second insulating layer A2, but is not limited thereto. In practice, it may be set as desired.

[0144] As shown, in some possible implementations, after the stacked structure 12 is formed in step 10, SiO2 (K1) can be filled in areas such as the gaps between the comb teeth b and the side surfaces of the stacked structure 12 using a chemical vapor deposition (CVD) process in step 201, and after the deposition is completed, the stacked structure 12 is planarized using a chemical mechanical planarization (CMP) process to form a filling structure 13.

[0145] Step 202 , referring to FIG. 14 , remove the connecting portions a in the first insulating layer A1 to form a plurality of trenches 21 on the side surface M1 of the filling structure 13 .

[0146] Schematically, in some possible implementations, the above step 202 may include: referring to FIG14(a), etching (e.g., dry etching) from the top of the filling structure 13 downward to the surface of the substrate 1 on the side close to the connection portion a (position E1) to remove a portion of the connection portion a on the side away from the comb-tooth portion b. At this time, the remaining connection portion a will be exposed on the side. Then, referring to FIG14(b), the remaining connection portion a is removed (recess) from the side M1 (i.e., the etched surface) of the filling structure 13 by etching (e.g., wet etching) to form a plurality of grooves 21 on the side M1 of the filling structure 13.

[0147] Step 203 , referring to FIG. 15 , a resistive switching layer 104 and a first signal line La are sequentially formed in the plurality of trenches 21 , and a second insulating material K2 is used to cover the side surfaces of the first signal line La.

[0148] The second insulating material K2 may be the same as the insulating material used in the second insulating layer A2, but is not limited thereto. In practice, it may be set as desired.

[0149] Illustratively, in some possible implementations, step 203 may include: Referring to FIG. 15( a ), a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process may be used to first fill the trench 21 with a resistive material (e.g., TiO 2 ) to form a resistive layer 104, and then fill it with a metal material (e.g., TiN) to form a first signal line La distributed in multiple layers and arranged in parallel. Next, referring to FIG. 15( b ), a chemical vapor deposition (CVD) process may be used to fill SiO 2 (K 2 ) on one side of the first signal line La, and then a chemical mechanical polishing (CMP) process may be used to planarize the first signal line La.

[0150] Step 204 , referring to FIG. 16 , remove the comb-teeth portions b in the first insulating layer A1 to form a plurality of holes 22 .

[0151] Schematically, in some possible implementation methods, the above-mentioned step 205 may include: referring to Figure 16, using a photolithography mask and a dry etching process, removing the comb tooth portion b from the side M2 ​​(the end face of the comb tooth portion b) of the filling structure 13 to form a plurality of holes 22, and exposing the resistive layer 104 at the bottom of the hole 22.

[0152] Step 205 , referring to FIG. 17 , a first metal layer 103 , a ferroelectric layer 102 , and a first metal line 101 are sequentially formed in the plurality of holes 22 , and a second signal line Lb connected to the first metal line 101 is formed at the opening side of the hole 22 .

[0153] Illustratively, in some possible implementations, step 205 may include step 2051, step 2052, and step 2053, as follows:

[0154] Step 2051 : Referring to FIG. 17 ( a ), a metal material is deposited in the plurality of holes 22 to form a first metal layer 103 .

[0155] Illustratively, in some possible implementations, step 2051 may include: using an atomic layer deposition (ALD) process to deposit a metal material (such as TiN) in a plurality of holes 22 to form a first metal layer 103, and using an etching process (such as dry etching) to remove (recess) the metal material deposited on the open side surface (M2) of the hole 22.

[0156] Step 2052 : Referring to FIG. 17 ( b ), a ferroelectric layer 102 is deposited in the hole 22 where the first metal layer 103 is formed.

[0157] For example, in some possible implementations, step 2052 may include: using an atomic layer deposition (ALD) process to deposit a ferroelectric material (such as HZO) in the hole 22 formed with the first metal layer 103 to form the ferroelectric layer 102. Of course, the ferroelectric material may extend to cover the surface (M2) on the opening side of the hole 22, and this application does not limit this.

[0158] Step 2053: Referring to (b) and (c) in Figure 17, a metal material is deposited in the hole 22 in which the ferroelectric layer is formed, and a first metal wire 101 is formed in the hole 22. At the same time, a metal film 101a is formed on the surface (M2) of the opening side of the hole 22, and the metal film 101a is etched to form a plurality of second signal lines Lb.

[0159] Illustratively, in some possible implementations, step 2053 may include: referring to FIG17(b), using an atomic layer deposition (ALD) process to deposit a metal material (e.g., TiN, W) in the hole 22 where the ferroelectric layer 102 is formed to form the first metal line 101, and forming a metal film 101a on the surface (M2) of the opening side of the hole 22; then, referring to FIG17(c), using a photolithography mask and a dry etching process, etching the metal film 101a to form a plurality of second signal lines Lb that are parallel to each other and perpendicular to the substrate 1. In other words, the first metal line 101 and the second signal line Lb are fabricated through a single process.

[0160] It should be understood that the resistive layer 104 and the first signal line La formed in step 203 are located in the removed area of ​​the connecting portion a; the first metal layer 103, the ferroelectric layer 102, and the first metal wire 101 formed in step 205 are located in the removed area of ​​the comb-tooth portion b, and the connecting portion a and the comb-tooth portion b are located on the same layer and connected, thereby ensuring that the first metal layer 103, the ferroelectric layer 102, the first metal wire 101 and the resistive layer 104 are self-aligned, that is, self-alignment of the capacitor C and the selector S is achieved.

[0161] In summary, by adopting the above-mentioned manufacturing method, the manufacturing of multi-layer memory cells 10 is completed through a single manufacturing process, so that the manufacturing cost of the memory array (such as the photolithography cost) does not increase accordingly with the increase in the number of memory cell layers, thereby achieving the purpose of reducing manufacturing costs and being more conducive to achieving high-density storage.

[0162] It should be noted that the above-mentioned manufacturing method is described by taking the manufacturing method based on a comb-shaped stacked structure 12 as an example. In practice, in step 10, the stacked structure of multiple first insulating layers A1 and multiple second insulating layers A2 is etched to form multiple comb-shaped stacked structures 12, so that multiple storage modules can be obtained in the subsequent manufacturing, and one comb-shaped stacked structure 12 corresponds to one storage module.

[0163] FIG18 is a top view of a storage array provided in an embodiment of the present application, and FIG19 is a side view of a storage array provided in an embodiment of the present application.

[0164] Referring to Figures 18 and 19, in some possible implementation methods, the storage array provided in the embodiment of the present application has multiple storage modules U, and one storage module U is manufactured on the basis of a comb-shaped stacked structure 12, that is, one storage module U includes a multi-layer stacked storage unit 10, multiple first signal lines La (X direction), and multiple second signal lines Lb (Z direction). The specific manufacturing process can be referred to the previous text.

[0165] The layout of multiple storage modules U can be designed as needed, and this application does not impose any restrictions on this.

[0166] Schematically, in some possible implementation methods, referring to Figures 18 and 19, in the storage array, two adjacent storage modules U can be arranged relative to each other at the comb teeth or at the connection parts. This application does not impose any restrictions on this. In practice, the storage modules U can be arranged as needed.

[0167] It should be understood that the size of the serial numbers of the above processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0168] For other relevant contents in the above-mentioned manufacturing method, you can refer to the corresponding parts in the above-mentioned storage array structure embodiment, which will not be repeated here; for other setting structures in the above-mentioned storage array structure embodiment, you can refer to the above-mentioned manufacturing method and related manufacturing methods for adjustment, which will not be repeated here one by one.

[0169] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A storage array, characterized in that: include: substrate; A plurality of first signal lines and a plurality of second signal lines are arranged on the substrate; the first signal lines extend in a direction parallel to the substrate, and the second signal lines extend in a direction perpendicular to the substrate; A multi-layer memory cell vertically stacked on the substrate; the memory cell comprises a selector and a capacitor arranged in a direction parallel to the substrate, and the selector and the capacitor are coupled in series between the first signal line and the second signal line; The second signal line is coupled to a plurality of the memory cells that are stacked, and the first signal line is coupled to a plurality of the memory cells that are located in the same layer.

2. The storage array according to claim 1, characterized in that: The capacitor is a ferroelectric capacitor.

3. The storage array according to claim 1 or 2, characterized in that: Projections of multiple layers of the memory cells on the substrate overlap.

4. The storage array according to any one of claims 1 to 3, characterized in that: The storage unit comprises: a first metal line, a ferroelectric layer, a first metal layer, and a resistive switching layer stacked in sequence in a direction parallel to the substrate; The first end of the first metal line is connected to the second signal line, the second end of the first metal line is connected to the first signal line through the ferroelectric layer, the first metal layer, and the resistive switching layer which are arranged in sequence, and the first metal line and the first signal line are located in the same layer; The first metal line, the ferroelectric layer, and the first metal layer are used to form the capacitor; The first signal line, the resistive switching layer, and the first metal layer are used to form the selector.

5. The storage array according to claim 4, characterized in that: The storage array includes: holes, the depth direction of the holes is parallel to the substrate; The ferroelectric layer and the first metal layer cover the bottom and sidewall of the hole, and the first metal layer is located inside the ferroelectric layer; the first metal wire is filled inside the first metal layer.

6. The storage array according to claim 4 or 5, characterized in that: The storage array comprises: a groove, the depth direction of the groove is parallel to the substrate; The resistive switching layer covers the bottom and sidewalls of the trench, and the first signal line is filled inside the resistive switching layer.

7. The storage array according to any one of claims 1 to 6, characterized in that: The plurality of first signal lines connected to the stacked layers of the storage units are stacked in parallel and are manufactured by a same photolithography process.

8. The storage array according to any one of claims 1 to 7, characterized in that: A plurality of second signal lines connected to the stacked multi-layer storage units are arranged in parallel and are manufactured by the same photolithography process.

9. The storage array according to any one of claims 4 to 8, characterized in that: The first metal line, the ferroelectric layer, the first metal layer, and the resistive switching layer in the multi-layer storage unit are respectively manufactured by the same photolithography process.

10. The storage array according to any one of claims 4 to 9, characterized in that: The resistance change layer can be switched between a high resistance state and a low resistance state under the control of voltage applied by the first signal line and the second signal line.

11. The storage array according to any one of claims 4 to 10, characterized in that: The resistive layer includes at least one of silicon or silicon compounds, germanium or germanium compounds, metal oxides, materials with metal-insulator transition characteristics, mixed ion-electron conductor materials, perovskite-type composite oxides, solid electrolytes or organic polymers.

12. The storage array according to any one of claims 4 to 10, characterized in that: The resistive switching layer includes a PNP junction or an NPN junction.

13. The storage array according to any one of claims 4 to 12, characterized in that: The ferroelectric layer includes hafnium oxide-based ferroelectric material or AlN doped with Sc.

14. A method for manufacturing a storage array, characterized in that: include: Forming a stacked structure on a substrate; wherein the stacked structure includes a plurality of first insulating layers and a plurality of second insulating layers sequentially overlapped and arranged in a direction perpendicular to the substrate; Remove multiple first insulating layers in the stacked structure, make a first signal line, a selector, and a capacitor in the removed area of ​​each first insulating layer, and form a second signal line perpendicular to the substrate on the side of the stacked structure; wherein the selector and the capacitor are arranged in a direction parallel to the substrate and form a storage unit, and the selector and the capacitor are coupled in series between the first signal line and the second signal line, the second signal line is coupled to the multiple storage units stacked, and the first signal line is coupled to the multiple storage units arranged in the same layer.

15. The method for manufacturing a storage array according to claim 14, characterized in that: The forming of a stacked structure on a substrate comprises: A plurality of first insulating layers and a plurality of second insulating layers are sequentially overlapped on a substrate, and the plurality of first insulating layers and the plurality of second insulating layers are etched as a whole to form the stacked structure; wherein the stacked structure is comb-shaped, and each film layer in the stacked structure includes a connecting portion and a plurality of comb-tooth portions connected to the connecting portion; The method of removing a plurality of the first insulating layers in the stacked structure, manufacturing a first signal line, a selector, and a capacitor in a removed region of each of the first insulating layers, and forming a second signal line perpendicular to the substrate on a side of the stacked structure includes: The plurality of first insulating layers in the stacked structure are removed, a first signal line and a selector are fabricated in the removed area of ​​the connecting portion in the first insulating layer, the capacitors are fabricated in the removed areas of the plurality of comb-tooth portions in the first insulating layer respectively, and a second signal line perpendicular to the substrate is formed at the end of the comb-tooth portion.

16. The method for manufacturing a storage array according to claim 15, characterized in that: The method of removing a plurality of the first insulating layers in the stacked structure, manufacturing a first signal line and a selector in a region where the connecting portion is removed in the first insulating layer, manufacturing capacitors in regions where a plurality of the comb-tooth portions are removed in the first insulating layer, and forming a second signal line perpendicular to the substrate at an end of the comb-tooth portion comprises: Filling the gaps in the stacked structure with a first insulating material to form a filling structure; Removing the connection portions in the first insulating layer to form a plurality of grooves on the side of the filling structure; forming a resistive switching layer and the first signal line in the plurality of the grooves in sequence, and covering the side surface where the first signal line is located with a second insulating material; Removing a plurality of the comb-teeth portions in the first insulating layer to form a plurality of holes; A first metal layer, a ferroelectric layer, and a first metal line are sequentially formed in the plurality of holes, and a second signal line connected to the first metal line is formed on the opening side of the hole.

17. The method for manufacturing a storage array according to claim 16, wherein: The removing of the connecting portions in the first insulating layers to form a plurality of grooves on the side of the filling structure includes: On a side close to the connecting portion, etching downward from the top of the filling structure to the substrate to remove a portion of the connecting portion away from the comb-tooth portion; The remaining connection parts are removed from the side surfaces of the filling structure by etching to form a plurality of grooves.

18. The method for manufacturing a storage array according to claim 16 or 17, characterized in that: The step of sequentially forming a first metal layer, a ferroelectric layer, and a first metal line in the plurality of holes, and forming a second signal line connected to the first metal line on the opening side of the hole comprises: Depositing metal material in the plurality of holes to form a first metal layer; depositing a ferroelectric layer in the hole formed with the first metal layer; A metal material is deposited in the hole where the ferroelectric layer is formed, a first metal line is formed in the hole, a metal film is formed on the surface of the hole opening side, and the metal film is etched to form a plurality of the second signal lines.

19. The method for manufacturing a storage array according to any one of claims 16 to 18, characterized in that: The first insulating material and the second insulating material are both the same as the insulating material in the second insulating layer.

20. A storage device, characterized in that: A controller and a storage array as described in any one of claims 1 to 13, wherein the storage array is electrically connected to the controller.

21. An electronic device, characterized in that: A circuit board and a storage device as claimed in claim 20, wherein the storage device is electrically connected to the circuit board.

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