Topcon cell, and topcon cell preparation method

Abstract

A TOPCon cell and a TOPCon cell preparation method, which belong to the field of solar cells. The cell comprises a substrate, wherein a side surface of the substrate is provided with a laminated passivation film and an electrode, the laminated passivation film comprising a tunneling layer, a first doped polycrystalline silicon layer, a diffusion barrier layer and a second doped polycrystalline silicon layer, which are sequentially arranged in a direction facing away from the substrate; and the side surface of the substrate that faces the electrode has a metallized region and a non-metallized region, and the diffusion barrier layer corresponds to the non-metallized region for preventing doping elements in the second doped polycrystalline silicon layer from diffusing into the first doped polycrystalline silicon layer, such that the doping concentration of the first doped polycrystalline silicon layer in the non-metallized region is lower than the doping concentration of the first doped polycrystalline silicon layer in the metallized region. Two doped polycrystalline silicon layers are used, and a diffusion barrier layer is provided in a non-metallized region, such that the doping concentration of the inner doped polycrystalline silicon layer is reduced, thereby improving the passivation effect while ensuring an Auger recombination rate.

Description

A TOPCon battery and a method for preparing the same

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on November 28, 2023, with application number 202311606504.3 and invention name “A TOPCon battery and a method for preparing a TOPCon battery”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of solar cells, and in particular to a TOPCon cell and a method for preparing the TOPCon cell. Background Art

[0003] In the current industrial production of crystalline silicon TOPCon (Tunnel Oxide Passivated Contact) cell technology, a stacked passivation structure consisting of a tunnel oxide layer and doped polysilicon is typically fabricated on the front, back, or both sides of the TOPCon cell. The doped polysilicon is deposited using chemical vapor deposition (CVD) onto the surface of the tunnel oxide layer of the crystalline silicon cell. This is then converted to a microcrystalline or polycrystalline silicon thin film through a high-temperature treatment.

[0004] To match the currently mature metallization paste printing technology, screen printing paste technology is typically used to form an ohmic contact with a passivating effect between the polysilicon thin film layer and the electrode. First, to ensure good ohmic contact between the electrode and the polysilicon thin film layer, the polysilicon thin film layer is typically doped with a high concentration. To minimize the Auger recombination rate caused by the high doping concentration in the polysilicon thin film layer, the thickness of the polysilicon thin film layer is typically minimized. However, reducing the thickness of the polysilicon thin film layer reduces the passivation effect of the polysilicon thin film layer. Second, due to the corrosive properties of current metallization pastes, especially the highly corrosive glass phase in aluminum paste, it can penetrate the polysilicon thin film layer during the subsequent high-temperature sintering process. Current polysilicon thin film layer thicknesses are typically controlled within a range greater than 120 nm. It is necessary to find the optimal balance between reducing the Auger recombination rate of the doped polysilicon thin film layer and improving the passivation effect. Therefore, how to reduce the Auger recombination rate while improving the passivation effect is a technical problem currently needed by those skilled in the art.

[0005] Summary of the Invention

[0006] The purpose of this application is to provide a TOPCon battery and a method for preparing a TOPCon battery, which can reduce the Auger recombination rate and improve the passivation effect, thereby improving the conversion efficiency of the battery.

[0007] To achieve the above-mentioned object, the present application provides a TOPCon battery, comprising: a substrate; a laminated passivation film and an electrode are provided on one side surface of the substrate;

[0008] The stacked passivation film comprises a tunneling layer, a first doped polysilicon layer, a diffusion barrier layer, and a second doped polysilicon layer, which are sequentially arranged in a direction away from the substrate;

[0009] The surface of the substrate on one side facing the electrode has a metallized area and a non-metallized area. The diffusion barrier layer corresponds to the non-metallized area and is used to prevent the doping elements in the second doped polysilicon layer from diffusing into the first doped polysilicon layer, so that the doping concentration of the first doped polysilicon layer in the non-metallized area is lower than the doping concentration of the first doped polysilicon layer in the metallized area.

[0010] Optionally, the diffusion barrier layer is a silicon oxide layer.

[0011] Optionally, the stacked passivation film is arranged on the back side of the substrate, the first doped polysilicon layer, the second doped polysilicon layer and the substrate use the same type of doping elements, the overall doping concentration of the first doped polysilicon layer is greater than the overall doping concentration of the substrate, and the overall doping concentration of the second doped polysilicon layer is higher than the overall doping concentration of the first doped polysilicon layer.

[0012] Optionally, a back passivation layer is provided on the surface of the laminated passivation film on the side facing away from the substrate, and the electrode passes through the back passivation layer and contacts the laminated passivation film; the back passivation layer comprises SiN x Film, SiO x N y Film, Al2O3 / SiN x Multilayer film, SiO x N y / SiN x At least one of the laminated films.

[0013] Optionally, the thickness of the first doped polysilicon layer is 20 nm to 40 nm, inclusive;

[0014] The thickness of the second doped polysilicon layer from the surface facing away from the substrate to the surface of the diffusion barrier layer facing away from the substrate is 20 nm-200 nm, including both ends.

[0015] Optionally, the overall doping concentration of the first doped polysilicon layer is 1E19cm -3 -3E20cm -3 , and include the values ​​at both ends;

[0016] The overall doping concentration of the second doped polysilicon layer is 5E20cm -3 -1E21cm -3 , including the values ​​at both ends.

[0017] To achieve the above objectives, the present application also provides a method for preparing a TOPCon battery, comprising:

[0018] A stacked passivation film layer is prepared on one side surface of a substrate; the stacked passivation film includes a tunneling layer, a first doped polysilicon layer, a diffusion barrier layer, and a second doped polysilicon layer, which are arranged in sequence along a direction away from the substrate; the surface of the substrate on one side corresponding to the stacked passivation film layer has a metallized area and a non-metallized area, and the diffusion barrier layer corresponds to the non-metallized area and is used to prevent the doping elements in the second doped polysilicon layer from diffusing into the first doped polysilicon layer, so that the doping concentration of the first doped polysilicon layer in the non-metallized area is lower than the doping concentration of the first doped polysilicon layer in the metallized area.

[0019] Optionally, the step of preparing a laminated passivation film layer on the surface of the substrate includes:

[0020] Depositing the tunneling layer on the surface of the substrate;

[0021] depositing a first intrinsic amorphous silicon layer on the surface of the tunneling layer;

[0022] preparing the diffusion barrier layer on the surface of the first intrinsic amorphous silicon layer corresponding to the non-metallized area;

[0023] Depositing a second intrinsic amorphous silicon layer on a surface of the first intrinsic amorphous silicon layer corresponding to the metallization region and a surface of the diffusion barrier layer;

[0024] Doping elements are diffused, and the doping elements are sequentially diffused into the second intrinsic amorphous silicon layer and the first intrinsic amorphous silicon layer in the metallized area, and the doping elements are sequentially diffused into the second intrinsic amorphous silicon layer, the diffusion barrier layer and the first intrinsic amorphous silicon layer in the non-metallized area, so that the second intrinsic amorphous silicon layer becomes the second doped polycrystalline silicon layer, and the first intrinsic amorphous silicon layer becomes the first doped polycrystalline silicon layer.

[0025] Optionally, after depositing the first intrinsic amorphous silicon layer on the surface of the tunneling layer, the method further comprises:

[0026] The first intrinsic amorphous silicon layer is lightly doped.

[0027] Optionally, the step of preparing a laminated passivation film layer on the surface of the substrate includes:

[0028] Depositing the tunneling layer on the surface of the substrate;

[0029] Depositing the first doped polysilicon layer on the surface of the tunneling layer by in-situ doping;

[0030] preparing the diffusion barrier layer on the surface of the first doped polysilicon layer corresponding to the non-metallized area;

[0031] Depositing the second doped polysilicon layer on the surface of the first doped polysilicon layer corresponding to the metallization region and the surface of the diffusion barrier layer;

[0032] Annealing is performed on the first doped polysilicon layer and the second doped polysilicon layer.

[0033] Obviously, the TOPCon cell provided by the present application adopts a double-layer doped polysilicon layer. While ensuring that the thickness of the inner doped polysilicon layer can achieve a good passivation effect, a diffusion barrier layer is added between the two doped polysilicon layers. The diffusion barrier layer corresponds to the non-metallized area and blocks the doping elements of the outer doped polysilicon layer, so that the doping concentration of the inner doped polysilicon layer is high in the metallized area and low in the non-metallized area, thereby reducing the overall doping concentration of the inner doped polysilicon layer and further reducing the Auger recombination rate; the concentration of the outer doped polysilicon layer is higher than that of the inner doped polysilicon layer, and the doping concentration of the inner doped polysilicon layer is high in the metallized area, which can ensure good ohmic contact. The present application also provides a preparation method for a TOPCon cell. The TOPCon cell prepared by the preparation method has the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0035] FIG1 is a structural diagram of a TOPCon battery provided in an embodiment of the present application;

[0036] FIG2 is a structural diagram of a laminated passivation film in a metallized region provided in an embodiment of the present application;

[0037] FIG3 is a structural diagram of a laminated passivation film in a non-metallized region provided in an embodiment of the present application;

[0038] FIG4 is a flow chart of a method for preparing a TOPCon battery provided in an embodiment of the present application;

[0039] FIG5 is a structural diagram of a TOPCon battery after texturing provided in an embodiment of the present application;

[0040] FIG6 is a structural diagram of a TOPCon cell after boron diffusion provided in an embodiment of the present application;

[0041] FIG7 is a partial enlarged view of a TOPCon cell after boron diffusion provided in an embodiment of the present application;

[0042] FIG8 is a structural diagram of a TOPCon battery after removing BSG according to an embodiment of the present application;

[0043] FIG9 is a structural diagram of a polished TOPCon battery provided in an embodiment of the present application;

[0044] FIG10 is a structural diagram of a patterned TOPCon battery provided in an embodiment of the present application;

[0045] FIG11 is a structural diagram of a TOPCon cell after forming a laminated passivation film according to an embodiment of the present application;

[0046] FIG12 is a structural diagram of a TOPCon cell after phosphorus diffusion provided in an embodiment of the present application;

[0047] FIG13 is a graph showing the variation of doping concentration with thickness according to an embodiment of the present application;

[0048] FIG14 is a structural diagram of a TOPCon cell after forming a front passivation film and a back passivation film according to an embodiment of the present application.

[0049] The reference numerals in the figures are as follows: 1-substrate / crystalline silicon substrate; 1a-first surface; 1b-second surface; 11a-doped layer / P-type doped layer; 11a′-BSG layer; 13-stacked passivation film; 131-tunneling silicon oxide layer; 132-first doped polysilicon layer / first intrinsic amorphous silicon layer; 1321-first high-passivation silicon-containing layer; 1322-first low-passivation silicon-containing layer; 133-diffusion barrier layer; 134-second doped polysilicon layer / second intrinsic amorphous silicon layer; 14-PSG layer; 151-back passivation layer; 152-front passivation layer; 161-back electrode; 162-front electrode. DETAILED DESCRIPTION

[0050] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0051] The embodiment of the present application provides a TOPCon battery, which may include: a substrate; a laminated passivation film and an electrode provided on one side surface of the substrate;

[0052] The stacked passivation film comprises a tunneling layer, a first doped polysilicon layer, a diffusion barrier layer and a second doped polysilicon layer which are sequentially arranged in a direction away from the substrate;

[0053] The surface of the substrate facing the electrode has a metallized area and a non-metallized area. The diffusion barrier layer corresponds to the non-metallized area and is used to prevent the doping elements in the second doped polysilicon layer from diffusing into the first doped polysilicon layer, so that the doping concentration of the first doped polysilicon layer in the non-metallized area is lower than the doping concentration of the first doped polysilicon layer in the metallized area.

[0054] This embodiment does not limit the specific type of substrate, and the specific type of substrate can be determined according to actual conditions. For example, the substrate can be a crystalline silicon substrate. This embodiment does not limit the specific type of substrate. For example, the substrate can be an N-type substrate; it can also be a P-type substrate. In this embodiment, the first doped polysilicon layer, the second doped polysilicon layer, and the substrate use the same type of doping elements. This embodiment does not limit the specific type of doping elements. For example, the doping element can be B (boron), P (phosphorus), or Ga (gallium). It should be noted that the corresponding doping element needs to be selected according to the specific type of substrate.

[0055] It should be noted that, in this embodiment, the laminated passivation film can be provided on the front and / or back of the substrate, that is, the front of the substrate may be provided with a laminated passivation film and a front electrode in sequence, and / or the back of the substrate may be provided with a laminated passivation film and a back electrode in sequence. When the front of the substrate is provided with a laminated passivation film and a front electrode in sequence, this embodiment does not limit the specific structure of the back of the substrate. When the back of the substrate is provided with a laminated passivation film and a back electrode in sequence, this embodiment does not limit the specific structure of the front of the substrate. For example, the front of the substrate may be provided with a doping layer and a front electrode in sequence. This embodiment does not limit the specific type of the doping layer, and the specific type of the doping layer may be determined according to the specific type of the substrate. For example, when the substrate is an N-type substrate, the doping layer may be a P-type doping layer.

[0056] This embodiment does not limit the specific type of tunneling layer, as long as it can form chemical passivation on the surface of the substrate. For example, the tunneling layer can be a tunneling silicon oxide layer. It should be noted that the tunneling silicon oxide layer can be prepared by high-temperature thermal oxidation of silicon atoms on the surface of a crystalline silicon substrate. Its function is to provide full-surface chemical passivation for the crystalline silicon substrate and to provide tunneling and / or perforation channels for the transport of photogenerated carriers generated in the crystalline silicon substrate to the electrodes. The thickness of the layer does not exceed 2 nm.

[0057] It should be noted that the amorphous silicon in the first doped polysilicon layer further enhances the chemical passivation effect of the tunneling silicon oxide layer. Furthermore, the amorphous silicon material itself has a much wider bandgap than the crystalline silicon substrate (1.12 eV). When doped with Group 3 and 5 elements (including B, P, and Ga), it provides partial field passivation for the transport of photogenerated carriers in the crystalline silicon. Furthermore, doping with Group 3 and 5 elements reduces the resistivity of the first doped polysilicon layer, thereby providing a conductive path for the transport of photogenerated carriers generated by the crystalline silicon substrate.

[0058] This embodiment does not limit the specific thickness of the first doped polysilicon layer. For example, the thickness of the first doped polysilicon layer 132 may be 20 nm-40 nm, including both ends.

[0059] It should be noted that, since a single thin tunneling layer is insufficient to provide optimal passivation for crystalline silicon cells, the addition of a first doped polysilicon layer can further enhance the passivation effect. However, if the thickness of the first doped polysilicon layer is too great, it will inevitably introduce too many foreign dopant atoms due to elemental doping, and thus too many recombination centers, which is not conducive to reducing the Auger recombination rate of the first doped polysilicon layer. If the thickness of the first doped polysilicon layer is too small, the passivation effect cannot be fully exerted.

[0060] This embodiment does not limit the specific overall doping concentration of the first doped polysilicon layer. For example, the overall doping concentration of the first doped polysilicon layer can be greater than the overall doping concentration of the substrate; can be less than the overall doping concentration of the substrate 1; or can be equal to the overall doping concentration of the substrate. It should be noted that when the overall doping concentration of the first doped polysilicon layer is greater than the overall doping concentration of the substrate, a surface field passivation effect can be established between the substrate and the first doped polysilicon layer, thereby accelerating the selective absorption of electrons or holes in photogenerated carriers.

[0061] In this embodiment, the diffusion barrier layer is adjacent to the first doped polysilicon layer corresponding to the metallization region and is used to prevent the dopant elements in the second doped polysilicon layer from diffusing into the first doped polysilicon layer. This embodiment does not limit the specific type of the diffusion barrier layer, as long as it can prevent the dopant elements from diffusing into the first doped polysilicon layer. For example, the diffusion barrier layer can be a silicon oxide layer. The silicon oxide layer can be composed of silicon dioxide deposited by CVD (Chemical Vapor Deposition). Specifically, it can be prepared by introducing oxygen or a carrier gas containing oxygen into the CVD deposition chamber and using oxygen to react with intrinsic amorphous silicon to produce an oxidation reaction.

[0062] It should be noted that during the preparation process of the TOPCon battery in this embodiment, when the intrinsic amorphous silicon is subsequently atomically doped to prepare the doped polysilicon layer, the denser crystal structure of silicon dioxide than that of intrinsic amorphous silicon is utilized to provide a good interface barrier layer for the atomic doping of intrinsic amorphous silicon, thereby slowing down the diffusion movement of doped atoms in the silicon dioxide layer serving as a diffusion barrier layer.

[0063] It should be noted that the second doped polysilicon layer is located on the surface of the diffusion barrier layer, away from the substrate. Deposited from intrinsic amorphous silicon by CVD, it is doped with dopant atoms and subjected to high-temperature crystallization. This layer provides full-surface chemical and field passivation for the crystalline silicon substrate. Furthermore, the high concentration of doping with Group 3 and 5 elements in the second doped polysilicon layer significantly enhances its electrical conductivity, providing a conductive path for the transport of photogenerated carriers from the crystalline silicon substrate.

[0064] It should be noted that, since the doping elements in the non-metallized area need to diffuse through the diffusion barrier layer to the first doped polysilicon layer, the overall doping concentration of the second doped polysilicon layer is higher than the overall doping concentration of the first doped polysilicon layer. This embodiment does not limit the specific value of the overall doping concentration of the first doped polysilicon layer or the second doped polysilicon layer. For example, the overall doping concentration of the first doped polysilicon layer can be 1E19cm -3 -3E20 cm -3 , and including the values ​​at both ends; the overall doping concentration of the second doped polysilicon layer can be 5E20cm -3 -1E21cm -3 , including the values ​​at both ends.

[0065] This embodiment does not limit the specific thickness of the second doped polysilicon layer. For example, the thickness from the surface of the second doped polysilicon layer facing away from the substrate to the surface of the diffusion barrier layer facing away from the substrate may be 20 nm-200 nm, including both ends.

[0066] It should be noted that the provision of a second doped polysilicon layer in this embodiment provides sufficient corrosion penetration thickness for the corrosive glass phase in the metallization paste, ensuring that the metal electrode material obtained after sintering the metallization paste during electrode printing does not burn through the tunneling layer. Specifically, the contact interface formed by the sintered metal electrode material under the corrosion of the glass phase in the metallization paste can be located in: the second doped polysilicon layer, the diffusion barrier layer, or the first doped polysilicon layer. As shown in Figure 1, when the electrode forms an ohmic contact with the first doped polysilicon layer, the differentiated doping concentrations of the doping elements in the first doped polysilicon layer enable the electrode to form a good ohmic contact with the first doped polysilicon layer with a higher doping concentration of the doping elements. The corresponding non-metallized region in the first doped polysilicon layer has a better passivation effect due to the lower phosphorus atom doping concentration, thereby improving the conversion efficiency of the battery. When the electrode forms an ohmic contact with the second doped polysilicon layer, electrons tend to transmit along the path of the second doped polysilicon layer with better conductivity, which can reduce the electron transmission resistance loss. In addition, the differentiated doping concentration formed by the doping elements in the first doped polysilicon layer is beneficial to reducing the doping concentration of the doping elements therein while ensuring the passivation effect of the first polysilicon layer, thereby reducing the Auger recombination rate caused by atomic doping, thereby improving the conversion efficiency of the battery.

[0067] When the laminated passivation film is disposed on the back side of the substrate, further, in order to enhance the passivation effect, in this embodiment, a back passivation layer may be disposed on the surface of the laminated passivation film on the side facing away from the substrate, and the electrode passes through the back passivation layer and contacts the laminated passivation film. This embodiment does not limit the specific type of the back passivation layer. For example, the back passivation layer may include SiN x Film, SiO x N y Film, Al2O3 / SiN x Multilayer film, SiO x N y / SiN x At least one of the laminated films.

[0068] Based on the above embodiments, the present application adopts a double-layer doped polysilicon layer, which can avoid penetration of the doped polysilicon layer during the printed electrode sintering process; while ensuring that the thickness of the inner doped polysilicon layer can achieve a good passivation effect, a diffusion barrier layer is added between the two doped polysilicon layers. The diffusion barrier layer corresponds to the non-metallized area and blocks the doping elements of the outer doped polysilicon layer, so that the doping concentration of the inner doped polysilicon layer is high in the metallized area and low in the non-metallized area, thereby reducing the Auger recombination rate; the concentration of the outer doped polysilicon layer is higher than the doping concentration of the inner doped polysilicon layer, and the doping concentration of the inner doped polysilicon layer is high in the metallized area, which can ensure good ohmic contact.

[0069] Please refer to FIG1 , which is a structural diagram of a TOPCon cell provided in an embodiment of the present application. The TOPCon cell may include: a substrate 1; a front surface of the substrate 1 is provided with a doping layer 11a, a front passivation layer 152, and a front electrode 162 in sequence; a back surface of the substrate 1 is provided with a laminated passivation film 13, a back surface passivation layer 151, and a back surface electrode 161 in sequence;

[0070] The stacked passivation film 13 includes a tunneling silicon oxide layer 131, a first doped polysilicon layer 132, a diffusion barrier layer 133, and a second doped polysilicon layer 134, which are sequentially arranged in a direction away from the substrate 1.

[0071] The surface of the substrate 1 facing the back electrode 161 has a metallized region and a non-metallized region. The diffusion barrier layer 133 corresponds to the non-metallized region and is used to prevent the dopant elements in the second doped polysilicon layer 134 from diffusing into the first doped polysilicon layer 132, so that the doping concentration of the first doped polysilicon layer 132 in the non-metallized region is lower than the doping concentration of the first doped polysilicon layer 132 in the metallized region.

[0072] The back electrode 161 is located on the first doped polysilicon layer 132 close to the surface of the substrate 1 , so that the back electrode 161 forms an ohmic contact with the first doped polysilicon layer 132 .

[0073] It should be noted that, along the longitudinal direction of the substrate 1, as shown in FIG2 , the metallized region includes, from the inside out, a tunneling silicon oxide layer 131, a first doped polysilicon layer 132, and a second doped polysilicon layer 134. As shown in FIG3 , the non-metallized region includes, from the inside out, a tunneling silicon oxide layer 131, a first doped polysilicon layer 132, a diffusion barrier layer 133, and a second doped polysilicon layer 134. The diffusion barrier layer 133 corresponds to the non-metallized region. When the stacked passivation film 13 is doped, the diffusion barrier layer 133 blocks the doping elements, thereby forming a first doped polysilicon layer 132 with a lower doping concentration in the non-metallized region. In contrast, the first doped polysilicon layer 132 corresponding to the metallized region has a relatively higher doping concentration due to the absence of the diffusion barrier layer 133 to block the diffusion of the doping elements, thereby forming a differential doping concentration in the first doped polysilicon layer 132.

[0074] Based on the above embodiments, the present application adopts a double-layer doped polysilicon layer. While ensuring that the thickness of the inner doped polysilicon layer can achieve a good passivation effect, a diffusion barrier layer 133 is added between the two doped polysilicon layers. The diffusion barrier layer 133 corresponds to the non-metallized area and plays a blocking role on the doping elements of the outer doped polysilicon layer, so that the doping concentration of the inner doped polysilicon layer is high in the metallized area and low in the non-metallized area, thereby reducing the overall doping concentration of the inner doped polysilicon layer, and then reducing the Auger recombination rate; through the front passivation layer 152 and the back passivation layer 151, the effect of the stacked passivation film 13 is superimposed to further enhance the passivation effect.

[0075] The present application also provides a method for preparing a TOPCon battery, which may include:

[0076] A stacked passivation film layer is prepared on one side surface of a substrate; the stacked passivation film includes a tunneling layer, a first doped polysilicon layer, a diffusion barrier layer, and a second doped polysilicon layer, which are sequentially arranged in a direction away from the substrate; a surface of the substrate corresponding to the side of the stacked passivation film layer has a metallized region and a non-metallized region, and the diffusion barrier layer corresponds to the non-metallized region and is used to prevent doping elements in the second doped polysilicon layer from diffusing into the first doped polysilicon layer, so that the doping concentration of the first doped polysilicon layer in the non-metallized region is lower than the doping concentration of the first doped polysilicon layer in the metallized region.

[0077] This embodiment does not limit the specific method of preparing the laminated passivation film, as long as it can be ensured that the laminated passivation film can be formed on the surface of the substrate. For example, the following two methods can be used:

[0078] (1) depositing a tunneling layer on the surface of the substrate; depositing a first intrinsic amorphous silicon layer on the surface of the tunneling layer; preparing a diffusion barrier layer on the surface of the first intrinsic amorphous silicon layer corresponding to the non-metallized region; depositing a second intrinsic amorphous silicon layer on the surface of the first intrinsic amorphous silicon layer corresponding to the metallized region and on the surface of the diffusion barrier layer; performing doping element diffusion, diffusing the doping elements into the second intrinsic amorphous silicon layer and the first intrinsic amorphous silicon layer in the metallized region in sequence, and diffusing the doping elements into the second intrinsic amorphous silicon layer, the diffusion barrier layer and the first intrinsic amorphous silicon layer in the non-metallized region in sequence, so that the second intrinsic amorphous silicon layer becomes a second doped polycrystalline silicon layer, and the first intrinsic amorphous silicon layer becomes a first doped polycrystalline silicon layer.

[0079] Furthermore, in order to avoid the doping concentration of the first doped polysilicon layer being too low, in this embodiment, after depositing the first intrinsic amorphous silicon layer on the surface of the tunneling layer, the first intrinsic amorphous silicon layer can be lightly doped to adjust the carrier transport performance of the first doped polysilicon layer.

[0080] (2) depositing a tunneling layer on the surface of the substrate; depositing a first doped polysilicon layer on the surface of the tunneling layer by in-situ doping; preparing a diffusion barrier layer on the surface of the first doped polysilicon layer corresponding to the non-metallized area; depositing a second doped polysilicon layer on the surface of the first doped polysilicon layer corresponding to the metallized area and on the surface of the diffusion barrier layer; and annealing the first doped polysilicon layer and the second doped polysilicon layer.

[0081] It should be noted that in method (1), the first doped polysilicon layer and the second doped polysilicon layer are prepared by impurity diffusion; in method (2), the first doped polysilicon layer and the second doped polysilicon layer are prepared by in-situ doping and annealing.

[0082] It should be noted that in this embodiment, the laminated passivation film can be provided on the front and / or back of the substrate, that is, the front of the substrate may be provided with a laminated passivation film and a front electrode in sequence, and / or the back of the substrate may be provided with a laminated passivation film and a back electrode in sequence. When the front of the substrate is provided with a laminated passivation film and a front electrode in sequence, this embodiment does not limit the specific structure of the back of the substrate. When the back of the substrate is provided with a laminated passivation film and a back electrode in sequence, this embodiment does not limit the specific structure of the front of the substrate. For example, the front of the substrate may be provided with a doped layer and a front electrode in sequence.

[0083] When a laminated passivation film and a back electrode are sequentially provided on the back side of the substrate, and a doping layer and a front electrode are sequentially provided on the front side of the substrate, the preparation method of this embodiment may include:

[0084] preparing a doped layer on the front side of the substrate;

[0085] After the doping layer is prepared, a laminated passivation film layer is prepared on the back side of the substrate; the laminated passivation film includes a tunneling layer, a first doped polysilicon layer, a diffusion barrier layer, and a second doped polysilicon layer, which are sequentially arranged in a direction away from the substrate; a surface of the substrate corresponding to the laminated passivation film layer has a metallized region and a non-metallized region, and the diffusion barrier layer corresponds to the non-metallized region and is used to prevent doping elements in the second doped polysilicon layer from diffusing into the first doped polysilicon layer, so that the doping concentration of the first doped polysilicon layer in the non-metallized region is lower than the doping concentration of the first doped polysilicon layer in the metallized region;

[0086] The back electrode is printed on the surface of the laminated passivation film facing away from the substrate, and the front electrode is printed on the surface of the doping layer facing away from the substrate to prepare a TOPCon battery.

[0087] Based on the above embodiments, the TOPCon battery prepared in the present application adopts a double-layer doped polysilicon layer. While ensuring that the thickness of the inner doped polysilicon layer can achieve a good passivation effect, a diffusion barrier layer is added between the two doped polysilicon layers. The diffusion barrier layer corresponds to the non-metallized area and blocks the doping elements of the outer doped polysilicon layer, so that the doping concentration of the inner doped polysilicon layer is high in the metallized area and low in the non-metallized area, thereby reducing the overall doping concentration of the inner doped polysilicon layer and further reducing the Auger recombination rate; the concentration of the outer doped polysilicon layer is higher than the doping concentration of the inner doped polysilicon layer, and the doping concentration of the inner doped polysilicon layer is high in the metallized area, which can ensure good ohmic contact.

[0088] Please refer to FIG4 , which is a flow chart of a method for preparing a TOPCon battery provided in an embodiment of the present application. The method may include:

[0089] S101: preparing a doping layer on the front side of the substrate.

[0090] This embodiment does not limit the specific method of preparing the doping layer. The specific method of preparing the doping layer can be determined according to the specific type of the doping layer. For example, when the doping layer is a P-type doping layer, boron diffusion can be performed on the substrate to prepare the doping layer on the front side of the substrate. It should be noted that a BSG (BoroSilicate Glass) layer may be formed on both sides of the substrate during the diffusion process. Furthermore, in this embodiment, the BSG layer on the back side of the substrate can also be removed after step S101. This embodiment does not limit the specific method of removing the BSG layer, as long as it is ensured that the BSG layer can be removed. For example, a chain cleaning method can be used to remove the BSG layer on the front and back sides of the substrate.

[0091] Furthermore, in order to improve the light trapping effect of the substrate, the present embodiment may further perform double-sided alkali texturing on the substrate before step S101 to obtain a substrate having a pyramid textured surface structure. It should be noted that after the double-sided alkali texturing is performed on the substrate, the back side of the substrate needs to be polished after the front side doping layer of the substrate is prepared to obtain a relatively flat back side.

[0092] S102: After the doping layer is prepared, a tunneling layer is deposited on the back side of the substrate.

[0093] This embodiment does not limit the specific method of depositing the tunneling layer. The specific method of depositing the tunneling layer can be determined according to the specific type of the tunneling layer. For example, when the tunneling layer is a tunneling silicon oxide layer, oxygen or a carrier gas containing oxygen (including but not limited to nitrogen or argon, helium and other inert gases) can be introduced into the CVD deposition chamber to obtain a tunneling silicon oxide layer through a thermal oxidation reaction between oxygen and silicon atoms on the back side of the crystalline silicon.

[0094] S103: depositing a first intrinsic amorphous silicon layer on the surface of the tunneling layer.

[0095] This embodiment does not limit the specific method of depositing the first intrinsic amorphous silicon layer. For example, a mixture of silicon source gas and / or carrier gas carrying silicon source gas may be introduced into the CVD deposition chamber, and the first intrinsic amorphous silicon layer may be obtained by depositing the silicon source gas on the surface of the tunneling layer under high temperature conditions.

[0096] S104: preparing a diffusion barrier layer on the surface of the first intrinsic amorphous silicon layer corresponding to the non-metallized area.

[0097] This embodiment does not limit the specific method of preparing the diffusion barrier layer. For example, oxygen or a carrier gas containing oxygen may be introduced into the CVD deposition chamber, and the oxygen reacts with the first intrinsic amorphous silicon to form the diffusion barrier layer.

[0098] It should be noted that oxygen directly contacts the silicon atoms in the first intrinsic amorphous silicon layer to oxidize and produce silicon oxide Si x O y Therefore, compared with the tunneling silicon oxide layer prepared by thermal oxidation of the crystalline silicon substrate, the silicon oxide Si prepared by oxidation of the first intrinsic amorphous silicon layer x O y The Si-O crystal structure is also relatively loose, which can provide an appropriate barrier for the subsequent diffusion of doping elements.

[0099] Given that the metallized and non-metallized regions have different requirements for the concentration of doping elements, if the patterning distribution is performed when the diffusion barrier layer is formed, the non-metallized region has a diffusion barrier layer to block the non-metallized region, while the non-metallized region does not. This means that the non-metallized and metallized regions have different doping concentrations. After the diffusion barrier layer is obtained by CVD deposition, the diffusion barrier layer is patterned to form a diffusion barrier layer on the surface corresponding to the first intrinsic amorphous silicon layer and the non-metallized region. The patterning steps are as follows:

[0100] A diffusion barrier layer is formed on the back side of the substrate; after the diffusion barrier layer is formed, a patterned mask corresponding to the non-metallized area is formed on the back side of the substrate; after the patterned mask is formed, the substrate is placed in an acid solution or an alkaline solution to remove the diffusion barrier layer from the area not covered by the patterned mask by etching; after the diffusion barrier layer is removed, the patterned mask is cleaned and removed. This embodiment does not limit the specific method of forming the patterned mask; for example, a patterned mask corresponding to the non-metallized area can be formed on the back side of the substrate by screen printing, laser transfer, or photolithography. When screen printing is used, this embodiment can form a patterned mask corresponding to the non-metallized area on the back side of the substrate by printing a slurry resistant to HF (hydrofluoric acid) corrosion or using an acid and alkali resistant wax.

[0101] S105 : Depositing a second intrinsic amorphous silicon layer on the surface of the first intrinsic amorphous silicon layer corresponding to the metallization region and on the surface of the diffusion barrier layer.

[0102] This embodiment does not limit the specific method of depositing the second intrinsic amorphous silicon layer. For example, a mixture of silicon source gas and / or carrier gas carrying silicon source gas may be introduced into a CVD deposition chamber, and the second intrinsic amorphous silicon layer may be obtained by depositing the silicon source gas on the surface of the first intrinsic amorphous silicon layer corresponding to the metallization area and the surface of the diffusion barrier layer under high temperature conditions.

[0103] S106: Perform doping element diffusion, diffuse the doping elements into the second intrinsic amorphous silicon layer and the first intrinsic amorphous silicon layer in the metallized area in sequence, and diffuse the doping elements into the second intrinsic amorphous silicon layer, the diffusion barrier layer and the first intrinsic amorphous silicon layer in the non-metallized area in sequence, so that the second intrinsic amorphous silicon layer becomes the second doped polycrystalline silicon layer, and the first intrinsic amorphous silicon layer becomes the first doped polycrystalline silicon layer.

[0104] This embodiment does not limit the specific method of diffusing the doping elements, as long as it can ensure that the doping elements can diffuse toward the substrate and diffuse into the second intrinsic amorphous silicon layer, the diffusion barrier layer and the first intrinsic amorphous silicon layer in sequence. For example, the doping element gas source and oxygen can be introduced into the CVD deposition chamber.

[0105] It should be noted that during the diffusion process, a PSG (PhosphoSilicate Glass) layer may be formed on the front edge of the substrate 1. Furthermore, in this embodiment, the PSG layer formed on the front edge of the substrate may be removed after step S106.

[0106] Furthermore, in order to enhance the passivation effect, in this embodiment, after step S106 , a front passivation layer may be deposited on the front surface of the substrate 1 ; and a back passivation layer may be printed on the back surface of the substrate 1 .

[0107] S107: Printing a back electrode on the surface of the laminated passivation film facing away from the substrate, and printing a front electrode on the surface of the doping layer facing away from the substrate, to prepare a TOPCon battery.

[0108] It should be noted that the front electrode or the back electrode is usually formed by printing a metallization paste.

[0109] Based on the above embodiments, the TOPCon battery prepared in the present application adopts a double-layer doped polysilicon layer. While ensuring that the thickness of the inner doped polysilicon layer can achieve a good passivation effect, a diffusion barrier layer is added between the two doped polysilicon layers. The diffusion barrier layer corresponds to the non-metallized area and blocks the doping elements of the outer doped polysilicon layer, so that the doping concentration of the inner doped polysilicon layer is high in the metallized area and low in the non-metallized area, thereby reducing the overall doping concentration of the inner doped polysilicon layer and further reducing the Auger recombination rate; the concentration of the outer doped polysilicon layer is higher than the doping concentration of the inner doped polysilicon layer, and the doping concentration of the inner doped polysilicon layer is high in the metallized area, which can ensure good ohmic contact.

[0110] The following describes the preparation process of the TOPCon cell with reference to a specific example. Please refer to Figures 5 to 14. In this embodiment, the substrate 1 is an N-type crystalline silicon substrate 1. The process is as follows:

[0111] Step 1: preparing a single-sided crystalline silicon substrate 1 with a polished surface;

[0112] 1. Referring to FIG5 , a crystalline silicon substrate 1 is subjected to double-sided alkali texturing to obtain a crystalline silicon substrate 1 having a pyramid texturing structure, wherein the light-facing surface of the crystalline silicon substrate 1 corresponds to a first surface 1 a , and the backlight-facing surface corresponds to a second surface 1 b ;

[0113] 2. Referring to FIG. 6 and FIG. 7 , boron diffusion is performed on the crystalline silicon substrate 1 having the pyramid texture structure to prepare a PN junction. A P-type doped layer 11 a (for forming a PN junction) and a BSG layer 11 a′ are formed on the first surface 1 a of the crystalline silicon substrate 1 . Similarly, a P-type doped layer and a BSG layer are also formed on the second surface 1 b of the crystalline silicon substrate 1 .

[0114] 3. Referring to FIG. 8 , the BSG layer on the second surface 1 b of the crystalline silicon substrate 1 is removed by a chain cleaning method;

[0115] 4. Referring to FIG. 9 , the second surface 1 b of the crystalline silicon substrate 1 is polished using a chain cleaning method to obtain a relatively flat second surface 1 b ;

[0116] Step 2: preparing a laminated passivation film 13 on the second surface 1b of the crystalline silicon substrate 1;

[0117] The silicon wafer is placed in a CVD deposition chamber to deposit a laminated passivation film 13;

[0118] In the first stage, oxygen or a carrier gas containing oxygen (including but not limited to nitrogen or an inert gas such as argon or helium) is introduced into the CVD deposition chamber, and a tunneling silicon oxide layer 131 is formed by a thermal oxidation reaction between the oxygen and silicon atoms on the back side of the crystalline silicon substrate 1.

[0119] In the second stage, a silicon source gas and / or a mixture of a carrier gas and a silicon source gas are introduced into the CVD deposition chamber, and the silicon source gas is deposited on the surface of the tunneling silicon oxide layer 131 under high temperature conditions to form a first intrinsic amorphous silicon layer 132. The first intrinsic amorphous silicon layer 132 has a first thickness W1 of 20 nm to 40 nm (inclusive). A doped polysilicon layer having a minimum thickness of 20 nm and a tunneling silicon oxide layer 131 having a thickness of approximately 1.5 nm can provide a satisfactory passivation level on the surface of the N-type crystalline silicon substrate 1.

[0120] In the third stage, oxygen or a carrier gas containing oxygen is introduced into the CVD deposition chamber, and the oxygen directly contacts the silicon atoms in the first intrinsic amorphous silicon layer 132 and undergoes an oxidation reaction with the silicon atoms to prepare a diffusion barrier layer 133 composed of a silicon oxide layer; wherein the oxygen directly contacts the silicon atoms in the first intrinsic amorphous silicon layer 132 and undergoes an oxidation reaction to prepare silicon oxide Si. x O y Therefore, compared with the tunneling silicon oxide layer 131 prepared by thermal oxidation of the crystalline silicon substrate 1, the silicon oxide Si prepared by oxidation of the first intrinsic amorphous silicon layer 132 x O y The Si-O crystal structure is also relatively loose, which can provide an appropriate barrier for the subsequent diffusion of doping elements;

[0121] Given that the metallized and non-metallized regions have different requirements for dopant element concentrations, if patterning is performed when the diffusion barrier layer 133 is formed, the non-metallized regions will have the diffusion barrier layer 133 as a barrier, while the non-metallized regions will not. This will result in different doping concentrations in the non-metallized and metallized regions. After the diffusion barrier layer 133 is formed by CVD deposition, a patterning process is performed on the diffusion barrier layer 133 to form the diffusion barrier layer 133 on the surface of the first intrinsic amorphous silicon layer 132 corresponding to the non-metallized regions. The patterning process steps are as follows:

[0122] After forming the diffusion barrier layer 133 on the back side of the crystalline silicon substrate 1, a patterned mask corresponding to the pattern of the non-metallized area is formed. The patterned mask can be prepared by screen printing, laser transfer, photolithography, etc.

[0123] Referring to FIG. 10 , in one embodiment, the patterned mask can be formed by printing a slurry, paste, or ink resistant to HF corrosion, or by using an acid- and alkali-resistant wax. The crystalline silicon wafer is placed in an HF solution, where the diffusion barrier layer 133 not protected by the patterned mask is removed by HF. The patterned mask is then cleaned and removed, forming a selectively patterned diffusion barrier layer 133 on the back side of the crystalline silicon substrate 1.

[0124] In the fourth stage, referring to FIG. 11 , a mixture of a silicon source gas and a carrier gas carrying the silicon source gas is introduced into the CVD deposition chamber. The silicon source gas is deposited under high temperature conditions on the surface of the first intrinsic amorphous silicon layer 132 corresponding to the metallized region on the back side of the substrate 1 and on the surface of the diffusion barrier layer 133 to form a second intrinsic amorphous silicon layer 134. The second intrinsic silicon-containing layer 134 has a second thickness of 20 nm to 200 nm (inclusive).

[0125] Step 3: diffusing doping elements on the back side of the crystalline silicon substrate 1;

[0126] 12 , a doping element gas source of POCl 3 (phosphorus oxychloride) and oxygen are introduced into the CVD deposition chamber. Oxygen reacts with POCl 3 to generate P 2 O 5 (phosphorus pentoxide). Phosphorus atoms in P 2 O 5 continuously diffuse toward the crystalline silicon substrate 1 under high temperature conditions. The phosphorus atoms sequentially diffuse into the second intrinsic amorphous silicon layer 134, the diffusion barrier layer 133, the first intrinsic amorphous silicon layer 132, and the tunneling silicon oxide layer 131. Through the annealing process brought about by the diffusion of phosphorus atoms, a second doped polysilicon layer 134, a diffusion barrier layer 133, a first doped polysilicon layer 132, a tunneling silicon oxide layer 131, and a PSG layer (not shown) doped with phosphorus atoms are formed on the back side of the crystalline silicon substrate 1, and a wrap-around PSG layer 14 is formed on the front edge of the crystalline silicon substrate 1.

[0127] The diffusion barrier layer 133 in the non-metallized region blocks the diffusion of phosphorus atoms, so that differentiated local doping concentrations are formed in the first intrinsic amorphous silicon layer 132 during phosphorus atom diffusion. That is, the first doped polysilicon layer 132 includes a first high-passivation silicon-containing layer 1321 corresponding to a higher phosphorus atom diffusion concentration, and a first low-passivation silicon-containing layer 1322 corresponding to a lower phosphorus atom diffusion concentration. It should be noted that the diffusion of phosphorus atoms in the first intrinsic amorphous silicon is diffuse in all directions. However, since the horizontal length of the diffusion barrier layer 133 is much longer than the vertical length of the diffusion barrier layer 133, the horizontal diffusion of phosphorus atoms can be ignored during the short phosphorus atom diffusion process. Therefore, the diffusion of phosphorus atoms in the first intrinsic amorphous silicon layer 132 can be physically approximated as the diffusion of phosphorus atoms only in the vertical direction.

[0128] The second doped polysilicon layer 134 has a second phosphorus atom doping concentration C1. The diffusion barrier layer 133 is a silicon oxide layer having a barrier effect on the diffusion of phosphorus atoms, and thus can effectively block the diffusion of phosphorus atoms. The phosphorus atom doping concentration in the diffusion barrier layer 133 is less than the second phosphorus atom doping concentration C1.

[0129] The first doped polysilicon layer 132 has a first phosphorus atom doping concentration C2. Since phosphorus atoms need to diffuse into the first doped polysilicon layer 132 through the diffusion barrier layer 133, the first phosphorus atom doping concentration C2 is less than the phosphorus atom doping concentration in the diffusion barrier layer 133.

[0130] Please refer to Figure 13. In the figure, the thicknesses of t1, t2, t3 and t4 are 90 nm, 95 nm, 120 nm and 125 nm respectively. The thickness direction corresponding to the X-axis is defined as: with the surface of the second doped polysilicon layer 134 as the reference plane, extending along the direction toward the silicon substrate 1. Specifically, the thickness t1 corresponds to the second thickness W2 of the second doped polysilicon layer 134, the thickness t2 corresponds to the thickness between the diffusion barrier layer 133 and the reference plane of the second doped polysilicon layer 134, the thickness t3 corresponds to the thickness between the first doped polysilicon layer 132 and the reference plane of the second doped polysilicon layer 134, and the thickness t4 corresponds to the thickness between the tunneling silicon oxide and the reference plane of the second doped polysilicon layer 134.

[0131] The Y-axis corresponds to the phosphorus doping concentration in each film layer of the stacked passivation film 13. Specifically, the second phosphorus doping concentration of the second doped polysilicon layer 134 is C1, the phosphorus doping concentration of the first doped polysilicon layer 132 is C2, and the phosphorus doping concentration between the crystalline silicon substrate 1 and the tunneling silicon oxide layer 131 is C3 (atoms / cm3) (where the concentrations of C1, C2, and C3 are 5E20cm3, respectively). -3 、3E20cm -3 and 6E19cm -3 );

[0132] Since the first thickness W1 and the second thickness W2 are both at the nanometer level, and the high-temperature phosphorus diffusion rate is comparable to that of the nanometer-level intrinsic amorphous silicon layer, it can be approximately considered that the diffusion concentration of phosphorus atoms in the first thickness W1 and the second thickness W2 is equal everywhere.

[0133] However, the presence of the diffusion barrier layer 133 reduces the diffusion concentration of phosphorus atoms from the second intrinsic amorphous silicon layer 134 to the first intrinsic amorphous silicon layer 132 , especially the silicon oxide layer prepared using the first intrinsic amorphous silicon layer 132 after the high temperature annealing treatment;

[0134] The second phosphorus atom doping concentration C1 in the second doped polysilicon layer 134 is 5E20 cm -3 -1E21cm -3(including the values ​​at both ends), the second doped polysilicon layer 134 with a higher doping concentration can provide an ideal ohmic contact for the back electrode 161, greatly reducing the transmission resistance loss of photogenerated carriers;

[0135] The first phosphorus atom doping concentration C2 in the first doped polysilicon layer 132 is 1E19 cm -3 -3E20cm -3 (including the values ​​at both ends), the first doped polysilicon layer 132 with a lower doping concentration can provide chemical passivation for the solar cell, and because of the lower doping concentration therein, the Auger recombination rate in the TOPCon cell can also be greatly reduced;

[0136] Step 4: forming a passivation film on the front and back sides of the crystalline silicon substrate 1 and preparing electrodes to obtain the solar cell structure shown in FIG. 1 .

[0137] Please refer to Figure 14. A back passivation film is formed on the back of the crystalline silicon substrate 1, and a front passivation film is formed on the front of the crystalline silicon substrate 1. Then, metallization paste is printed on the front and back of the crystalline silicon substrate 1 to prepare the TOPCon battery shown in Figure 1.

[0138] The principles and implementation methods of the present application are described herein using specific examples, and the various embodiments are in a progressive relationship. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. The description of the above embodiments is only used to help understand the method and core ideas of the present application. For those of ordinary skill in the art, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

[0139] It should also be noted that, in this specification, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

Claims

1. A TOPCon battery, characterized in that: include: A substrate; a laminated passivation film and an electrode are provided on one side surface of the substrate; The stacked passivation film comprises a tunneling layer, a first doped polysilicon layer, a diffusion barrier layer, and a second doped polysilicon layer which are sequentially arranged in a direction away from the substrate; The surface of the substrate on one side facing the electrode has a metallized area and a non-metallized area, and the diffusion barrier layer corresponds to the non-metallized area and is used to prevent the doping elements in the second doped polysilicon layer from diffusing into the first doped polysilicon layer, so that the doping concentration of the first doped polysilicon layer in the non-metallized area is lower than the doping concentration of the first doped polysilicon layer in the metallized area.

2. The TOPCon battery according to claim 1, characterized in that The diffusion barrier layer is a silicon oxide layer.

3. The TOPCon battery according to claim 1, characterized in that The stacked passivation film is arranged on the back side of the substrate, the first doped polysilicon layer, the second doped polysilicon layer and the substrate use the same type of doping elements, the overall doping concentration of the first doped polysilicon layer is greater than the overall doping concentration of the substrate, and the overall doping concentration of the second doped polysilicon layer is higher than the overall doping concentration of the first doped polysilicon layer.

4. The TOPCon cell according to claim 3, wherein a back passivation layer is disposed on a surface of the laminated passivation film on a side away from the substrate, the electrode passes through the back passivation layer and contacts the laminated passivation film; the back passivation layer comprises SiN x Film, SiO x N y Film, Al2O3 / SiN x Laminated film, SiO x N y / SiN x At least one of the laminated films.

5. The TOPCon battery according to claim 1, characterized in that The thickness of the first doped polysilicon layer is 20 nm to 40 nm, including both ends; The thickness of the second doped polysilicon layer from a surface facing away from the substrate to a surface of the diffusion barrier layer facing away from the substrate is 20 nm-200 nm, including both ends.

6. The TOPCon battery according to claim 1, characterized in that The overall doping concentration of the first doped polysilicon layer is 1E19 cm -3 -3E20cm -3 , and includes the values ​​at both ends; The overall doping concentration of the second doped polysilicon layer is 5E20cm -3 -1E21cm -3 , including the values ​​at both ends.

7. A method for preparing a TOPCon battery, characterized in that: include: A stacked passivation film layer is prepared on one side surface of the substrate; the stacked passivation film includes a tunneling layer, a first doped polysilicon layer, a diffusion barrier layer, and a second doped polysilicon layer, which are arranged in sequence along a direction away from the substrate; the substrate has a metallized area and a non-metallized area on one side surface corresponding to the stacked passivation film layer, and the diffusion barrier layer corresponds to the non-metallized area and is used to block the doping elements in the second doped polysilicon layer from diffusing into the first doped polysilicon layer, so that the doping concentration of the first doped polysilicon layer in the non-metallized area is lower than the doping concentration of the first doped polysilicon layer in the metallized area.

8. The TOPCon battery according to claim 7, characterized in that The method of preparing a laminated passivation film layer on the surface of the substrate comprises: Depositing the tunneling layer on the surface of the substrate; Depositing a first intrinsic amorphous silicon layer on the surface of the tunneling layer; Prepare the diffusion barrier layer on the surface of the first intrinsic amorphous silicon layer corresponding to the non-metallized area; Depositing a second intrinsic amorphous silicon layer on a surface of the first intrinsic amorphous silicon layer corresponding to the metallization region and a surface of the diffusion barrier layer; Doping elements are diffused, and the doping elements are sequentially diffused into the second intrinsic amorphous silicon layer and the first intrinsic amorphous silicon layer in the metallized area, and the doping elements are sequentially diffused into the second intrinsic amorphous silicon layer, the diffusion barrier layer and the first intrinsic amorphous silicon layer in the non-metallized area, so that the second intrinsic amorphous silicon layer becomes the second doped polysilicon layer, and the first intrinsic amorphous silicon layer becomes the first doped polysilicon layer.

9. The TOPCon battery according to claim 8, characterized in that After depositing a first intrinsic amorphous silicon layer on the surface of the tunnel layer, the method further comprises: The first intrinsic amorphous silicon layer is lightly doped.

10. The TOPCon battery according to claim 7, characterized in that: The method of preparing a laminated passivation film layer on the surface of the substrate comprises: Depositing the tunneling layer on the surface of the substrate; Depositing the first doped polysilicon layer on the surface of the tunneling layer by in-situ doping; Prepare the diffusion barrier layer on the surface of the first doped polysilicon layer corresponding to the non-metallized area; The surface of the first doped polysilicon layer corresponding to the metallization region and the diffusion resistance Depositing the second doped polysilicon layer on the surface of the barrier layer; The first doped polysilicon layer and the second doped polysilicon layer are annealed.

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