Reconfigurable coprocessor, chip, multi-core signal processing system, and computing method

By segmenting the data flow graphs calculated by the neural network into sub-computing flow graphs and configuring a reconstructible computing array, the problem of frequent configuration of neural network computing tasks in the prior art is solved, and efficient computing efficiency and resource utilization are achieved.

WO2025112704A1PCT designated stage expired Publication Date: 2025-06-05BEIJING SMARTCHIP MICROELECTRONICS TECHNOLOGY CO LTD
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Patent Information

Application Number
PCT/CN2024/114104
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Priority Date
2023-11-28
Filing Date
2024-08-23
Publication Date
2025-06-05

AI Technical Summary

Technical Problem

When performing neural network computing tasks, existing reconfigurable computing systems need to configure reconfigurable computing arrays multiple times, resulting in inefficient computing.

Method used

By dividing the corresponding data flow graph of the neural network calculation into a series of sub-computing flow graphs, and configuring the reconfigurable computing units in the reconfigurable computing array based on the sub-computing flow graph, the number of configurations is reduced, and the parallel execution of multiple reconfigurable computing units is realized.

Benefits of technology

This greatly improves the computing efficiency, reduces the number of configurations of reconfigurable computing arrays, and improves the utilization rate of reconfigurable computing arrays.

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Abstract

The present disclosure relates to the technical field of processors, and in particular to a reconfigurable coprocessor, a chip, a multi-core signal processing system, and a computing method. The reconfigurable coprocessor comprises a main controller module, a reconfiguration controller module, and a reconfigurable computing array; the reconfiguration controller module comprises a reconfiguration controller and at least one sub-algorithm module; the reconfigurable computing array comprises one or more reconfigurable computing units; and each reconfigurable computing unit comprises a plurality of computing resources. The reconfiguration controller segments a data flow diagram corresponding to designated neural network computing to obtain a plurality of sub-computing flow diagrams, and on the basis of the plurality of sub-computing flow diagrams, determines the types of computing cores for computing the plurality of sub-computing flow diagrams and activates a corresponding sub-algorithm module for each computing core; and on the basis of the corresponding computing core, the sub-algorithm module configures an interconnection mode of the computing resources in the corresponding reconfigurable computing unit. According to the present disclosure, by repeatedly using consistent computing cores, the configuration consumption of reconfigurable computing arrays can be reduced.
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Citation Information

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