Memory

Abstract

Provided in the present disclosure is a memory. In the memory, with respect to each storage array member not at a head or tail position, each bit line therein is coupled to a corresponding stress test power supply, and a stress test power supply corresponding to each first bit line is different from a stress test power supply corresponding to a second bit line adjacent thereto; and, with respect to a storage array member at the head or tail position, each first bit line therein is coupled to a corresponding stress test power supply, and a stress test power supply corresponding to each odd-numbered first bit line is different from a stress test power supply corresponding to each even-numbered first bit line.

Description

A memory

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on November 28, 2023, with application number 202311634142.9 and application name “A Memory”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of semiconductors, and in particular to a memory. Background Art

[0003] With the development of semiconductor technology, the integration requirements and performance standards of memory are gradually increasing, so the internal circuit structure is also gradually being optimized. Providing a supporting test method for the optimized internal circuit structure is also a problem that needs to be solved.

[0004] Summary of the Invention

[0005] An embodiment of the present disclosure provides a memory.

[0006] The technical solution of the present disclosure is achieved as follows:

[0007] In a first aspect, the present disclosure provides a memory, comprising N memory array slices arranged in sequence along a first direction, where N is a natural number; each of the memory array slices comprises a plurality of first bit lines and a plurality of second bit lines, and the first bit lines and the second bit lines are alternately arranged along a second direction; for the memory array slices at non-head and tail positions, the first bit line and the adjacent second bit line are electrically isolated; for the memory array slices at the head and tail positions, the first bit line is electrically connected to the second bit line adjacent to the first side, and the first bit line is electrically isolated from the second bit line adjacent to the second side; the first side and the second side are two opposite sides along the second direction; along the first The memory array slices are numbered in one direction; and in each of the memory array slices, the first bit lines are numbered along a second direction, and the second bit lines are numbered along a second direction; for the memory array slices at non-head and tail positions, each of the bit lines is coupled to a corresponding pressure test power supply, and the pressure test power supply corresponding to the first bit line is different from the pressure test power supply corresponding to the adjacent second bit line; for the memory array slices at the head and tail positions, the first bit lines are coupled to a corresponding pressure test power supply, and the pressure test power supply corresponding to the odd-numbered first bit lines is different from the pressure test power supply corresponding to the even-numbered first bit lines.

[0008] In some embodiments, the first bit line of the odd-numbered storage array slice is the second bit line, and the first bit line of the even-numbered storage array slice is the first bit line; a readout amplifier module is distributed between every two storage array slices, and the readout amplifier module includes a plurality of sensitive amplifiers arranged in sequence along the second direction; the first end of the sensitive amplifier is connected to one of the second bit lines on the third side through a first depolarization switch, and the second end of the sensitive amplifier is connected to one of the second bit lines on the third side through a first isolation switch; the second end of the sensitive amplifier is also connected to one of the first bit lines on the fourth side through a second depolarization switch, and the first end of the sensitive amplifier is also connected to one of the first bit lines on the fourth side through a second isolation switch; the third side and the fourth side are opposite sides along the first direction; the first end or the second end of each of the sensitive amplifiers is also connected to a precharge source through a corresponding precharge switch, so that each bit line is coupled to one of the precharge sources.

[0009] In some embodiments, for the storage array slices at non-head and tail positions, the pre-charge source coupled to the bit lines therein is used as the stress test power supply; for the storage array slices at the head and tail positions, the first bit lines therein are also coupled to the respective edge test power supplies through the first test switch, and the edge test power supplies coupled to the first bit lines are used as the stress test power supply.

[0010] In some embodiments, for the storage array slices at non-head and tail positions, the bit lines therein are also coupled to the respective pre-charge sources through the column selection switch and the second test switch; for the storage array slices at the head and tail positions, the first bit lines therein are also coupled to the respective pre-charge sources through the column selection switch and the second test switch; for each of the storage array slices, the pre-charge source coupled to each bit line is used as the stress test power supply.

[0011] In some embodiments, for the storage array slices at non-head and tail positions, the bit lines therein are also coupled to respective preset test power supplies through a column selection switch and a second test switch; for the storage array slices at the head and tail positions, the first bit lines therein are also coupled to respective preset test power supplies through a column selection switch and a second test switch; for each of the storage array slices, the preset test power supply coupled to each bit line is used as the stress test power supply.

[0012] In some embodiments, the readout amplifier modules are numbered along a first direction; for the odd-numbered readout amplifier modules, the first end or the second end of the sensitive amplifier therein is connected to a first pre-charge source through a corresponding pre-charge switch; for the even-numbered readout amplifier modules, the first end or the second end of the sensitive amplifier therein is connected to a second pre-charge source through a corresponding pre-charge switch, so that the stress test power supply corresponding to the first bit line is different from the stress test power supply corresponding to the adjacent second bit line.

[0013] In some embodiments, for the memory array slices at the head and tail positions, the odd-numbered first bit lines are connected to the first edge test power supply via their respective first test switches, and the even-numbered first bit lines are connected to the second edge test power supply via their respective first test switches; or, for the first memory array slice, the odd-numbered first bit lines are connected to the first edge test power supply via their respective first test switches, and the even-numbered first bit lines are connected to the second edge test power supply via their respective first test switches; for the last memory array slice, the odd-numbered first bit lines are connected to the second edge test power supply via their respective first test switches, and the even-numbered first bit lines are connected to the first edge test power supply via their respective first test switches.

[0014] In some embodiments, the memory is configured to control the first edge test power supply to a first voltage value, the second edge test power supply to a second voltage value, the first pre-charge power supply to a third voltage value, the second pre-charge power supply to a fourth voltage value, and perform a bit line stress test operation; and to control the first edge test power supply to a second voltage value, the second edge test power supply to a first voltage value, the first pre-charge power supply to a fourth voltage value, the second pre-charge power supply to a third voltage value, and perform the bit line stress test operation; wherein the first voltage value is different from the second voltage value, and the third voltage value is different from the fourth voltage value; in the bit line stress test operation, all the first test switches are in a closed state, the isolation switches and depolarization switches between the memory array slices at the head and tail positions and the adjacent read-out amplifier modules are in an off state, and the remaining isolation switches, the remaining depolarization switches and all pre-charge switches are in a closed state.

[0015] In some embodiments, the bit lines in the memory array slices at the head and tail positions are electrically connected to the adjacent sensitive amplifier modules through the first depolarization switch or the first isolation switch; the memory further comprises: a command control circuit configured to generate a test enable signal, an initial isolation signal and an initial depolarization signal; wherein, when the memory is instructed to perform the bit line stress test operation, the test enable signal, the initial isolation signal and the initial depolarization signal are all in a valid state; a first preprocessing circuit configured to generate a first edge isolation signal and a second edge isolation signal based on an edge test parameter group and the initial isolation signal; and to generate a first edge depolarization signal and a second edge depolarization signal based on the edge test parameter group and the initial depolarization signal; a second preprocessing circuit configured to generate a first internal isolation signal and a second internal isolation signal based on an internal test parameter group and the initial isolation signal. internal isolation signal; and based on the internal test parameter group and the initial depolarization signal, generate a first internal depolarization signal and a second internal depolarization signal; wherein, all the first test switches are controlled by the test enable signal, and the first isolation switch, the second isolation switch, the first depolarization switch, and the second depolarization switch between the readout amplifier modules at the head and tail positions and the adjacent storage array slices are controlled one by one by the first edge isolation signal, the second edge isolation signal, the first edge depolarization signal, and the second edge depolarization signal; the first isolation switch, the second isolation switch, the first depolarization switch, and the second depolarization switch between the readout amplifier modules at non-head and tail positions and the adjacent storage array slices are controlled correspondingly by the first internal isolation signal, the second internal isolation signal, the first internal depolarization signal, and the second internal depolarization signal.

[0016] In some embodiments, the edge test parameter group includes a first test parameter and a second test parameter, and the internal test parameter group includes a third test parameter and a fourth test parameter; if the first test parameter is in the first state, the second edge isolation signal and the second edge depolarization signal are one-to-one corresponding to the initial isolation signal and the initial depolarization signal at the same level; if the first test parameter is in the second state, the second edge isolation signal and the second edge depolarization signal are both invalid; if the second test parameter is in the first state, the first edge isolation signal and the first edge depolarization signal are one-to-one corresponding to the initial isolation signal and the initial depolarization signal at the same level; if the second test parameter is in the second state, the first edge isolation signal and the first edge depolarization signal are both invalid; if the fourth test parameter is in the second state, the first edge isolation signal and the first edge depolarization signal are both invalid. If the parameter is in the first state, the first internal isolation signal and the first internal depolarization signal have the same level as the initial isolation signal and the initial depolarization signal in one-to-one correspondence; if the fourth test parameter is in the second state, the first internal isolation signal and the first internal depolarization signal are both invalid; if the third test parameter is in the first state, the second internal isolation signal and the second internal depolarization signal have the same level as the initial isolation signal and the initial depolarization signal in one-to-one correspondence; if the third test parameter is in the second state, the second internal isolation signal and the second internal depolarization signal are both invalid; wherein, in the process of the memory being instructed to perform a bit line stress test operation, the second test parameter is in the second state, and the first test parameter, the third test parameter and the fourth test parameter are all in the first state.

[0017] In some embodiments, the first state is a high level and the second state is a low level; the first preprocessing circuit includes: a first AND gate, whose two input ends respectively receive the first test parameter and the initial isolation signal, and whose output end outputs the second edge isolation signal; a second AND gate, whose two input ends respectively receive the second test parameter and the initial isolation signal, and whose output end outputs the first edge isolation signal; a third AND gate, whose two input ends respectively receive the first test parameter and the initial depolarization signal, and whose output end outputs the second edge depolarization signal; a fourth AND gate, whose two input ends respectively receive the second test parameter and the initial depolarization signal, and whose output end outputs the first edge depolarization signal.

[0018] In some embodiments, the bit line in the first memory array slice is electrically connected to the adjacent sensitive amplifier module through the first depolarization switch or the first isolation switch, and the bit line in the last memory array slice is electrically connected to the sensitive amplifier modules at the first and last positions through the second depolarization switch or the second isolation switch. The memory further includes: a command control circuit configured to generate a test enable signal, an initial isolation signal, and an initial depolarization signal; wherein, when the memory is instructed to perform the stress test operation, the test enable signal, the initial isolation signal, and the initial depolarization signal are all in valid state; a second pre-processing circuit is configured to generate a first internal isolation signal and a second internal isolation signal based on the internal test parameter group and the initial isolation signal; and generate a first internal depolarization signal and a second internal depolarization signal based on the internal test parameter group and the initial depolarization signal; a third pre-processing circuit is configured to generate a first head-end isolation signal and a second head-end isolation signal based on the head-end test parameter group and the initial isolation signal; and generate a first head-end depolarization signal and a second head-end depolarization signal based on the head-end test parameter group and the initial depolarization signal; a fourth pre-processing circuit is configured to generate a first head-end depolarization signal and a second head-end depolarization signal based on the tail-end test parameter group and the initial isolation signal signal, generates a first tail end isolation signal and a second tail end isolation signal; and generates a first tail end deflection signal and a second tail end deflection signal based on the tail end test parameter group and the initial deflection signal; wherein all the first test switches are controlled by the test enable signal, and the first isolation switch, the second isolation switch, the first deflection switch, and the second deflection switch between the first readout amplifier module and the adjacent storage array chip are controlled one by one by the first head end isolation signal, the second head end isolation signal, the first head end deflection signal, and the second head end deflection signal; the last readout amplifier module and the adjacent The first isolation switch, the second isolation switch, the first depolarization switch, and the second depolarization switch between the storage array slices are controlled one by one by the first tail end isolation signal, the second tail end isolation signal, the first tail end depolarization signal, and the second tail end depolarization signal; the first isolation switch, the second isolation switch, the first depolarization switch, and the second depolarization switch between the readout amplifier modules at non-head and tail positions and the adjacent storage array slices are controlled one by one by the first internal isolation signal, the second internal isolation signal, the first internal depolarization signal, and the second internal depolarization signal.

[0019] In some embodiments, the internal test parameter group includes at least a third test parameter and a fourth test parameter; the head-end test parameter group includes a fifth test parameter and a sixth test parameter, and the tail-end test parameter group includes a seventh test parameter and an eighth test parameter; if the third test parameter is in the first state, the second internal isolation signal and the second internal depolarization signal have the same level as the initial isolation signal and the initial depolarization signal in one-to-one correspondence; if the third test parameter is in the second state, the second internal isolation signal and the second internal depolarization signal are both invalid; if the fourth test parameter is in the first state, the first internal isolation signal and the first internal depolarization signal have the same level as the initial isolation signal and the initial depolarization signal in one-to-one correspondence; if the fourth test parameter is in the second state, the first internal isolation signal and the first internal depolarization signal are both invalid; if the fifth test parameter is in the first state, the second head-end isolation signal and the second head-end depolarization signal have the same level as the initial isolation signal and the initial depolarization signal in one-to-one correspondence; if the fifth test parameter is in the second state, the second head-end isolation signal and the second head-end depolarization signal are both invalid; If the sixth test parameter is in the first state, the first head-end isolation signal and the first head-end depolarization signal have the same level as the initial isolation signal and the initial depolarization signal respectively; if the sixth test parameter is in the second state, the first head-end isolation signal and the first head-end depolarization signal are both invalid; if the seventh test parameter is in the first state, the second tail-end isolation signal and the second tail-end depolarization signal have the same level as the initial isolation signal and the initial depolarization signal respectively; if the seventh test parameter is in the second state, the second tail-end isolation signal and the second tail-end depolarization signal are both invalid; if the eighth test parameter is in the first state, the first tail-end isolation signal and the first tail-end depolarization signal have the same level as the initial isolation signal and the initial depolarization signal respectively; if the eighth test parameter is in the second state, the first tail-end isolation signal and the first tail-end depolarization signal are both invalid; wherein, in the process in which the memory is instructed to perform a bit line stress test operation, the sixth test parameter and the seventh test parameter are in the second state, and the third test parameter, the fourth test parameter, the fifth test parameter, and the eighth test parameter are all in the first state.

[0020] In some embodiments, the first state is a high level and the second state is a low level; the second preprocessing circuit includes: a fifth AND gate, whose two input ends respectively receive the third test parameter and the initial isolation signal, and whose output end outputs the second internal isolation signal; a sixth AND gate, whose two input ends respectively receive the fourth test parameter and the initial isolation signal, and whose output end outputs the first internal isolation signal; a seventh AND gate, whose two input ends respectively receive the third test parameter and the initial depolarization signal, and whose output end outputs the second internal depolarization signal; an eighth AND gate, whose two input ends respectively receive the fourth test parameter and the initial depolarization signal, and whose output end outputs the first internal depolarization signal.

[0021] In some embodiments, the first state is a high level and the second state is a low level; the third preprocessing circuit includes: a ninth AND gate, whose two input ends respectively receive the fifth test parameter and the initial isolation signal, and whose output end outputs the second first-end isolation signal; a tenth AND gate, whose two input ends respectively receive the sixth test parameter and the initial isolation signal, and whose output end outputs the first first-end isolation signal; an eleventh AND gate, whose two input ends respectively receive the fifth test parameter and the initial depolarization signal, and whose output end outputs the second first-end depolarization signal; a twelfth AND gate, whose two input ends respectively receive the sixth test parameter and the initial depolarization signal, and whose output end outputs the second first-end depolarization signal. The first head-end depolarization signal is outputted at the end; the fourth preprocessing circuit includes: a thirteenth AND gate, whose two input ends respectively receive the seventh test parameter and the initial isolation signal, and whose output end outputs the second tail-end isolation signal; a fourteenth AND gate, whose two input ends respectively receive the eighth test parameter and the initial isolation signal, and whose output end outputs the first tail-end isolation signal; a fifteenth AND gate, whose two input ends respectively receive the seventh test parameter and the initial depolarization signal, and whose output end outputs the second tail-end depolarization signal; a sixteenth AND gate, whose two input ends respectively receive the eighth test parameter and the initial depolarization signal, and whose output end outputs the first tail-end depolarization signal.

[0022] In some embodiments, the bit lines in the storage array slices that are not at the first or last position are coupled to their respective local data lines via their respective column selection switches; wherein: for the second bit line in the storage array slices that are not at the first or last position and are odd-numbered and the first bit line in the storage array slices that are not at the first or last position and are even-numbered, the coupled local data lines are also connected to the first pre-charge source via their respective second test switches; for the first bit line in the storage array slices that are not at the first or last position and are odd-numbered and the second bit line in the storage array slices that are not at the first or last position and are even-numbered, the coupled local data lines are also connected to the second pre-charge source via their respective second test switches.

[0023] In some embodiments, for the storage array slices at the head and tail positions, the first bit lines therein are coupled to their respective local data lines via respective column selection switches; wherein: for the storage array slices at the head and tail positions, the local data lines coupled to the odd-numbered first bit lines are coupled to the second pre-charge source via the second test switch, and the local data lines coupled to the even-numbered first bit lines are coupled to the first pre-charge source via the second test switch; or, for the first storage array slice, the local data lines coupled to the odd-numbered first bit lines are coupled to the second pre-charge source via the second test switch, and the local data lines coupled to the even-numbered first bit lines are coupled to the first pre-charge source via the second test switch; and, for the last storage array slice, the local data lines coupled to the odd-numbered first bit lines are coupled to the first pre-charge source via the second test switch, and the local data lines coupled to the even-numbered second bit lines are coupled to the first pre-charge source via the second test switch.

[0024] In some embodiments, the memory is configured to control all isolation switches, depolarization switches and pre-charge switches to be in the off state, control all column selection switches and the second test switch to be in the closed state, and control the first pre-charge source to be the first voltage value and the second pre-charge source to be the second voltage value to perform a bit line stress test; or, control all isolation switches, depolarization switches and pre-charge switches to be in the off state, control all column selection switches and the second test switch to be in the closed state, and control the first pre-charge source to be the second voltage value and the second pre-charge source to be the first voltage value to perform another bit line stress test.

[0025] In some embodiments, for the storage array slices that are not at the first or last position, each of the bit lines therein is coupled to its own local data line via its own column selection switch; for the second bit line in the storage array slices that are not at the first or last position and are odd-numbered and for the first bit line in the storage array slices that are not at the first or last position and are even-numbered, the coupled local data line is coupled to the first preset test power supply via the second test switch; for the first bit line in the storage array slices that are not at the first or last position and are odd-numbered and for the second bit line in the storage array slices that are not at the first or last position and are even-numbered, the coupled local data line is coupled to the second preset test power supply via the second test switch.

[0026] In some embodiments, for the storage array slices at the head and tail positions, the first bit lines therein are all coupled to their respective local data lines via respective column selection switches; wherein: for the storage array slices at the head and tail positions, the local data lines corresponding to the odd-numbered first bit lines are coupled to the second preset test power supply via the second test switch, and the local data lines corresponding to the even-numbered first bit lines are coupled to the first preset test power supply via the second test switch; or, for the first storage array slice, the local data lines corresponding to the odd-numbered first bit lines are coupled to the second preset test power supply via the second test switch, and the local data lines corresponding to the even-numbered first bit lines are coupled to the first preset test power supply via the second test switch; for the last storage array slice, the local data lines corresponding to the odd-numbered first bit lines are coupled to the first preset test power supply via the second test switch, and the local data lines corresponding to the even-numbered first bit lines are coupled to the second preset test power supply via the test switch.

[0027] In some embodiments, the memory is configured to control all isolation switches and depolarization switches to be in an off state, control all pre-charge switches to be in a closed state, and control the pre-charge power supply to a fifth voltage value; control all column selection switches and second test switches to be in a closed state, and control the first preset test power supply to be a first voltage value and the second preset test power supply to be a second voltage value to perform a bit line stress test; control all isolation switches and depolarization switches to be in an off state, control all pre-charge switches to be in a closed state, and control the pre-charge power supply to be a fifth voltage value; control all column selection switches and second test switches to be in a closed state, and control the first preset test power supply to be a second voltage value and the second preset test power supply to be a first voltage value to perform another bit line stress test; wherein, the voltage of the fifth voltage value is between the voltage of the first voltage value and the voltage of the second voltage value.

[0028] The disclosed embodiment provides a memory that reduces the area of ​​a memory array chip located at an edge to half the area of ​​other memory array chips, thereby reducing the chip area and improving the integration level. At the same time, for the memory, each bit line in the memory array chips at non-head and tail positions is coupled to a stress test power supply, and the first bit line in the memory array chips at the head and tail positions is coupled to the stress test power supply. This can simultaneously cause two adjacent bit lines in the memory array chips at non-head and tail positions to be at different voltages, and the odd-numbered first bit lines and the even-numbered first bit lines in the memory array chips at the head and tail positions to be at different voltages. This can efficiently implement bit line stress testing, improve the test process of the memory structure, and ensure factory performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG1 is a schematic diagram of a partial structure of a DRAM;

[0030] FIG2 is a second schematic diagram of a partial structure of a DRAM;

[0031] FIG3A is a schematic diagram of a partial structure of a memory provided by an embodiment of the present disclosure;

[0032] FIG3B is a second schematic diagram of a partial structure of a memory provided by an embodiment of the present disclosure;

[0033] FIG4 is a third schematic diagram of a partial structure of a memory provided by an embodiment of the present disclosure;

[0034] FIG5 is a fourth schematic diagram of a partial structure of a memory provided by an embodiment of the present disclosure;

[0035] FIG6 is a schematic structural diagram of a sensitive amplifier provided by an embodiment of the present disclosure;

[0036] FIG7 is a fifth schematic diagram of a partial structure of a memory provided by an embodiment of the present disclosure;

[0037] FIG8 is a first schematic diagram of a control portion of a memory provided by an embodiment of the present disclosure;

[0038] FIG9 is a second schematic diagram of a control portion of a memory provided by an embodiment of the present disclosure;

[0039] FIG10 is a sixth schematic diagram of a partial structure of a memory provided by an embodiment of the present disclosure;

[0040] FIG11 is a seventh schematic diagram of a partial structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0042] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0043] If similar descriptions of "first / second" appear in the application documents, the following explanation is added. In the following description, the terms "first / second / third" are merely used to distinguish similar objects and do not represent a specific order for the objects. It is understandable that "first / second / third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0045] Taking dynamic random access memory (DRAM) as an example, see Figure 1, which shows a partial structural diagram of a DRAM provided by an embodiment of the present disclosure. As shown in Figure 1, the core of a DRAM is a memory array chip (or section), a readout amplifier module, a row decoding and control (XDEC) circuit, a column decoding and control (YDEC) circuit, a secondary read amplifier (SSa) circuit, and a write driver circuit. The secondary read amplifier circuit and the write driver circuit are collectively referred to as the SSa & Write Driver circuit.

[0046] The memory array chip is composed of a large number of memory cells (or cells). Word lines (WL) and bit lines (BL) can be used to read, write or refresh data from selected memory cells.

[0047] Generally speaking, the 65 memory array slices along the first direction can serve as a repeatable structure within the memory (e.g., a half bank). Further enlarging Figure 1, see Figure 2. The bit lines within each memory array slice (e.g., 11_1, 11_2, ..., 11_65) are alternately referred to as the first bit line BLa and the second bit line BLb (Figure 2 only illustrates a portion of the first bit line BLa and the second bit line BLb). Specifically, for odd-numbered memory array slices (e.g., 11_1, 11_3, ..., 11_65), the first bit line is the second bit line BLb; for even-numbered memory array slices (e.g., 11_2, 11_4, ..., 11_64), the first bit line is the first bit line BLa. The distinction between the first bit line BLa and the second bit line BLb is simply a position-based division; in reality, the first bit line BLa and the second bit line BLb have exactly the same physical structure.

[0048] A readout amplifier module (e.g., 12_1, 12_2, ..., 12_64) is set between every two memory array chips. Each readout amplifier module includes multiple sense amplifiers (Sa). One end of each Sa is connected to the bit line in the memory array chip on one side (e.g., the top), and the other end of Sa is connected to the bit line in the memory array chip on the other side (e.g., the bottom).

[0049] Please refer to Figures 1 and 2. The word line signal is given by XDEC to turn on the target word line in the memory array chip, and then the column select signal is given by YDEC to control the corresponding Sa operation, and then exchange electrical signals with the target bit line, and finally write, read or refresh data to the target memory cell.

[0050] As shown in FIG2 , for the memory array slices at the head and tail positions (edge), only half of the bit lines can be connected to the adjacent readout amplifier modules, which results in the other half of the bit lines and their corresponding memory cells being unusable. For example, the first bit line BLa in the memory array slices 11_1 and 11_65 is not connected to the readout amplifier module, resulting in a waste of memory cells and hindering the improvement of chip integration.

[0051] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0052] In one embodiment of the present disclosure, referring to FIG. 3A or FIG. 3B , a partial structural diagram of a memory 10 provided in an embodiment of the present disclosure is shown. As shown in FIG. 3A or FIG. 3B , the memory 10 includes N memory array slices (e.g., 11_1, 11_2, ..., 11_N) arranged sequentially along a first direction. Here, N can be any natural number. FIG. 3A illustrates N as an odd number, while FIG. 3B illustrates N as an even number.

[0053] Please refer to Figures 3A and 3B. Each memory array chip includes multiple first bit lines BLa and multiple second bit lines BLb, and the first bit lines BLa and the second bit lines BLb are arranged alternately along the second direction; for memory array chips at non-head and tail positions (for example, 11_2...11_N-1), the first bit line BLa and the adjacent second bit lines BLb are electrically isolated; for memory array chips at the head and tail positions (for example, 11_1 and 11_N), the first bit line BLa is electrically connected to the second bit line BLb adjacent to the first side (for example, the left side along the second direction), and the first bit line BLa is electrically isolated from the second bit line BLb adjacent to the second side (for example, the right side along the second direction), that is, the first side and the second side are opposite sides along the second direction.

[0054] Here, the sensitive amplifier circuit 10 in the embodiment of the present disclosure is applied to a variety of signal amplification scenarios, such as DRAM, synchronous dynamic random access memory (SDRAM), double-speed DRAM, low-power DRAM, etc., and those skilled in the art can flexibly apply it.

[0055] It should be noted that for the memory array slices (11_1, 11_N) at the head and tail positions, since the two bit lines are essentially connected to form a single bit line, the length of each bit line can be shortened by nearly half. Specifically, for memory array slices not at the head and tail positions, the distance between one end of each bit line connected to Sa and the other end of the bit line is recorded as L1. For memory array slices at the head and tail positions, the distance between one end of the entire bit line (first bit line + second bit line) connected to Sa and the other end of the entire bit line is recorded as L2, where L1 = L2.

[0056] Therefore, the area of ​​the memory array slices (11_1, 11_N) at the first and last positions is shortened by nearly half compared to the area of ​​the memory array slices (11_2...11_N-1) at non-first and last positions, the integration of the memory 10 is improved, and the overall area occupied by the memory unit is reduced.

[0057] Please note that although eight bit lines are shown for each memory array slice in FIG. 3A or FIG. 3B , this is merely an abbreviation. In reality, there are many bit lines in each memory array slice.

[0058] The following illustrations and explanations are all based on N=65. Please adapt to the situation where N is an even number or other values.

[0059] In particular, bitline stress testing (BL stress) is a key performance test for memory 10. This testing method involves applying different voltages to adjacent bitlines and subsequently observing whether the memory cells function properly. For the memory 10 shown in Figures 3A or 3B , the bitline structure of the leading and trailing memory array slices (11_1, 11_N) differs from the bitline structure of the non-leading and trailing memory array slices (11_2 ... 11_N-1), making BL stress testing impossible using conventional methods.

[0060] Therefore, the embodiment of the present disclosure further provides a method for testing the BL stress of the memory 10 shown in FIG. 3A or FIG. 3B .

[0061] For the convenience of explanation, with respect to Figure 3A or Figure 3B, for the odd-numbered memory array slices (11_1, 11_3, 11_5...), the first bit line is the second bit line BLb; for the even-numbered memory array slices (11_2, 11_4, 11_6...), the first bit line is the first bit line BLa. For each memory array slice, the first bit lines BLa therein are numbered sequentially along the second direction, and the second bit lines BLb therein are numbered sequentially along the second direction.

[0062] Taking the odd-numbered starting point as an example, refer to FIG. 4 (which uses N=65 as an example; please adapt to other values ​​of N). The bit lines in the memory array slice 11_1 are sequentially arranged along the second direction as BLbo, BLao, BLbe, and BLae. The bit lines in the memory array slice 11_2 are sequentially arranged along the second direction as BLao, BLbo, BLae, and BLbe.

[0063] An embodiment of the present disclosure provides a memory 10, in which, for storage array slices (11_2, 11_3, ..., 11_64) at non-head and tail positions, each bit line is coupled to a corresponding stress test power supply TXo / TXe, and the stress test power supply corresponding to the first bit line Blaa is different from the stress test power supply corresponding to the adjacent second bit line BLb; for example, referring to FIG5 , for storage array slice 11_2, the stress test power supply corresponding to Blaa is TXo, and the stress test power supply corresponding to Blb is TXe; for storage array slice 11_3, the stress test power supply corresponding to Blaa is TXe, and the stress test power supply corresponding to Blb is TXo.

[0064] For the first and last memory array slices (11_1, 11_65), the first bit lines are both coupled to corresponding stress test power supplies, and the stress test power supplies corresponding to the odd-numbered first bit lines BLao are different from the stress test power supplies corresponding to the even-numbered first bit lines BLae. It should be understood that in FIG5 , the first bit lines Blao in the memory array slice are specifically coupled to the corresponding stress test power supplies via their electrical connections Blb; using FIG5 as an example, the stress test power supply corresponding to Blao is TXe, and the stress test power supply corresponding to Blae is TXo.

[0065] In particular, FIG5 is only an example. In actual scenarios, there are more design methods for stress test power supplies. For example, for storage array slices that are not at the first or last position, all first bit lines are connected to TXo, and all second bit lines are connected to Txe.

[0066] 5 , a sense amplifier module is distributed between every two memory array slices, and the sense amplifier modules are numbered along a first direction, that is, the sense amplifier modules are numbered 12_1, 12_2, ..., 12_64 in sequence along the first direction.

[0067] The sense amplifier module includes a plurality of sense amplifiers Sa arranged sequentially along a second direction. For each sense amplifier module, the sense amplifiers are numbered along the second direction, with odd-numbered sense amplifiers Sa represented by 40o and even-numbered sense amplifiers Sa represented by 40e. The structure of each sense amplifier Sa is shown in FIG6 . As shown in FIG6 , the sense amplifier Sa includes a first transistor 21, a second transistor 22, a third transistor 23, and a fourth transistor 24, which are cross-coupled. The drains of the first transistor 21 and the third transistor 23 are both connected to a second complementary bit line SaBlb, the drains of the second transistor 22 and the fourth transistor 24 are both connected to a first complementary bit line SaBLa, the gate of the third transistor 23 is connected to the first bit line BLa, and the gate of the fourth transistor 24 is connected to the second bit line BLb. Furthermore, NCS refers to a pull-down module, and PCS refers to a pull-up module. This section does not affect the understanding of the disclosed solution and is not further explained.

[0068] Referring to Figure 6 , the first end of the sense amplifier Sa is connected to a second bit line BLb on the third side (e.g., upward along the first direction) via a first depolarization switch 31, and the second end of the sense amplifier Sa is connected to a second bit line BLb on the third side via a first isolation switch 32. The second end of the sense amplifier Sa is also connected to a first bit line BLa on the fourth side (e.g., downward along the first direction) via a second depolarization switch 33, and the first end of the sense amplifier Sa is also connected to a first bit line BLa on the fourth side via a second isolation switch 34. In other words, the third and fourth sides are opposite sides along the third direction.

[0069] Exemplarily, the first depolarization switch 31 , the second depolarization switch 33 , the first isolation switch 32 and the second isolation switch 34 are all transistors.

[0070] The first terminal or the second terminal of each sense amplifier Sa is further connected to the precharge source VAD via a corresponding precharge switch 35. It should be understood that in FIG6 , the second bit line BLb is coupled to the precharge source VAD via the first depolarization switch 31 and the precharge switch 35, and the first bit line Bla is coupled to the precharge source VAD via the second isolation switch 34 and the precharge switch 35. That is, each bit line is coupled to a precharge source VAD, and the two bit lines connected to the same sense amplifier share the same precharge source VAD.

[0071] In this way, the embodiment of the present disclosure provides a memory that reduces the area of ​​the memory array chip located at the edge to half the area of ​​other memory array chips. At the same time, each bit line of the memory array chip has its own stress test power supply, which can efficiently implement bit line stress testing.

[0072] In a first specific embodiment, for the memory array slices (11_2, 11_3...11_64) at non-head and tail positions, the pre-charge source coupled to the bit lines therein is used as a stress test power supply; however, for the memory array slices (11_1, 11_65) at the head and tail positions, the first bit lines therein are also coupled to their respective edge test power supplies through the first test switch, and the edge test power supply coupled to the first bit lines is used as a stress test power supply.

[0073] The following are specific instructions.

[0074] Please refer to Figure 7. The memory 10 includes two groups of pre-charge sources VAD, one group is called the first pre-charge source VAD2O, and the other group is called the second pre-charge source VAD2E; only for the storage array slices (11_2, 11_3...11_64) at non-head and tail positions, the first pre-charge source VAD2O is used as the stress test power supply Txo, and the second pre-charge source VAD2E is used as the stress test power supply Txe.

[0075] On the one hand, as shown in Figure 7, for the odd-numbered readout amplifier modules (12_1, 12_3...12_63), the first end or the second end of the sensitive amplifier Sa therein is also connected to the first pre-charge source VAD2O through the pre-charge switch 35; for the even-numbered readout amplifier modules (12_2, 12_4...12_64), the first end or the second end of the sensitive amplifier Sa therein is also connected to the second pre-charge source VAD2E through the pre-charge switch 35, so as to realize that the stress test power supply corresponding to the first bit line BLa is different from the stress test power supply corresponding to the adjacent second bit line BLb.

[0076] It should be understood that in Figure 7, the second end of the odd-numbered sense amplifier 40o is connected to the corresponding pre-charge source through the pre-charge switch 35, and the first end of the even-numbered sense amplifier 40e is connected to the corresponding pre-charge source through the pre-charge switch 35, but this does not constitute a corresponding limitation, as long as the pre-charge source corresponding to the sense amplifier Sa in the odd-numbered readout amplifier module is the first pre-charge source VAD2O, and the pre-charge source corresponding to the sense amplifier Sa in the even-numbered readout amplifier module is the second pre-charge source VAD2E.

[0077] On the other hand, the memory 10 also includes two groups of edge test power supplies, one group is called the first edge test power supply VAD2Eedge, and the other group is called the second edge test power supply VAD2Oedge; for the memory array slices at the head and tail positions (11_1 and 11_65), the first edge test power supply VAD2Eedge is used as the stress test power supply TXe, and the second edge test power supply VAD2Oedge is used as the stress test power supply TXo.

[0078] In one case, referring to FIG7 , for the memory array slices (11_1, 11_65) at the head and tail positions, the odd-numbered first bit lines BLao are connected to the first edge test power supply VAD2Eedge via their respective first test switches 13, and the even-numbered first bit lines BLae are connected to the second edge test power supply VAD2Oedge via their respective first test switches 13, so that the stress test power supply corresponding to the odd-numbered first bit lines BLao is different from the stress test power supply corresponding to the even-numbered first bit lines BLae.

[0079] In another case, for the first memory array chip 11_1, the odd-numbered first bit lines BLao are connected to the first edge test power supply VAD2Eedge via their respective test switches, and the even-numbered first bit lines BLae are connected to the second edge test power supply VAD2Oedge via their respective test switches; for the last memory array chip 11_65, the odd-numbered first bit lines BLao are connected to the second edge test power supply VAD2Oedge via their respective test switches, and the even-numbered first bit lines BLae are connected to the first edge test power supply VAD2Eedge via their respective test switches, so that the test power supply corresponding to the odd-numbered first bit lines BLao is different from the test power supply corresponding to the even-numbered first bit lines BLae.

[0080] In this way, adjacent bit lines in the memory array slices at non-head and tail positions are connected to different pre-charge sources, and the odd-numbered first bit lines BLao and the even-numbered first bit lines BLae in the memory array slices at the head and tail positions are connected to different edge test power supplies, thereby conveniently implementing the bit line stress test BL stress and ensuring the product performance of the memory.

[0081] Based on the structure of FIG7 , the process of the memory 10 performing BL stress on the memory array slices at non-head and tail positions is as follows:

[0082] First, the memory 10 is specifically configured to control the first edge test power supply VAD2Eedge to a first voltage value, the second edge test power supply VAD2Oedge to a second voltage value, the first precharge power supply VAD2O to a third voltage value, and the second precharge power supply VAD2E to a fourth voltage value, and perform a bit line stress test operation; wherein the first voltage value and the second voltage value are different, and the third voltage value and the fourth voltage value are different. For example, the first voltage value is a high level and the second voltage value is a low level, or vice versa; the third voltage value is a high level and the fourth voltage value is a low level, or vice versa.

[0083] At the same time, during the bit line stress test operation, all first test switches 13 are in a closed state, the isolation switches and depolarization switches between the memory array slices at the head and tail positions and the adjacent readout amplifier modules are in an off state, and the remaining isolation switches, the remaining depolarization switches and all pre-charge switches are in a closed state.

[0084] Assume that the first voltage value=the third voltage value=the high level, the second voltage value=the fourth voltage value=the low level, and take the memory structure shown in FIG7 as an example for specific description:

[0085] Thus, on the one hand, the isolation switches and depolarization switches between the memory array chips at non-head and tail positions and the adjacent sense amplifier modules are all in a closed state, so that the bit lines therein are electrically connected to their respective pre-charge sources via the corresponding sense amplifiers. Specifically:

[0086] (1) In the odd-numbered memory array slices (e.g., memory array slices 11_3, 11_5, ..., 11_63) that are not at the first or last position, the first bit lines BLa are all at a low level (precharged by VAD2E), and the second bit lines BLb are all at a high level (precharged by VAD2O);

[0087] (2) For even-numbered memory array slices (e.g., memory array slices 11_2, 11_4, ..., 11_64) that are not at the first or last position, the first bit lines BLa are all at a high level (precharged by VAD2O), and the second bit lines BLb are all at a low level (precharged by VAD2E).

[0088] On the other hand, since the isolation switches and depolarization switches between the first and last memory array chips and the adjacent sense amplifier modules are in the off state, the first bit lines BLa of the first and last memory array chips are not connected to the corresponding precharge power sources; however, since all the first test switches 13 are turned on, the first bit lines BLa of the first and last memory array chips are connected to the corresponding test power sources; specifically:

[0089] (3) For the memory array chips 11_1 and 11_65, the odd-numbered first bit line BLao and the second bit line BLbo electrically connected thereto are both at a high level (precharged by VAD2Eedge); the even-numbered first bit line BLa and the second bit line BLb electrically connected thereto are both at a low level (precharged by VAD2OEdge).

[0090] In this way, by simply controlling the voltage value of each power supply terminal and the working state of the corresponding switch, adjacent bit lines in all memory array slices can be set to different level values, thereby conveniently performing a bit line stress test.

[0091] In some embodiments, the memory 10 is further configured to control the first edge test power supply VAD2Eedge to the second voltage value, the second edge test power supply VAD2Oedge to the first voltage value, the first pre-charge source VAD2O to the fourth voltage value, the second pre-charge source VAD2E to the third voltage value, and perform a bit line stress test operation.

[0092] Assume that the first voltage value=the third voltage value=the high level, the second voltage value=the fourth voltage value=the low level, and take the memory structure shown in FIG7 as an example for specific description:

[0093] (4) In the odd-numbered memory array slices (e.g., memory array slices 11_3, 11_5, ..., 11_63) that are not at the first or last position, the first bit lines BLa are all at a high level (precharged by VAD2E), and the second bit lines BLb are all at a low level (precharged by VAD2O);

[0094] (5) For the memory array slices that are not at the first or last position and have even numbers (e.g., memory array slices 11_2, 11_4, ..., 11_64), the first bit lines BLa are all at a low level (by VAD2O), and the second bit lines BLb are all at a high level (by VAD2E).

[0095] (6) For the memory array chips 11_1 and 11_65, the odd-numbered first bit lines BLa and the second bit lines BLb electrically connected thereto are both at a low level (precharged by VAD2Eedge); the even-numbered first bit lines BLa and the second bit lines BLb electrically connected thereto are both at a high level (precharged by VAD2OEdge).

[0096] In this way, by dividing the precharge power source into two groups for management and additionally providing separate test power sources for the bit lines in the memory array slices at the head and tail positions, the bit line stress test can be efficiently implemented.

[0097] To implement the above-mentioned test method, please refer to FIG6 , the gate of the first depolarization switch 31 and the gate of the second depolarization switch 33 are connected to different control signals OcEnb and OcEna, respectively, and the gate of the first isolation switch 32 and the gate of the second isolation switch 34 are connected to different control signals Isob and Isoa, respectively.

[0098] 6 and 7 , it can be seen that the sense amplifier module 12_1 is connected to the memory array chip 11_1 via the first depolarization switch 31 and the first isolation switch 32, but the sense amplifier module 12_64 is connected to the memory array chip 11_65 via the second depolarization switch 33 and the second isolation switch 34. To more conveniently implement the above-described testing method, in a specific embodiment, by changing certain definitions (for example, changing the definitions of the first bit line BLa and the second bit line BLb in the last and second-to-last memory array chips, or changing the definitions of the depolarization switch and the isolation switch in the sense amplifier module 12_64), the sense amplifier module 12_64 is connected to the memory array chip 11_65 via the first depolarization switch 31 and the first isolation switch 32.

[0099] That is, the bit lines in the memory array slices at the head and tail positions are connected to the adjacent sense amplifier modules via the first depolarization switch 31 or the first isolation switch 32. Therefore, it is only necessary to turn off the first depolarization switch 31 and the first isolation switch 32 corresponding to the sense amplifier module 12_1 and the sense amplifier module 12_64 to electrically isolate the memory array slices at the head and tail positions from the adjacent sense amplifier Sa. At this point, referring to FIG. 7 , the memory 10 further includes a command control circuit (not shown in FIG. 8 ), a first preprocessing circuit 50, and a second preprocessing circuit 60. Specifically,

[0100] a command control circuit configured to generate a test enable signal, an initial isolation signal IsoPre, and an initial depolarization signal OcPre; wherein, when the memory 10 is instructed to perform a bit line stress test operation, the test enable signal, the initial isolation signal IsoPre, and the initial depolarization signal OcPre are all in a valid state;

[0101] The first pre-processing circuit 50 is configured to generate a first edge isolation signal IsobEdge and a second edge isolation signal IsoaEdge based on the edge test parameter group TmEdge<1:0> and the initial isolation signal IsoPre; and to generate a first edge depolarization signal OcEnbEdge and a second edge depolarization signal OcEnaEdge based on the edge test parameter group TmEdge<1:0> and the initial depolarization signal OcPre;

[0102] The second pre-processing circuit 60 is configured to generate a first internal isolation signal IsobInter and a second internal isolation signal IsoaInter based on the internal test parameter group TmInter<1:0> and the initial isolation signal IsoPre; and to generate a first internal depolarization signal OcEnbInter and a second internal depolarization signal OcEnaInter based on the internal test parameter group TmInter<1:0> and the initial depolarization signal OcPre;

[0103] Among them, the test enable signal is used to control all the first test switches 13; at the same time, (1) the first edge isolation signal IsobEdge is used to control the first isolation switch 32 between the readout amplifier modules at the head and tail positions and the storage array slices at the head and tail positions; (2) the second edge isolation signal IsoaEdge is used to control the second isolation switch 34 between the readout amplifier modules at the head and tail positions and the storage array slices at non-head and tail positions; (3) the first edge depolarization signal OcEnbEdge is used to control the first depolarization switch 31 between the readout amplifier modules at the head and tail positions and the storage array slices at the head and tail positions; (4) the second edge depolarization signal OcEnaEdge is used to control the readout amplifier modules at the head and tail positions and the storage array slices at non-head and tail positions. The second depolarization switch 33 between the array slices; (5) the first internal isolation signal IsobInter is used to control the first isolation switch 32 between the readout amplifier module at the non-head and tail positions and the adjacent storage array slice; (6) the second internal isolation signal IsoaInter is used to control the second isolation switch 34 between the readout amplifier module at the non-head and tail positions and the adjacent storage array slice; (7) the first internal depolarization signal OcEnbInter is used to control the first depolarization switch 31 between the readout amplifier module at the non-head and tail positions and the adjacent storage array slice; (8) the second internal depolarization signal OcEnaInter is used to control the second depolarization switch 33 between the readout amplifier module at the non-head and tail positions and the adjacent storage array slice.

[0104] In this way, the bit lines in the storage array chip are divided into two categories. During the bit line stress test, the first pre-charge source VAD2O and the second pre-charge source VAD2E are used to charge the two consecutive first bit lines BLa and the second bit line BLb in the storage array chips at non-head and tail positions respectively. The first edge test power supply VAD2Eedge and the second edge test power supply VAD2Oedge are used to charge the two adjacent first bit lines BLa (and their respective electrically connected second bit lines BLb) in the storage array chips at the head and tail positions respectively. This can make the adjacent bit lines of the entire storage array chip be in different voltage states, and the bit line stress test can be completed efficiently, saving energy consumption and avoiding the problems of bit line overcharging and excessive pressure.

[0105] In a specific embodiment, as shown in FIG8 , the edge test parameter group includes at least a first test parameter TmEdge <0> , the second test parameter TmEdge <1> , the internal test parameter group includes at least the third test parameter TmInter <0> And the fourth test parameter TmInter <1> .

[0106] If the second test parameter TmEdge <1> In the first state, the first edge isolation signal IsobEdge and the first edge depolarization signal OcEnbEdge correspond to the initial isolation signal IsoPre and the initial depolarization signal OcPre in the same level; if the second test parameter TmEdge <1> In the second state, the first edge isolation signal IsobEdge and the first edge depolarization signal OcEnbEdge are both invalid;

[0107] If the first test parameter TmEdge <0> In the first state, the second edge isolation signal IsoaEdge and the second edge depolarization signal OcEnaEdge have the same level as the initial isolation signal IsoPre and the initial depolarization signal OcPre. If the first test parameter TmEdge <0> In the second state, the second edge isolation signal IsoaEdge and the second edge depolarization signal OcEnaEdge are both invalid;

[0108] If the fourth test parameter TmInter <1> In the first state, the first internal isolation signal IsobInter and the first internal depolarization signal OcEnbInter correspond to the initial isolation signal IsoPre and the initial depolarization signal OcPre in the same level; if the fourth test parameter TmInter <1> In the second state, the first internal isolation signal IsobInter and the first internal depolarization signal OcEnbInter are both invalid;

[0109] If the third test parameter TmInter <0> In the first state, the second internal isolation signal IsoaInter and the second internal depolarization signal OcEnaInter correspond to the initial isolation signal IsoPre and the initial depolarization signal OcPre in the same level; if the third test parameter TmInter <0> In the second state, the second internal isolation signal IsoaInter and the second internal depolarization signal OcEnaInter are both invalid.

[0110] When the memory is instructed to perform a bit line stress test operation, the second test parameter TmEdge <1> In the second state, the first test parameter TmEdge <0> , the third test parameter TmInter <0> And the fourth test parameter TmInter <1> All are in the first state.

[0111] It should be noted that, for the above isolation signal, depolarization signal and pre-charge signal, when they are invalid, the corresponding switches are in the off state; when they are valid, the corresponding switches are in the on state.

[0112] A specific working scenario is provided: the first isolating switch 32, the second isolating switch 34, the first depolarization switch 31, and the second depolarization switch 33 are all N-type field effect transistors, effective refers to a high-level state, and invalid refers to a low-level state.

[0113] Then, during the bit line stress test operation, TmEdge<1:0>=01, TmInter<1:0>=11, therefore, the first edge isolation signal IsobEdge=the first edge depolarization signal OcEnbEdge=0, and the second edge isolation signal IsoaEdge=the second edge depolarization signal OcEnaEdge=1, so that the sense amplifier module 12_1 is electrically isolated from the memory array chip 11_1, and the sense amplifier module 12_64 is electrically isolated from the memory array chip 11_65, that is, the bit lines in the memory array chips at the head and tail positions are electrically isolated from the corresponding pre-charge power sources; however, the sense amplifier module 12_1 is electrically connected to the memory array chip 11_2, the sense amplifier module 12_64 is electrically connected to the memory array chip 11_64, and the sense amplifier modules 12_2 to 12_63 in the middle part are each electrically connected to the memory array chips on both sides, so that the bit lines in the memory array chips other than the head and tail positions are electrically connected to the corresponding pre-charge power sources.

[0114] In the above scenario, referring to FIG8 , the first pre-processing circuit 50 includes:

[0115] The first AND gate 501, whose two input terminals receive the first test parameter TmEdge <0> and an initial isolation signal IsoPre, and an output terminal thereof outputs a second edge isolation signal IsoaEdge;

[0116] The second AND gate 502, whose two input terminals receive the second test parameter TmEdge <1> and an initial isolation signal IsoPre, and an output terminal thereof outputs a first edge isolation signal IsobEdge;

[0117] The third AND gate 503, whose two input terminals receive the first test parameter TmEdge <0> and an initial depolarization signal OcPre, and an output end thereof outputs a second edge depolarization signal OcEnaEdge;

[0118] The fourth AND gate 504 has two input terminals receiving the second test parameter TmEdge <1> and an initial depolarization signal OcPre, and an output terminal thereof outputs a first edge depolarization signal OcEnbEdge;

[0119] The second pre-processing circuit 60 includes:

[0120] The fifth AND gate 601, whose two input terminals receive the third test parameter TmInter respectively <0> and an initial isolation signal IsoPre, and an output terminal thereof outputs a second internal isolation signal IsoaInter;

[0121] The sixth AND gate 602, whose two input terminals receive the fourth test parameter TmInter respectively <1> and an initial isolation signal IsoPre, and an output terminal thereof outputs a first internal isolation signal IsobInter;

[0122] The seventh AND gate 603, whose two input terminals receive the third test parameter TmInter respectively <0> and an initial depolarization signal OcPre, and an output terminal thereof outputs a second internal depolarization signal OcEnaInter;

[0123] The eighth AND gate 604 has two input terminals receiving the fourth test parameter TmInter <1> and the initial depolarization signal OcPre, and its output end outputs the first internal depolarization signal OcEnbInter.

[0124] In another specific embodiment, please refer to Figures 6 and 7, the read-out amplifier module 12_1 is connected to the storage array chip 11_1 through the first depolarization switch 31 and the first isolation switch 32, but the read-out amplifier module 12_64 is connected to the storage array chip 11_65 through the second depolarization switch 33 and the second isolation switch 34.

[0125] That is, the bit lines in the first memory array slice 11_1 are electrically connected to the adjacent sensitive amplifier modules via a first depolarization switch or a first isolation switch, while the bit lines in the last memory array slice 11_65 are electrically connected to the first and last sensitive amplifier modules via a second depolarization switch or a second isolation switch. Referring to FIG. 9 , memory 10 further includes a command control circuit, a second preprocessing circuit 50 , a third preprocessing circuit 70 , and a fourth preprocessing circuit 80 .

[0126] A command control circuit (not shown in FIG9 ) is configured to generate a test enable signal, an initial isolation signal IsoPre, and an initial depolarization signal OcPre; wherein, when the memory is instructed to perform a stress test operation, the test enable signal, the initial isolation signal IsoPre, and the initial depolarization signal OcPre are all in a valid state;

[0127] The second pre-processing circuit 60 is configured to generate a first internal isolation signal IsobInter and a second internal isolation signal IsoaInter based on the internal test parameter group TmInter<1:0> and the initial isolation signal IsoPre; and to generate a first internal depolarization signal OcEnbInter and a second internal depolarization signal OcEnaInter based on the internal test parameter group and the initial depolarization signal OcPre;

[0128] The third pre-processing circuit 70 is configured to generate a first head-end isolation signal IsobEdge0 and a second head-end isolation signal IsoaEdge0 based on the head-end test parameter group TmEdge0<1:0> and the initial isolation signal IsoPre; and to generate a first head-end depolarization signal OcEnbEdge0 and a second head-end depolarization signal OcEnaEdge0 based on the head-end test parameter group and the initial depolarization signal OcPre;

[0129] The fourth pre-processing circuit 80 is configured to generate a first tail end isolation signal IsobEdge1 and a second tail end isolation signal IsoaEdge1 based on the tail end test parameter group TmEdge1<1:0> and the initial isolation signal IsoPre; and to generate a first tail end depolarization signal OcEnbEdge1 and a second tail end depolarization signal OcEnaEdge1 based on the tail end test parameter group and the initial depolarization signal OcPre;

[0130] Among them, all the test switches 13 are controlled by the test enable signal, and the first isolation switch, the second isolation switch, the first depolarization switch, and the second depolarization switch between the first readout amplifier module 11_1 and the adjacent storage array chip are controlled one by one by the first head end isolation signal IsobEdge0, the second head end isolation signal IsoaEdge0, the first head end depolarization signal OcEnbEdge0, and the second head end depolarization signal OcEnaEdge0; the first isolation switch 31, the second isolation switch 33, the first depolarization switch 32, and the second depolarization switch 34 between the last readout amplifier module 11_65 and the adjacent storage array chip are controlled one by one by The first tail end isolation signal IsobEdge1, the second tail end isolation signal IsoaEdge1, the first tail end depolarization signal OcEnbEdge1, and the second edge tail end depolarization signal; an isolation switch 31, a second isolation switch 33, a first depolarization switch 32, and a second depolarization switch 34 between the readout amplifier modules (11_2, 11_3...11_64) at non-head and tail positions and the adjacent memory array chips are controlled one by one by the first internal isolation signal IsobInter, the second internal isolation signal IsoaInter, the first internal depolarization signal OcEnbInter, and the second internal depolarization signal OcEnaInter.

[0131] In some embodiments, the internal test parameter group includes at least a third test parameter TmInter <0> And the fourth test parameter TmInter <1> ; The first end test parameter group includes the fifth test parameter TmEdge0 <0> The sixth test parameter TmEdge0 <1> , the tail end test parameter group includes the seventh test parameter TmEdge1 <0> and the eighth test parameter TmEdge1 <1> ;

[0132] If the third test parameter TmInter <0> In the first state, the second internal isolation signal IsoaInter and the second internal depolarization signal OcEnaInter correspond to the initial isolation signal IsoPre and the initial depolarization signal OcPre in the same level; if the third test parameter TmInter <0> In the second state, the second internal isolation signal IsoaInter and the second internal depolarization signal OcEnaInter are both invalid;

[0133] If the fourth test parameter TmInter <1> In the first state, the first internal isolation signal IsobInter and the first internal depolarization signal OcEnbInter correspond to the initial isolation signal IsoPre and the initial depolarization signal OcPre in the same level; if the fourth test parameter TmInter <1> In the second state, the first internal isolation signal IsobInter and the first internal depolarization signal OcEnbInter are both invalid;

[0134] If the fifth test parameter TmEdge0 <0> In the first state, the second head-end isolation signal IsoaEdge0 and the second head-end deflection signal OcEnaEdge0 correspond to the initial isolation signal IsoPre and the initial deflection signal OcPre in the same level; if the fifth test parameter TmEdge0 <0> In the second state, the second head-end isolation signal IsoaEdge0 and the second head-end depolarization signal OcEnaEdge0 are both invalid;

[0135] If the sixth test parameter TmEdge0 <1> In the first state, the first head-end isolation signal IsobEdge0 and the first head-end deflection signal OcEnbEdge0 correspond to the initial isolation signal IsoPre and the initial deflection signal OcPre in the same level; if the sixth test parameter TmEdge0 <1> In the second state, the first head-end isolation signal IsobEdge0 and the first head-end deflection signal OcEnbEdge0 are both invalid;

[0136] If the seventh test parameter TmEdge1 <0> In the first state, the second tail end isolation signal IsoaEdge1 and the second tail end deflection signal OcEnaEdge1 correspond to the initial isolation signal IsoPre and the initial deflection signal OcPre in the same level; if the seventh test parameter TmEdge1 <0> In the second state, the second tail end isolation signal IsoaEdge1 and the second tail end depolarization signal OcEnaEdge1 are both invalid;

[0137] If the eighth test parameter TmEdge1 <1> In the first state, the first tail end isolation signal IsobEdge1 and the first tail end deflection signal OcEnbEdge1 correspond to the initial isolation signal IsoPre and the initial deflection signal OcPre in the same level; if the eighth test parameter TmEdge1 <1> In the second state, the first tail end isolation signal IsobEdge1 and the first tail end debiasing signal OcEnbEdge1 are both invalid;

[0138] In the process where the memory is instructed to perform the bit line stress test operation, the sixth test parameter TmEdge0 <1> And the seventh test parameter TmEdge1 <0> For the second state, the third test parameter TmInter <0> , the fourth test parameter TmInter <1> , the fifth test parameter TmEdge0 <0> 、The eighth test parameter TmEdge1 <1> All are in the first state.

[0139] Specifically, during the execution of the bit line stress test operation, TmEdge0<1:0>=01, TmInter<1:0>=11, TmEdge1<1:0>=10, therefore, the sense amplifier module 12_1 is electrically isolated from the storage array chip 11_1, and the sense amplifier module 12_64 is electrically isolated from the storage array chip 11_65, but the sense amplifier module 12_1 is electrically connected to the storage array chip 11_2, and the sense amplifier module 12_64 is electrically connected to the storage array chip 11_64; the sense amplifier modules 12_2 to 12_63 are each electrically connected to the storage array chips on both sides; thus, the bit lines in the storage array chips at non-head and tail positions can all be precharged by the precharge power source, but the bit lines in the storage array chips at the head and tail positions cannot be precharged by the precharge power source, but are charged via the edge test power supply.

[0140] In the above scenario, the structure of the second pre-processing circuit 60 is also as shown in FIG8 and will not be described in detail.

[0141] Referring to FIG9 , the third pre-processing circuit 70 includes:

[0142] The ninth AND gate 701, whose two input terminals receive the fifth test parameter TmEdge0 respectively. <0> and the initial isolation signal IsoPre, and its output end outputs the second first-end isolation signal IsoaEdge0;

[0143] The tenth AND gate 702, whose two input terminals receive the sixth test parameter TmEdge0 respectively. <1> and the initial isolation signal IsoPre, and its output end outputs the first head-end isolation signal IsobEdge0;

[0144] The eleventh AND gate 703, whose two input terminals receive the fifth test parameter TmEdge0 respectively. <0> and the initial depolarization signal OcPre, and the output end thereof outputs the second first-end depolarization signal OcEnaEdge0;

[0145] The twelfth AND gate 704 has two input terminals receiving the sixth test parameter TmEdge0 <1> and the initial depolarization signal OcPre, and the output end thereof outputs the first head-end depolarization signal OcEnbEdge0;

[0146] In this scenario, referring to FIG8 , the fourth pre-processing circuit 80 includes:

[0147] The thirteenth AND gate 801 has two input terminals receiving the seventh test parameter TmEdge1 <0> and the initial isolation signal IsoPre, and the output end thereof outputs the second tail end isolation signal IsoaEdge1;

[0148] The fourteenth AND gate 802 has two input terminals receiving the eighth test parameter TmEdge1 <1> and an initial isolation signal IsoPre, and an output end thereof outputs a first tail end isolation signal IsobEdge1;

[0149] The fifteenth AND gate 803 has two input terminals receiving the seventh test parameter TmEdge1 <0> and the initial depolarization signal OcPre, and the output end thereof outputs the second tail end depolarization signal OcEnaEdge1;

[0150] The sixteenth AND gate 804 has two input terminals receiving the eighth test parameter TmEdge1 <1> and the initial depolarization signal OcPre, and its output end outputs the first tail depolarization signal OcEnbEdge1.

[0151] In summary, the embodiments of the present disclosure provide a memory that reduces the area of ​​the memory array slice located at the edge to half the area of ​​other memory array slices; at the same time, the pre-charge power supply is divided into two groups for management, and a separate edge test power supply is additionally provided for the bit lines in the memory array slices at the head and tail positions, which can efficiently implement bit line stress testing, improve the test process of the memory of this structure, and ensure factory performance.

[0152] In a second specific embodiment, for non-first and last memory array slices (11_2, 11_3, ..., 11_64), the bit lines therein are also coupled to their respective precharge sources via a column select switch and a second test switch. For first and last memory array slices (11_1, 11_65), the first bit lines therein are also coupled to their respective precharge sources via a column select switch and a second test switch. In other words, only when both the column select switch and the second test switch are turned on is the first bit line electrically connected to its own precharge source. For each memory array slice, the precharge source coupled to each bit line serves as a stress test power supply.

[0153] The following are specific instructions.

[0154] Please refer to Figure 10. The memory 10 includes two groups of pre-charge sources, namely a first pre-charge source VAD2O and a second pre-charge source VAD2E.

[0155] At the same time, in one possibility, for all storage array slices, each bit line is coupled to the first pre-charge source VAD2O through its own pre-charge switch 35, but one type of bit line is connected to the first pre-charge source VAD2O through the column selection switch + the second test switch, and another type of bit line is connected to the second pre-charge source VAD2E through the column selection switch + the second test switch. In this way, during the stress test, the pre-charge switch 35 is disconnected, and the column selection switch + the second test switch are both closed, so that one of the two adjacent bit lines (in the internal array slice) (or the two consecutively numbered first bit lines in the first and last array slices) is pre-charged by the first pre-charge source VAD2O, and the other is pre-charged by the second pre-charge source VAD2E; during normal operation, the pre-charge switch 35 is closed, the second test switch is disconnected, and all bit lines are pre-charged by the first pre-charge source VAD2O, thereby realizing a normal pre-charge function.

[0156] Similarly, in another possibility, for all memory array slices, each bit line is coupled to the second pre-charge source VAD2E through its own pre-charge switch 35; or, in another possibility, some bit lines are coupled to the first pre-charge source VAD2O through their own pre-charge switches 35, and the remaining bit lines are coupled to the second pre-charge source VAD2E through their own pre-charge switches 35, such as the situation described in the previous embodiment.

[0157] Please refer to Figures 6 and 10. In addition to being coupled to the corresponding pre-charge source through the pre-charge switch 35, each bit line is also coupled to the pre-charge source through the column enable switch 38+the second test switch 14; at the same time, during the stress test, the pre-charge switch 35 is turned off, and the column enable switch 38+the second test switch 14 are both closed. At this time, the first pre-charge source VAD2O and the second pre-charge source VAD2E can be used as stress test power supplies TXo and TXe, respectively.

[0158] Specifically, for the non-first and last positions of the storage array slices (11_2, 11_3...11_64), the bit lines therein are all coupled to their respective local data lines (IO / ION) via their respective column selection switches 38; wherein: (1) for the second bit line BLb in the non-first and last positions and odd-numbered storage array slices (11_3, 11_5...11_63) and the first bit line BLa of the even-numbered storage array slices (11_2, 11_4...11_64), the coupled local data lines are also connected to the first pre-charge source VAD2O through their respective second test switches 14; (2) for the first bit line BLa in the non-first and last positions and odd-numbered storage array slices (11_3, 11_5...11_63) and the second bit line BLb of the even-numbered storage array slices (11_2, 11_4...11_65), the coupled local data lines are also connected to the second pre-charge source VAD2E through their respective second test switches 14.

[0159] At the same time, for the memory array slices (11_1, 11_65) at the first and last positions, the first bit lines therein are coupled to the respective local data lines via the respective column selection switches.

[0160] In one case, referring to FIG10 , (1) for the memory array slices (11_1, 11_65) at the head and tail positions, the local data line coupled to the odd-numbered first bit line BLao is coupled to the second pre-charge source VAD2E via the second test switch 14, and the local data line coupled to the even-numbered second bit line BLae is coupled to the first pre-charge source VAD2O via the second test switch 14.

[0161] In another case, for the first memory array slice 11_1, the local data line coupled to the odd-numbered first bit line BLao is coupled to the second pre-charge source VAD2E via the second test switch 14, and the local data line coupled to the even-numbered first bit line BLae is coupled to the first pre-charge source VAD2O via the second test switch 14; and, for the last memory array slice 11_65, the local data line coupled to the odd-numbered first bit line BLao is coupled to the first pre-charge source VAD2O via the second test switch 14, and the local data line coupled to the even-numbered first bit line BLae is coupled to the second pre-charge source VAD2E via the second test switch 14.

[0162] Simply put, for the first and last memory array slices, the precharge source to which the first bit line is connected via precharge switch 35 and the precharge source to which the first bit line is connected via column select switch 38 + second test switch 14 may not be the same precharge source. Consider a scenario where all first bit lines BLa in memory array slice 11_1 are connected to first precharge source VAD2O via precharge switch 35, but Blao in memory array slice 11_1 is coupled to second precharge source VAD2E via column select switch 38 + second test switch 14, and Blae is coupled to first precharge source VAD2O via column select switch 38 + second test switch 14. This is just one possible scenario. Furthermore, during a bitline stress test, all bit lines are connected to their corresponding precharge sources via column select switch 38 + second test switch 14, but the precharge switches are closed. During a normal precharge operation, all bit lines are connected to their corresponding precharge sources via precharge switches, but the column select switch 38 + second test switch 14 are closed.

[0163] Based on the structure of FIG10 , the process of the memory 10 performing BL stress on the memory array slices at non-head and tail positions is as follows:

[0164] The memory 10 is configured to control all isolation switches, debiasing switches, and precharge switches to be in an off state, control all column selection switches and a second test switch to be in a closed state, and control the first precharge source to be at a first voltage value and the second precharge source to be at a second voltage value, so as to perform a bit line stress test;

[0165] Thus, during the bit line stress test, all bit lines are connected to the corresponding precharge source via the column select switch 38 + the second test switch 14. Assuming that the first voltage value = the third voltage value = a high level (e.g., 1.55V), and the second voltage value = the fourth voltage value = a low level (e.g., 0V), refer to FIG. 10 , specifically:

[0166] (1) In the odd-numbered memory array slices (e.g., memory array slices 11_3, 11_5, ..., 11_63) that are not at the first or last position, the first bit lines BLa are all at a low level (precharged by VAD2E), and the second bit lines BLb are all at a high level (precharged by VAD2O);

[0167] (2) For even-numbered memory array slices (e.g., memory array slices 11_2, 11_4, ..., 11_64) that are not at the first or last position, the first bit lines BLa are all at a high level (precharged by VAD2O), and the second bit lines BLb are all at a low level (precharged by VAD2E).

[0168] (3) For the memory array chips 11_1 and 11_65, the odd-numbered first bit lines BLao and the second bit lines BLbo electrically connected thereto are both at a low level (precharged by VAD2E); the even-numbered first bit lines BLa and the second bit lines BLb electrically connected thereto are both at a high level (precharged by VAD2O).

[0169] In addition, the memory 10 is also configured to control all isolation switches, debiasing switches and pre-charge switches to be in the off state, control all column selection switches and the second test switch to be in the closed state, and control the first pre-charge source to be the second voltage value and the second pre-charge source to be the first voltage value to perform another bit line stress test.

[0170] Assume that the first voltage value = the third voltage value = a high level, and the second voltage value = the fourth voltage value = a low level, referring to FIG10 , specifically:

[0171] (4) In the odd-numbered memory array slices (e.g., memory array slices 11_3, 11_5, ..., 11_63) that are not at the first or last position, the first bit lines BLa are all at a high level (precharged by VAD2E), and the second bit lines BLb are all at a low level (precharged by VAD2O);

[0172] (5) For the memory array slices that are not at the first or last position and have even numbers (e.g., memory array slices 11_2, 11_4, ..., 11_64), the first bit lines BLa are all at a low level (precharged by VAD2O), and the second bit lines BLb are all at a high level (precharged by VAD2E);

[0173] (6) For the memory array chips 11_1 and 11_65, the odd-numbered first bit lines BLao and the second bit lines BLbo electrically connected thereto are both at a high level (precharged by VAD2E); the even-numbered first bit lines BLa and the second bit lines BLb electrically connected thereto are both at a low level (precharged by VAD2O).

[0174] An embodiment of the present disclosure provides a memory in which each bit line is further connected to a precharge source via a column selection switch and a second test switch to serve as a stress test power supply. On the one hand, this allows efficient bit line stress testing, improves the test process of the memory structure, and ensures factory performance. On the other hand, it eliminates the need to provide two separate sets of edge test power supplies for the memory array slices at the head and tail positions, thereby reducing circuit area.

[0175] In a third specific embodiment, for the memory array slices (11_2, 11_3...11_64) at non-head and tail positions, the bit lines therein are also coupled to their respective preset test power supplies through the column selection switch 38 and the second test switch 14; for the memory array slices (11_1, 11_65) at the head and tail positions, the first bit lines therein are also coupled to their respective preset test power supplies through the column selection switch and the second test switch; for each memory array slice, the preset test power supply coupled to each bit line is used as a stress test power supply.

[0176] That is, in addition to the pre-charge power supply, the memory 10 is also provided with two sets of preset test power supplies, namely the first preset test power supply Vintlp2o and the second preset test power supply Vintlp2o, which are used as stress test power supplies TXo and TXe respectively.

[0177] The following are specific instructions.

[0178] Please refer to Figures 6 and 11. For the non-first and last position memory array slices (11_2, 11_3 ... 11_64), each bit line therein is coupled to its own local data line (IO / ION) via its own column selection switch 38; (1) for the second bit line BLb in the non-first and last position and odd numbered memory array slices (11_3, 11_5 ... 11_63) and the first bit line BLb in the non-first and last position and even numbered memory array slices (11_2, 11_4 ... 11_64), A first bit line BLa, the local data line coupled thereto is coupled to the first preset test power Vintlp2o via the second test switch 14; (2) for the first bit line BLa in the odd-numbered memory array slices (11_3, 11_5...11_63) that are not at the head or tail position and the second bit line BLb in the even-numbered memory array slices (11_2, 11_4...11_65), the local data line coupled thereto is coupled to the second preset test power Vintlp2e via the second test switch 14.

[0179] At the same time, for the first and last memory array slices (11_1, 11_65), the first bit lines therein are coupled to the respective local data lines via respective column selection switches; wherein:

[0180] In one case, see Figure 11, (1) for the memory array slices (11_1, 11_65) at the head and tail positions, the local data line coupled to the odd-numbered first bit line BLao is coupled to the second preset test power Vintlp2e via the second test switch 14, and the local data line coupled to the even-numbered second bit line BLae is coupled to the first preset test power Vintlp2o via the second test switch 14.

[0181] In another case, for the first memory array chip 11_1, the local data line coupled to the odd-numbered first bit line BLao is coupled to the second preset test power supply Vintlp2e via the second test switch 14, and the local data line coupled to the even-numbered first bit line BLae is coupled to the first preset test power supply Vintlp2o via the second test switch 14; and, for the last memory array chip 11_65, the local data line coupled to the odd-numbered first bit line BLao is coupled to the first preset test power supply Vintlp2o via the second test switch 14, and the local data line coupled to the even-numbered first bit line BLae is coupled to the second preset test power supply Vintlp2e via the second test switch 14.

[0182] Exemplarily, the first preset test power supply can be the pre-charge power supply of the local data line IO, and the second preset test power supply can be the pre-charge power supply of the local data line ION, without adding an additional independent power supply, thus saving circuit area.

[0183] Based on the structure of FIG11 , the process of the memory 10 performing BL stress on the memory array slices at non-head and tail positions is as follows:

[0184] The memory 10 is configured to control all the isolation switches and the debiasing switches to be in the off state, control all the pre-charge switches to be in the closed state, and control the pre-charge power supply VAD to be the fifth voltage value; control all the column selection switches and the second test switch to be in the closed state, and control the first preset test power supply to be the first voltage value and the second preset test power supply to be the second voltage value to perform a bit line stress test.

[0185] It should be noted that the fifth voltage value is between the first voltage value and the second voltage value. Thus, the first voltage value can be a high level (e.g., 1.55V), the second voltage value can be a low level (e.g., 0V), and the fifth voltage value can be 0.5V. Thus, during the bit line stress test, the pull-up unit NCS and the pull-down unit PCS are precharged to 0.5V by the precharge source VAD via the precharge switch 38, so that the sense amplifier SA is not over-stressed.

[0186] Under the above voltage conditions, as shown in Figure 11,

[0187] (1) In the odd-numbered memory array slices (e.g., memory array slices 11_3, 11_5, ..., 11_63) that are not at the first or last position, the first bit lines BLa are all at a low level (precharged by Vintlp2e), and the second bit lines BLb are all at a high level (precharged by Vintlp2o).

[0188] (2) For the memory array slices that are not at the first or last position and have even numbers (e.g., memory array slices 11_2, 11_4, ..., 11_64), the first bit lines BLa are all at a high level (precharged by Vintlp2o), and the second bit lines BLb are all at a low level (precharged by Vintlp2e);

[0189] (3) For the memory array chips 11_1 and 11_65, the odd-numbered first bit lines BLao and the second bit lines BLbo electrically connected thereto are both at a low level (precharged by Vintlp2e); the even-numbered first bit lines BLae and the second bit lines BLbe electrically connected thereto are both at a high level (precharged by Vintlp2o).

[0190] In addition, the memory 10 is further configured to control all isolation switches and debiasing switches to be in an off state, control all precharge switches to be in a closed state, and control the precharge power supply to be a fifth voltage value; control all column selection switches and the second test switch to be in a closed state, and control the first preset test power supply to be the second voltage value and the second preset test power supply to be the first voltage value, so as to perform another bit line stress test;

[0191] Assume that the first voltage value = the third voltage value = high level, the second voltage value = the fourth voltage value = low level, and the fifth voltage value = 0.5V. Please refer to FIG11 . Specifically:

[0192] (4) In the odd-numbered memory array slices (e.g., memory array slices 11_3, 11_5, ..., 11_63) that are not at the first or last position, the first bit lines BLa are all at a high level (precharged by Vintlp2e), and the second bit lines BLb are all at a low level (precharged by Vintlp2o).

[0193] (5) For the memory array slices that are not at the first or last position and have even numbers (e.g., memory array slices 11_2, 11_4, ..., 11_64), the first bit lines BLa are all at a low level (precharged by Vintlp2o), and the second bit lines BLb are all at a high level (precharged by Vintlp2e).

[0194] (6) For the memory array chips 11_1 and 11_65, the odd-numbered first bit lines BLao and the second bit lines BLbo electrically connected thereto are both at a high level (precharged by Vintlp2e); the even-numbered first bit lines BLa and the second bit lines BLb electrically connected thereto are both at a low level (precharged by Vintlp2o).

[0195] Simply put, during the bit line stress test, all bit lines are connected to the corresponding preset test power supply through the column selection switch 38 + the second test switch 14, and the pre-charge switch is turned on, so that the pull-up module PCS and the pull-down module NCS are approximately 0.5V, avoiding excessive stress of the sensitive amplifier SA; in the conventional pre-charge operation, all bit lines are connected to the corresponding pre-charge source through the pre-charge switch, but the column selection switch 38 + the second test switch 14 is closed.

[0196] The disclosed embodiments provide a memory device that reduces the area of ​​a memory array chip located at an edge to half the area of ​​other memory array chips. In addition to a pre-charge source, two sets of preset test power supplies are provided, which can efficiently implement bit line stress testing, improve the test process of the memory device with this structure, and ensure factory performance.

[0197] In another embodiment of the present disclosure, a testing method is provided, which is applied to the aforementioned memory 10, wherein the memory 10 includes N memory array chips arranged in sequence along a first direction, the memory array chips include multiple first bit lines and multiple second bit lines, and the first bit lines and the second bit lines are alternately arranged along a second direction; for memory array chips at non-head and tail positions, the first bit line and the adjacent second bit line are electrically isolated; for memory array chips at the head and tail positions, the first bit line is electrically connected to the second bit line adjacent to the first side and the first bit line is electrically isolated from the second bit line adjacent to the second side.

[0198] For the convenience of explanation, the storage array slices are numbered along the first direction. For the odd-numbered storage array slices, the first bit line is the second bit line; for the even-numbered storage array slices, the first bit line is the first bit line; for each storage array slice, the first bit lines therein are numbered sequentially along the second direction, and the second bit lines therein are numbered sequentially along the second direction.

[0199] The method includes:

[0200] S901: During the execution of the bit line stress test operation, for the memory array slices at the first and last positions, each first bit line is charged using the stress test power supply corresponding to each first bit line; and for the memory array slices not at the first and last positions, each bit line is charged using the stress test power supply corresponding to each bit line; the above are performed simultaneously.

[0201] Among them, for the storage array slices at the head and tail positions, the voltage of the pressure test power supply corresponding to the odd-numbered first bit line is different from the voltage of the pressure test power supply corresponding to the even-numbered first bit line; for the storage array slices not at the head and tail positions, the voltage of the pressure test power supply corresponding to the first bit line is different from the voltage of the pressure test power supply corresponding to the adjacent second bit line.

[0202] In summary, for the aforementioned memory 10, the embodiment of the present disclosure also provides a testing method, which can make the adjacent bit lines of all memory array slices at different voltages through one step, and can efficiently implement bit line stress testing, improve the testing process of the memory of this structure, and ensure factory performance.

[0203] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0204] The serial numbers of the embodiments of the present disclosure are for descriptive purposes only and do not represent the merits of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments when there is no conflict. The features disclosed in the several product embodiments provided in the present disclosure can be arbitrarily combined to obtain new product embodiments when there is no conflict. The features disclosed in the several method or device embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments when there is no conflict.

[0205] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A memory (10), characterized in that: The memory comprises N memory array slices (11_1, 11_2...11_N) arranged in sequence along a first direction, where N is a natural number; each of the memory array slices comprises a plurality of first bit lines (Bla) and a plurality of second bit lines (Blb), and the first bit lines and the second bit lines are alternately arranged along a second direction; for the memory array slices (11_2...11_N-1) at non-head and tail positions, the first bit line and the adjacent second bit line are electrically isolated; for the memory array slices (11_1 and 11_N) at head and tail positions, the first bit line is electrically connected to the second bit line adjacent to the first side, and the first bit line is electrically isolated from the second bit line adjacent to the second side; the first side and the second side are two sides opposite to each other along the second direction; The memory array slices are numbered along a first direction; and in each of the memory array slices, the first bit lines are numbered along a second direction, and the second bit lines are numbered along the second direction; For the memory array slices at non-head and tail positions, each of the bit lines is coupled to a corresponding pressure test power supply, and the pressure test power supply corresponding to the first bit line is different from the pressure test power supply corresponding to the adjacent second bit line; For the memory array slices at the head and tail positions, the first bit lines therein are all coupled to corresponding stress test power supplies, and the stress test power supplies corresponding to the odd-numbered first bit lines are different from the stress test power supplies corresponding to the even-numbered first bit lines.

2. The memory (10) according to claim 1, characterized in that: The first bit line of the odd-numbered memory array slice is the second bit line, and the first bit line of the even-numbered memory array slice is the first bit line; A readout amplifier module is distributed between every two of the storage array chips, and the readout amplifier module includes a plurality of sensitive amplifiers (Sa) arranged in sequence along a second direction; a first end of the sensitive amplifier is connected to one of the second bit lines on the third side through a first depolarization switch (31), and a second end of the sensitive amplifier is connected to one of the second bit lines on the third side through a first isolation switch (32); The second end of the sensitive amplifier is also connected to one of the first bit lines on the fourth side through a second depolarization switch (33), and the first end of the sensitive amplifier is also connected to one of the first bit lines on the fourth side through a second isolation switch (34); the third side and the fourth side are opposite to each other along the first direction. Both sides; The first terminal or the second terminal of each of the sense amplifiers is also connected to a precharge source (VAD) through a corresponding precharge switch (35), so that each bit line is coupled to one of the precharge sources.

3. The memory (10) according to claim 2, characterized in that: For the memory array slices at non-head and tail positions, the precharge source coupled to the bit lines therein is used as the stress test power source; For the memory array slices at the head and tail positions, the first bit lines are also coupled to respective edge test power supplies through first test switches, and the edge test power supplies coupled to the first bit lines are used as the stress test power supplies.

4. The memory (10) according to claim 2, characterized in that: For the memory array slices not at the head or tail position, the bit lines therein are also coupled to the respective precharge sources through a column selection switch and a second test switch; For the memory array slices at the head and tail positions, the first bit lines are also coupled to the respective pre-charge sources through a column selection switch and a second test switch; For each of the memory array slices, the precharge source coupled to each bit line is used as the stress test power source.

5. The memory (10) according to claim 2, characterized in that For the memory array slices not at the head or tail, the bit lines therein are also coupled to respective preset test power supplies through a column selection switch and a second test switch; For the memory array slices at the head and tail positions, the first bit lines are also coupled to respective preset test power supplies through the column selection switch and the second test switch; For each of the memory array chips, the preset test power source coupled to each bit line is used as the stress test power source.

6. The memory (10) according to claim 3, characterized in that: Numbering the readout amplifier modules along a first direction; For the odd-numbered readout amplifier modules (12_1, 12_3, ..., 12_63), the first end or the second end of the sense amplifier is connected to the first precharge source through a corresponding precharge switch; for the even-numbered readout amplifier modules (12_1, 12_3, ..., 12_63), the first end or the second end of the sense amplifier is connected to the first precharge source through a corresponding precharge switch; The read-out amplifier modules (12_2, 12_4...12_64) are numbered, wherein the first end or the second end of the sensitive amplifier is connected to the second pre-charge source through a corresponding pre-charge switch, so that the stress test power supply corresponding to the first bit line is different from the stress test power supply corresponding to the adjacent second bit line.

7. The memory (10) according to claim 6, characterized in that For the memory array slices at the head and tail positions, the odd-numbered first bit lines are connected to the first edge test power supply (VAD2Eedge) via their respective first test switches (13), and the even-numbered first bit lines are connected to the second edge test power supply (VAD2Oedge) via their respective first test switches (13); or, For the first memory array slice, the odd-numbered first bit lines are connected to the first edge test power supply via their respective first test switches, and the even-numbered first bit lines are connected to the second edge test power supply via their respective first test switches; for the last memory array slice, the odd-numbered first bit lines are connected to the second edge test power supply via their respective first test switches, and the even-numbered first bit lines are connected to the first edge test power supply via their respective first test switches.

8. The memory (10) according to claim 7, characterized in that The memory is configured to control the first edge test power supply to a first voltage value, the second edge test power supply to a second voltage value, the first precharge power supply to a third voltage value, the second precharge power supply to a fourth voltage value, and perform a bit line stress test operation; as well as, Controlling the first edge test power supply to a second voltage value, the second edge test power supply to a first voltage value, the first precharge power supply to a fourth voltage value, the second precharge power supply to a third voltage value, and performing the bit line stress test operation; Wherein, the first voltage value is different from the second voltage value, and the third voltage value is different from the fourth voltage value; In the bit line stress test operation, all first test switches are in a closed state, the isolation switches and depolarization switches between the storage array chips at the head and tail positions and the adjacent read-out amplifier modules are in an off state, and the remaining isolation switches, the remaining depolarization switches and all pre-charge switches are in a closed state.

9. The memory (10) according to claim 8, characterized in that The bit lines in the memory array slices at the head and tail positions are electrically connected to the adjacent sensitive amplifier modules through the first depolarization switch or the first isolation switch; the memory further includes: A command control circuit configured to generate a test enable signal, an initial isolation signal and an initial depolarization signal; wherein, when the memory is instructed to perform the bit line stress test operation, the test enable signal, the initial isolation signal and the initial depolarization signal are all in a valid state; A first preprocessing circuit (50) is configured to generate a first edge isolation signal and a second edge isolation signal based on an edge test parameter group and the initial isolation signal; and to generate a first edge depolarization signal and a second edge depolarization signal based on the edge test parameter group and the initial depolarization signal; A second preprocessing circuit (60) is configured to generate a first internal isolation signal and a second internal isolation signal based on an internal test parameter group and the initial isolation signal; and to generate a first internal depolarization signal and a second internal depolarization signal based on the internal test parameter group and the initial depolarization signal; Among them, all the first test switches are controlled by the test enable signal, and the first isolation switch, the second isolation switch, the first depolarization switch, and the second depolarization switch between the read-out amplifier modules at the head and tail positions and the adjacent storage array chips are controlled by the first edge isolation signal, the second edge isolation signal, the first edge depolarization signal, and the second edge depolarization signal respectively; the first isolation switch, the second isolation switch, the first depolarization switch, and the second depolarization switch between the read-out amplifier modules at non-head and tail positions and the adjacent storage array chips are controlled by the first internal isolation signal, the second internal isolation signal, the first internal depolarization signal, and the second internal depolarization signal respectively.

10. The memory (10) according to claim 9, characterized in that The edge test parameter group includes a first test parameter and a second test parameter, and the internal test parameter group includes a third test parameter and a fourth test parameter; If the first test parameter is in the first state, the second edge isolation signal and the second edge depolarization signal have the same level as the initial isolation signal and the initial depolarization signal in one-to-one correspondence; if the first test parameter is in the second state, the second edge isolation signal and the second edge depolarization signal are both invalid; If the second test parameter is in the first state, the first edge isolation signal and the first edge depolarization signal have the same level as the initial isolation signal and the initial depolarization signal in a one-to-one correspondence; If the second test parameter is in the second state, the first edge isolation signal and the first edge depolarization signal are both invalid; If the fourth test parameter is in the first state, the first internal isolation signal and the first internal depolarization signal have the same level as the initial isolation signal and the initial depolarization signal in one-to-one correspondence; if the fourth test parameter is in the second state, the first internal isolation signal and the first internal depolarization signal are both invalid; If the third test parameter is in the first state, the second internal isolation signal and the second internal depolarization signal have the same level as the initial isolation signal and the initial depolarization signal in one-to-one correspondence; if the third test parameter is in the second state, the second internal isolation signal and the second internal depolarization signal are both invalid; Wherein, when the memory is instructed to perform a bit line stress test operation, the second test parameter is in the second state, and the first test parameter, the third test parameter and the fourth test parameter are all in the first state.

11. The memory (10) according to claim 10, characterized in that The first state is a high level, and the second state is a low level; The first preprocessing circuit comprises: A first AND gate (501), two input ends of which receive the first test parameter and the initial isolation signal respectively, and an output end of which outputs the second edge isolation signal; A second AND gate (502), two input ends of which receive the second test parameter and the initial isolation signal respectively, and an output end of which outputs the first edge isolation signal; A third AND gate (503), two input ends of which receive the first test parameter and the initial depolarization signal respectively, and an output end of which outputs the second edge depolarization signal; The fourth AND gate (504) has two input ends receiving the second test parameter and the initial depolarization signal respectively, and an output end outputting the first edge depolarization signal.

12. The memory (10) according to claim 8, characterized in that The bit line in the first memory array slice is electrically connected to the adjacent sensitive amplifier module through the first depolarization switch or the first isolation switch, and the bit line in the last memory array slice is electrically connected to the sensitive amplifier modules at the first and last positions through the second depolarization switch or the second isolation switch, and the memory further includes: A command control circuit configured to generate a test enable signal, an initial isolation signal, and an initial depolarization signal; wherein, when the memory is instructed to perform the stress test operation, the test enable signal, the initial isolation signal, and the initial depolarization signal are all in a valid state; A second preprocessing circuit (6) is configured to generate a first internal isolation signal and a second internal isolation signal based on the internal test parameter group and the initial isolation signal; and to generate a first internal depolarization signal and a second internal depolarization signal based on the internal test parameter group and the initial depolarization signal; A third preprocessing circuit (70) is configured to generate a first head-end isolation signal and a second head-end isolation signal based on the head-end test parameter group and the initial isolation signal; and to generate a first head-end depolarization signal and a second head-end depolarization signal based on the head-end test parameter group and the initial depolarization signal; A fourth preprocessing circuit (80) is configured to generate a first tail end isolation signal and a second tail end isolation signal based on the tail end test parameter group and the initial isolation signal; and to generate a first tail end depolarization signal and a second tail end depolarization signal based on the tail end test parameter group and the initial depolarization signal; Among them, all the first test switches are controlled by the test enable signal, the first isolation switch, the second isolation switch, the first depolarization switch, and the second depolarization switch between the first read-out amplifier module and the adjacent storage array chip are controlled by the first head-end isolation signal, the second head-end isolation signal, the first head-end depolarization signal, and the second head-end depolarization signal in a one-to-one correspondence; the first isolation switch, the second isolation switch, the first depolarization switch, and the second depolarization switch between the last read-out amplifier module and the adjacent storage array chip are controlled by the first tail-end isolation signal, the second tail-end isolation signal, the first tail-end depolarization signal, and the second tail-end depolarization signal in a one-to-one correspondence; the first isolation switch, the second isolation switch, the first depolarization switch, and the second depolarization switch between the read-out amplifier module at the non-head-tail position and the adjacent storage array chip are controlled by the first internal isolation signal, the second internal isolation signal, the first internal depolarization signal, and the second internal depolarization signal in a one-to-one correspondence.

13. The memory (10) according to claim 12, characterized in that The internal test parameter group includes at least a third test parameter and a fourth test parameter; the head-end test parameter group includes a fifth test parameter and a sixth test parameter, and the tail-end test parameter group includes a seventh test parameter and an eighth test parameter; If the third test parameter is in the first state, the second internal isolation signal and the second internal depolarization signal have the same level as the initial isolation signal and the initial depolarization signal in one-to-one correspondence; if the third test parameter is in the second state, the second internal isolation signal and the second internal depolarization signal are both invalid; If the fourth test parameter is in the first state, the first internal isolation signal and the first internal depolarization signal have the same level as the initial isolation signal and the initial depolarization signal in one-to-one correspondence; if the fourth test parameter is in the second state, the first internal isolation signal and the first internal depolarization signal are both invalid; If the fifth test parameter is in the first state, the second head-end isolation signal and the second head-end depolarization signal have the same level as the initial isolation signal and the initial depolarization signal in one-to-one correspondence; if the fifth test parameter is in the second state, the second head-end isolation signal and the second head-end depolarization signal are both invalid; If the sixth test parameter is in the first state, the first head-end isolation signal and the first head-end depolarization signal have the same level as the initial isolation signal and the initial depolarization signal in one-to-one correspondence; if the sixth test parameter is in the second state, the first head-end isolation signal and the first head-end depolarization signal are both invalid; If the seventh test parameter is in the first state, the second tail end isolation signal and the second tail end depolarization signal have the same level as the initial isolation signal and the initial depolarization signal in one-to-one correspondence; if the seventh test parameter is in the second state, the second tail end isolation signal and the second tail end depolarization signal are both invalid; If the eighth test parameter is in the first state, the first tail end isolation signal and the first tail end depolarization signal have the same level as the initial isolation signal and the initial depolarization signal in one-to-one correspondence; if the eighth test parameter is in the second state, the first tail end isolation signal and the first tail end depolarization signal are both invalid; Wherein, in the process that the memory is instructed to perform the bit line stress test operation, the sixth test parameter and the seventh test parameter are in the second state, and the third test parameter, the fourth test parameter and the The parameter, the fifth test parameter, and the eighth test parameter are all in the first state.

14. The memory (10) according to claim 10 or 13, characterized in that: The first state is a high level, and the second state is a low level; The second preprocessing circuit comprises: a fifth AND gate (601), wherein two input terminals receive the third test parameter and the initial isolation signal respectively, and an output terminal outputs the second internal isolation signal; a sixth AND gate (602), whose two input terminals receive the fourth test parameter and the initial isolation signal respectively, and whose output terminal outputs the first internal isolation signal; a seventh AND gate (603), whose two input ends respectively receive the third test parameter and the initial depolarization signal, and whose output end outputs the second internal depolarization signal; An eighth AND gate (604) has two input terminals receiving the fourth test parameter and the initial depolarization signal respectively, and an output terminal outputting the first internal depolarization signal.

15. The memory (10) according to claim 13, characterized in that The first state is a high level, and the second state is a low level; The third preprocessing circuit comprises: a ninth AND gate (701), wherein two input ends thereof receive the fifth test parameter and the initial isolation signal respectively, and an output end thereof outputs the second first-end isolation signal; a tenth AND gate (702), whose two input ends respectively receive the sixth test parameter and the initial isolation signal, and whose output end outputs the first head-end isolation signal; An eleventh AND gate (703), two input ends of which receive the fifth test parameter and the initial depolarization signal respectively, and an output end of which outputs the second first-end depolarization signal; A twelfth AND gate (704), two input ends of which receive the sixth test parameter and the initial depolarization signal respectively, and an output end of which outputs the first first-end depolarization signal; The fourth preprocessing circuit comprises: A thirteenth AND gate (801), two input ends of which receive the seventh test parameter and the initial isolation signal respectively, and an output end of which outputs the second tail end isolation signal; The fourteenth AND gate (802) has two input terminals receiving the eighth test parameter and the initial isolation parameter, respectively. The output end of the device outputs the first tail end isolation signal; A fifteenth AND gate (803), two input ends of which receive the seventh test parameter and the initial depolarization signal respectively, and an output end of which outputs the second tail end depolarization signal; The sixteenth AND gate (804) has two input ends receiving the eighth test parameter and the initial depolarization signal respectively, and an output end outputting the first tail end depolarization signal.

16. The memory (10) according to claim 4, characterized in that For the memory array slices not at the head or tail positions, the bit lines therein are coupled to respective local data lines via respective column selection switches; wherein: For the second bit lines in the odd-numbered memory array slices that are not at the head or tail position and the first bit lines in the even-numbered memory array slices that are not at the head or tail position, the local data lines coupled thereto are also connected to the first precharge source (VAD2O) through the respective second test switches; For the first bit lines in the storage array slices that are not at the first or last position and have odd numbers and the second bit lines in the storage array slices that are not at the first or last position and have even numbers, their coupled local data lines are also connected to the second pre-charge source (VAD2E) through their respective second test switches.

17. The memory (10) according to claim 16, characterized in that For the memory array slices at the head and tail positions, the first bit lines are coupled to respective local data lines via respective column selection switches; wherein: For the memory array slices at the head and tail positions, the local data lines coupled to the odd-numbered first bit lines are coupled to the second precharge source via the second test switch, and the local data lines coupled to the even-numbered first bit lines are coupled to the first precharge source via the second test switch; Alternatively, for the first storage array slice, the local data line coupled to the odd-numbered first bit line is coupled to the second pre-charge source via the second test switch, and the local data line coupled to the even-numbered first bit line is coupled to the first pre-charge source via the second test switch; and, for the last storage array slice, the local data line coupled to the odd-numbered first bit line is coupled to the first pre-charge source via the second test switch, and the local data line coupled to the even-numbered second bit line is coupled to the first pre-charge source via the second test switch.

18. The memory (10) according to claim 17, characterized in that The memory is configured to control all isolation switches, debiasing switches and precharge switches to be in an off state, control all column selection switches and second test switches to be in a closed state, and control the first precharge source to be a first voltage value and the second precharge source to be a second voltage value, so as to perform a bit line stress test; or, Control all isolation switches, debiasing switches and pre-charge switches to be in the off state, control all column selection switches and the second test switch to be in the closed state, and control the first pre-charge source to be the second voltage value and the second pre-charge source to be the first voltage value to perform another bit line stress test.

19. The memory (10) according to claim 5, characterized in that For the memory array slices not at the head or tail position, each of the bit lines is coupled to a respective local data line via a respective column selection switch; For the second bit lines in the odd-numbered memory array slices that are not at the head or tail position, and the first bit lines in the even-numbered memory array slices that are not at the head or tail position, the local data lines coupled thereto are coupled to the first preset test power supply via the second test switch; For the first bit lines in the non-first and last positions and odd-numbered storage array slices and the second bit lines in the non-first and last positions and even-numbered storage array slices, the coupled local data lines are coupled to the second preset test power supply via the second test switch.

20. The memory (10) according to claim 19, characterized in that For the memory array slices at the head and tail positions, the first bit lines are coupled to respective local data lines via respective column selection switches; wherein: For the memory array slices at the head and tail positions, the local data lines corresponding to the odd-numbered first bit lines are coupled to the second preset test power supply via the second test switch, and the local data lines corresponding to the even-numbered first bit lines are coupled to the first preset test power supply via the second test switch; Alternatively, for the first memory array slice, the local data lines corresponding to the odd-numbered first bit lines are coupled to the second preset test power supply via the second test switch, and the local data lines corresponding to the even-numbered first bit lines are coupled to the first preset test power supply via the second test switch; for the last memory array slice, the local data lines corresponding to the odd-numbered first bit lines are coupled to the first preset test power supply via the second test switch, and the local data lines corresponding to the even-numbered first bit lines are coupled to the first preset test power supply via the second test switch. The test switch is coupled to a second preset test power source.

21. The memory (10) according to claim 20, characterized in that The memory is configured to control all isolation switches and debiasing switches to be in an off state, control all precharge switches to be in a closed state, and control the precharge power source to be a fifth voltage value; control all column selection switches and second test switches to be in a closed state, and control the first preset test power source to be a first voltage value and the second preset test power source to be a second voltage value, so as to perform a bit line stress test; Controlling all the isolation switches and the debiasing switches to be in an off state, controlling all the pre-charge switches to be in a closed state, and controlling the pre-charge power source to be a fifth voltage value; controlling all the column selection switches and the second test switches to be in a closed state, and controlling the first preset test power source to be a second voltage value and the second preset test power source to be a first voltage value, so as to perform another bit line stress test; The voltage of the fifth voltage value is between the voltage of the first voltage value and the voltage of the second voltage value.

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