Array substrate and display apparatus

Abstract

Provided are an array substrate and a display apparatus. The array substrate comprises a substrate, and a first metal layer, a first insulating layer, a second insulating layer, and a first electrode layer (21) which are provided on the surface of one side of the substrate. The first electrode layer (21) comprises a first electrode pattern, the first electrode pattern being electrically connected to the first metal layer by means of a first via hole (H1) and a second via hole (H2). The orthographic projection of the first electrode layer (21) on the substrate covers the orthographic projection of the first via hole (H1) on the substrate. The ratio of the overlapping area of the orthographic projection of the first electrode layer (21) on the substrate and the orthographic projection of the second via hole (H2) on the substrate to the orthographic projection of the second via hole (H2) on the substrate is greater than or equal to 0.85 and less than or equal to 0.99. An alignment liquid diffuses on the first electrode layer (21) and around the second via hole (H2), and is guided by the shape of the first electrode layer (21) to diffuse into resin holes, so as to achieve uniform in-plane diffusion, thereby eliminating small black dots and facilitating uniform diffusion of the alignment liquid, improving image quality and reducing non-uniformity of images.

Description

Array substrate and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202311659648.5 filed in China on November 30, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0004] In the related art, as display devices increasingly develop towards narrow bezels, high refresh rates, high resolutions, and high pixel per inch (PPI), the display substrates used need to meet the requirements of increased pixel density and aperture ratio. The corresponding array substrates need to use high-mobility active layer materials and smaller transistors, and adopt a small hole design to improve the aperture ratio / transmittance. Oxide materials have become a common active layer material used in transistors due to their certain transparency, high mobility, and relatively simple preparation process. Typically, the array substrate of a display panel has a gate metal layer, a source / drain metal layer, a semiconductor layer, an organic layer, an insulating layer, and two transparent conductive layers. The two transparent conductive layers are divided into a bottom transparent electrode and an upper transparent electrode. Display technology requires digging a hole in the organic layer (the organic layer can be a resin layer) and further etching an insulating layer hole in the middle, so that the upper transparent conductive layer is adjacent to the drain metal. However, the transparent electrode needs to effectively cover all the resin layer holes and the insulating layer holes to prevent the etching solution from penetrating and corroding during the etching process. However, high pixel density is low, and the resin pores are small. When the transparent electrode fully covers the resin layer pores, it is not conducive to the spread of the applied alignment liquid around the resin pores. Figure 1 shows a schematic diagram of the alignment liquid coating on the plate surface. An APR (Asahi Photosensitive Resins) plate is hung on the plate ketone. The APR carries the alignment liquid, which is transferred to the array substrate surface after being printed on the array substrate. The surface of the APR plate is densely dotted, and each dot is a boss. The gaps between the bosses carry the alignment liquid. When the transparent electrode effectively covers all the resin layer pores, the alignment liquid is difficult to spread evenly here, resulting in black dots on the grayscale display screen.

[0005] Summary of the Invention

[0006] The main purpose of the present disclosure is to provide an array substrate and a display device, which solves the problem that the existing array substrate is transferred to the surface of the array substrate after printing on the surface of the array substrate, while the surface of the APR plate is densely dotted, each dot is a boss, and the gaps between the bosses are filled with alignment liquid. When the transparent electrode effectively covers all the holes in the resin layer, the alignment liquid is not easy to spread evenly here, resulting in black dot-like defects on the grayscale display screen.

[0007] In one aspect, an embodiment of the present disclosure provides an array substrate, comprising a substrate, and a first metal layer, a first insulating layer, a second insulating layer, and a first electrode layer provided on a surface of one side of the substrate;

[0008] The first electrode layer includes a first electrode pattern, and the first electrode pattern is electrically connected to the first metal layer through a first via hole and a second via hole;

[0009] The first via hole is located at and passes through the first insulating layer; the second via hole is located at and passes through the second insulating layer;

[0010] The orthographic projection of the first electrode layer on the substrate covers the orthographic projection of the first via on the substrate; the ratio of the overlapping area of ​​the orthographic projection of the first electrode layer on the substrate and the orthographic projection of the second via on the substrate to the orthographic projection area of ​​the second via on the substrate is greater than or equal to 0.85 and less than or equal to 0.99.

[0011] Optionally, the first electrode layer has a plurality of opening structures separated from each other, and an orthographic projection of at least one end of the opening structure on the substrate overlaps with an orthographic projection of the second via hole on the substrate.

[0012] Optionally, the array substrate according to at least one embodiment of the present disclosure further includes a second electrode layer disposed between the second insulating layer and the first electrode layer;

[0013] The orthographic projection of the second electrode layer on the substrate does not overlap with the orthographic projection of the first via hole on the substrate and the orthographic projection of the second via hole on the substrate.

[0014] Optionally, the array substrate according to at least one embodiment of the present disclosure includes a plurality of rows of first signal lines, a plurality of columns of second signal lines, and a plurality of pixel units defined by intersections of the first signal lines and the second signal lines, disposed on the substrate;

[0015] Each of the pixel units includes a first electrode pattern, a second electrode pattern, a first via hole, a second via hole, and a transistor; the transistor includes an active pattern;

[0016] The active pattern includes a first connecting portion and a second connecting portion;

[0017] The first connection portion is electrically connected to the second signal line through a third via hole; the second connection portion is electrically connected to the first electrode layer;

[0018] The third via hole and the first via hole are not in the same pixel unit.

[0019] Optionally, the array substrate according to at least one embodiment of the present disclosure includes a plurality of rows of first signal lines, a plurality of columns of second signal lines, and a plurality of pixel units defined by intersections of the first signal lines and the second signal lines, disposed on the substrate;

[0020] Each of the pixel units includes a first electrode pattern, a second electrode pattern, a first via hole, a second via hole, and a transistor; the transistor includes an active pattern;

[0021] Along a direction extending parallel to the first signal line, a maximum distance between an orthographic projection of an edge of the second via hole on the substrate and an orthographic projection of an edge of the first electrode pattern at the second via hole on the substrate is within a distance range.

[0022] Optionally, the first electrode pattern includes a connection pattern and a plurality of pixel electrode groups electrically connected to each other, and the pixel electrode group includes a plurality of pixel electrodes electrically connected to each other;

[0023] A first portion of an orthographic projection of the second via hole on the substrate is not covered by the first electrode pattern, and the first portion is close to the orthographic projection of the pixel electrode on the substrate;

[0024] A second portion of an orthographic projection of the second via on the substrate is not covered by the first electrode pattern, and the first portion and the second portion are arranged on opposite sides;

[0025] The second portion is close to an orthographic projection of the first signal line on the substrate.

[0026] Optionally, the edge of the orthographic projection of the second via on the substrate is an oblique-angle rectangle, a rectangle, or a rounded-corner rectangle;

[0027] The orthographic projection of the first signal line on the substrate is arranged on a first side of the orthographic projection of the second via hole on the substrate, and the orthographic projection of the pixel electrode on the substrate is arranged on a second side of the orthographic projection of the second via hole on the substrate; the first side and the second side are opposite sides;

[0028] The first portion is disposed at a corner where the orthographic projection of the second via hole on the substrate is close to the pixel electrode and the active pattern, and the second portion is disposed at a corner where the orthographic projection of the second via hole on the substrate is close to the first signal line and the first connecting portion.

[0029] Optionally, a third portion of the orthographic projection of the second via on the substrate is not covered by the first electrode pattern, and the third portion is close to the orthographic projection of the first signal line on the substrate.

[0030] Optionally, the edge of the orthographic projection of the second via on the substrate is an oblique-angle rectangle, a rectangle, or a rounded-corner rectangle;

[0031] The third portion is disposed at a corner of the second via hole close to the first signal line and the active pattern.

[0032] Optionally, the second electrode pattern includes a common electrode and four auxiliary connection parts;

[0033] The common electrode included in the pixel unit is electrically connected to the common electrodes in four pixel units adjacent to the pixel unit through the four auxiliary connection parts respectively;

[0034] The orthographic projections of two of the four auxiliary connecting portions on the substrate respectively overlap with the orthographic projections of the corresponding second signal lines on the substrate;

[0035] The orthographic projections of the other two auxiliary connecting portions of the four auxiliary connecting portions on the substrate partially overlap with the orthographic projections of the corresponding first signal lines on the substrate.

[0036] Optionally, the distance range is greater than or equal to 0.8 μm and less than or equal to 1.2 μm; or,

[0037] The distance range is greater than or equal to a first distance threshold, and the first distance threshold is greater than or equal to 0.8 μm and less than or equal to 1.2 μm.

[0038] Optionally, the first electrode pattern includes a connection pattern and a plurality of pixel electrode groups electrically connected to each other, and the pixel electrode group includes a plurality of pixel electrodes electrically connected to each other;

[0039] A fourth portion of the orthographic projection of the second via hole on the substrate is not covered by the first electrode pattern, and the fourth portion is close to the orthographic projection of the pixel electrode on the substrate.

[0040] Optionally, the edge of the orthographic projection of the second via on the substrate is an oblique-angle rectangle, a rectangle, or a rounded-corner rectangle;

[0041] The fourth portion is arranged where the orthographic projection of the second via hole on the substrate is close to the pixel electrode and close to a corner of the active pattern.

[0042] Optionally, the distance range is greater than or equal to 1.8 μm and less than or equal to 2.2 μm; or,

[0043] The distance range is greater than or equal to a second distance threshold, and the second distance threshold is greater than or equal to 1.8 μm and less than or equal to 2.2 μm.

[0044] Optionally, the second electrode pattern includes a common electrode and a first auxiliary connection portion;

[0045] The common electrode included in the pixel unit is electrically connected to the common electrode in a pixel unit adjacent to the pixel unit through the first auxiliary connection portion;

[0046] An orthographic projection of the first auxiliary connecting portion on the substrate partially overlaps with an orthographic projection of the second signal line on the substrate.

[0047] Optionally, the edge of the orthographic projection of the second via on the substrate is an oblique-angle rectangle, a rectangle, or a rounded-corner rectangle;

[0048] The fourth portion is arranged at a corner where an orthographic projection of the second via hole on the substrate is close to the pixel electrode and away from the active pattern.

[0049] Optionally, the distance range is greater than or equal to 1.3 μm and less than or equal to 1.7 μm; or,

[0050] The distance range is greater than or equal to a third distance threshold, and the third distance threshold is greater than or equal to 1.3 μm and less than or equal to 1.7 μm.

[0051] Optionally, the second electrode pattern includes a common electrode, a first auxiliary connection portion and a second auxiliary connection portion;

[0052] The common electrode of one pixel unit is electrically connected to the common electrode of another pixel unit located in the same row and adjacent to the pixel unit via the first auxiliary connection portion; the orthographic projection of the first auxiliary connection portion on the substrate partially overlaps with the orthographic projection of the pixel electrode on the substrate;

[0053] The common electrode included in one of the pixel units is electrically connected to the common electrode included in a pixel unit located in the same column and adjacent to the pixel unit through the second auxiliary connection portion; the orthographic projection of the second auxiliary connection portion on the substrate partially overlaps with the orthographic projection of the pixel electrode on the substrate.

[0054] Optionally, the edge of the orthographic projection of the second via on the substrate is a polygon;

[0055] The fourth portion is disposed at a corner of the second via hole on the substrate where an orthographic projection is away from the pixel electrode and the active pattern.

[0056] Optionally, the second electrode pattern includes a common electrode, a first auxiliary connection portion and a second auxiliary connection portion;

[0057] The common electrode of one of the pixel units is electrically connected to the common electrode of a pixel unit located in the same row and adjacent to the pixel unit via the first auxiliary connection portion; the orthographic projection of the first auxiliary connection portion on the substrate partially overlaps with the orthographic projection of the second signal line on the substrate;

[0058] The common electrode included in one of the pixel units is electrically connected to the common electrode included in a pixel unit located in the same column and adjacent to the pixel unit through the second auxiliary connection portion, and the orthographic projection of the second auxiliary connection portion on the substrate partially overlaps with the orthographic projection of the first signal line on the substrate.

[0059] Optionally, the edge of the orthographic projection of the second via on the substrate is an oblique-angle rectangle, a rectangle, or a rounded-corner rectangle;

[0060] The first electrode pattern includes a connection pattern and a plurality of pixel electrode groups electrically connected to each other, and the pixel electrode group includes a plurality of pixel electrodes electrically connected to each other;

[0061] The orthographic projection of the pixel electrode on the substrate is located on a second side of the orthographic projection of the second via hole on the substrate;

[0062] The lower edge of the orthographic projection of the connecting pattern on the substrate is consistent with the edge portion of the orthographic projection of the second via on the substrate; and / or, the upper edge of the orthographic projection of the connecting pattern on the substrate is consistent with the edge portion of the orthographic projection of the second via on the substrate.

[0063] Optionally, the first electrode pattern includes a connection pattern and a plurality of pixel electrode groups electrically connected to each other, and the pixel electrode group includes a plurality of pixel electrodes electrically connected to each other;

[0064] The orthographic projection of the pixel electrode on the substrate at least partially overlaps with the orthographic projection of the second via hole on the substrate.

[0065] Optionally, the distance range is greater than or equal to 1.3 μm and less than or equal to 1.7 μm; or,

[0066] The distance range is greater than or equal to a fourth distance threshold, and the fourth distance threshold is greater than or equal to 1.3 μm and less than or equal to 1.7 μm.

[0067] Optionally, an edge of an orthographic projection of the second via hole on the substrate is a polygon.

[0068] In a second aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned array substrate.

[0069] An embodiment of the present disclosure provides an array substrate and a display device, in which the orthographic projection of the first electrode layer on the substrate partially covers the orthographic projection of the second via hole on the substrate, so that the alignment liquid diffuses around the first electrode layer and the second via hole and is guided by the shape of the first electrode layer to diffuse into the resin hole, achieving uniform diffusion in the surface, thereby eliminating small black spots. For high PPI (pixel density) display products and ultra-high PPI display products, oxide processes and organic film processes are conducive to uniform diffusion of the alignment liquid, improving picture quality and reducing picture unevenness. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] FIG1 is a schematic diagram of coating an alignment liquid on a substrate surface;

[0071] FIG2 is a planar layout diagram of an array substrate according to at least one embodiment of the present disclosure;

[0072] 3A and 3B are partially enlarged plan layout diagrams of FIG. 2 ;

[0073] FIG4 is a planar layout diagram of the gate metal layer in FIG3A ;

[0074] FIG5 is a planar layout diagram of the semiconductor layer in FIG3A;

[0075] 6A and 6B are planar layout diagrams of the source / drain metal layer in FIG3 ;

[0076] FIG7A is a schematic diagram of a layout diagram of an orthographic projection of the second via hole H2 in FIG3A on the substrate;

[0077] FIG7B is a schematic diagram of the superposition of the second via hole and the first electrode layer in FIG3A ;

[0078] FIG8A is a planar layout diagram of the second electrode layer in FIG3A ;

[0079] 8B is a planar layout diagram of the second electrode layer, gate metal layer, and source / drain metal layer stacks in FIG. 3A ;

[0080] 9A and 9B are plan layout diagrams of the first electrode layer in FIG. 3A ;

[0081] FIG10 is a stacked diagram of the first electrode layer, the second via hole, and the first via hole in FIG3A ;

[0082] FIG11 is a planar layout diagram of an array substrate according to at least one embodiment of the present disclosure;

[0083] 12A and 12B are partially enlarged plan layout diagrams of FIG. 11 ;

[0084] FIG13 is a planar layout diagram of the gate metal layer in FIG12A;

[0085] FIG14 is a planar layout diagram of the semiconductor layer in FIG12A;

[0086] FIG15 is a planar layout diagram of the source / drain metal layer in FIG12A;

[0087] FIG16A is a layout diagram of an orthographic projection of the second via hole in FIG12A on the substrate;

[0088] FIG16B is a schematic diagram of a stack of the second via hole and the first electrode layer in FIG12A;

[0089] FIG17A is a planar layout diagram of the second electrode layer in FIG12A;

[0090] 17B is a planar layout diagram of the stack of the second electrode layer, the gate metal layer, and the source / drain metal layer in FIG. 12A ;

[0091] 18A and 18B are plan layout diagrams of the first electrode layer in FIG. 12A ;

[0092] FIG19 is a schematic diagram of the superposition of the first electrode layer, the second via hole and the first via hole in FIG12A;

[0093] FIG20 is a layout diagram of an array substrate according to at least one embodiment of the present disclosure;

[0094] 21A and 21B are partially enlarged plan layout diagrams of FIG. 20 ;

[0095] FIG22 is a planar layout diagram of the gate metal layer in FIG21A;

[0096] FIG23 is a planar layout diagram of the semiconductor layer in FIG21A;

[0097] FIG24 is a planar layout diagram of the source / drain metal layer in FIG21A;

[0098] FIG25A is a layout diagram of an orthographic projection of the second via hole in FIG21A on the substrate;

[0099] FIG25B is a schematic diagram of the stacking of the second via hole and the first electrode layer in FIG21A;

[0100] FIG26A is a planar layout diagram of the second electrode layer in FIG21A;

[0101] 26B is a planar layout diagram of the stack of the second electrode layer and the source / drain metal layer in FIG. 21 ;

[0102] 27A and 27B are plan layout diagrams of the first electrode layer in FIG. 21A ;

[0103] FIG28 is a schematic diagram of the superposition of the first electrode layer, the second via hole, and the first via hole in FIG21A;

[0104] FIG29 is a planar layout diagram of an array substrate according to at least one embodiment of the present disclosure;

[0105] 30A and 30B are partially enlarged plan layout diagrams of FIG. 29 ;

[0106] FIG31 is a planar layout diagram of the gate metal layer in FIG30A;

[0107] FIG32 is a planar layout diagram of the semiconductor layer in FIG30A;

[0108] FIG33 is a planar layout diagram of the source / drain metal layer in FIG30A;

[0109] FIG34A is a planar layout diagram of an orthographic projection of the second via hole in FIG30A on the substrate;

[0110] FIG34B is a schematic diagram of the stacking of the second via hole and the first electrode layer in FIG30A;

[0111] FIG35A is a planar layout diagram of the second electrode layer in FIG30A;

[0112] FIG35B is a planar layout diagram of the stack of the second electrode layer and the first electrode layer in FIG30A;

[0113] 36A and 36B are plan layout diagrams of the first electrode layer in FIG 30A ;

[0114] FIG37 is a schematic diagram of the superposition of the first electrode layer, the second via hole and the first via hole in FIG30A;

[0115] 38A and 38B are plan layout diagrams of an array substrate according to at least one embodiment of the present disclosure;

[0116] FIG39 is a planar layout diagram of the gate metal layer in FIG38A;

[0117] FIG40 is a planar layout of the semiconductor layer in FIG38A;

[0118] FIG41 is a planar layout diagram of the source / drain metal layer in FIG38A;

[0119] FIG42A is a plan layout diagram of the second via hole in FIG38A;

[0120] FIG42B is a schematic diagram of the stacking of the second via hole and the first electrode layer in FIG38A;

[0121] FIG43A is a planar layout diagram of the second electrode layer in FIG38A;

[0122] FIG43B is a planar layout diagram of the stack between the second electrode layer and the source / drain metal layer in FIG38A;

[0123] 44A and 44B are planar layouts of the first electrode layer in FIG 38A;

[0124] FIG45 is a superimposed diagram of the first electrode layer and the second via hole in FIG38A;

[0125] FIG46 is a layout diagram of the second via hole H2 in at least one embodiment of the present disclosure;

[0126] 47A and 47B are planar layout diagrams of the first electrode layer in at least one embodiment of the present disclosure;

[0127] FIG48 is a superimposed diagram of a first electrode layer, a first via hole, and a second via hole in at least one embodiment of the present disclosure;

[0128] FIG49 is a layout diagram of the second via hole H2 in at least one embodiment of the present disclosure;

[0129] 50A and 50B are planar layout diagrams of the first electrode layer in at least one embodiment of the present disclosure;

[0130] FIG51 is an overlay diagram of the first electrode layer, the first via hole, and the second via hole in at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0131] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0132] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0133] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0134] The array substrate according to the embodiment of the present disclosure includes a substrate, and a first metal layer, a first insulating layer, a second insulating layer, and a first electrode layer arranged in sequence in a direction away from the substrate;

[0135] The first electrode layer includes a first electrode pattern; the first electrode pattern is electrically connected to the first metal layer through a first via hole and a second via hole;

[0136] The first via hole is located at and passes through the first insulating layer; the second via hole is located at and passes through the second insulating layer;

[0137] The orthographic projection of the first electrode layer on the substrate covers the orthographic projection of the first via on the substrate; the ratio of the overlapping area of ​​the orthographic projection of the first electrode layer on the substrate and the orthographic projection of the second via on the substrate to the orthographic projection area of ​​the second via on the substrate is greater than or equal to 0.85 and less than or equal to 0.99.

[0138] An embodiment of the present disclosure provides an array substrate, in which the orthographic projection of the first electrode layer on the substrate partially covers the orthographic projection of the second via on the substrate, so that the alignment liquid diffuses around the first electrode layer and the second via and is guided by the shape of the first electrode layer to diffuse into the resin hole, achieving uniform diffusion within the surface, thereby eliminating small black spots. For high PPI (pixel density) display products and ultra-high PPI display products, oxide processes and organic film processes are conducive to uniform diffusion of the alignment liquid, improving picture quality and reducing picture unevenness.

[0139] In a specific implementation, the first electrode pattern may completely cover the first via hole.

[0140] In related technologies, the first via (the first via may be a via passing through the insulating layer) and the second via (the second via may be a via passing through the organic layer) on a high PPI display product are small in size, and the first electrode layer completely covers the vias to prevent the etching solution from penetrating, thereby causing uneven printing of the alignment liquid and forming small black spots on the grayscale screen.

[0141] Optionally, the first insulating layer may be an organic layer, the first electrode layer may be a pixel electrode layer, and the second electrode layer may be a common electrode layer.

[0142] In at least one embodiment of the present disclosure, the first electrode layer has a plurality of opening structures separated from each other, and an orthographic projection of at least one end of the opening structure on the substrate partially overlaps with an orthographic projection of the second via on the substrate.

[0143] In Figures 2 to 51, an XY coordinate system is drawn, wherein the X direction is a first direction and the Y direction is a second direction. The first direction X may be, for example, a horizontal direction and the second direction Y may be, for example, a vertical direction.

[0144] FIG2 is a layout diagram of an array substrate according to at least one embodiment of the present disclosure.

[0145] In FIG2 , the first electrode layer is labeled 21 , the second electrode layer is labeled 22 ; the first via hole is labeled H1 , and the second via hole is labeled H2 .

[0146] 3A and 3B are plan layout diagrams of a partial area in FIG. 2 .

[0147] In FIG3A , 21 is a first electrode layer, 22 is a second electrode layer, 23 is a gate metal layer, 24 is a source / drain metal layer, and 20 is a semiconductor layer.

[0148] In Figure 3B, the pixel electrode group is labeled PXZ, the common electrode is labeled VCOM, the first via hole is labeled H1, the second via hole is labeled H2, the first data line is labeled DL1, the second data line is labeled DL2, the gate line is labeled GL, and the third via hole is labeled H3.

[0149] Figure 4 is a planar layout diagram of the gate metal layer in Figure 3A, Figure 5 is a planar layout diagram of the semiconductor layer in Figure 3A, Figures 6A and 6B are planar layout diagrams of the source-drain metal layer in Figure 3A, Figure 7A is a schematic diagram of the layout diagram of the orthographic projection of the second via H2 in Figure 3A on the substrate, and Figure 7B is a schematic diagram of the superposition of the second via and the first electrode layer in Figure 3A; Figure 8A is a planar layout diagram of the second electrode layer in Figure 3A, and Figure 8B is a planar layout diagram of the stacked layers of the second electrode layer, gate metal layer and source-drain metal layer in Figure 3A; Figures 9A and 9B are planar layout diagrams of the first electrode layer in Figure 3A, and Figure 10 is a stacked diagram of the first electrode layer, second via and first via in Figure 3A.

[0150] In at least the embodiments of the present disclosure, the second signal line may include a first portion, a second portion, and a third portion that are interconnected; the first portion is a portion of the second signal line that overlaps with the first signal line, and a width of the first portion along the horizontal direction may be greater than a width of the third portion along the horizontal direction, or the width of the first portion along the horizontal direction may be the same as a width of the third portion along the horizontal direction;

[0151] The second portion may be a connecting portion of the second signal line extending to the left, and the second portion is configured to overlap with a second connecting portion included in the active pattern.

[0152] Optionally, the first signal line may be a gate line, and the second signal line may be a data line.

[0153] In FIG. 6A , the line labeled DL1 is the first data line, and the line labeled DL2 is the second data line.

[0154] In FIG6B , the second data line includes a first portion B1 , a second portion B2 , a first third portion B13 , and a second third portion B23 ;

[0155] The width of the first portion B1 along the horizontal direction is greater than the width of B13 along the horizontal direction; the width of the first portion B1 along the horizontal direction is greater than the width of B23 along the horizontal direction;

[0156] The second part B2 is set on the left side of B13;

[0157] B1, B2, B13 and B23 are connected.

[0158] In FIG. 6B , three dotted lines are drawn for separating the first portion B1 , the second portion B2 , the first third portion B13 , and the second third portion B23 .

[0159] In FIG. 7A , the edge labeled H2W is the orthographic projection of H2 on the substrate.

[0160] In FIG9A , the pixel electrode is labeled PXZ, and the connection pattern is labeled X1 ; the connection pattern X1 is interconnected with the pixel electrode PXZ, and the first electrode pattern includes the connection pattern X1 and the pixel electrode group PXZ electrically connected to each other.

[0161] As shown in FIG9B , the first electrode layer includes a first opening structure K1 , a second opening structure K2 , and a third opening structure K3 ;

[0162] The first opening structure K1, the second opening structure K2 and the third opening structure K3 are separated from each other;

[0163] As shown in Figures 3A and 3B, the orthographic projection of one end of the first opening structure K1 on the substrate partially overlaps with the orthographic projection of the second via H2 on the substrate. As shown in Figure 9B, a pixel electrode group includes a first pixel electrode PX1, a second pixel electrode PX2, a third pixel electrode PX3, and a fourth pixel electrode PX4 that are electrically connected to each other;

[0164] K1 is set between PX1 and PX2, K2 is set between PX2 and PX3, and K3 is set between PX3 and PX4.

[0165] As shown in FIG. 9A and FIG. 9B , the pattern labeled X1 is a connection pattern.

[0166] As shown in FIG9B , the first dotted line for dividing the connection pattern X1 is a dotted line extending in the horizontal direction, which is used to separate the connection pattern X1 from the second pixel electrode PX2;

[0167] The second imaginary line for dividing the connection pattern X1 is an imaginary line extending in the vertical direction, which is used to separate the connection pattern X1 from the third pixel electrode PX3 and to separate the connection pattern X1 from the fourth pixel electrode PX4.

[0168] In at least one embodiment of the present disclosure, the array substrate may further include a second electrode layer disposed between the second insulating layer and the first electrode layer;

[0169] The orthographic projection of the second electrode layer on the substrate does not overlap with the orthographic projection of the first via hole on the substrate and the orthographic projection of the second via hole on the substrate.

[0170] Optionally, the second electrode layer may be a common electrode layer, and the second electrode layer may include a common electrode and an auxiliary connection pattern.

[0171] During specific implementation, the second electrode layer may not cover the first via hole.

[0172] In at least one embodiment of the present disclosure, the first electrode layer can be an upper transparent electrode, and the second electrode layer can be a bottom transparent electrode. The upper transparent electrode fully covers the first via hole, and the upper transparent electrode partially covers the second via hole. Therefore, the alignment liquid diffuses around the upper transparent electrode and the resin hole and is guided by the shape of the transparent electrode to diffuse into the second via hole, achieving uniform diffusion within the surface, thereby eliminating small black spots.

[0173] The array substrate according to at least one embodiment of the present disclosure includes a plurality of rows of first signal lines, a plurality of columns of second signal lines, and a plurality of pixel units defined by the intersection of the first signal lines and the second signal lines, disposed on the substrate;

[0174] Each of the pixel units includes a first electrode pattern, a second electrode pattern, a first via hole, a second via hole, and a transistor; the transistor includes an active pattern;

[0175] The active pattern includes a first connecting portion and a second connecting portion;

[0176] The first connection portion is electrically connected to the second signal line through a third via hole; the second connection portion is electrically connected to the first electrode layer;

[0177] The third via hole and the first via hole are not in the same pixel unit.

[0178] Optionally, the first signal line may be a gate line, the second signal line may be a data line, the gate line may extend along a first direction, the data line may extend along a second direction, and the first direction intersects the second direction;

[0179] The first direction may be a horizontal direction, and the second direction may be a vertical direction; or, the first direction may be a vertical direction, and the second direction may be a horizontal direction.

[0180] As shown in FIG5 , the active pattern labeled A0 is the transistor, the first connection portion L1 included in the active pattern labeled A01 is the active pattern, and the second connection portion L2 included in the active pattern labeled A02 is the active pattern.

[0181] As shown in FIG. 3B to FIG. 9B , the second connection portion L2 is electrically connected to the data line DL through the third via hole H3;

[0182] The third via hole H3 and the first via hole H1 are not in the same pixel unit.

[0183] In FIG3B , the pixel unit labeled P1 is the first pixel unit, and the pixel unit labeled P2 is the second pixel unit;

[0184] The gate line GL is disposed between the first pixel unit P1 and the second pixel unit P2;

[0185] The first data line DL1 is disposed on the left side of the first pixel unit P1 , and the second data line DL2 is disposed on the right side of the first pixel unit P1 .

[0186] In at least one embodiment of the present disclosure, along a direction extending parallel to the first signal line, a maximum distance between the orthographic projection of an edge of the second via on the substrate and the orthographic projection of an edge of the first electrode pattern at the second via on the substrate is within a distance range.

[0187] In a specific implementation, the orthographic projection of the edge of the first electrode pattern at the second via hole on the substrate is arranged within the orthographic projection of the second via hole on the substrate.

[0188] In at least one embodiment of the present disclosure, the first electrode pattern includes a connection pattern and a plurality of pixel electrode groups electrically connected to each other, and the pixel electrode group includes a plurality of pixel electrodes electrically connected to each other;

[0189] A first portion of an orthographic projection of the second via hole on the substrate is not covered by the first electrode pattern, and the first portion is close to the orthographic projection of the pixel electrode on the substrate;

[0190] A second portion of an orthographic projection of the second via on the substrate is not covered by the first electrode pattern, and the first portion and the second portion are arranged on opposite sides;

[0191] The second portion is close to an orthographic projection of the first signal line on the substrate.

[0192] In a specific implementation, a portion of the positive projection of the second via on the substrate is not covered by the first electrode pattern, the first electrode is close to the pixel electrode, and a second portion of the positive projection of the second via on the substrate is not covered by the first electrode pattern, and the first portion and the second portion are arranged on opposite sides.

[0193] In at least one embodiment of the present disclosure, the array substrate further includes a second metal layer (the second metal layer may be a gate metal layer) disposed between the base and the first metal layer (the first metal layer may be a source / drain metal layer), and the second metal pattern on the second metal layer includes a first signal line;

[0194] The second portion is close to an orthographic projection of the first signal line on the substrate.

[0195] In a specific implementation, the second portion of the orthographic projection of the second via hole on the substrate is close to the orthographic projection of the first signal line on the substrate.

[0196] Optionally, the first signal line may be a gate line.

[0197] As shown in FIG3A , FIG3B and FIG10 , the orthographic projection of the first electrode pattern on the substrate partially covers the second via H2 , but does not completely cover the second via H2 ; the common electrode VCOM does not cover the second via H2 , and the first electrode pattern completely covers the first via H1 .

[0198] A first portion H21 of the second via hole H2 on the substrate and a second portion H22 of the second via hole H2 on the substrate are not covered by the first electrode pattern;

[0199] The first portion H21 is close to the pixel electrode, and the second portion H22 is close to the gate line GL.

[0200] In at least one embodiment of the array substrate shown in FIG3A and FIG3B , insulating layers of different thicknesses are provided between the gate metal layer and the semiconductor layer, the source / drain metal layer and the common electrode layer, and the common electrode layer and the pixel electrode layer.

[0201] A first insulating layer (the first insulating layer may be an organic layer, which may be a resin layer), a second insulating layer and a first electrode layer (the first electrode layer may be a pixel electrode layer) may be provided between the first metal layer (the first metal layer may be a source-drain metal layer) and the first electrode layer. Etched holes may be provided on the organic layer and part of the insulating layer for conducting the electrodes. The first electrode layer and the second electrode layer may be transparent conductive layers, which may be obtained by depositing indium tin oxide. The thickness of the transparent conductive layer may be greater than or equal to 400 angstroms and less than or equal to 900 angstroms.

[0202] In at least one embodiment of the present disclosure, the edge of the orthographic projection of the second via hole on the substrate may be a beveled rectangle, a rectangle, or a rounded rectangle;

[0203] The orthographic projection of the first signal line on the substrate is arranged on a first side of the orthographic projection of the second via hole on the substrate, and the orthographic projection of the pixel electrode on the substrate is arranged on a second side of the orthographic projection of the second via hole on the substrate; the first side and the second side are opposite sides;

[0204] The first portion is disposed at a corner where the orthographic projection of the second via hole on the substrate is close to the pixel electrode and the active pattern, and the second portion is disposed at a corner where the orthographic projection of the second via hole on the substrate is close to the first signal line and the first connecting portion.

[0205] Optionally, the first side may be downward, and the second side may be upward.

[0206] As shown in FIG7A , the first portion H21 is close to each pixel electrode and the active pattern A0 , and the second portion H22 is close to the gate line GL and the active pattern A0 ;

[0207] H21 is set at the upper right corner of the second via hole, and H22 is set at the lower right corner of the second via hole.

[0208] As shown in FIG. 7B , the upper right corner of the second via hole H2 and the lower right corner of the second via hole H2 are not covered by the first electrode pattern.

[0209] In a specific implementation, the edge of the orthographic projection of the second via on the substrate can be a beveled rectangle, a rectangle or a rounded rectangle, the orthographic projection of the gate line on the substrate is below the orthographic projection of the second via on the substrate, the orthographic projection of the pixel electrode on the substrate is arranged above the orthographic projection of the second via on the substrate, the first part can be arranged at the upper right corner of the orthographic projection of the second via on the substrate, and the second part can be arranged at the lower right corner of the orthographic projection of the second via on the substrate.

[0210] In at least one embodiment of the present disclosure, the distance range may be greater than or equal to 0.8 μm and less than or equal to 1.2 μm; or,

[0211] The distance range may be greater than or equal to a first distance threshold, and the first distance threshold may be greater than or equal to 0.8 μm and less than or equal to 1.2 μm.

[0212] In at least one embodiment corresponding to FIG. 2 to FIG. 10 , along a direction extending parallel to the gate line GL, a maximum distance between an orthographic projection of an edge of the second via hole H2 on the substrate and an orthographic projection of an edge of the first electrode pattern at the second via hole H2 on the substrate is within a distance range;

[0213] The distance range is greater than or equal to 0.8 μm and less than or equal to 1.2 μm; or,

[0214] The distance range is greater than or equal to a first distance threshold, and the first distance threshold is greater than or equal to 0.8 μm and less than or equal to 1.2 μm.

[0215] In at least one embodiment of the present disclosure, the second electrode pattern may include a common electrode and four auxiliary connection portions;

[0216] The common electrode included in the pixel unit is electrically connected to the common electrodes in four pixel units adjacent to the pixel unit through the four auxiliary connection parts respectively;

[0217] The orthographic projections of two of the four auxiliary connecting portions on the substrate respectively overlap with the orthographic projections of the corresponding second signal lines on the substrate;

[0218] The orthographic projections of the other two auxiliary connecting portions of the four auxiliary connecting portions on the substrate partially overlap with the orthographic projections of the corresponding first signal lines on the substrate.

[0219] As shown in FIG8A , the first auxiliary connection portion is labeled FL1, the second auxiliary connection portion is labeled FL2, and the third auxiliary connection portion is labeled FL3;

[0220] The common electrode VCOM is electrically connected to the common electrode on the left side through FL1, the common electrode VCOM is electrically connected to the common electrode on the right side through FL2, and the common electrode VCOM is electrically connected to the common electrode on the bottom side through FL3;

[0221] As shown in Figure 8B, the orthographic projection of FL1 on the substrate partially overlaps with the orthographic projection of the first data line DL1 on the substrate, the orthographic projection of FL2 on the substrate partially overlaps with the orthographic projection of the second data line DL2 on the substrate, and the orthographic projection of FL3 on the substrate partially overlaps with the orthographic projection of the gate line GL on the substrate.

[0222] In at least one embodiment shown in Figures 2 to 10, the common electrode VCOM can also be electrically connected to the common electrode above through a fourth auxiliary electrode portion, and the orthographic projection of the fourth auxiliary electrode portion on the substrate can partially overlap with the orthographic projection of the upper gate line on the substrate.

[0223] As shown in FIG. 8A and FIG. 8B , FL1 and FL2 extend in the horizontal direction, and FL3 extends in the vertical direction.

[0224] In at least one embodiment of the present disclosure, the array substrate further includes a second metal layer disposed between the base and the first metal layer, and the second metal pattern on the second metal layer includes a first signal line;

[0225] A third portion of an orthographic projection of the second via hole on the substrate is not covered by the first electrode pattern, and the third portion is close to the orthographic projection of the first signal line on the substrate.

[0226] In a specific implementation, a third portion of the orthographic projection of the second via hole on the substrate, which is close to the orthographic projection of the first signal line on the substrate, is not covered by the first electrode pattern.

[0227] In at least one embodiment of the present disclosure, the edge of the orthographic projection of the second via on the substrate may be a beveled rectangle, a rectangle, or a rounded rectangle; the third portion may be arranged at a corner of the orthographic projection of the second via on the substrate close to the first signal line and the active pattern.

[0228] FIG11 is a planar layout diagram of an array substrate according to at least one embodiment of the present disclosure.

[0229] In FIG11 , the first electrode layer is labeled 21 , the second electrode layer is labeled 22 ; the first via hole is labeled H1 , and the second via hole is labeled H2 .

[0230] 12A and 12B are plan layout diagrams of a partial area in FIG. 11 .

[0231] Figure 13 is a plan layout diagram of the gate metal layer in Figure 12A, Figure 14 is a plan layout diagram of the semiconductor layer in Figure 12A, Figure 15 is a plan layout diagram of the source-drain metal layer in Figure 12A, Figure 16A is a plan layout diagram of the positive projection of the second via in Figure 12A on the substrate, and Figure 16B is a schematic diagram of the stacking of the second via and the first electrode layer in Figure 12A; Figure 17A is a plan layout diagram of the second electrode layer in Figure 12A, and Figure 17B is a plan layout diagram of the stacking of the second electrode layer, the gate metal layer and the source-drain metal layer in Figure 12A; Figures 18A and 18B are plan layout diagrams of the first electrode layer in Figure 12A, and Figure 19 is a schematic diagram of the superposition of the first electrode layer, the second via and the first via in Figure 12A.

[0232] In FIG12A , the first electrode layer is labeled 21 , the second electrode layer is labeled 22 , the gate metal layer is labeled 23 , the source / drain metal layer is labeled 24 , and the semiconductor layer is labeled 20 .

[0233] In Figure 12B, the pixel electrode group is labeled PXZ, the common electrode is labeled VCOM, the first via hole is labeled H1, the second via hole is labeled H2, the gate line is labeled GL, the third via hole is labeled H3, the first data line is labeled DL1, and the second data line is labeled DL2.

[0234] In FIG13 , the gate lines are labeled GL.

[0235] In FIG14 , the active pattern is labeled A0; the first connection portion is labeled L1, and the second connection portion is labeled L2; as shown in FIG12A to FIG19 , the second connection portion L2 is electrically connected to the second data line DL2 through the third via H3;

[0236] In FIG15 , the line labeled DL1 is the first data line, and the line labeled DL2 is the second data line;

[0237] In FIG16A , the edge of H2 is labeled H2W; the third portion of the orthographic projection of the second via hole H2 on the substrate is labeled H23; and the third portion H23 is located at the lower right corner of the second via hole H2.

[0238] As shown in FIG. 16B , the lower right corner of the second via hole H2 is not covered by the first electrode pattern.

[0239] As shown in FIG. 12B , FIG. 14 and FIG. 16A , the third portion H23 is close to the gate line GL, and the third portion H23 is close to the active pattern A0 , and the third portion H23 is disposed at the lower right corner of the second via hole.

[0240] In FIG17A and FIG17B , the common electrode is labeled VCOM;

[0241] As shown in FIG17A , the first auxiliary connection portion is labeled FL1, the second auxiliary connection portion is labeled FL2, and the third auxiliary connection portion is labeled FL3;

[0242] The common electrode VCOM is electrically connected to the common electrode on the left side through FL1, the common electrode VCOM is electrically connected to the common electrode on the right side through FL2, and the common electrode VCOM is electrically connected to the common electrode on the bottom side through FL3;

[0243] As shown in Figure 17B, the orthographic projection of FL1 on the substrate partially overlaps with the orthographic projection of the first data line DL1 on the substrate, the orthographic projection of FL2 on the substrate partially overlaps with the orthographic projection of the second data line DL2 on the substrate, and the orthographic projection of FL3 on the substrate partially overlaps with the orthographic projection of the gate line GL on the substrate.

[0244] In at least one embodiment shown in Figures 11 to 19, the common electrode VCOM can also be electrically connected to the common electrode above through a fourth auxiliary electrode portion, and the orthographic projection of the fourth auxiliary electrode portion on the substrate can partially overlap with the orthographic projection of the upper gate line on the substrate.

[0245] As shown in FIG. 17A and FIG. 17B , FL1 and FL2 extend in the horizontal direction, and FL3 extends in the vertical direction.

[0246] In FIG. 18A , the pixel electrode is labeled PXZ, and the connection pattern is labeled X1 . The connection pattern X1 is connected to the pixel electrode PX.

[0247] In FIG18B , the first pixel electrode is labeled PX1 , the second pixel electrode is labeled PX2 , the third pixel electrode is labeled PX3 , and the fourth pixel electrode is labeled PX4 ;

[0248] A first opening structure K1 is provided between PX1 and PX2 , a second opening structure K2 is provided between PX2 and PX3 , and a third opening structure K3 is provided between PX3 and PX4 .

[0249] As shown in FIG18B , the first dotted line for dividing the connection pattern X1 is a dotted line extending in the horizontal direction, which is used to separate the connection pattern X1 from the first pixel electrode PX1;

[0250] The second dotted line for dividing the connection pattern X1 is a dotted line extending in the vertical direction, which is used to separate the connection pattern X1 from the second pixel electrode PX2, the connection pattern X1 from the third pixel electrode PX3, and the connection pattern X1 from the fourth pixel electrode PX4.

[0251] As shown in FIG11 to FIG19 , a third portion H23 of the orthographic projection of the second via hole H2 on the substrate is not covered by the first electrode pattern, and the third portion H23 is close to the orthographic projection of the gate line GL on the substrate;

[0252] As shown in Figures 11 to 19, the first electrode pattern completely covers the orthographic projection of the first via H1 on the substrate, and the first electrode pattern partially covers the orthographic projection of the second via H2 on the substrate; the common electrode VCOM does not cover the second via H2, and the first electrode pattern completely covers the first via H1;

[0253] The portion of the orthographic projection of the second via hole on the substrate that is not covered by the first electrode pattern is the third portion H23 , and the third portion H23 is close to the orthographic projection of the gate line on the substrate.

[0254] Optionally, the edge of the orthographic projection of the second via on the substrate is an oblique-angle rectangle, a rectangle, or a rounded-corner rectangle;

[0255] The orthographic projection of the gate line on the substrate is below the orthographic projection of the second via hole on the substrate;

[0256] The third portion is disposed at a lower right corner of an orthographic projection of the second via hole on the substrate.

[0257] In a specific implementation, the edge of the orthographic projection of the second via on the substrate can be a beveled rectangle, a rectangle or a rounded rectangle; the orthographic projection of the gate line on the substrate can be below the orthographic projection of the second via on the substrate; the third part can be arranged at the lower right corner of the orthographic projection of the second via on the substrate.

[0258] In at least one embodiment of the array substrate shown in FIG. 11 to FIG. 19 , along a direction extending parallel to the gate line GL, a maximum distance between an orthographic projection of an edge of the second via hole H2 on the substrate and an orthographic projection of an edge of the first electrode pattern at the second via hole H2 on the substrate is within a distance range;

[0259] The distance range is greater than or equal to 0.8 μm and less than or equal to 1.2 μm; or,

[0260] The distance range is greater than or equal to a first distance threshold, and the first distance threshold is greater than or equal to 0.8 μm and less than or equal to 1.2 μm.

[0261] In at least one embodiment of the present disclosure, the first electrode pattern includes a connection pattern and a plurality of pixel electrode groups electrically connected to each other, and the pixel electrode group includes a plurality of pixel electrodes electrically connected to each other;

[0262] A fourth portion of the orthographic projection of the second via hole on the substrate is not covered by the first electrode pattern, and the fourth portion is close to the orthographic projection of the pixel electrode on the substrate.

[0263] In a specific implementation, the fourth portion of the orthographic projection of the second via hole on the substrate that is not covered by the first electrode pattern is close to the orthographic projection of the pixel electrode on the substrate.

[0264] FIG20 is a layout diagram of an array substrate according to at least one embodiment of the present disclosure.

[0265] In FIG20 , the element labeled 21 is the first electrode layer, the element labeled 22 is the second electrode layer; the element labeled H1 is the first via hole, and the element labeled H2 is the second via hole.

[0266] 21A and 21B are plan layout diagrams of a partial area in FIG. 20 .

[0267] Figure 22 is a plan layout diagram of the gate metal layer in Figure 21A, Figure 23 is a plan layout diagram of the semiconductor layer in Figure 21A, Figure 24 is a plan layout diagram of the source-drain metal layer in Figure 21A, Figure 25A is a plan layout diagram of the positive projection of the second via in Figure 21A on the substrate, and Figure 25B is a schematic diagram of the stacking of the second via and the first electrode layer in Figure 21A; Figure 26A is a plan layout diagram of the second electrode layer in Figure 21, and Figure 26B is a plan layout diagram of the stacking of the second electrode layer and the source-drain metal layer in Figure 21; Figures 27A and 27B are plan layout diagrams of the first electrode layer in Figure 21A, and Figure 28 is a schematic diagram of the superposition of the first electrode layer, the second via and the first via in Figure 21A.

[0268] In FIG21A , the first electrode layer is labeled 21 , the second electrode layer is labeled 22 , the gate metal layer is labeled 23 , the source / drain metal layer is labeled 24 , and the semiconductor layer is labeled 20 .

[0269] In FIG21B , PXZ is a pixel electrode group, VCOM is a common electrode, H1 is a first via hole, H2 is a second via hole, GL is a gate line, DL1 is a first data line, and DL2 is a second data line.

[0270] In FIG22 , the gate lines are labeled GL.

[0271] In FIG23 , the active pattern is labeled A0;

[0272] In FIG24 , the line labeled DL is a data line;

[0273] In FIG25A , the edge of H2 is labeled H2W; the fourth portion of the orthographic projection of the second via hole H2 on the substrate is labeled H24;

[0274] In FIG. 26A and FIG. 26B , VCOM is a common electrode.

[0275] In FIG. 27A , the pixel electrode group is labeled PXZ, and the connection pattern is labeled X1 . The connection pattern X1 is connected to the pixel electrode group PXZ.

[0276] As shown in FIG27B , the first pixel electrode is labeled PX1, the second pixel electrode is labeled PX2, the third pixel electrode is labeled PX3, the fourth pixel electrode is labeled PX4, and the fifth pixel electrode is labeled PX5;

[0277] A first opening structure K1 is provided between PX1 and PX2, a second opening structure K2 is provided between PX2 and PX3, a third opening structure K3 is provided between PX3 and PX4, and a fourth opening structure K4 is provided between PX4 and PX5.

[0278] As shown in FIG27B , the first dotted line for dividing the connection pattern X1 is a dotted line extending in the horizontal direction, which is used to separate the connection pattern X1 from the second pixel electrode PX2 and the connection pattern X1 from the third pixel electrode PX3 ;

[0279] The second dotted line for dividing the connection pattern X1 is a dotted line extending in the vertical direction, which is used to separate the connection pattern X1 and the fourth pixel electrode PX4, and to separate the connection pattern X1 and the fifth pixel electrode PX5;

[0280] The third dotted line for dividing the connection pattern X3 is used to separate the connection pattern X1 from the first pixel electrode PX1.

[0281] As shown in FIG21 to FIG28 , a fourth portion H24 of the orthographic projection of the second via hole H2 on the substrate is not covered by the first electrode pattern, and the fourth portion H24 is close to the orthographic projection of each pixel electrode on the substrate;

[0282] As shown in Figures 21 to 28, the first electrode pattern completely covers the orthographic projection of the first via on the substrate, and partially covers the orthographic projection of the second via on the substrate; the common electrode VCOM does not cover the second via H2, and the first electrode pattern completely covers the first via H1.

[0283] Optionally, the edge of the orthographic projection of the second via on the substrate is an oblique-angle rectangle, a rectangle, or a rounded-corner rectangle;

[0284] The fourth portion is arranged at a corner where an orthographic projection of the second via hole on the substrate is close to the pixel electrode and away from the active pattern.

[0285] As shown in Figures 21 to 28, the edge of the orthographic projection of the second via hole on the substrate can be a beveled rectangle, the fourth part H24 is arranged at the upper left corner of the orthographic projection of H2 on the substrate, the orthographic projection of each pixel electrode on the substrate is arranged above the orthographic projection of the second via hole H2 on the substrate, and the orthographic projection of the active pattern A0 on the substrate is arranged on the left side of the orthographic projection of the second via hole H2 on the substrate.

[0286] Optionally, the distance range is greater than or equal to 1.8 μm and less than or equal to 2.2 μm; or,

[0287] The distance range is greater than or equal to a third distance threshold, and the third distance threshold is greater than or equal to 1.8 μm and less than or equal to 2.2 μm.

[0288] In at least one embodiment shown in FIG. 21 to FIG. 28 , along a direction extending parallel to the gate line GL, a maximum distance between an orthographic projection of an edge of the second via hole H2 on the substrate and an orthographic projection of an edge of the first electrode pattern at the second via hole H2 on the substrate is within a distance range;

[0289] The distance range is greater than or equal to 1.8 μm and less than or equal to 2.2 μm; or,

[0290] The distance range is greater than or equal to a second distance threshold, and the first distance threshold is greater than or equal to 1.8 μm and less than or equal to 2.2 μm.

[0291] In at least one embodiment of the present disclosure, the second electrode pattern includes a common electrode and a first auxiliary connection portion;

[0292] The common electrode included in the pixel unit is electrically connected to the common electrode in a pixel unit adjacent to the pixel unit through the first auxiliary connection portion;

[0293] An orthographic projection of the first auxiliary connecting portion on the substrate partially overlaps with an orthographic projection of the second signal line on the substrate.

[0294] As shown in FIG26B , the second electrode pattern includes a common electrode VCOM and a first auxiliary connection portion FL1 ;

[0295] The common electrode VCOM is electrically connected to the common electrode on the right side through the first auxiliary connection portion FL1;

[0296] An orthographic projection of the first auxiliary link FL1 on the substrate partially overlaps with an orthographic projection of the second data line DL2 on the substrate.

[0297] In at least one embodiment of the present disclosure, the edge of the orthographic projection of the second via on the substrate is an oblique-angle rectangle, a rectangle, or a rounded-corner rectangle;

[0298] The fourth portion is arranged at a corner where an orthographic projection of the second via hole on the substrate is close to the pixel electrode and away from the active pattern.

[0299] Optionally, the orthographic projection of the pixel electrode on the substrate may be arranged to the right of the orthographic projection of the second via hole on the substrate, and the orthographic projection of the active pattern on the substrate may be arranged above the orthographic projection of the second via hole on the substrate;

[0300] The fourth portion may be disposed at an upper right corner of an orthographic projection of the second via hole on the substrate.

[0301] FIG29 is a planar layout diagram of an array substrate according to at least one embodiment of the present disclosure.

[0302] In FIG29 , the element labeled 21 is the first electrode layer, the element labeled 22 is the second electrode layer; the element labeled H1 is the first via hole, and the element labeled H2 is the second via hole.

[0303] 30A and 30B are plan layout diagrams of a partial area in FIG. 29 .

[0304] Figure 31 is a planar layout diagram of the gate metal layer in Figure 30A, Figure 32 is a planar layout diagram of the semiconductor layer in Figure 30A, Figure 33 is a planar layout diagram of the source and drain metal layers in Figure 30A, Figure 34A is a planar layout diagram of the positive projection of the second via in Figure 30A on the substrate, and Figure 34B is a schematic diagram of the stacking of the second via and the first electrode layer in Figure 30A; Figure 35A is a planar layout diagram of the second electrode layer in Figure 30A, and Figure 35B is a planar layout diagram of the stacking of the second electrode layer and the first electrode layer in Figure 30A; Figures 36A and 36B are planar layout diagrams of the first electrode layer in Figure 30A, and Figure 37 is a schematic diagram of the superposition of the first electrode layer, the second via and the first via in Figure 30A.

[0305] In FIG30A , the number 21 is the first electrode layer, the number 22 is the second electrode layer, the number 23 is the gate metal layer, the number 24 is the source / drain metal layer, and the number 20 is the semiconductor layer.

[0306] In Figure 30B, H1 is the first via hole, H2 is the second via hole, PXZ is the pixel electrode group, VCOM is the common electrode, GL1 is the first gate line, GL2 is the second gate line, DL is the data line, and A0 is the active pattern.

[0307] In FIG31 , the first gate line is labeled GL1 and the second gate line is labeled GL2 . The first gate line GL1 and the second gate line GL2 extend in the horizontal direction.

[0308] In FIG32 , A0 is an active pattern, L1 is a first connection portion, and L2 is a second connection portion.

[0309] In FIG33 , the line labeled DL is a data line.

[0310] In FIG34 , the portion labeled H2W is the edge of H2 ; and the portion labeled H24 is the fourth portion included in the orthographic projection of the second via hole H2 on the substrate.

[0311] In at least one embodiment of the present disclosure, the second electrode pattern may include a common electrode, a first auxiliary connection portion, and a second auxiliary connection portion;

[0312] The common electrode of one pixel unit is electrically connected to the common electrode of another pixel unit located in the same row and adjacent to the pixel unit via the first auxiliary connection portion; the orthographic projection of the first auxiliary connection portion on the substrate partially overlaps with the orthographic projection of the pixel electrode on the substrate;

[0313] The common electrode included in one of the pixel units is electrically connected to the common electrode included in a pixel unit located in the same column and adjacent to the pixel unit through the second auxiliary connection portion; the orthographic projection of the second auxiliary connection portion on the substrate partially overlaps with the orthographic projection of the pixel electrode on the substrate.

[0314] In FIG35A and FIG35B , VCOM is a common electrode, FL1 is a first auxiliary connection portion, and FL2 is a second auxiliary connection portion; FL1 extends in the horizontal direction, and FL2 extends in the vertical direction;

[0315] The common electrode VCOM is electrically connected to the common electrode on the left side through the first auxiliary connection portion FL1;

[0316] The common electrode VCOM is electrically connected to the common electrode below through the second auxiliary connection portion FL2 .

[0317] As shown in FIG35B , the orthographic projection of FL1 on the substrate partially overlaps with the orthographic projection of the pixel electrode group PXZ on the substrate;

[0318] The orthographic projection of FL2 on the substrate partially overlaps with the orthographic projection of the pixel electrode group PXZ on the substrate.

[0319] In FIG36A , the pixel electrode group is labeled PXZ, and the connection pattern is labeled X1. The pixel electrode group PXZ is connected to the connection pattern X1.

[0320] As shown in FIG36B , the first pixel electrode is labeled PX1, the second pixel electrode is labeled PX2, the third pixel electrode is labeled PX3, the fourth pixel electrode is labeled PX4, and the fifth pixel electrode is labeled PX5;

[0321] A first opening structure K1 is provided between PX1 and PX2 , a second opening structure K2 is provided between PX2 and PX3 , a third opening structure K3 is provided between PX3 and PX4 , and a fifth opening structure K5 is provided between PX4 and PX5 .

[0322] As shown in FIG36A and FIG36B , the first dotted line for dividing the connection pattern X1 is a dotted line extending in the horizontal direction, which is used to separate the connection pattern X1 from the first pixel electrode PX1 and the connection pattern X1 from the second pixel electrode PX2;

[0323] The second dotted line for dividing the connection pattern X1 is used to separate the connection pattern X1 and the third pixel electrode PX4, and to separate the connection pattern X1 and the third pixel electrode PX3;

[0324] The third dotted line for dividing the connection pattern X3 is a dotted line extending in the vertical direction, and is used to separate the connection pattern X1 and the fourth pixel electrode PX4;

[0325] The fourth imaginary line for dividing the connection pattern X1 is an imaginary line extending in the horizontal direction, and is used to separate the connection pattern X1 and the fifth pixel electrode PX5.

[0326] As shown in FIG29 to FIG37 , a fourth portion H24 of the orthographic projection of the second via hole H2 on the substrate is not covered by the first electrode pattern, and the fourth portion H24 is close to the orthographic projection of the pixel electrode PX on the substrate;

[0327] As shown in Figures 29 to 37, the first electrode pattern completely covers the orthographic projection of the first via on the substrate, and partially covers the orthographic projection of the second via on the substrate; the common electrode VCOM does not cover the second via H2, and the first electrode pattern completely covers the first via H1.

[0328] As shown in Figures 29 to 37, the orthographic projection of the pixel electrode PX on the substrate is set to the right of the orthographic projection of the second via hole H2 on the substrate, and the fourth part H24 is set at the upper right corner of the orthographic projection of the second via hole H2 on the substrate.

[0329] Optionally, the distance range is greater than or equal to 1.3 μm and less than or equal to 1.7 μm; or,

[0330] The distance range is greater than or equal to a third distance threshold, and the third distance threshold is greater than or equal to 1.3 μm and less than or equal to 1.7 μm

[0331] In at least one embodiment corresponding to FIG. 29 to FIG. 37 , along a direction extending parallel to the gate line GL, a maximum distance between an orthographic projection of an edge of the second via hole H2 on the substrate and an orthographic projection of an edge of the first electrode pattern at the second via hole H2 on the substrate is within a distance range;

[0332] The distance range is greater than or equal to 1.3 μm and less than or equal to 1.7 μm; or,

[0333] The distance range is greater than or equal to a third distance threshold, and the third distance threshold is greater than or equal to 1.3 μm and less than or equal to 1.7 μm.

[0334] In at least one embodiment of the present disclosure, the edge of the orthographic projection of the second via hole on the substrate is a polygon;

[0335] The fourth portion is disposed at a corner of the second via hole on the substrate where an orthographic projection is away from the pixel electrode and the active pattern.

[0336] 38A and 38B are planar layout diagrams of an array substrate according to at least one embodiment of the present disclosure.

[0337] Figure 39 is a planar layout diagram of the gate metal layer in Figure 38A, Figure 40 is a planar layout diagram of the semiconductor layer in Figure 38A, Figure 41 is a planar layout diagram of the source-drain metal layer in Figure 38A, Figure 42A is a planar layout diagram of the second via in Figure 38A, Figure 43A is a planar layout diagram of the second electrode layer in Figure 38A, and Figure 43B is a planar layout diagram of the stacking between the second electrode layer and the source-drain metal layer in Figure 38A; Figures 44A and 44B are planar layout diagrams of the first electrode layer in Figure 38A, and Figure 45 is a schematic diagram of the superposition of the first electrode layer and the second via in Figure 38A.

[0338] In FIG38A , the number 21 is the first electrode layer, the number 22 is the second electrode layer, the number 23 is the gate metal layer, the number 24 is the source / drain metal layer, and the number 20 is the semiconductor layer.

[0339] In Figure 38B, the pixel electrode group is labeled PXZ, the common electrode is labeled VCOM, the first via hole is labeled H1, the second via hole is labeled H2, the gate line is labeled GL, the first data line is labeled DL1, the second data line is labeled DL2, and the active pattern is labeled A0.

[0340] In Figure 39, the gate line is labeled GL. In Figure 40, the active pattern is labeled A0. In Figure 41, the first data line is labeled DL1, and the second data line is labeled DL2.

[0341] In at least one embodiment of the present disclosure, the second electrode pattern may include a common electrode, a first auxiliary connection portion, and a second auxiliary connection portion;

[0342] The common electrode of one of the pixel units is electrically connected to the common electrode of a pixel unit located in the same row and adjacent to the pixel unit via the first auxiliary connection portion; the orthographic projection of the first auxiliary connection portion on the substrate partially overlaps with the orthographic projection of the second signal line on the substrate;

[0343] The common electrode included in one of the pixel units is electrically connected to the common electrode included in a pixel unit located in the same column and adjacent to the pixel unit through the second auxiliary connection portion, and the orthographic projection of the second auxiliary connection portion on the substrate partially overlaps with the orthographic projection of the first signal line on the substrate.

[0344] In FIG. 43A and FIG. 43B , VCOM is a common electrode, and FL1 is a first auxiliary connection portion.

[0345] As shown in FIG43A , the common electrode VCOM is electrically connected to the common electrode on the left side through a first auxiliary connection portion FL1 , and FL1 extends in the horizontal direction.

[0346] In the embodiment corresponding to FIG. 43A , the common electrode VCOM may also be electrically connected to the common electrode below through a second auxiliary connection portion, and the second auxiliary connection portion extends in the vertical direction.

[0347] As shown in FIG. 43B , the orthographic projection of FL1 on the substrate partially overlaps with the orthographic projection of the first data line DL1 on the substrate.

[0348] In FIG43A , the auxiliary connection portion labeled FL0 is used to electrically connect the common electrode on the left side of the common electrode VCOM, and the connection portion of the common electrode provided below the common electrode;

[0349] As shown in FIG. 43B , the orthographic projection of FL0 on the substrate partially overlaps with the orthographic projection of the gate line GL on the substrate.

[0350] In FIG44A , the pixel electrode is labeled PX, and the connection pattern is labeled X1 . The connection pattern X1 is connected to the pixel electrode PX.

[0351] In FIG44B , the first pixel electrode is labeled PX1 , the second pixel electrode is labeled PX2 , the third pixel electrode is labeled PX3 , and the fourth pixel electrode is labeled PX4 ;

[0352] A first opening structure K1 is provided between PX1 and PX2 , a second opening structure K2 is provided between PX2 and PX3 , and a third opening structure K3 is provided between PX3 and PX4 .

[0353] As shown in FIG44B , the dotted lines used to divide the connection pattern X1 are used to separate the connection pattern X1 and the first pixel electrode PX1, separate the connection pattern X1 and the second pixel electrode PX2, separate the connection pattern X1 and the third pixel electrode PX3, and separate the connection pattern X1 and the fourth pixel electrode PX4.

[0354] In FIG45 , the pixel electrode is labeled PX, the second via hole is labeled H2, and the first via hole is labeled H1.

[0355] In FIG. 42A , the portion labeled H2W is the edge of H2 ; and the portion labeled H24 is the fourth portion included in the orthographic projection of the second via hole H2 on the substrate.

[0356] As shown in FIG38A to FIG45 , a fourth portion H24 of the orthographic projection of the second via hole H2 on the substrate is not covered by the first electrode pattern, and the fourth portion H24 is close to the orthographic projection of the pixel electrode PX on the substrate;

[0357] As shown in Figures 38A to 45, the first electrode pattern completely covers the orthographic projection of the first via on the substrate, and partially covers the orthographic projection of the second via on the substrate; the common electrode VCOM does not cover the second via H2, and the first electrode pattern completely covers the first via H1.

[0358] As shown in Figures 38A to 45, the orthographic projection of the pixel electrode PX on the substrate is set to the right of the orthographic projection of the second via hole H2 on the substrate, and the fourth part H24 is set at the lower left corner of the orthographic projection of the second via hole H2 on the substrate.

[0359] Figure 46 is a layout diagram of the second via H2 in at least one embodiment of the present disclosure; Figures 47A and 47B are planar layout diagrams of the first electrode layer in at least one embodiment of the present disclosure; Figure 48 is a schematic diagram of the superposition of the first electrode layer, the first via and the second via in at least one embodiment of the present disclosure.

[0360] In FIG46 , the edge of H2 is labeled H2W; as shown in FIG47A , the pixel electrode group is labeled PXZ, and the connection pattern is labeled X1.

[0361] As shown in FIG47B , the first pixel electrode is labeled PX1, the second pixel electrode is labeled PX2, the third pixel electrode is labeled PX3, and the fourth pixel electrode is labeled PX4;

[0362] A first opening structure K1 is provided between PX1 and PX2 , a second opening structure K2 is provided between PX2 and PX3 , and a third opening structure K3 is provided between PX3 and PX4 .

[0363] As shown in FIG47B , the first dotted line for dividing the connection pattern X1 is used to separate the connection pattern X1 from the first pixel electrode PX1 and the connection pattern X1 from the second pixel electrode PX2. The first dotted line is a dotted line extending in the horizontal direction.

[0364] The second imaginary line for dividing the connection pattern X1 is used to separate the connection pattern X1 and the third pixel electrode PX3 , and to separate the connection pattern X1 and the fourth pixel electrode PX4 . The second imaginary line is an imaginary line extending in the vertical direction.

[0365] As shown in FIG48 , the lower right corner of the second via hole H2 is not covered by the first electrode pattern, and the first electrode pattern partially covers the second via hole H2;

[0366] As shown in FIG. 46 to FIG. 48 , the first electrode pattern completely covers the first via hole H1 .

[0367] As shown in Figures 46 to 48, the overlapping area of ​​the orthographic projection of the first electrode pattern on the substrate and the orthographic projection of the second via H2 on the substrate is the first area, and the overlapping area of ​​the first area and the orthographic projection of the second via H2 on the substrate can be greater than or equal to 0.85 and less than or equal to 0.99.

[0368] Optionally, the edge of the orthographic projection of the second via on the substrate is an oblique-angle rectangle, a rectangle, or a rounded-corner rectangle;

[0369] The first electrode pattern includes a connection pattern electrically connected to each other and a plurality of pixel electrode groups, and the pixel electrode group includes a connection pattern electrically connected to each other and a plurality of pixel electrodes;

[0370] The orthographic projection of the pixel electrode on the substrate is located on a second side of the orthographic projection of the second via hole on the substrate;

[0371] The lower edge of the orthographic projection of the connecting pattern on the substrate is consistent with the edge portion of the orthographic projection of the second via on the substrate; and / or, the upper edge of the orthographic projection of the connecting pattern on the substrate is consistent with the edge portion of the orthographic projection of the second via on the substrate.

[0372] In a specific implementation, as shown in FIG48 , the lower edge of the orthographic projection of the connection pattern X1 on the substrate is consistent with the edge portion of the orthographic projection of the second via H2 on the substrate, and the upper edge of the orthographic projection of the connection pattern X1 on the substrate is consistent with the edge portion of the orthographic projection of the second via H2 on the substrate.

[0373] In at least one embodiment of the present disclosure, the first electrode pattern includes a connection pattern and a plurality of pixel electrode groups electrically connected to each other, and the pixel electrode group includes a plurality of pixel electrodes electrically connected to each other;

[0374] The orthographic projection of the first electrode pattern on the substrate at least partially overlaps with the orthographic projection of the second via hole on the substrate.

[0375] Figure 49 is a layout diagram of the second via H2 in at least one embodiment of the present disclosure; Figures 50A and 50B are planar layout diagrams of the first electrode layer in at least one embodiment of the present disclosure; Figure 51 is a schematic diagram of the superposition of the first electrode layer, the first via and the second via in at least one embodiment of the present disclosure.

[0376] In FIG50A, the pixel electrode is labeled PX, and the connection pattern is labeled X1, and PX and X1 are connected.

[0377] As shown in FIG50B , the first pixel electrode is labeled PX1, the second pixel electrode is labeled PX2, the third pixel electrode is labeled PX3, the fourth pixel electrode is labeled PX4, and the fifth pixel electrode is labeled PX5;

[0378] A first opening structure K1 is provided between PX1 and PX2 , a second opening structure K2 is provided between PX2 and PX3 , a third opening structure K3 is provided between PX3 and PX4 , and a fourth opening structure K4 is provided between PX4 and PX45 .

[0379] As shown in Figure 50B, the dotted line used to divide the connection pattern X1 is used to separate the connection pattern X1 and the first pixel electrode PX1, separate the connection pattern X1 and the second pixel electrode PX2, separate the connection pattern X1 and the third pixel electrode PX3, separate the connection pattern X1 and the fourth pixel electrode PX4, and separate the connection pattern X1 and the fifth pixel electrode PX5.

[0380] As shown in FIG. 49 to FIG. 51 , the orthographic projection of the first electrode pattern on the substrate at least partially overlaps with the orthographic projection of the second via H2 on the substrate.

[0381] Optionally, the distance range is greater than or equal to 1.3 μm and less than or equal to 1.7 μm; or,

[0382] The distance range is greater than or equal to a fourth distance threshold, and the fourth distance threshold is greater than or equal to 1.3 μm and less than or equal to 1.7 μm.

[0383] Optionally, an edge of an orthographic projection of the second via hole on the substrate is a polygon.

[0384] The display device described in the embodiment of the present disclosure includes the above-mentioned array substrate.

[0385] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. An array substrate, comprising a substrate, and a first metal layer, a first insulating layer, a second insulating layer and a first electrode layer arranged on a surface of one side of the substrate; The first electrode layer includes a first electrode pattern, and the first electrode pattern is electrically connected to the first metal layer through a first via hole and a second via hole; The first via hole is located in and passes through the first insulating layer; The second via hole is located in and passes through the second insulating layer; The orthographic projection of the first electrode layer on the substrate covers the orthographic projection of the first via hole on the substrate; A ratio of an overlapping area of ​​an orthographic projection of the first electrode layer on the substrate and an orthographic projection of the second via hole on the substrate to an orthographic projection area of ​​the second via hole on the substrate is greater than or equal to 0.85 and less than or equal to 0.

99.

2. The array substrate according to claim 1, wherein: The first electrode layer has a plurality of opening structures separated from each other, and an orthographic projection of at least one end of the opening structure on the substrate overlaps with an orthographic projection of the second via hole on the substrate.

3. The array substrate according to claim 1, wherein: Also includes a second electrode layer disposed between the second insulating layer and the first electrode layer; The orthographic projection of the second electrode layer on the substrate does not overlap with the orthographic projection of the first via hole on the substrate and the orthographic projection of the second via hole on the substrate.

4. The array substrate according to claim 1, wherein: It includes a plurality of rows of first signal lines, a plurality of columns of second signal lines, and a plurality of pixel units defined by the intersection of the first signal lines and the second signal lines, which are arranged on the substrate; Each of the pixel units includes a first electrode pattern, a second electrode pattern, a first via hole, a second via hole and a transistor; the transistor includes an active pattern; The active pattern includes a first connection portion and a second connection portion; The first connection portion is electrically connected to the second signal line through a third via hole; the second connection portion is electrically connected to the first electrode layer; The third via hole and the first via hole are not in the same pixel unit.

5. The array substrate according to claim 1, wherein: It includes a plurality of rows of first signal lines, a plurality of columns of second signal lines, and a plurality of pixel units defined by the intersection of the first signal lines and the second signal lines, which are arranged on the substrate; Each of the pixel units includes a first electrode pattern, a second electrode pattern, a first via hole, a second via hole and a transistor; the transistor includes an active pattern; Along a direction extending parallel to the first signal line, a maximum distance between an orthographic projection of an edge of the second via hole on the substrate and an orthographic projection of an edge of the first electrode pattern at the second via hole on the substrate is within a distance range.

6. The array substrate according to claim 5, wherein: The first electrode pattern includes a connection pattern and a plurality of pixel electrode groups electrically connected to each other, and the pixel electrode group includes a plurality of pixel electrodes electrically connected to each other; A first portion of the orthographic projection of the second via hole on the substrate is not covered by the first electrode pattern. A portion close to the orthographic projection of the pixel electrode on the substrate; A second portion of an orthographic projection of the second via hole on the substrate is not covered by the first electrode pattern, and the first portion and the second portion are arranged on opposite sides; The second portion is close to an orthographic projection of the first signal line on the substrate.

7. The array substrate according to claim 6, wherein: The edge of the orthographic projection of the second via hole on the substrate is an oblique-angle rectangle, a rectangle or a rounded-corner rectangle; The orthographic projection of the first signal line on the substrate is arranged on a first side of the orthographic projection of the second via hole on the substrate, and the orthographic projection of the pixel electrode on the substrate is arranged on a second side of the orthographic projection of the second via hole on the substrate; the first side and the second side are opposite sides; The first portion is disposed at a corner where the orthographic projection of the second via hole on the substrate is close to the pixel electrode and the active pattern, and the second portion is disposed at a corner where the orthographic projection of the second via hole on the substrate is close to the first signal line and the first connecting portion.

8. The array substrate according to claim 5, wherein: A third portion of an orthographic projection of the second via hole on the substrate is not covered by the first electrode pattern, and the third portion is close to an orthographic projection of the first signal line on the substrate.

9. The array substrate according to claim 8, wherein: The edge of the orthographic projection of the second via hole on the substrate is an oblique-angle rectangle, a rectangle or a rounded-corner rectangle; The third portion is disposed at a corner of the second via hole close to the first signal line and the active pattern.

10. The array substrate according to claim 7 or 9, wherein: The second electrode pattern includes a common electrode and four auxiliary connection parts; The common electrode included in the pixel unit is electrically connected to the common electrodes in four pixel units adjacent to the pixel unit through the four auxiliary connection parts respectively; The orthographic projections of two of the four auxiliary connecting portions on the substrate overlap with the orthographic projections of the corresponding second signal lines on the substrate respectively; Orthographic projections of the other two auxiliary connecting portions of the four auxiliary connecting portions on the substrate overlap with orthographic projections of the corresponding first signal lines on the substrate respectively.

11. The array substrate according to any one of claims 6 to 9, wherein: The distance range is greater than or equal to 0.8 μm and less than or equal to 1.2 μm; or, The distance range is greater than or equal to a first distance threshold, and the first distance threshold is greater than or equal to 0.8 μm and less than or equal to 1.2 μm.

12. The array substrate according to claim 5, wherein: The first electrode pattern includes a connection pattern and a plurality of pixel electrode groups electrically connected to each other, and the pixel electrode group includes a plurality of pixel electrodes electrically connected to each other; A fourth portion of the orthographic projection of the second via hole on the substrate is not covered by the first electrode pattern, and the fourth portion is close to the orthographic projection of the pixel electrode on the substrate.

13. The array substrate according to claim 12, wherein: The edge of the orthographic projection of the second via hole on the substrate is an oblique-angle rectangle, a rectangle or a rounded-corner rectangle; The fourth portion is arranged at a position where an orthographic projection of the second via hole on the substrate is close to the pixel electrode and close to a corner of the active pattern.

14. The array substrate according to claim 12 or 13, wherein: The distance range is greater than or equal to 1.8 μm and less than or equal to 2.2 μm; or, The distance range is greater than or equal to a second distance threshold, and the second distance threshold is greater than or equal to 1.8 μm and less than or equal to 2.2 μm.

15. The array substrate according to any one of claims 12 to 14, characterized in that: The second electrode pattern includes a common electrode and a first auxiliary connection portion; A common electrode included in the pixel unit is electrically connected to a common electrode in a pixel unit adjacent to the pixel unit through the first auxiliary connection portion; An orthographic projection of the first auxiliary connection portion on the substrate partially overlaps with an orthographic projection of the second signal line on the substrate.

16. The array substrate according to claim 12, wherein: The edge of the orthographic projection of the second via hole on the substrate is an oblique-angle rectangle, a rectangle or a rounded-corner rectangle; The fourth portion is disposed at a corner where an orthographic projection of the second via hole on the substrate is close to the pixel electrode and away from the active pattern.

17. The array substrate according to claim 16, wherein: The distance range is greater than or equal to 1.3 μm and less than or equal to 1.7 μm; or, The distance range is greater than or equal to a third distance threshold, and the third distance threshold is greater than or equal to 1.3 μm and less than or equal to 1.7 μm.

18. The array substrate according to claim 16 or 17, wherein: The second electrode pattern includes a common electrode, a first auxiliary connection portion and a second auxiliary connection portion; The common electrode included in one of the pixel units is electrically connected to the common electrode included in a pixel unit located in the same row and adjacent to the pixel unit through the first auxiliary connection portion; the orthographic projection of the first auxiliary connection portion on the substrate partially overlaps with the orthographic projection of the pixel electrode on the substrate; The common electrode included in one of the pixel units is electrically connected to the common electrode included in a pixel unit located in the same column and adjacent to the pixel unit through the second auxiliary connection portion; the orthographic projection of the second auxiliary connection portion on the substrate partially overlaps with the orthographic projection of the pixel electrode on the substrate.

19. The array substrate according to claim 12, wherein: The edge of the orthographic projection of the second via hole on the substrate is a polygon; The fourth portion is disposed at a corner of the second via hole on the substrate where an orthographic projection is away from the pixel electrode and the active pattern.

20. The array substrate according to claim 19, wherein: The second electrode pattern includes a common electrode, a first auxiliary connection portion and a second auxiliary connection portion; A common electrode included in one of the pixel units is electrically connected to a common electrode included in a pixel unit located in the same row and adjacent to the pixel unit through the first auxiliary connection portion; an orthographic projection of the first auxiliary connection portion on the substrate partially overlaps with an orthographic projection of the second signal line on the substrate; The common electrode included in one of the pixel units is electrically connected to the common electrode included in a pixel unit located in the same column and adjacent to the pixel unit through the second auxiliary connection portion, and the orthographic projection of the second auxiliary connection portion on the substrate partially overlaps with the orthographic projection of the first signal line on the substrate.

21. The array substrate according to claim 1, wherein: The edge of the orthographic projection of the second via hole on the substrate is an oblique-angle rectangle, a rectangle or a rounded-corner rectangle; The first electrode pattern includes a connection pattern and a plurality of pixel electrode groups electrically connected to each other, and the pixel electrode group includes a plurality of pixel electrodes electrically connected to each other; The orthographic projection of the pixel electrode on the substrate is located on a second side of the orthographic projection of the second via hole on the substrate; The lower edge of the orthographic projection of the connection pattern on the substrate is consistent with the edge portion of the orthographic projection of the second via hole on the substrate; And / or, an upper edge of an orthographic projection of the connection pattern on the substrate is consistent with an edge portion of an orthographic projection of the second via hole on the substrate.

22. The array substrate according to claim 5, wherein: The first electrode pattern includes a connection pattern and a plurality of pixel electrode groups electrically connected to each other, and the pixel electrode group includes a plurality of pixel electrodes electrically connected to each other; The orthographic projection of the pixel electrode on the substrate at least partially overlaps with the orthographic projection of the second via hole on the substrate.

23. The array substrate according to claim 22, wherein: The distance range is greater than or equal to 1.3 μm and less than or equal to 1.7 μm; or, The distance range is greater than or equal to a fourth distance threshold, and the fourth distance threshold is greater than or equal to 1.3 μm and less than or equal to 1.7 μm.

24. The array substrate according to claim 22, wherein: The edge of the orthographic projection of the second via hole on the substrate is a polygon.

25. A display device comprising the array substrate according to any one of claims 1 to 24.

Images