Semiconductor device and manufacturing method therefor, and electronic device

Abstract

Provided are a semiconductor device and a manufacturing method therefor, and an electronic device. The method comprises: providing a substrate, wherein a first interlayer dielectric layer is formed on the substrate; forming a first electrode sheet layer, a ferroelectric dielectric layer, and a second electrode sheet layer on the first interlayer dielectric layer, wherein the second electrode sheet layer comprises tungsten; forming a patterned first bottom anti-reflection layer, a patterned first oxide hard mask layer, a patterned first metal hard mask layer, and a patterned second bottom anti-reflection layer on the second electrode sheet layer; and using the first bottom anti-reflection layer, the first oxide hard mask layer, the first metal hard mask layer, and the second bottom anti-reflection layer as masks to etch the second electrode sheet layer, the ferroelectric dielectric layer, and the first electrode sheet layer so as to form a ferroelectric capacitor. According to the solution of the present disclosure, the second electrode sheet layer comprises tungsten, and the first bottom anti-reflection layer, the first oxide hard mask layer, the first metal hard mask layer, and the second bottom anti-reflection layer are used as masks to etch the second electrode sheet layer, the ferroelectric dielectric layer, and the first electrode sheet layer so as to form the ferroelectric capacitor, thereby improving the performance of products.

Description

Semiconductor device and manufacturing method thereof, and electronic device Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] Ferroelectric RAM (FRAM) is a new type of memory that combines the non-volatility of read-only memory (ROM) and the non-volatility of random access memory (RAM). It has the advantages of strong durability, high-speed reading and writing, and low power consumption. It has been widely used in various fields.

[0003] The core part of ferroelectric memory is the ferroelectric capacitor. The ferroelectric capacitor in ferroelectric memory generally adopts the MIM (metal / insulator / metal) structure. The manufacturing process of the MIM structure is generally to first deposit a metal layer as the lower plate, then grow a layer of ferroelectric thin film material as the dielectric layer, and then deposit a metal layer as the upper plate. Finally, photolithography and etching are performed to obtain the MIM structure. Summary of the Invention

[0004] In one aspect, the present disclosure provides a method for preparing a semiconductor device, comprising:

[0005] providing a substrate on which a first interlayer dielectric layer is formed;

[0006] forming a first plate layer, a ferroelectric dielectric layer and a second plate layer from bottom to top on the first interlayer dielectric layer, wherein the second plate layer comprises tungsten;

[0007] forming a patterned first bottom anti-reflection layer, a patterned first oxide hard mask layer, a patterned first metal hard mask layer and a patterned second bottom anti-reflection layer on the second electrode layer from bottom to top;

[0008] Using the patterned first bottom anti-reflection layer, the patterned first oxide hard mask layer, the patterned first metal hard mask layer and the patterned second bottom anti-reflection layer as masks, the second electrode layer, the ferroelectric dielectric layer and the first electrode layer are etched to form a ferroelectric capacitor.

[0009] In some embodiments, the patterned first bottom anti-reflective layer and the patterned second bottom anti-reflective layer include silicon oxynitride, and the patterned first metal hard mask layer includes titanium nitride.

[0010] In some embodiments, the thickness of the patterned first bottom anti-reflective layer ranges from 400 to 600 angstroms, the thickness of the patterned first oxide hard mask layer ranges from 100 to 200 angstroms, the thickness of the patterned first metal hard mask layer ranges from 400 to 600 angstroms, and the thickness of the patterned second bottom anti-reflective layer ranges from 300 to 350 angstroms.

[0011] In some embodiments, the second electrode layer includes at least a top layer and a bottom layer stacked one above the other, wherein the top layer includes a tungsten layer, and the bottom layer includes a titanium nitride layer.

[0012] In some embodiments, the top layer has a thickness in the range of 1000-1700 angstroms.

[0013] In some embodiments, forming a patterned first bottom anti-reflective layer, a patterned first oxide hard mask layer, a patterned first metal hard mask layer, and a patterned second bottom anti-reflective layer on the second electrode layer from bottom to top includes:

[0014] forming a first bottom anti-reflection layer, a first oxide hard mask layer, a first metal hard mask layer, a second bottom anti-reflection layer and a patterned photoresist layer on the second electrode layer from bottom to top;

[0015] The second bottom anti-reflective layer, the first metal hard mask layer, the first oxide hard mask layer and the first bottom anti-reflective layer are etched using the patterned photoresist layer as a mask to obtain the patterned first bottom anti-reflective layer, the patterned first oxide hard mask layer, the patterned first metal hard mask layer and the patterned second bottom anti-reflective layer.

[0016] In some embodiments, the preparation method further includes: forming a transistor on the substrate, the first interlayer dielectric layer covering the transistor, and a first conductive plug formed in the first interlayer dielectric layer to electrically connect the transistor and the ferroelectric capacitor.

[0017] In some embodiments, the preparation method further includes: forming a second interlayer dielectric layer between the first interlayer dielectric layer and the substrate; forming a second conductive plug and a third conductive plug in the second interlayer dielectric layer; forming a first conductive layer and a second conductive layer in the first interlayer dielectric layer, wherein the second conductive plug electrically connects the first conductive layer and the drain region of the transistor, and the third conductive plug electrically connects the second conductive layer and the source region of the transistor.

[0018] In some embodiments, the ferroelectric capacitor includes an etched second electrode layer, an etched ferroelectric dielectric layer, and an etched first electrode layer. After forming the ferroelectric capacitor, the preparation method further includes: forming a third interlayer dielectric layer, the third interlayer dielectric layer covering the first interlayer dielectric layer and the ferroelectric capacitor; forming a fourth conductive plug in the third interlayer dielectric layer; forming a third conductive layer on the third interlayer dielectric layer, the fourth conductive plug electrically connecting the third conductive layer and the ferroelectric capacitor.

[0019] In some embodiments, the first plate layer comprises titanium nitride, and the ferroelectric layer comprises zirconium-doped hafnium oxide.

[0020] Another aspect of the present disclosure provides a semiconductor device, which is manufactured using the aforementioned method.

[0021] Yet another aspect of the present disclosure provides an electronic device, comprising the aforementioned semiconductor device.

[0022] The semiconductor device, preparation method thereof, and electronic device of the embodiments disclosed herein form a second electrode layer including tungsten, and the second electrode layer serves as the upper electrode of the ferroelectric capacitor. By using the first bottom anti-reflection layer, the first oxide hard mask layer, the first metal hard mask layer, and the second bottom anti-reflection layer as masks, the second electrode layer, the ferroelectric dielectric layer, and the first electrode layer are etched to form a ferroelectric capacitor, thereby solving the problem in the related art of being unable to form a ferroelectric capacitor due to the addition of a tungsten layer on the upper electrode of the ferroelectric capacitor, thereby improving the residual polarization strength and the number of read and write times of the product, thereby improving the performance of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The following drawings of the present disclosure are incorporated herein as part of the present disclosure for understanding the present disclosure. The drawings show embodiments of the present disclosure and their descriptions are used to explain the principles of the present disclosure.

[0024] FIG1 shows a flow chart of a method for manufacturing a semiconductor device according to a specific embodiment of the present disclosure.

[0025] 2A-2F are schematic cross-sectional views of a device obtained by sequentially implementing the steps of a method for manufacturing a semiconductor device according to a specific embodiment of the present disclosure.

[0026] FIG3 shows a circuit netlist diagram of a 1T1C unit structure according to a specific embodiment of the present disclosure.

[0027] FIG. 4 shows an array layout of a 1T1C unit structure according to a specific embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] Next, the present disclosure will be described more fully in conjunction with the accompanying drawings, which illustrate embodiments of the present disclosure. However, the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make the disclosure thorough and complete and to fully convey the scope of the present disclosure to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals throughout represent like elements.

[0029] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part.

[0030] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0031] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0032] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implant passes as the implant is made. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to limit the scope of the present disclosure.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art of the present disclosure. It will also be understood that terms such as those defined in commonly used dictionaries should be understood to have a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0034] In order to fully understand the present disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed by the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0035] In the related art, adding a tungsten layer to the upper board of the MIM structure can effectively improve the residual polarization strength and read and write times of the product. However, after adding the tungsten layer, due to the physical and chemical properties of tungsten itself, etching cannot penetrate the tungsten layer and the MIM structure, and ultimately leads to the inability to form a ferroelectric capacitor. As a result, the related art cannot improve the residual polarization strength and read and write times of the product by adding a tungsten layer, and thus the performance of the product cannot be improved.

[0036] Therefore, in view of the existence of the aforementioned technical problems, the present disclosure proposes a method for preparing a semiconductor device, as shown in FIG1 , which mainly includes the following steps S1 to S4 .

[0037] Step S1: providing a substrate, on which a first interlayer dielectric layer is formed.

[0038] Step S2 : forming a first plate layer, a ferroelectric layer, and a second plate layer in sequence on the first interlayer dielectric layer, wherein the second plate layer comprises tungsten.

[0039] Step S3 , sequentially forming a patterned first bottom anti-reflection layer, a first oxide hard mask layer, a first metal hard mask layer, and a second bottom anti-reflection layer on the second electrode layer.

[0040] Step S4 , using the first bottom anti-reflection layer, the first oxide hard mask layer, the first metal hard mask layer and the second bottom anti-reflection layer as masks, etching the second electrode layer, the ferroelectric dielectric layer and the first electrode layer to form a ferroelectric capacitor.

[0041] The preparation method of the semiconductor device disclosed in the present invention forms a second electrode layer including tungsten, and the second electrode layer serves as the upper electrode of the ferroelectric capacitor. By using the first bottom anti-reflection layer, the first oxide hard mask layer, the first metal hard mask layer and the second bottom anti-reflection layer as masks, the second electrode layer, the ferroelectric dielectric layer and the first electrode layer are etched to form a ferroelectric capacitor. This solves the problem in the related art that a ferroelectric capacitor cannot be formed due to the addition of a tungsten layer on the upper electrode of the ferroelectric capacitor, thereby improving the residual polarization strength and the number of read and write times of the product, thereby improving the performance of the product.

[0042] Example 1

[0043] Below, the preparation method of the semiconductor device disclosed in the present invention is described in detail with reference to Figures 1 to 2F, wherein Figure 1 shows a flow chart of the preparation method of a semiconductor device according to a specific embodiment of the present invention, and Figures 2A-2F show cross-sectional schematic diagrams of the device obtained by sequentially implementing the steps of the preparation method of a semiconductor device according to a specific embodiment of the present invention.

[0044] Illustratively, the method for preparing a semiconductor device disclosed herein includes the following steps S1 to S4 .

[0045] First, step S1 is performed to provide a substrate, on which a first interlayer dielectric layer is formed.

[0046] The semiconductor device may be any suitable type of device known to those skilled in the art. In this embodiment, the technical solution of the present disclosure is explained and illustrated mainly by taking the case where the semiconductor device is a ferroelectric memory as an example.

[0047] Specifically, as shown in Figures 2A to 2C, substrate 200 includes a bulk silicon base. Substrate 200 may include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors. Substrate 200 may also include a multilayer structure consisting of at least two of Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors. Substrate 200 may include silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), or germanium on insulator (GeOI).

[0048] In one example, as shown in FIG2C , a first interlayer dielectric layer 201 is formed on a substrate 200. For example, various deposition methods commonly used in the art can be used to form the first interlayer dielectric layer 201, for example, it can be formed by a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method, or an atomic layer deposition (ALD) method. For example, the material of the first interlayer dielectric layer 201 may include insulating materials such as silicon dioxide, fluorocarbons, carbon-doped silicon oxide, or silicon carbonitride, and the present disclosure is not limited thereto. For example, after forming the first interlayer dielectric layer 201, the method for preparing the semiconductor device further includes: performing a planarization treatment on the first interlayer dielectric layer 201. For example, non-limiting examples of the planarization method include a mechanical planarization method or a chemical mechanical polishing planarization method.

[0049] Next, step S2 is performed to sequentially form a first plate layer, a ferroelectric dielectric layer, and a second plate layer on the first interlayer dielectric layer, wherein the second plate layer includes tungsten. Specifically, as shown in FIG2C , a first plate layer 202, a ferroelectric dielectric layer 203, and a second plate layer 204 are sequentially formed on the first interlayer dielectric layer 201, wherein the second plate layer 204 includes tungsten. Exemplarily, various deposition methods commonly used in the art can be used to form the first plate layer 202, the ferroelectric dielectric layer 203, and the second plate layer 204, for example, they can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In this embodiment, atomic layer deposition (ALD) is used to form the first plate layer 202, the ferroelectric dielectric layer 203, and the second plate layer 204. For example, the first electrode layer 202 is the lower electrode of the ferroelectric capacitor finally formed in the subsequent process, and the second electrode layer 204 is the upper electrode of the ferroelectric capacitor finally formed in the subsequent process, wherein the upper electrode 204 includes tungsten, which can improve the residual polarization strength and read and write times of the final product, thereby improving the overall performance of the product.

[0050] In one example, as shown in FIG2C , the second electrode layer 204 includes at least a top layer 2041 and a bottom layer 2042 stacked one above the other, wherein the top layer 2041 includes a tungsten layer and the bottom layer 2042 includes a titanium nitride layer. For example, the second electrode layer 204 includes a titanium nitride layer and a tungsten layer located on the titanium nitride layer, which can improve the residual polarization strength and read / write times of the final product, thereby improving the overall performance of the product. In other embodiments, the second electrode layer 204 may further include other conductive layers located between the top layer 2041 and the bottom layer 2042, and this disclosure is not limited thereto. Illustratively, the thickness of the top layer 2041 ranges from 1000 to 1700 angstroms. For example, the thickness of the top layer 2041 can be 1000 angstroms, 1100 angstroms, 1200 angstroms, 1300 angstroms, 1400 angstroms, 1500 angstroms, 1550 angstroms, 1600 angstroms, 1700 angstroms, etc. When the top layer 2041 is a tungsten layer, the thickness of the tungsten layer ranges from 1000 to 1700 angstroms. Illustratively, the thickness of the bottom layer 2042 is 250 angstroms. When the bottom layer 2042 is a titanium nitride layer, the thickness of the titanium nitride layer is 250 angstroms. In other embodiments, the bottom layer 2042 can also have any other suitable thickness range.

[0051] In one example, the first electrode layer 202 includes titanium nitride, and the ferroelectric dielectric layer 203 includes zirconium doped hafnium oxide. 1-x Zr x O2, also known as HZO) is an extension of hafnium oxide (HfO) based ferroelectric materials and is a new type of ferroelectric material. Compared with traditional ferroelectric materials, Hf 1-x Zr x O2's HfO2 (hafnium dioxide) and ZrO2 (zirconium dioxide) are used in the gate oxide of MOSFET (metal oxide semiconductor field effect transistor) and the dielectric layer of DRAM (dynamic random access memory). Therefore, HZO ferroelectric materials are well compatible with CMOS (complementary metal oxide semiconductor) processes. At the same time, they can also show strong ferroelectricity at an ultra-thin thickness of about 10nm, and have excellent scalability. In addition, based on the ultra-thin thickness, Hf 1-x Zr x O2 also exhibits significant advantages in ferroelectricity and erase speed. For example, the thickness of the first electrode layer 202 is 250 angstroms, and the thickness of the ferroelectric dielectric layer 203 is in the range of 6-10 nm. For example, the thickness of the ferroelectric dielectric layer 203 can be 6 nm, 7 nm, 7.5 nm, 8 nm, 9 nm, 10 nm, etc. In other embodiments, the first electrode layer 202 and the ferroelectric dielectric layer 203 can also have any other suitable thickness range.

[0052] Next, step S3 is performed to sequentially form a patterned first bottom anti-reflection layer, a first oxide hard mask layer, a first metal hard mask layer, and a second bottom anti-reflection layer on the second electrode layer. Specifically, as shown in FIG2D , a patterned first bottom anti-reflection layer 205, a first oxide hard mask layer 206, a first metal hard mask layer 207, and a second bottom anti-reflection layer 208 are sequentially formed on the second electrode layer 204.

[0053] In one example, as shown in FIG2C and FIG2D , a patterned first bottom anti-reflection layer 205, a first oxide hard mask layer 206, a first metal hard mask layer 207, and a second bottom anti-reflection layer 208 are sequentially formed on the second electrode layer 204, including: sequentially forming the first bottom anti-reflection layer 205, the first oxide hard mask layer 206, the first metal hard mask layer 207, the second bottom anti-reflection layer 208, and a patterned photoresist layer 209 on the second electrode layer; and sequentially etching the second bottom anti-reflection layer 208, the first metal hard mask layer 207, the first oxide hard mask layer 206, and the first bottom anti-reflection layer 205 using the patterned photoresist layer 209 as a mask to obtain the patterned first bottom anti-reflection layer 205, the first oxide hard mask layer 206, the first metal hard mask layer 207, and the second bottom anti-reflection layer 208. Exemplarily, the area covered by the patterned photoresist layer 209 is the area where the ferroelectric capacitor is to be formed in a subsequent process. For example, various deposition methods commonly used in the art may be used to form the first bottom anti-reflection layer 205, the first oxide hard mask layer 206, the first metal hard mask layer 207, and the second bottom anti-reflection layer 208. For example, they may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). For example, dry etching may be used in this step, including but not limited to reactive ion etching (RIE), ion beam etching, plasma etching, and other etching processes.

[0054] In one example, the first bottom anti-reflective layer 205 and the second bottom anti-reflective layer 208 include silicon oxynitride, the first metal hard mask layer 207 includes titanium nitride, and the first oxide hard mask layer 206 is formed by oxygen ion deposition. For example, the first oxide hard mask layer 206 can be formed by physical vapor deposition (PVD).

[0055] In one example, the thickness of the first bottom anti-reflection layer 205 ranges from 400 to 600 angstroms, for example, the thickness of the first bottom anti-reflection layer 205 can be 400 angstroms, 500 angstroms, 550 angstroms, 600 angstroms, etc.; the thickness of the first oxide hard mask layer 206 ranges from 100 to 200 angstroms, for example, the thickness of the first oxide hard mask layer 206 can be 100 angstroms, 150 angstroms, 180 angstroms, 200 angstroms, etc.; the thickness of the first metal hard mask layer 207 ranges from 400 to 600 angstroms, for example, the thickness of the first metal hard mask layer 207 can be 400 angstroms, 450 angstroms, 500 angstroms, 600 angstroms, etc.; the thickness of the second bottom anti-reflection layer 208 ranges from 300 to 350 angstroms, for example, the thickness of the second bottom anti-reflection layer 208 can be 300 angstroms, 310 angstroms, 320 angstroms, 330 angstroms, 340 angstroms, 350 angstroms, etc. For example, if the thickness of the first metal hard mask layer 207 is 500 angstroms, the first metal hard mask layer 207 may be deposited twice, with each deposition being 250 angstroms thick, so as to form a first metal hard mask layer 207 with a thickness of 500 angstroms.

[0056] In one example, when the top layer of the second electrode layer 204 includes a tungsten layer, first forming a first bottom anti-reflective layer 205 and a first oxide hard mask layer 206 on the second electrode layer 204 can help relieve the stress of the second electrode layer 204, which is beneficial to improving the performance of the ferroelectric capacitor finally formed. Secondly, when the second plate layer 204, the ferroelectric dielectric layer 203, and the first plate layer 202 are subsequently etched using the patterned first bottom anti-reflective layer 205, the first oxide hard mask layer 206, the first metal hard mask layer 207, and the second bottom anti-reflective layer 208 as a mask to form the ferroelectric capacitor, the patterned first bottom anti-reflective layer 205, the first oxide hard mask layer 206, the first metal hard mask layer 207, and the second bottom anti-reflective layer 208 are also etched away. The first metal hard mask layer 207 primarily protects the ferroelectric capacitor from being damaged by etching. Therefore, the thickness of the first metal hard mask layer 207 is generally selected to be 400-600 angstroms. A first metal hard mask layer 207 that is too thin may cause etching damage to the ferroelectric capacitor. In addition, the second bottom anti-reflective layer 208 is used to reduce light reflection during the photolithography process and facilitate the photolithography process steps such as resist coating and development.

[0057] Finally, step S4 is performed, using the first bottom anti-reflection layer, the first oxide hard mask layer, the first metal hard mask layer, and the second bottom anti-reflection layer as masks, etching the second plate layer, the ferroelectric dielectric layer, and the first plate layer to form a ferroelectric capacitor. Specifically, as shown in FIG2E , using the patterned first bottom anti-reflection layer 205, the first oxide hard mask layer 206, the first metal hard mask layer 207, and the second bottom anti-reflection layer 208 as masks, etching the second plate layer 204, the ferroelectric dielectric layer 203, and the first plate layer 202 to form a ferroelectric capacitor. Exemplarily, dry etching can be used in this step, including but not limited to reactive ion etching (RIE), ion beam etching, plasma etching, and other etching processes.

[0058] The above describes various embodiments of the method for preparing a semiconductor device of the present disclosure. The following is an embodiment of a combination of the above embodiments. Specifically, as shown in Figures 2C and 2D, first, the second bottom anti-reflection layer 208, the first metal hard mask layer 207, the first oxide hard mask layer 206, and the first bottom anti-reflection layer 205 are sequentially etched using the patterned photoresist layer 209 as a mask to obtain the patterned first bottom anti-reflection layer 205, the first oxide hard mask layer 206, the first metal hard mask layer 207, and the second bottom anti-reflection layer 208. Then, the second electrode layer 204, the ferroelectric dielectric layer 203, and the first electrode layer 202 are etched using the patterned first bottom anti-reflection layer 205, the first oxide hard mask layer 206, the first metal hard mask layer 207, and the second bottom anti-reflection layer 208 as a mask to form a ferroelectric capacitor. The second plate layer 204 includes at least a top layer 2041 and a bottom layer 2042 stacked one above the other, wherein the top layer 2041 includes a tungsten layer and the bottom layer 2042 includes a titanium nitride layer. Etching the second plate layer 204, the ferroelectric dielectric layer 203, and the first plate layer 202 to form a ferroelectric capacitor may include the following steps: first, etching the top layer 2041 of the second plate layer 204; then, etching the bottom layer 2042 of the second plate layer 204, the ferroelectric dielectric layer 203, and the first plate layer 202 to form the ferroelectric capacitor. For example, dry etching may be used in this step, including but not limited to reactive ion etching (RIE), ion beam etching, plasma etching, and other etching processes.

[0059] In one example, as shown in Figures 2A to 2D , the device further includes a transistor formed on a substrate 200, a first interlayer dielectric layer 201 covering the transistor, and a first conductive plug 210 formed in the first interlayer dielectric layer 201 to electrically connect the transistor and the ferroelectric capacitor. For example, as shown in Figure 2A , a shallow trench isolation structure 211 is also included.

[0060] Specifically, as shown in Figures 2A to 2C, the transistor includes a gate structure 212, a source region 213, and a drain region 214. The gate structure 212 includes a polysilicon gate layer and a gate dielectric layer, wherein the gate dielectric layer serves as an isolation and protection layer. Exemplarily, the gate structure 212 may further include sidewalls located on both sides of the polysilicon gate layer. Exemplarily, a self-aligned silicide layer is also formed on the gate structure 212, the source region 213, and the drain region 214.

[0061] In one example, as shown in Figures 2A to 2C, a second interlayer dielectric layer 215 is further formed between the first interlayer dielectric layer 201 and the substrate 200. For example, various deposition methods commonly used in the art can be used to form the second interlayer dielectric layer 215, for example, it can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD). For example, the material of the second interlayer dielectric layer 215 may include insulating materials such as silicon dioxide, fluorocarbons, carbon-doped silicon oxide, or silicon carbonitride, and the present disclosure is not limited to this. For example, after forming the second interlayer dielectric layer 215, the second interlayer dielectric layer 215 is further included: performing a planarization treatment on the second interlayer dielectric layer 215. For example, non-limiting examples of the planarization treatment include a mechanical planarization method or a chemical mechanical polishing planarization method.

[0062] In one example, as shown in Figures 2A to 2C, a first conductive layer 216 and a second conductive layer 217 are further formed in the first interlayer dielectric layer 201, and a second conductive plug 218 and a third conductive plug 219 are further formed in the second interlayer dielectric layer 215, wherein the second conductive plug 218 electrically connects the first conductive layer 216 and the drain region 214 of the transistor, and the third conductive plug 219 electrically connects the second conductive layer 217 and the source region 213 of the transistor, so that the ferroelectric capacitor can be electrically connected to the source region 213 of the transistor through the first conductive plug 210, the second conductive layer 217 and the third conductive plug 219.

[0063] In one example, as shown in FIG2F , after forming the ferroelectric capacitor, the method further includes: forming a third interlayer dielectric layer 220, the third interlayer dielectric layer 220 covering the first interlayer dielectric layer 201 and the ferroelectric capacitor; forming a fourth conductive plug 221 in the third interlayer dielectric layer 220; and forming a third conductive layer 222 on the third interlayer dielectric layer 220, the fourth conductive plug 221 electrically connecting the third conductive layer 222 and the ferroelectric capacitor. Exemplarily, the material of the third interlayer dielectric layer 220 may include an insulating material such as silicon dioxide, fluorocarbon, carbon-doped silicon oxide, or silicon carbonitride, but this disclosure is not limited thereto. Exemplarily, the third interlayer dielectric layer 220 may be formed using various deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Exemplarily, after forming the third interlayer dielectric layer 220, the method further includes: performing a planarization process on the third interlayer dielectric layer 220. For example, non-limiting examples of the planarization process include mechanical planarization or chemical mechanical polishing. For example, after forming the third interlayer dielectric layer 220, an annealing process is further performed to activate the ferroelectric properties of the ferroelectric dielectric layer 203 in the ferroelectric capacitor.

[0064] In one example, a transistor and a ferroelectric capacitor can together form a 1T1C (1 Transistor-1 Capacitor) unit structure, wherein the polysilicon gate layer in the transistor's gate structure 212 serves as a word line (WL), the first conductive layer 216 serves as a bit line (BL), and the third conductive layer 222 serves as a plate line (PL). The circuit netlist and array layout of the 1T1C unit structure are shown in Figures 3 and 4, respectively. By way of example, the ferroelectric capacitor is gated by controlling WL, and BL and PL apply positive and negative voltages to the ferroelectric capacitor, respectively. Because the intermediate ferroelectric dielectric layer 203 has ferroelectric properties, different iron domains (polarizations) are formed under positive and negative electric fields. These iron domains do not disappear with the removal of the external electric field, thereby allowing the ferroelectric capacitor to store different charges and achieve a storage function.

[0065] The description of the key steps of the method for preparing the semiconductor device disclosed in the present invention has been completed. The preparation of a complete semiconductor device may also include other steps, which will not be described in detail here.

[0066] It is worth mentioning that the above steps are only examples, and the order of the above steps can be adjusted without conflict.

[0067] In summary, the preparation method of the semiconductor device disclosed in the present invention forms a second electrode layer including tungsten, and the second electrode layer serves as the upper electrode of the ferroelectric capacitor. By using the first bottom anti-reflection layer, the first oxide hard mask layer, the first metal hard mask layer and the second bottom anti-reflection layer as masks, the second electrode layer, the ferroelectric dielectric layer and the first electrode layer are etched to form a ferroelectric capacitor, which solves the problem in the related art that a ferroelectric capacitor cannot be formed due to the addition of a tungsten layer on the upper electrode of the ferroelectric capacitor, thereby improving the residual polarization strength and the number of read and write times of the product, thereby improving the performance of the product.

[0068] Example 2

[0069] The present disclosure also provides a semiconductor device, which is prepared by the method of the aforementioned embodiment 1. Specifically, as shown in Figure 2F, the semiconductor device includes a substrate 200, a first interlayer dielectric layer 201 on the substrate 200, and a first electrode layer 202, a ferroelectric dielectric layer 203 and a second electrode layer 204 on the first interlayer dielectric layer 201. The first electrode layer 202, the ferroelectric dielectric layer 203 and the second electrode layer 204 together form a ferroelectric capacitor, wherein the second electrode layer 204 includes tungsten.

[0070] In one example, the substrate 200 includes a bulk silicon substrate. The substrate 200 may include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors. The substrate 200 may also include a multilayer structure consisting of at least two of Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors. The substrate 200 may include silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), or germanium on insulator (GeOI).

[0071] This concludes the introduction to the structure of the semiconductor device disclosed herein. A complete device may also include other components, which will not be detailed here.

[0072] Since the semiconductor device disclosed herein has a second plate layer comprising tungsten and the second plate layer serves as the upper plate of the ferroelectric capacitor, the residual polarization strength and the number of read and write times of the product are increased, thereby improving the performance of the product.

[0073] Example 3

[0074] The present disclosure further provides an electronic device, which includes the semiconductor device described in the second embodiment or the semiconductor device prepared by the method described in the first embodiment.

[0075] The electronic device can be any electronic product or device, such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD, DVD, navigation system, camera, camcorder, voice recorder, MP3, MP4, PSP, or any other electronic product or device. It can also be an intermediate product incorporating the aforementioned semiconductor device, such as a mobile phone motherboard incorporating the integrated circuit. The electronic device of the disclosed embodiment has improved performance due to its use of the aforementioned semiconductor device.

[0076] Although a number of embodiments have been described herein, it should be understood that a variety of other modifications and embodiments may be devised by those skilled in the art, all of which fall within the spirit and scope of the concepts of the present disclosure. More particularly, various modifications and changes may be made to the arrangements and / or component parts of the subject matter within the scope of the present disclosure, the drawings, and the appended claims. In addition to modifications and changes to the component parts and / or arrangements, the use of alternatives will also be readily apparent to those skilled in the art.

Claims

1. A method for preparing a semiconductor device, characterized in that: The method comprises: providing a substrate on which a first interlayer dielectric layer is formed; forming a first plate layer, a ferroelectric dielectric layer and a second plate layer from bottom to top on the first interlayer dielectric layer, wherein the second plate layer comprises tungsten; forming a patterned first bottom anti-reflection layer, a patterned first oxide hard mask layer, a patterned first metal hard mask layer and a patterned second bottom anti-reflection layer from bottom to top on the second electrode layer; Using the patterned first bottom anti-reflection layer, the patterned first oxide hard mask layer, the patterned first metal hard mask layer and the patterned second bottom anti-reflection layer as masks, the second plate layer, the ferroelectric dielectric layer and the first plate layer are etched to form a ferroelectric capacitor.

2. The preparation method according to claim 1, characterized in that: The patterned first bottom anti-reflection layer and the patterned second bottom anti-reflection layer include silicon oxynitride, and the patterned first metal hard mask layer includes titanium nitride.

3. The preparation method according to claim 1, characterized in that: The thickness of the patterned first bottom anti-reflection layer ranges from 400 to 600 angstroms, the thickness of the patterned first oxide hard mask layer ranges from 100 to 200 angstroms, the thickness of the patterned first metal hard mask layer ranges from 400 to 600 angstroms, and the thickness of the patterned second bottom anti-reflection layer ranges from 300 to 350 angstroms.

4. The preparation method according to claim 1, characterized in that: The second electrode layer at least includes a top layer and a bottom layer stacked up and down, wherein the top layer includes a tungsten layer, and the bottom layer includes a titanium nitride layer.

5. The preparation method according to claim 4, characterized in that: The thickness of the top layer ranges from 1000-1700 angstroms.

6. The preparation method according to claim 1, characterized in that: The method of forming a patterned first bottom anti-reflection layer, a patterned first oxide hard mask layer, a patterned first metal hard mask layer and a patterned second bottom anti-reflection layer from bottom to top on the second electrode layer includes: forming a first bottom anti-reflection layer, a first oxide hard mask layer, a first metal hard mask layer, a second bottom anti-reflection layer and a patterned photoresist layer from bottom to top on the second electrode layer; Using the patterned photoresist layer as a mask, the second bottom anti-reflective layer, the first metal hard mask layer, the first oxide hard mask layer and the first bottom anti-reflective layer are etched to obtain the patterned first bottom anti-reflective layer, the patterned first oxide hard mask layer, the patterned first metal hard mask layer and the patterned second bottom anti-reflective layer.

7. The preparation method according to claim 1, characterized in that: The preparation method further includes: forming a transistor on the substrate, wherein the first interlayer dielectric layer covers the transistor, and a first conductive plug is formed in the first interlayer dielectric layer to electrically connect the transistor and the ferroelectric capacitor.

8. The preparation method according to claim 7, characterized in that: The preparation method further comprises: forming a second interlayer dielectric layer between the first interlayer dielectric layer and the substrate; forming a second conductive plug and a third conductive plug in the second interlayer dielectric layer; A first conductive layer and a second conductive layer are formed in the first interlayer dielectric layer, wherein the second conductive plug electrically connects the first conductive layer and the drain region of the transistor, and the third conductive plug electrically connects the second conductive layer and the source region of the transistor.

9. The preparation method according to claim 1, characterized in that: The ferroelectric capacitor comprises an etched second plate layer, an etched ferroelectric dielectric layer and an etched first plate layer. After forming the ferroelectric capacitor, the preparation method further comprises: forming a third interlayer dielectric layer, wherein the third interlayer dielectric layer covers the first interlayer dielectric layer and the ferroelectric capacitor; forming a fourth conductive plug in the third interlayer dielectric layer; A third conductive layer is formed on the third interlayer dielectric layer, and the fourth conductive plug electrically connects the third conductive layer and the ferroelectric capacitor.

10. The preparation method according to any one of claims 1 to 9, characterized in that: The first electrode layer includes titanium nitride, and the ferroelectric dielectric layer includes zirconium-doped hafnium oxide.

11. A semiconductor device, characterized in that: The semiconductor device is prepared by the method according to any one of claims 1 to 10.

12. An electronic device, characterized in that: The electronic device includes the semiconductor device according to claim 11.

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