Data processing method and apparatus

Abstract

A data processing method and apparatus, relating to the technical field of communications. The method is applied to flexible Ethernet (FlexE). The method comprises: receiving an initial data stream sent by a FlexE instance; and periodically inserting a padding sequence into the initial data stream to obtain a first data stream, wherein the first data stream comprises the padding sequence which appears periodically, the padding sequence comprises n consecutive padding code blocks, and n is an integer greater than or equal to 4. The present application provides a FlexE-oriented method capable of inserting more padding code blocks into a data stream, and the method can be applicable to higher-rate PHY interfaces such as an 800 gigabyte Ethernet (GE) PHY interface and a 1.6 TE PHY interface, and can adapt to the evolution of Ethernet standards.

Description

Data processing method and device

[0001] This application claims priority to Chinese patent application filed on November 30, 2023, with application number 202311654455.0 and application name “Data Processing Method and Apparatus,” the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to a data processing method and device. Background Art

[0003] In the communications field, Ethernet technology inserts alignment markers (AMs) to implement multi-channel alignment and block delimiting at the physical layer (PHY). Specifically, the transmitting PHY interface periodically inserts AM blocks into the data stream and transmits the data stream containing the AM blocks. After receiving the data stream containing the AM blocks, the receiving PHY interface locates and removes the AM blocks from the data stream and sends the remaining blocks to higher layers for processing. Typically, different PHY interface rates insert different AM blocks into the data stream. For example, according to current standards, the AM insertion ratio of a 100 Gigabit Ethernet (GE) PHY interface is 1 / 16384 (i.e., a 100GE PHY interface inserts one AM code block every 16383 code blocks in the data stream), the AM insertion ratios of 50GE PHY interfaces, 200GE PHY interfaces, 400GE PHY interfaces, and 800GE PHY interfaces are all 1 / 20480, and the AM insertion ratio of a 1.6 Terabit Ethernet (TE) PHY interface is 1 / 81920.

[0004] The Flexible Ethernet (FlexE) protocol is a standard protocol defined by the Optical Internetworking Forum (OIF) standardization organization. The FlexE protocol introduces the concept of a FlexE port. A FlexE port includes several 50GE PHY interfaces, 100GE PHY interfaces, 200GE PHY interfaces and / or 400GE PHY interfaces, and may also include 800GE PHY interfaces, 1.6TE PHY interfaces, etc. in the future. The available bandwidth of a FlexE port is the sum of the available bandwidth provided by the PHY interfaces in the FlexE port to the FlexE port. The available bandwidth provided by the PHY interface to the FlexE port is the bandwidth of the PHY interface after deducting the AM overhead (that is, the bandwidth occupied by the AM code block) from the bandwidth of the PHY interface. Since the AM insertion ratios of PHY interfaces of different rates are different, the available bandwidth provided to the FlexE port by PHY interfaces of different rates is different. In order to enable intercommunication between FlexE ports composed of PHY interfaces of different rates, it is necessary to insert pad code blocks into the data stream sent by the FlexE port with larger available bandwidth to occupy space, thereby reducing the available bandwidth of the FlexE port.

[0005] The current FlexE standard defines a method for inserting padding blocks. The transmitter inserts two padding blocks every 163,830 blocks in the data stream. However, this method is primarily designed for 50GE, 200GE, and 400GE PHY interfaces. As Ethernet standards evolve, PHY interface rates continue to increase toward 800GE and 1.6TE. This method is difficult to apply to higher-rate PHY interfaces, such as 800GE and 1.6TE. Summary of the Invention

[0006] This application provides a data processing method and apparatus. The technical solution of this application is targeted at FlexE and can insert a large number of padding blocks into the data stream. It is applicable to higher-speed PHY interfaces such as 800GE PHY interfaces and 1.6TE PHY interfaces, and can adapt to the evolution of Ethernet standards. The solution of this application is as follows.

[0007] In a first aspect, a data processing method is provided, applied to FlexE, the method comprising: receiving an initial data stream sent by a FlexE instance; periodically inserting a padding sequence into the initial data stream to obtain a first data stream, the first data stream including the periodically appearing padding sequence, the padding sequence including n consecutive padding code blocks, where n is an integer greater than or equal to 4.

[0008] The data processing method may be executed by a FlexE shim at the transmitting end, specifically by a pad processing module in the FlexE shim.

[0009] The technical solution provided by the present application is that the padding sequence periodically inserted into the initial data stream includes n consecutive padding code blocks, where n is an integer greater than or equal to 4. Thus, the present application provides a FlexE-oriented method for inserting a large number of padding code blocks into a data stream, which is applicable to higher-speed PHY interfaces such as 800GE PHY interfaces and 1.6TE PHY interfaces, and can adapt to the evolution of Ethernet standards.

[0010] In a second aspect, a data processing method is provided, which is applied to FlexE. The method includes: receiving an initial data stream, which is obtained by interleaving multiple data streams sent by multiple FlexE instances; periodically inserting a padding sequence into the initial data stream to obtain a first data stream, wherein the first data stream includes the periodically appearing padding sequence, and the padding sequence includes n consecutive padding code blocks, where n is an integer greater than or equal to 16.

[0011] The data processing method may be executed by a FlexE shim at the transmitting end, specifically by a pad processing module in the FlexE shim.

[0012] The technical solution provided by the present application is that the padding sequence periodically inserted into the initial data stream includes n consecutive padding code blocks, where n is an integer greater than or equal to 16. Thus, the present application provides a FlexE-oriented method for inserting a large number of padding code blocks into a data stream, which is applicable to higher-speed PHY interfaces such as 800GE PHY interfaces and 1.6TE PHY interfaces, and can adapt to the evolution of Ethernet standards.

[0013] Optionally, in the first and second aspects above, the n filler code blocks include x first filler code blocks and y second filler code blocks, the first filler code block is a globally unique control code block in the first data stream, the second filler code block is an error code block, x is a positive integer, and y is a positive integer. For example, the first filler code block is a P1 code block in the current FlexE standard, and the second filler code block is a P2 code block in the current FlexE standard.

[0014] The technical solution provided by this application facilitates the FlexE shim at the receiving end to find the first padding block and, based on it, the padding sequence inserted into the initial data stream by the transmitting FlexE shim. Because the first padding block is the P1 block in the current FlexE standard, and the second padding block is the P2 block in the current FlexE standard, the technical solution provided by this application effectively inherits the pad encapsulation format of the current FlexE standard, simplifying implementation.

[0015] Optionally, in the first aspect and the second aspect, the n padding code blocks include x first padding code blocks and y second padding code blocks, and the x first padding code blocks and the y second padding code blocks satisfy any one of the following conditions:

[0016] x=1, y=n-1, the y second filling code blocks are located after the first filling code block, and the y second filling code blocks are continuous with the first filling code block; or,

[0017] n is an even number, x=y=n / 2, the y second padding code blocks are located after the x first padding code blocks, and the y second padding code blocks are continuous with the x first padding code blocks; or,

[0018] n is an even number, x=y=n / 2, the padding sequence includes n / 2 code block groups, each code block group includes a first padding code block and a second padding code block, in each code block group, the second padding code block is located after the first padding code block and is continuous with the first padding code block, and the padding code blocks in the n / 2 code block groups are continuous; or

[0019] The x first filling code blocks include x1 first filling code blocks and x2 first filling code blocks, the y second filling code blocks are located between the x1 first filling code blocks and the x2 first filling code blocks, the x1 first filling code blocks, the y second filling code blocks and the x2 first filling code blocks are continuous, x1+x2=x, x1 and x2 are both positive integers.

[0020] Optionally, in the first aspect and the second aspect, the n padding code blocks include x first padding code blocks and y second padding code blocks, and the n padding code blocks further include z third padding code blocks, where z is a positive integer;

[0021] The y second filling code blocks are located after the x first filling code blocks and before the z third filling code blocks, and the x first filling code blocks, the y second filling code blocks, and the z third filling code blocks are continuous; or,

[0022] The z third filling code blocks are located after the x first filling code blocks and before the y second filling code blocks. The x first filling code blocks, the z third filling code blocks, and the y second filling code blocks are continuous.

[0023] Optionally, in the above-mentioned first and second aspects, the third filling code block is a data code block.

[0024] The technical solution provided by the present application is that since the third filling code block is a data code block, and the first filling code block and the second filling code block are both control code blocks, therefore, when the n consecutive filling code blocks in the filling sequence include x first filling code blocks, y second filling code blocks and z third filling code blocks, the z third filling code blocks are arranged between the x first filling code blocks and the y second filling code blocks, so that the z third filling code blocks are not adjacent to the actual data code blocks in the first data stream, which can avoid confusion between the third filling code block and the actual data code blocks in the first data stream, thereby avoiding contamination of the actual data code blocks in the first data stream by the third filling code block.

[0025] Optionally, in the first and second aspects above, the third filling code block includes at least one code block identifier. For example, the at least one code block identifier is a plurality of code block identifiers.

[0026] The technical solution provided by this application, because the third padding code block includes at least one code block identifier, allows the FlexE shim at the receiving end to identify the third padding code block only by identifying the code block identifier in the third padding code block, thereby simplifying the process of the FlexE shim at the receiving end searching for the third padding code block. If the third padding code block includes multiple code block identifiers, even if some of the multiple code block identifiers experience bit errors during the transmission of the third padding code block, the FlexE shim at the receiving end can still find the third padding code block based on the correct code block identifiers among the multiple code block identifiers, thereby improving the fault tolerance of the FlexE shim at the receiving end in searching for the third padding code block.

[0027] The present application reduces the dependency between the padding code blocks in the padding sequence by setting the third padding code block to include a code block identifier. Even if some padding code blocks in the padding sequence are erroneous, it does not affect the FlexE shim at the receiving end from searching for the padding sequence in the first data stream.

[0028] Optionally, in the first and second aspects above, the third filler code block further includes at least one check mark, which is used to verify the correctness of the at least one code block identifier in the third filler code block. That is, the third filler code block includes at least one code block identifier and at least one check mark. For example, the third filler code block includes multiple code block identifiers and multiple check marks.

[0029] The technical solution provided by the present application is that, since the third padding code block includes at least one code block identifier and at least one check identifier, the FlexE shim at the receiving end can verify the correctness of the at least one code block identifier based on the at least one check identifier during the process of searching for the third padding code block, and then identify the third padding code block based on the correct code block identifier among the at least one check identifier, thereby simplifying the process of the FlexE shim at the receiving end searching for the third padding code block. In the case where the third padding code block includes multiple code block identifiers and multiple check identifiers, even if some of the multiple code block identifiers and / or the multiple check identifiers have errors during the transmission of the third padding code block, the FlexE shim at the receiving end can still verify the correctness of the multiple code block identifiers based on the correct check identifier among the multiple check identifiers, and then find the third padding code block based on the correct code block identifier among the multiple code block identifiers, thereby improving the fault tolerance of the FlexE shim at the receiving end in searching for the third padding code block.

[0030] Optionally, in the first aspect and the second aspect, in the third filling code block, the number of the at least one code block identifier is equal to the number of the at least one check identifier; or, the sum of the number of the at least one code block identifier and the number of the at least one check identifier is an odd number.

[0031] The technical solution provided by the present application sets the number of code block identifiers in the third filling code block to be equal to the number of check identifiers, or the sum of the number of code block identifiers and the number of check identifiers to be an odd number, which can facilitate the FlexE shim at the receiving end to find the third filling code block. For example, for any third filling code block, when the number of code block identifiers in the third filling code block is equal to the number of check identifiers, the code block identifiers and check identifiers in the third filling code block can have a one-to-one correspondence, and each check identifier is used to verify the correctness of the corresponding code block identifier. When the FlexE shim at the receiving end successfully verifies at least one code block identifier in the third filling code block, the FlexE shim at the receiving end considers that the at least one code block identifier is correct, and the FlexE shim at the receiving end considers that the third filling code block has been successfully identified, that is, that the third filling code block has been found. For another example, for any third padding code block, if the sum of the number of code block identifiers and the number of check identifiers in the third padding code block is an odd number, and the FlexE shim at the receiving end, in the process of searching for the third padding code block, determines that the sum of the number of correct code block identifiers and the number of correct check identifiers in the third padding code block exceeds half of the sum of the number of code block identifiers and the number of check identifiers in the third padding code block, the FlexE shim at the receiving end deems that the third padding code block has been successfully identified, that is, the third padding code block has been found. Optionally, if the sum of the number of code block identifiers and the number of check identifiers in the third padding code block is an odd number, and half of the sum of the number of code block identifiers and the number of check identifiers in the third padding code block is not an integer, in which case half of the sum of the number of code block identifiers and the number of check identifiers in the third padding code block may be rounded up for identification and judgment.

[0032] In a third aspect, a data processing method is provided, which is applied to FlexE. The method includes: obtaining a first data stream, where the first data stream is one of the multiple data streams obtained by deinterleaving, and the first data stream includes a periodically appearing filling sequence, and the filling sequence includes n consecutive filling code blocks, where n is an integer greater than or equal to 4; searching for filling code blocks in the first data stream to find the filling sequence; determining that the filling sequence is found when multiple filling code blocks found consecutively in the first data stream meet a preset condition, and the preset condition includes: the number of the multiple filling code blocks is greater than a preset threshold and the number of the multiple filling code blocks is less than or equal to n.

[0033] The data processing method may be executed by a FlexE shim at the receiving end, specifically by a pad processing module in the FlexE shim.

[0034] The technical solution provided by the present application is that since the first data stream includes a periodically appearing filling sequence, the filling sequence includes n consecutive filling code blocks, where n is an integer greater than or equal to 4. Therefore, the present application provides a FlexE-oriented method for inserting more filling code blocks in the data stream, which can be applied to higher-speed PHY interfaces such as 800GE PHY interfaces and 1.6TE PHY interfaces, and can adapt to the evolution of Ethernet standards. Since the FlexE shim at the receiving end determines that the filling sequence is found when the number of multiple filling code blocks found continuously in the first data stream is greater than a preset threshold and less than or equal to n, and the number of multiple filling code blocks found continuously does not need to be equal to n, that is, it is not necessary for all filling code blocks in the filling sequence to be detected correctly, the present application provides a method for finding the filling sequence using a soft decision method. The process of the FlexE shim at the receiving end finding the filling sequence is relatively relaxed, the fault tolerance capability of finding the filling sequence is better, and the probability of successfully finding the filling sequence can be maintained without degradation.

[0035] In a fourth aspect, a data processing method is provided, which is applied to FlexE, and the method includes: obtaining a first data stream, the first data stream is obtained by periodically inserting a filling sequence into an initial data stream, and the initial data stream is obtained by interleaving multiple data streams sent by multiple FlexE instances, the first data stream includes the periodically appearing filling sequence, and the filling sequence includes n consecutive filling code blocks, where n is an integer greater than or equal to 16; searching for filling code blocks in the first data stream to find the filling sequence; determining that the filling sequence is found when multiple filling code blocks found continuously in the first data stream meet a preset condition, and the preset condition includes: the number of the multiple filling code blocks is greater than a preset threshold and the number of the multiple filling code blocks is less than or equal to n.

[0036] The data processing method may be executed by a FlexE shim at the receiving end, specifically by a pad processing module in the FlexE shim.

[0037] The technical solution provided by the present application is that since the first data stream includes a periodically appearing padding sequence, the padding sequence includes n consecutive padding code blocks, where n is an integer greater than or equal to 16, the present application provides a FlexE-oriented method for inserting more padding code blocks in the data stream, which can be applied to higher-speed PHY interfaces such as 800GE PHY interfaces and 1.6TE PHY interfaces, and can adapt to the evolution of Ethernet standards. Since the FlexE shim at the receiving end determines that the padding sequence is found when the number of multiple padding code blocks found continuously in the first data stream is greater than a preset threshold and less than or equal to n, and the number of multiple padding code blocks found continuously does not need to be equal to n, that is, it is not necessary for all padding code blocks in the padding sequence to be detected correctly, the present application provides a method for finding the padding sequence using a soft decision method, and the process of the FlexE shim at the receiving end finding the padding sequence is relatively relaxed, the fault tolerance capability of finding the padding sequence is better, and the probability of successfully finding the padding sequence can be maintained without degradation.

[0038] Optionally, in the above-mentioned third and fourth aspects, the n filling code blocks include x first filling code blocks and y second filling code blocks, the first filling code block is a globally unique control code block in the first data stream, the second filling code block is an error code block, x is a positive integer, and y is a positive integer.

[0039] Optionally, in the third and fourth aspects above, the n padding code blocks include x first padding code blocks and y second padding code blocks, and the x first padding code blocks and the y second padding code blocks satisfy any one of the following conditions:

[0040] x=1, y=n-1, the y second filling code blocks are located after the first filling code block, and the y second filling code blocks are continuous with the first filling code block; or,

[0041] n is an even number, x=y=n / 2, the y second padding code blocks are located after the x first padding code blocks, and the y second padding code blocks are continuous with the x first padding code blocks; or,

[0042] n is an even number, x=y=n / 2, the padding sequence includes n / 2 code block groups, each code block group includes a first padding code block and a second padding code block, in each code block group, the second padding code block is located after the first padding code block and is continuous with the first padding code block, and the padding code blocks in the n / 2 code block groups are continuous; or

[0043] The x first filling code blocks include x1 first filling code blocks and x2 first filling code blocks, the y second filling code blocks are located between the x1 first filling code blocks and the x2 first filling code blocks, the x1 first filling code blocks, the y second filling code blocks and the x2 first filling code blocks are continuous, x1+x2=x, x1 and x2 are both positive integers.

[0044] Optionally, in the third and fourth aspects above, the n padding code blocks include x first padding code blocks and y second padding code blocks, and the n padding code blocks further include z third padding code blocks, where z is a positive integer;

[0045] The y second filling code blocks are located after the x first filling code blocks and before the z third filling code blocks, and the x first filling code blocks, the y second filling code blocks, and the z third filling code blocks are continuous; or,

[0046] The z third filling code blocks are located after the x first filling code blocks and before the y second filling code blocks. The x first filling code blocks, the z third filling code blocks, and the y second filling code blocks are continuous.

[0047] Optionally, in the third and fourth aspects above, the third filling code block is a data code block.

[0048] Optionally, in the third and fourth aspects above, the third filling code block includes at least one code block identifier.

[0049] Optionally, in the third and fourth aspects above, the third filling code block further includes at least one check mark, and the at least one check mark is used to check the correctness of the at least one code block mark.

[0050] Optionally, in the above-mentioned third aspect and fourth aspect, in the third filling code block, the number of the at least one code block identifier is equal to the number of the at least one check identifier; or, the sum of the number of the at least one code block identifier and the number of the at least one check identifier is an odd number.

[0051] Optionally, in the above-mentioned third and fourth aspects, the n filling code blocks include x first filling code blocks, the first filling code block is a globally unique control code block in the first data stream, x is a positive integer, and searching for filling code blocks in the first data stream to find the filling sequence includes: searching for the first filling code block in the first data stream; and searching for the filling sequence in the first data stream based on the first filling code block found in the first data stream.

[0052] Optionally, in the third and fourth aspects above, searching for the padding sequence in the first data stream based on a first padding code block found in the first data stream includes: determining n-1 code blocks following a first first padding code block found in the first data stream, the n-1 code blocks being continuous and the n-1 code blocks being continuous with the first first padding code block; and searching for the padding code block in the n-1 code blocks by detecting the n-1 code blocks. Optionally, the multiple padding code blocks found continuously in the first data stream include the first first padding code block found in the first data stream and the padding code blocks found in the n-1 code blocks following the first first padding code block.

[0053] The technical solution provided by the present application is that after the FlexE shim at the receiving end finds the first first filling code block in the first data stream, it searches for a filling code block in the n-1 code blocks after the first first filling code block. This can avoid the length of the data segment between the first filling code block and the last filling code block among the multiple filling code blocks successively found by the FlexE shim at the receiving end in the first data stream being greater than n, that is, avoiding the multiple filling code blocks successively found by the FlexE shim at the receiving end not being filling code blocks in the same filling sequence.

[0054] Optionally, detecting the n-1 code blocks to search for a filling code block in the n-1 code blocks includes: mapping the first filling code block and the n-1 code blocks into a code block bitmap; and detecting the n-1 code blocks based on the code block bitmap to search for a filling code block in the n-1 code blocks.

[0055] The technical solution provided by the present application is that the FlexE shim at the receiving end maps the first first filling code block and the n-1 code blocks after the first first filling code block found in the first data stream into a code block bitmap each time it searches for a filling sequence, and then searches for the filling code block based on the code block bitmap. This can avoid the situation where the FlexE shim at the receiving end successively finds multiple filling code blocks that are not filling code blocks in the same filling sequence.

[0056] Optionally, the n filling code blocks include a third filling code block, the third filling code block includes at least one code block identifier, and mapping the first first filling code block and the n-1 code blocks into the code block bitmap includes: mapping the third filling code block into the code block bitmap based on the code block identifier in the third filling code block.

[0057] In the technical solution provided by the present application, since the third filling code block includes a code block identifier, the FlexE shim at the receiving end can conveniently map the third filling code block into a code block bitmap based on the code block identifier in the third filling code block.

[0058] Optionally, the third filling code block also includes at least one check identifier, and mapping the third filling code block to the code block bitmap based on the code block identifier in the third filling code block includes: checking the correctness of the at least one code block identifier based on the at least one check identifier; and mapping the third filling code block to the code block bitmap based on the correct code block identifier in the at least one code block identifier.

[0059] The technical solution provided by the present application is that since the third filling code block includes a check identifier, the FlexE shim at the receiving end can verify the correctness of the code block identifier in the third filling code block based on the check identifier in the third filling code block, thereby preventing the FlexE shim at the receiving end from mapping the third filling code block into the code block bitmap based on an incorrect code block identifier, thereby improving the accuracy of the FlexE shim at the receiving end in mapping the third filling code block.

[0060] In a fifth aspect, a data processing device is provided for use in FlexE. The data processing device includes at least one functional unit configured to execute the method provided in the first aspect or any optional embodiment of the first aspect. The at least one functional unit may be implemented based on software, hardware, or a combination of software and hardware, and may be combined or divided based on the specific implementation.

[0061] Optionally, the data processing device includes: a transceiver unit and a processing unit. The transceiver unit is configured to perform the transceiver operations in the method provided in the first aspect or any optional embodiment of the first aspect, and the processing unit is configured to perform operations other than the transceiver operations in the method provided in the first aspect or any optional embodiment of the first aspect.

[0062] Optionally, the transceiver unit is configured to receive an initial data stream sent by the FlexE instance;

[0063] The processing unit is configured to periodically insert a filling sequence into the initial data stream to obtain a first data stream, wherein the first data stream includes the periodically appearing filling sequence, and the filling sequence includes n consecutive filling code blocks, where n is an integer greater than or equal to 4.

[0064] In a sixth aspect, a data processing device is provided for use in FlexE. The data processing device includes at least one functional unit configured to execute the method provided in the second aspect or any optional embodiment of the second aspect. The at least one functional unit may be implemented based on software, hardware, or a combination of software and hardware, and may be combined or divided based on the specific implementation.

[0065] Optionally, the data processing device includes: a transceiver unit and a processing unit. The transceiver unit is configured to perform the transceiver operations in the method provided in the second aspect or any optional manner of the second aspect, and the processing unit is configured to perform operations other than the transceiver operations in the method provided in the second aspect or any optional manner of the second aspect.

[0066] Optionally, the transceiver unit is configured to receive an initial data stream, where the initial data stream is obtained by interleaving multiple data streams sent by multiple FlexE instances;

[0067] The processing unit is configured to periodically insert a filling sequence into the initial data stream to obtain a first data stream, wherein the first data stream includes the periodically appearing filling sequence, and the filling sequence includes n consecutive filling code blocks, where n is an integer greater than or equal to 16.

[0068] Optionally, in the above-mentioned fifth and sixth aspects, the n filling code blocks include x first filling code blocks and y second filling code blocks, the first filling code block is a globally unique control code block in the first data stream, the second filling code block is an error code block, the x is a positive integer, and the y is a positive integer.

[0069] Optionally, in the fifth and sixth aspects above, the x first filling code blocks and the y second filling code blocks satisfy any one of the following conditions:

[0070] x=1, y=n-1, the y second filling code blocks are located after the first filling code block, and the y second filling code blocks are continuous with the first filling code block; or,

[0071] The n is an even number, x=y=n / 2, the y second padding code blocks are located after the x first padding code blocks, and the y second padding code blocks are continuous with the x first padding code blocks; or,

[0072] n is an even number, x=y=n / 2, the padding sequence includes n / 2 code block groups, each code block group includes one first padding code block and one second padding code block, in each code block group, the second padding code block is located after the first padding code block and is continuous with the first padding code block, and the padding code blocks in the n / 2 code block groups are continuous; or

[0073] The x first filling code blocks include x1 first filling code blocks and x2 first filling code blocks, the y second filling code blocks are located between the x1 first filling code blocks and the x2 first filling code blocks, the x1 first filling code blocks, the y second filling code blocks and the x2 first filling code blocks are continuous, x1+x2=x, and x1 and x2 are both positive integers.

[0074] Optionally, in the fifth and sixth aspects above, the n padding code blocks further include z third padding code blocks, where z is a positive integer;

[0075] The y second filling code blocks are located after the x first filling code blocks and before the z third filling code blocks, and the x first filling code blocks, the y second filling code blocks, and the z third filling code blocks are continuous; or,

[0076] The z third filling code blocks are located after the x first filling code blocks and before the y second filling code blocks, and the x first filling code blocks, the z third filling code blocks and the y second filling code blocks are continuous.

[0077] Optionally, in the fifth and sixth aspects above, the third filling code block is a data code block.

[0078] Optionally, in the fifth and sixth aspects above, the third filling code block includes at least one code block identifier.

[0079] Optionally, in the fifth and sixth aspects above, the third filling code block further includes at least one check mark, and the at least one check mark is used to verify the correctness of the at least one code block mark.

[0080] Optionally, in the above-mentioned fifth aspect and sixth aspect, the number of the at least one code block identifier is equal to the number of the at least one check identifier; or, the sum of the number of the at least one code block identifier and the number of the at least one check identifier is an odd number.

[0081] In a seventh aspect, a data processing device is provided for use in FlexE. The data processing device includes at least one functional unit configured to execute the method provided in the third aspect or any optional embodiment of the third aspect. The at least one functional unit may be implemented based on software, hardware, or a combination of software and hardware, and may be combined or divided based on the specific implementation.

[0082] Optionally, the data processing device includes: a transceiver unit and a processing unit. The transceiver unit is configured to perform the transceiver operations in the method provided in the third aspect or any optional manner of the third aspect, and the processing unit is configured to perform operations other than the transceiver operations in the method provided in the third aspect or any optional manner of the third aspect.

[0083] Optionally, the transceiver unit is configured to obtain a first data stream, where the first data stream is one of the multiple data streams obtained by deinterleaving, the first data stream includes a periodically appearing padding sequence, the padding sequence includes n consecutive padding code blocks, where n is an integer greater than or equal to 4;

[0084] The processing unit is configured to search for a filling code block in the first data stream to find the filling sequence; and to determine that the filling sequence is found when multiple filling code blocks found consecutively in the first data stream meet a preset condition, wherein the preset condition includes: the number of the multiple filling code blocks is greater than a preset threshold and the number of the multiple filling code blocks is less than or equal to n.

[0085] In an eighth aspect, a data processing device is provided for use in FlexE. The data processing device includes at least one functional unit configured to execute the method provided in the fourth aspect or any optional embodiment of the fourth aspect. The at least one functional unit may be implemented based on software, hardware, or a combination of software and hardware, and may be combined or divided based on the specific implementation.

[0086] Optionally, the data processing device includes: a transceiver unit and a processing unit. The transceiver unit is configured to perform the transceiver operations in the method provided in the third aspect or any optional manner of the third aspect, and the processing unit is configured to perform operations other than the transceiver operations in the method provided in the fourth aspect or any optional manner of the fourth aspect.

[0087] Optionally, the transceiver unit is configured to obtain a first data stream, where the first data stream is obtained by periodically inserting a padding sequence into an initial data stream, where the initial data stream is obtained by interleaving multiple data streams sent by multiple FlexE instances, and the first data stream includes the periodically appearing padding sequence, where the padding sequence includes n consecutive padding code blocks, where n is an integer greater than or equal to 16;

[0088] The processing unit is configured to search for a filling code block in the first data stream to find the filling sequence; and to determine that the filling sequence is found when multiple filling code blocks found consecutively in the first data stream meet a preset condition, wherein the preset condition includes: the number of the multiple filling code blocks is greater than a preset threshold and the number of the multiple filling code blocks is less than or equal to n.

[0089] Optionally, in the above-mentioned seventh and eighth aspects, the n filling code blocks include x first filling code blocks and y second filling code blocks, the first filling code block is a globally unique control code block in the first data stream, the second filling code block is an error code block, the x is a positive integer, and the y is a positive integer.

[0090] Optionally, in the seventh and eighth aspects above, the x first filling code blocks and the y second filling code blocks satisfy any one of the following conditions:

[0091] x=1, y=n-1, the y second filling code blocks are located after the first filling code block, and the y second filling code blocks are continuous with the first filling code block; or,

[0092] The n is an even number, x=y=n / 2, the y second padding code blocks are located after the x first padding code blocks, and the y second padding code blocks are continuous with the x first padding code blocks; or,

[0093] n is an even number, x=y=n / 2, the padding sequence includes n / 2 code block groups, each code block group includes one first padding code block and one second padding code block, in each code block group, the second padding code block is located after the first padding code block and is continuous with the first padding code block, and the padding code blocks in the n / 2 code block groups are continuous; or

[0094] The x first filling code blocks include x1 first filling code blocks and x2 first filling code blocks, the y second filling code blocks are located between the x1 first filling code blocks and the x2 first filling code blocks, the x1 first filling code blocks, the y second filling code blocks and the x2 first filling code blocks are continuous, x1+x2=x, and x1 and x2 are both positive integers.

[0095] Optionally, in the seventh and eighth aspects above, the n padding code blocks further include z third padding code blocks, where z is a positive integer;

[0096] The y second filling code blocks are located after the x first filling code blocks and before the z third filling code blocks, and the x first filling code blocks, the y second filling code blocks, and the z third filling code blocks are continuous; or,

[0097] The z third filling code blocks are located after the x first filling code blocks and before the y second filling code blocks, and the x first filling code blocks, the z third filling code blocks and the y second filling code blocks are continuous.

[0098] Optionally, in the seventh and eighth aspects above, the third filling code block is a data code block.

[0099] Optionally, in the seventh and eighth aspects above, the third filling code block includes at least one code block identifier.

[0100] Optionally, in the seventh and eighth aspects above, the third filling code block further includes at least one check mark, and the at least one check mark is used to verify the correctness of the at least one code block mark.

[0101] Optionally, in the above-mentioned seventh aspect and eighth aspect, the number of the at least one code block identifier is equal to the number of the at least one check identifier; or, the sum of the number of the at least one code block identifier and the number of the at least one check identifier is an odd number.

[0102] Optionally, in the above-mentioned seventh and eighth aspects, the n filling code blocks include x first filling code blocks, the first filling code block is a globally unique control code block in the first data stream, and x is a positive integer. The processing module is used to: search for the first filling code block in the first data stream; and search for the filling sequence in the first data stream based on the first filling code block found in the first data stream.

[0103] Optionally, in the above-mentioned seventh aspect and eighth aspect, the processing module is used to: determine the n-1 code blocks after the first first filling code block found in the first data stream, the n-1 code blocks are continuous, and the n-1 code blocks are continuous with the first first filling code block; and search for the filling code block in the n-1 code blocks by detecting the n-1 code blocks.

[0104] Optionally, in the above-mentioned seventh aspect and eighth aspect, the processing module is used to: map the first first filling code block and the n-1 code blocks into a code block bitmap; and detect the n-1 code blocks based on the code block bitmap to search for a filling code block in the n-1 code blocks.

[0105] Optionally, in the above-mentioned seventh and eighth aspects, the n filling code blocks include a third filling code block, the third filling code block includes at least one code block identifier, and the processing module is used to map the third filling code block to the code block bitmap based on the code block identifier in the third filling code block.

[0106] Optionally, in the above-mentioned seventh and eighth aspects, the third filling code block also includes at least one check identifier, and the processing module is used to: verify the correctness of the at least one code block identifier based on the at least one check identifier; and map the third filling code block to the code block bitmap based on the correct code block identifier among the at least one code block identifier.

[0107] In the ninth aspect, a data processing device is provided, comprising a memory and a processor; the memory is used to store a computer program; the processor is used to execute the computer program stored in the memory so that the data processing device performs the method provided in the first aspect or any optional manner of the first aspect, or performs the method provided in the second aspect or any optional manner of the second aspect, or performs the method provided in the third aspect or any optional manner of the third aspect, or performs the method provided in the fourth aspect or any optional manner of the fourth aspect.

[0108] In a tenth aspect, a communication system is provided, comprising a transmitting end and a receiving end. The transmitting end comprises the data processing apparatus provided in the fifth aspect, any optional embodiment of the fifth aspect, the sixth aspect, any optional embodiment of the sixth aspect, or the ninth aspect. The receiving end comprises the data processing apparatus provided in the seventh aspect, any optional embodiment of the seventh aspect, the eighth aspect, any optional embodiment of the eighth aspect, or the ninth aspect.

[0109] In the eleventh aspect, a computer-readable storage medium is provided, which stores a computer program. When the computer program is executed, it implements the method provided by the first aspect or any optional method of the first aspect, or implements the method provided by the second aspect or any optional method of the second aspect, or implements the method provided by the third aspect or any optional method of the third aspect, or implements the method provided by the fourth aspect or any optional method of the fourth aspect.

[0110] In the twelfth aspect, a computer program product is provided, which includes a program or code. When the program or code is executed, it implements the method provided by the first aspect or any optional method of the first aspect, or implements the method provided by the second aspect or any optional method of the second aspect, or implements the method provided by the third aspect or any optional method of the third aspect, or implements the method provided by the fourth aspect or any optional method of the fourth aspect.

[0111] In the thirteenth aspect, a chip is provided, which includes a programmable logic circuit and / or program instructions. When the chip is running, it is used to implement the method provided by the first aspect or any optional method of the first aspect, or to implement the method provided by the second aspect or any optional method of the second aspect, or to implement the method provided by the third aspect or any optional method of the third aspect, or to implement the method provided by the fourth aspect or any optional method of the fourth aspect.

[0112] Optionally, the chip is a FlexE shim.

[0113] The technical effects of the above-mentioned second to thirteenth aspects can refer to the technical effects of the first aspect and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0114] FIG1 is an architecture diagram of a FlexE protocol provided in an embodiment of the present application;

[0115] FIG2 is a schematic diagram of a switch provided in an embodiment of the present application;

[0116] FIG3 is a schematic diagram of the bandwidth of a FlexE port provided in an embodiment of the present application;

[0117] FIG4 is a schematic diagram of a data stream including a padding code block provided by an embodiment of the present application;

[0118] FIG5 is a schematic diagram of a P1 code block provided in an embodiment of the present application;

[0119] FIG6 is a schematic diagram of a P2 code block provided in an embodiment of the present application;

[0120] FIG7 is a schematic diagram of an application scenario provided by an embodiment of the present application;

[0121] FIG8 is a schematic diagram of another application scenario provided by an embodiment of the present application;

[0122] FIG9 is a schematic diagram of another application scenario provided by an embodiment of the present application;

[0123] FIG10 is a flow chart of a data processing method provided in an embodiment of the present application;

[0124] FIG11 is a schematic diagram of a schematic diagram of a third filling code block provided in an embodiment of the present application;

[0125] FIG12 is a schematic diagram of another schematic diagram of a third filling code block provided in an embodiment of the present application;

[0126] FIG13 is a schematic diagram of a schematic diagram of yet another third filling code block provided in an embodiment of the present application;

[0127] FIG14 is a schematic diagram of a schematic diagram of yet another third filling code block provided in an embodiment of the present application;

[0128] FIG15 is a schematic diagram of a first data stream provided in an embodiment of the present application;

[0129] FIG16 is a schematic diagram of another first data stream provided in an embodiment of the present application;

[0130] FIG17 is a schematic diagram of another first data stream provided in an embodiment of the present application;

[0131] FIG18 is a schematic diagram of another first data stream provided in an embodiment of the present application;

[0132] FIG19 is a schematic diagram of another first data stream provided in an embodiment of the present application;

[0133] FIG20 is a schematic diagram of another first data stream provided in an embodiment of the present application;

[0134] FIG21 is a schematic diagram of another first data stream provided in an embodiment of the present application;

[0135] FIG22 is a flowchart of another data processing method provided in an embodiment of the present application;

[0136] FIG23 is a schematic diagram of a code block bitmap provided in an embodiment of the present application;

[0137] FIG24 is a flowchart of another data processing method provided in an embodiment of the present application;

[0138] FIG25 is a flowchart of another data processing method provided in an embodiment of the present application;

[0139] FIG26 is a schematic diagram of a data processing device provided in an embodiment of the present application;

[0140] FIG27 is a schematic diagram of another data processing device provided in an embodiment of the present application;

[0141] FIG28 is a schematic diagram of another data processing device provided in an embodiment of the present application;

[0142] Figure 29 is a schematic diagram of another data processing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0143] The embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

[0144] In the communications field, Ethernet technology inserts alignment markers (AMs) to implement functions such as multi-channel alignment and code block delimitation at the physical layer (PHY). Specifically, the PHY interface on the transmitting end periodically inserts AM code blocks into the data stream and sends a data stream containing AM code blocks. After receiving the data stream containing AM code blocks, the PHY interface on the receiving end finds and deletes the AM code blocks in the data stream and then sends the remaining code blocks to the upper layer for processing. Specifically, the PHY includes a physical coding sublayer (PCS). The PCS on the transmitting end inserts AM code blocks, while the PCS on the receiving end finds and deletes AM code blocks. Typically, PHY interfaces of different rates insert different proportions of AM code blocks into the data stream. For example, according to the current standard, the AM insertion ratio of a 100GE PHY interface is 1 / 16384, the AM insertion ratio of a 50GE PHY interface, a 200GE PHY interface, a 400GE PHY interface, and an 800GE PHY interface is 1 / 20480, and the AM insertion ratio of a 1.6TE PHY interface is 1 / 81920.

[0145] The Flexible Ethernet (FlexE) protocol is a standard protocol defined by the Optical Internetworking Forum (OIF). The FlexE protocol introduces the concept of a FlexE port, also known as a physical interface group, physical link group, PHY group, or FlexE group. A FlexE port includes several 50GE PHY interfaces, 100GE PHY interfaces, 200GE PHY interfaces, and / or 400GE PHY interfaces, and may also include higher-speed PHY interfaces such as 800GE PHY interfaces and 1.6TE PHY interfaces in the future. A FlexE port supports one or more FlexE instances. Each FlexE instance introduces a fixed periodic frame structure and divides time slots based on time-division multiplexing (TDM). One or more time slots support an Ethernet data stream or carry the data stream of a Flexible Ethernet client (FlexE client). That is, an Ethernet data stream corresponds to one or more timeslots, or a FlexE client data stream is carried by one or more timeslots, with different FlexE client data streams carried in different timeslots. For example, for a 100 gigabit per second (Gbps) FlexE instance, its periodic frame structure includes 20 timeslots, each with a bandwidth of 5 Gbps. Each timeslot has 1023 × 8 = 8184 66-bit transmission windows, and the bandwidth of each 66-bit transmission window is 5 Gbps / 8184 = 0.61 megabits per second (Mbps).

[0146] The FlexE protocol achieves rate decoupling between the medium access control (MAC) layer and the physical layer (PHY) by introducing the FlexE adaptation layer (FlexE shim). That is, the rate of the MAC layer does not need to correspond one-to-one with the rate of the PHY. For example, Figure 1 is an architectural diagram of the FlexE protocol. As shown in Figure 1, the FlexE protocol defines the FlexE client, FlexE shim, and FlexE group (also known as the FlexE group and the FlexE port). The FlexE client is a MAC layer service. The MAC layer service is a data stream encoded with 64B / 66B. The data stream includes multiple code blocks with a length of 66 bits. The rate of the MAC layer service is 10Gbps, 40Gbps, or m*25Gbps, where m is a positive integer. The FlexE group includes several PHY interfaces to provide greater bandwidth. The FlexE shim is used to multiplex and demultiplex data streams based on TDM technology. For example, the FlexE shim at the transmitter is used to multiplex data streams based on TDM technology, and the FlexE shim at the receiver is used to demultiplex data streams based on TDM technology. For example, Figure 1 shows p FlexE clients, and shows that the FlexE group includes k PHY interfaces, where p and k are both positive integers. Each FlexE client represents a 64B / 66B-encoded data stream at the MAC layer, and the rates of the p FlexE clients can be equal or unequal. As shown in Figure 1, the FlexE shim at the transmitter is used to map the code blocks of the p FlexE clients to the FlexE group for transmission in a TDM manner, and the FlexE shim at the transmitter is used to insert 64B / 66B-encoded overhead (OH) code blocks at fixed intervals into the code block stream (i.e., the data stream) mixed with the code blocks of the p FlexE clients. The OH code blocks are used by the FlexE shim at the receiver for code block delimiting and demultiplexing. The FlexE shim at the receiving end is used to obtain the code block stream in which the code blocks of the p FlexE clients are mixed and the OH code blocks are inserted, first lock and parse the OH code blocks, and then demultiplex the code blocks of each FlexE client based on the OH code blocks.

[0147] Currently, FlexE ports can consist of multiple 50GE PHY interfaces, multiple 100GE PHY interfaces, multiple 200GE PHY interfaces, or multiple 400GE PHY interfaces. In the future, FlexE ports may also consist of 800GE PHY interfaces, 1.6TE PHY interfaces, or even higher-speed PHY interfaces. There is a need for interconnection between FlexE ports consisting of PHY interfaces of different speeds. To enable interoperability between FlexE ports consisting of PHY interfaces of different speeds, the available bandwidth of different FlexE ports consisting of PHY interfaces of different speeds must be equal. For example, as shown in Figure 2, a FlexE-enabled switch has an uplink FlexE port with two 100GE PHY interfaces and a downlink FlexE port with one 200GE PHY interface. The uplink FlexE port and the downlink FlexE port are interconnected via FlexE cross-connection. To enable interoperability between the uplink FlexE port and the downlink FlexE port, the available bandwidth of the uplink FlexE port must be equal to the available bandwidth of the downlink FlexE port. In fact, although the PHY interfaces of different rates (such as 50GE, 100GE, 200GE, 400GE, 800GE, and 1.6TE) have an integer multiple relationship in nominal bandwidth, there are differences in the available bandwidth they provide to the FlexE port. Specifically, the available bandwidth provided by the PHY interface to the FlexE port is the bandwidth after deducting the AM overhead from the bandwidth of the PHY interface, and the available bandwidth of the FlexE port is the sum of the available bandwidths provided by the PHY interfaces in the FlexE port to the FlexE port. Since the AM insertion ratios of PHY interfaces of different rates are different, the available bandwidths provided to the FlexE port by PHY interfaces of different rates are different. In order to interconnect FlexE ports composed of PHY interfaces of different rates, that is, in order to make the available bandwidths of different FlexE ports composed of PHY interfaces of different rates equal, it is necessary to insert a filler code block into the data stream sent by the FlexE port with a larger available bandwidth to occupy space, so as to reduce the available bandwidth of the FlexE port. For example, it is necessary to insert a filler code block into the data stream sent by the downstream FlexE port of the switch shown in Figure 2 to occupy space.

[0148] For example, 64 50GE PHY interfaces, 32 100GE PHY interfaces, 16 200GE PHY interfaces, 8 400GE PHY interfaces, 4 800GE PHY interfaces, or 2 1.6TE PHY interfaces can form a FlexE port with a total bandwidth of 3.2 terabit per second (Tbps). However, since the AM insertion ratio of the 100GE PHY interface is 1 / 16384, the AM insertion ratio of the 50GE PHY interface, 200GE PHY interface, 400GE PHY interface, and 800GE PHY interface is 1 / 20480, and the AM insertion ratio of the 1.6TE PHY interface is 1 / 81920. Therefore, the available bandwidth of a FlexE port consisting of 32 100GE PHY interfaces, the available bandwidth of a FlexE port consisting of 64 50GE PHY interfaces, 16 200GE PHY interfaces, 8 400GE PHY interfaces, or 4 800GE PHY interfaces, and the available bandwidth of a FlexE port consisting of 2 1.6TE PHY interfaces are different. To ensure that the available bandwidth of a FlexE port consisting of 32 100GE PHY interfaces, the available bandwidth of a FlexE port consisting of 64 50GE PHY interfaces, 16 200GE PHY interfaces, 8 400GE PHY interfaces, or 4 800GE PHY interfaces, and the available bandwidth of a FlexE port consisting of two 1.6TE PHY interfaces are equal, it is necessary to insert padding blocks into the data streams sent by the FlexE port consisting of 64 50GE PHY interfaces, 16 200GE PHY interfaces, 8 400GE PHY interfaces, or 4 800GE PHY interfaces, and to insert padding blocks into the data streams sent by the FlexE port consisting of two 1.6TE PHY interfaces. Furthermore, the proportion of padding blocks inserted into the data stream sent by a FlexE port consisting of two 1.6TE PHY interfaces is higher than the proportion of padding blocks inserted into the data stream sent by a FlexE port consisting of 64 50GE PHY interfaces, 16 200GE PHY interfaces, 8 400GE PHY interfaces, or 4 800GE PHY interfaces.For example, as shown in Figure 3, 32 100GE PHY interfaces, 4 800GE PHY interfaces or 2 1.6TE PHY interfaces can all constitute a FlexE port with a total bandwidth of 3.2Tbps. However, since the AM insertion ratio of the 100GE PHY interface is higher than that of the 800GE PHY interface, and the AM insertion ratio of the 800GE PHY interface is higher than that of the 1.6TE PHY interface, padding blocks are respectively inserted into the data stream sent by the FlexE port composed of the four 800GE PHY interfaces and the data stream sent by the FlexE port composed of the two 1.6TE PHY interfaces to take up space. Moreover, the ratio of padding blocks inserted in the data stream sent by the FlexE port composed of the two 1.6TE PHY interfaces is higher than the ratio of padding blocks inserted in the data stream sent by the FlexE port composed of the four 800GE PHY interfaces. In this way, the available bandwidth of the FlexE port consisting of the two 1.6TE PHY interfaces and the available bandwidth of the FlexE port consisting of the four 800GE PHY interfaces are reduced, and the available bandwidth of the FlexE port consisting of the 32 100GE PHY interfaces, the available bandwidth of the FlexE port consisting of the four 800GE PHY interfaces, and the available bandwidth of the FlexE port consisting of the two 1.6TE PHY interfaces are made equal, thereby achieving intercommunication between the FlexE port consisting of the 32 100GE PHY interfaces, the FlexE port consisting of the four 800GE PHY interfaces, and the FlexE port consisting of the two 1.6TE PHY interfaces.

[0149] The current FlexE standard, specifically the FlexE 2.2 implementation agreement, defines a method for inserting and detecting padding blocks. The FlexE shim at the transmitting end inserts two padding blocks every 163,830 blocks in the data stream and sends a data stream containing the padding blocks. After the FlexE shim at the receiving end receives the data stream containing the padding blocks, it performs padding block detection on the data stream to find the two padding blocks. If both padding blocks are detected correctly, the FlexE shim at the receiving end determines that the detection is successful, meaning that the FlexE shim at the receiving end has found the two padding blocks. Furthermore, the FlexE shim at the receiving end deletes the padding blocks from the data stream and sends the remaining blocks to upper layers for processing. For example, Figure 4 shows a data stream after inserting padding blocks using the padding block insertion method defined in the current FlexE standard. In this data stream, two padding blocks are inserted every 163,830 code blocks (for ease of distinction, these 163,830 code blocks are referred to as data code blocks in Figure 4). These two padding blocks are respectively a P1 code block and a P2 code block. The length of the P1 code block and the length of the P2 code block are both 66 bits. The P1 code block is a globally unique control code block in the data stream, and the P2 code block is an error code block. After the receiving FlexE shim receives the data stream containing the P1 code block and the P2 code block, the receiving FlexE shim first detects and locks the globally unique P1 code block, and then detects whether the code block immediately following the locked P1 code block is a P2 code block. If the receiving end's FlexE shim detects that the block immediately following the P1 block is a P2 block, the receiving end's FlexE shim considers both P1 and P2 blocks detected successfully. The receiving end's FlexE shim deletes the P1 and P2 blocks from the data stream and sends the remaining blocks to upper layers for processing. If the receiving end's FlexE shim detects that the block immediately following the P1 block is not a P2 block, the receiving end's FlexE shim considers P2 block detection a failure. The receiving end's FlexE shim re-detects and locks onto the P1 block from the current detection position, and then checks whether the block immediately following the locked P1 block is a P2 block until detection succeeds.

[0150] As an example, please refer to Figure 5, which shows a schematic diagram of a P1 code block. The P1 code block is 66 bits long. Bits 1 and 2 of the P1 code block indicate the type of the P1 code block. The value "10" of these bits 1 and 2 indicates that the P1 code block is a control code block. The value "0x4B" of bits 3 to 10 of the P1 code block indicates that bits 11 to 34 of the P1 code block are data information. Bits 35 to 38 of the P1 code block are a delimiter field, used to separate the data information bits 11 to 34 from the control information bits 39 to 66. The value "0x5" of bits 35 to 38 is an internationally accepted value. When the value of bits 35 to 38 is "0x5," bits 11 to 14 reuse the value "0x0" in the FlexE standard, and bits 15 to 34 reuse the value "0xF_FFFF" in the FlexE standard.

[0151] As an example, please refer to Figure 6, which shows a schematic diagram of a P2 code block. The length of the P2 code block is 66 bits. Bits 1 and 2 of the P2 code block indicate the type of the P2 code block. The value of "10" for these bits indicates that the P2 code block is a control code block. Bits 3 to 10 of the P1 code block indicate the specific type of the control code block. The value of "0x1E" for these bits indicates that the P2 code block is an error code block. The values ​​of bits 11 to 17, bits 18 to 24, bits 25 to 31, bits 32 to 38, bits 39 to 45, bits 46 to 52, bits 53 to 59, and bits 60 to 66 of the P2 code block are all "0x1E."

[0152] It should be noted that the bits in the P1 code block and the bits in the P2 code block are described above in order from high to low. The bits in the P1 code block and the bits in the P2 code block can also be described in order from low to high. Regardless of the order in which the bits in the P1 code block and the bits in the P2 code block are described, the meaning of the various fields in the P1 code block and the meaning of the various fields in the P2 code block do not change. In addition, this article only introduces the P1 code block and the P2 code block for example. For a detailed description of the P1 code block and the P2 code block, please refer to the relevant standard documents.

[0153] The current FlexE standard defines a method for inserting padding blocks primarily for 50GE, 200GE, and 400GE PHY interfaces. However, as Ethernet standards evolve, PHY interface rates continue to increase toward 800GE and 1.6TE. The current FlexE standard defines a method for inserting padding blocks that is difficult to apply to higher-rate PHY interfaces, such as 800GE and 1.6TE. For example, according to the current FlexE standard, the number of padding blocks required within a pad cycle (e.g., 163,830 blocks) is 2. However, as Ethernet standards evolve, a FlexE port may include an 800GE or 1.6TE PHY interface, and the number of padding blocks required within a pad cycle may evolve to 4, 8, 16, or even more. Therefore, a new insertion method is needed to adapt to the evolution of Ethernet standards.

[0154] In addition, in the detection method of the padding code blocks defined in the current FlexE standard, the detection is successful only when all the padding code blocks inserted by the FlexE shim at the receiving end in a pad cycle are correctly detected (the detection is considered successful only when the FlexE shim at the receiving end finds consecutive P1 code blocks and P2 code blocks). This results in poor fault tolerance of the detection method. Specifically, at the same bit error rate, that is, at the same bit error probability (BER), as the number of padding code blocks inserted in a pad cycle increases, the probability of joint detection failure of multiple padding code blocks increases, resulting in poor fault tolerance of the detection method. For example, according to the detection method of the padding code blocks defined in the current FlexE standard, at BER=1×10 -13 In the case of , if the FlexE shim at the transmitting end inserts two padding blocks within one pad period, the FlexE shim at the receiving end needs to jointly detect the padding block with the two blocks. The probability of failure of the joint detection of the two blocks is about 1.3×10 -11 (The total length of the two code blocks is 66×2=132 bits. When one bit in the 132 bits is wrong, the detection is considered to have failed. Therefore, the probability of detection failure is 132×1×10 -13 , which is approximately equal to 1.3×10 -11 If the transmitting FlexE shim inserts 8 padding blocks within a pad period, the receiving FlexE shim needs to detect the padding blocks using the 8 blocks. The probability of failure in the joint detection of the 8 blocks is approximately 5.3×10 -11If the FlexE shim at the transmitting end inserts 16 pad blocks in one pad cycle, the FlexE shim at the receiving end needs to detect the pad blocks by combining all 16 blocks. The probability of failure in combined detection of all 16 blocks is about 1×10 -10 If the FlexE shim at the transmitting end inserts 32 padding blocks in one pad cycle, the FlexE shim at the receiving end needs to detect the padding blocks by combining the 32 blocks. The probability of failure in the combined detection of the 32 blocks is about 2.1×10 -10 If the FlexE shim at the transmitting end inserts 64 padding blocks in one pad cycle, the FlexE shim at the receiving end needs to detect the padding blocks by combining all 64 blocks. The probability of failure in the combined detection of 64 blocks is 4.2×10 -10 If the FlexE shim at the transmitting end inserts 128 padding blocks in one pad cycle, the FlexE shim at the receiving end needs to detect the padding blocks using all 128 blocks. The probability of failure to detect the 128 blocks is about 8.5×10 -10 If the FlexE shim at the transmitting end inserts 256 padding blocks in one pad cycle, the FlexE shim at the receiving end needs to detect the padding blocks by combining all 256 blocks. The probability of failure in the combined detection of all 256 blocks is about 1.7×10 -9 As can be seen, as the number of padding blocks inserted in a pad cycle increases, the probability of joint detection failure of multiple blocks increases exponentially, which can easily affect the normal operation of FlexE.

[0155] The present application provides a data processing method and apparatus, which involves the insertion and detection (or searching and identifying) of padding blocks. In the data processing method provided in the present application, the FlexE shim at the transmitting end (specifically, the pad processing module in the FlexE shim at the transmitting end) periodically inserts a padding sequence into the initial data stream to obtain a first data stream, wherein the padding sequence includes n consecutive padding blocks. After the FlexE shim at the receiving end (specifically, the pad processing module in the FlexE shim at the receiving end) obtains the first data stream, it searches for padding blocks in the first data stream to find the padding sequence. The FlexE shim at the receiving end determines that the padding sequence has been found if the number of padding blocks found consecutively in the first data stream is greater than a preset threshold and less than or equal to n, that is, determines that the padding sequence detection is successful (or the pad detection is successful). n is an integer greater than or equal to 4, or n is an integer greater than or equal to 16. For example, when the initial data stream is the data stream of a FlexE instance in the FlexE shim at the transmitting end, n is an integer greater than or equal to 4. In the case where the initial data stream is a data stream obtained by interleaving multiple data streams of multiple FlexE instances in the FlexE shim of the transmitting end, n is an integer greater than or equal to 16. It can be seen that the embodiment of the present application provides a FlexE-oriented method for inserting more padding code blocks in a data stream, which can be applied to higher-speed PHY interfaces such as 800GE PHY interfaces and 1.6TE PHY interfaces, and can adapt to the evolution of Ethernet standards. In addition, since the number of padding code blocks found continuously by the FlexE shim at the receiving end in the first data stream is greater than a preset threshold and less than or equal to n, it is determined that the padding sequence is found, that is, the pad detection is successful, and the number of multiple padding code blocks found continuously does not need to be equal to n, that is, it is not necessary for all padding code blocks in the padding sequence to be detected correctly. Therefore, the process of the FlexE shim at the receiving end to find the padding sequence is relatively relaxed, the fault tolerance capability of finding the padding sequence is better, and the probability of successfully finding the padding sequence can be maintained without degradation.

[0156] The technical solution of this application is introduced below, and the application scenario of this application is first introduced.

[0157] Please refer to Figure 7, which shows a schematic diagram of an application scenario of an embodiment of the present application. This application scenario provides a communication system. The communication system includes a transmitting end and a receiving end. The transmitting end and the receiving end are communicatively connected. For example, the transmitting end and the receiving end are connected via an optical fiber.

[0158] Specifically, the transmitting end and the receiving end both include a PHY interface, and the PHY interface of the transmitting end is connected to the PHY interface of the receiving end via an optical fiber. For example, the transmitting end includes a PHY interface with at least one rate of 50GE, 100GE, 200GE, 400GE, 800GE, and 1.6TE, and the receiving end includes a PHY interface with at least one rate of 50GE, 100GE, 200GE, 400GE, 800GE, and 1.6TE. As shown in Figure 7, the transmitting end and the receiving end both include a physical layer (also called a PHY layer or a PHY chip), and the PHY interface is located in the physical layer. The PHY interface includes a physical coding sublayer (PCS), a physical medium attachment (PMA), a physical medium dependent (PMD), etc. The transmitting end and the receiving end transmit data streams via the PHY interface. When sending a data stream to the receiving end, the transmitting end's PHY interface periodically inserts AM blocks into the data stream and transmits the data stream containing the AM blocks. After receiving the data stream containing the AM blocks, the receiving end's PHY interface locates and removes the AM blocks from the data stream, then passes the remaining blocks to upper layers for processing. This allows the use of AM blocks to implement functions such as multi-channel alignment and block delimiting at the physical layer. The AM insertion ratio varies for PHY interfaces of different rates. For example, according to current standards, the AM insertion ratio for a 100GE PHY interface is 1 / 16384, for 50GE, 200GE, 400GE, and 800GE PHY interfaces is 1 / 20480, and for a 1.6TE PHY interface is 1 / 81920.

[0159] In an embodiment of the present application, both the transmitter and the receiver support FlexE functionality. Both the transmitter and the receiver include a FlexE shim and at least one FlexE port. A FlexE port includes at least one PHY interface, for example, a FlexE port is composed of multiple PHY interfaces. The available bandwidth of a FlexE port is the sum of the available bandwidths provided by the PHY interfaces in the FlexE port to the FlexE port, and the available bandwidth provided by the PHY interfaces to the FlexE port is the bandwidth of the PHY interfaces after deducting the AM overhead. Since the AM insertion ratios of PHY interfaces of different rates are different, the available bandwidths provided by PHY interfaces of different rates to the FlexE port are different. As shown in Figure 7, both the transmitter and the receiver also include a MAC layer, and the FlexE shim is located between the MAC layer and the physical layer. The FlexE shim is used to implement communication between the MAC layer and the physical layer, and to achieve rate decoupling between the MAC layer and the physical layer. At the transmitter, the FlexE shim processes the data stream after receiving it from the MAC layer, and then sends the processed data stream to the physical layer. At the receiving end, the FlexE shim processes the data stream after receiving it from the physical layer, and then sends the processed data stream to the MAC layer. The FlexE shim at the transmitting end processes the data stream sent by the MAC layer, including time slot mapping the data stream, inserting padding blocks into the data stream, and interleaving multiple data streams. The FlexE shim at the receiving end processes the data stream sent by the physical layer, including deinterleaving the data stream, searching for and deleting padding blocks in the data stream, and time slot demapping the data stream. As shown in FIG7 , in an embodiment of the present application, both the FlexE shim at the transmitting end and the FlexE shim at the receiving end include a pad processing module. The pad processing module in the FlexE shim at the transmitting end inserts padding blocks into the data stream, and the pad processing module in the FlexE shim at the receiving end searches for and deletes padding blocks in the data stream. The pad processing module in the FlexE shim at the transmitting end is also called a pad insertion module, and the pad processing module in the FlexE shim at the receiving end is also called a pad deletion module. The data flow between the MAC layer and the FlexE shim is also called the FlexE client data flow.

[0160] In an embodiment of the present application, the FlexE shim at the transmitting end may first insert a padding code block into the data stream, and then interleave the multiple data streams containing the padding code block. Correspondingly, the FlexE shim at the receiving end may first deinterleave the data stream to obtain a multiple data stream, and then search for and delete the padding code blocks in the multiple data streams. Alternatively, the FlexE shim at the transmitting end may first interleave the multiple data streams, and then insert a padding code block into the interleaved data stream. Correspondingly, the FlexE shim at the receiving end may first search for and delete the padding code block in the data stream, and then deinterleave the data stream after deleting the padding code block. Based on this, the application scenarios of the embodiments of the present application are introduced in two cases below.

[0161] In the first scenario, the FlexE shim at the transmitting end first inserts padding blocks into the data stream and then interleaves the multiple data streams containing the padding blocks. Correspondingly, the FlexE shim at the receiving end first deinterleaves the data streams to obtain multiple data streams and then searches for and deletes the padding blocks in the multiple data streams. Please refer to Figure 8, which shows a schematic diagram of another application scenario provided by an embodiment of the present application. The communication system provided in this application scenario includes a transmitting end and a receiving end, both of which include a MAC layer, a FlexE shim, and a physical layer.

[0162] As shown in Figure 8, the FlexE shim of the transmitting end includes an overhead (OH) processing module, a time slot allocation scheduler (calendar), p idle (idle) addition and deletion modules, multiple FlexE instances, multiple pad processing modules and multiple interleaving modules, where p is a positive integer. The OH processing module, the p idle addition and deletion modules and the multiple FlexE instances are respectively connected to the time slot allocation scheduler, and the OH processing module is respectively connected to the multiple FlexE instances, the multiple FlexE instances are connected one-to-one with the multiple pad processing modules, each interleaving module is connected to at least two pad processing modules, and different interleaving modules are connected to different pad processing modules. In addition, the interleaving module of the transmitting end is connected to the PHY interface of the transmitting end. For example, the multiple interleaving modules of the transmitting end are connected one-to-one with the multiple PHY interfaces of the transmitting end.

[0163] As shown in Figure 8, the FlexE shim at the receiving end includes an OH processing module, a time slot allocation scheduler, p idle addition and deletion modules, multiple FlexE instances, multiple pad processing modules, and multiple deinterleaving modules. The OH processing module, the p idle addition and deletion modules, and the multiple FlexE instances are respectively connected to the time slot allocation scheduler, and the OH processing module is respectively connected to the multiple FlexE instances, the multiple FlexE instances are connected one-to-one with the multiple pad processing modules, each deinterleaving module in the multiple deinterleaving modules is connected to at least two pad processing modules, and different deinterleaving modules are connected to different pad processing modules. In addition, the deinterleaving module at the receiving end is connected to the PHY interface of the receiving end. For example, the multiple deinterleaving modules at the receiving end are connected one-to-one with the multiple PHY interfaces of the receiving end.

[0164] As shown in FIG8 , the multiple PHY interfaces of the transmitting end are connected to the multiple PHY interfaces of the receiving end in a one-to-one correspondence.

[0165] As shown in Figure 8, FlexE clients 1 through p represent p data flows exchanged between the MAC layer and the FlexE shim. These p data flows are all 64B / 66B encoded, and each of these p data flows consists of multiple 66-bit code blocks. The interleaving module in the transmitting FlexE shim is also called a 66b interleaving module, and the deinterleaving module in the receiving FlexE shim is also called a 66b deinterleaving module.

[0166] Referring to Figure 8 , the processing flow at the transmitting end includes: the MAC layer obtains p data streams (i.e., FlexE clients 1 to p) and sends the p data streams to the FlexE shim; the FlexE shim processes the p data streams and sends the processed data streams to the physical layer; the physical layer performs some physical layer processing on the data stream sent by the FlexE shim (such as inserting AM code blocks into the data stream), and sends the processed data stream to the receiving end through the PHY interface.

[0167] With reference to FIG8 , the processing procedure of the FlexE shim at the sending end is as follows.

[0168] Each of the p idle addition and deletion modules is configured to receive a data stream (FlexE client) sent by the MAC layer, perform idle addition and deletion on the data stream (adding idle code blocks or deleting some code blocks from the data stream), and send the idle addition and deletion data stream to the timeslot allocation scheduler. This idle addition and deletion of the data stream enables the data stream rate to adapt to the timeslot allocation scheduler rate.

[0169] The timeslot allocation scheduler is configured to receive p data streams sent by the p idle add / drop modules, perform timeslot mapping on the p data streams in a TDM manner to obtain multiple data streams mixed with code blocks of the p data streams (each data stream in the multiple data streams includes code blocks in multiple data streams in the p data streams), insert OH code blocks into each of the multiple data streams under the control of the OH processing module, and send the multiple data streams after the OH code blocks are inserted to the multiple FlexE instances in a one-to-one correspondence.

[0170] Each of the multiple FlexE instances is configured to receive a data stream sent by the timeslot allocation scheduler, perform sub-timeslot mapping on the data stream in a TDM manner, insert an OH code block into the data stream under the control of the OH processing module, and send the data stream with the OH code block inserted to the corresponding pad processing module. The FlexE instance is also referred to as a sub-timeslot allocation scheduler (sub calendar), and the FlexE instance can be a 100GE FlexE instance, which is not limited in this embodiment of the present application.

[0171] Each of the multiple pad processing modules is configured to receive a data stream sent by a corresponding FlexE instance, periodically insert a padding sequence into the data stream, and send the data stream with the padding sequence inserted to a corresponding interleaving module. The padding sequence includes n consecutive padding code blocks, where n is an integer greater than or equal to 4 for the application scenario shown in FIG8 .

[0172] Each of the multiple interleaving modules is used to: receive multiple data streams containing padding sequences sent by the corresponding multiple pad processing modules, interleave the multiple data streams to obtain an interleaved data stream, and send the data stream to the physical layer.

[0173] Referring to Figure 8 , the processing flow at the receiving end includes: the physical layer receives the data stream through the PHY interface, the physical layer performs some physical layer processing on the data stream (such as deleting the AM code blocks in the data stream, etc.), and sends the processed data stream to the FlexE shim; the FlexE shim processes the data stream to obtain p data streams (i.e., FlexE clients 1~p) and sends the p data streams to the MAC layer.

[0174] 8 , the processing process of the receiving-end FlexE shim is as follows.

[0175] Each of the multiple deinterleaving modules is used to: receive a data stream sent by the physical layer, deinterleave the data stream to obtain multiple data streams, and send the multiple data streams to the corresponding multiple pad processing modules in a one-to-one correspondence.

[0176] Each of the multiple pad processing modules is configured to receive a data stream sent by a corresponding deinterleaving module, search for and remove a padding sequence from the data stream, and send the data stream after the padding sequence is removed to the corresponding FlexE instance. The padding sequence includes n consecutive padding code blocks, where n is an integer greater than or equal to 4 for the application scenario shown in FIG8 .

[0177] Each of the multiple FlexE instances is configured to receive a data stream sent by a corresponding pad processing module, search for and delete the OH code blocks in the data stream under the control of the OH processing module, perform sub-timeslot demapping on the data stream in a TDM manner, and send the demapped data stream to the timeslot allocation scheduler. The FlexE instance is also referred to as a sub-timeslot allocation scheduler (sub calendar), and the FlexE instance can be a 100GE FlexE instance, which is not limited in this embodiment of the present application.

[0178] The timeslot allocation scheduler is used to: receive the multiple data streams sent by the multiple FlexE instances, search and delete the OH code blocks in the multiple data streams under the control of the OH processing module, perform timeslot demapping on the multiple data streams in a TDM manner to obtain p data streams, and send the p data streams to the p idle add / delete modules one by one.

[0179] Each of the p idle addition and deletion modules is configured to receive a data stream sent by the time slot allocation scheduler, perform idle addition and deletion on the data stream (add idle code blocks in the data stream or delete some code blocks) to obtain a FlexE client, and send the FlexE client to the MAC layer.

[0180] In the second scenario, the FlexE shim on the transmitting end first interleaves multiple data streams and then inserts padding blocks into the interleaved data stream. Correspondingly, the FlexE shim on the receiving end first searches for and removes padding blocks from the data stream and then deinterleaves the data stream after the padding blocks are removed. Please refer to Figure 9, which shows a schematic diagram of another application scenario provided by an embodiment of the present application. The communication system provided in this application scenario includes a transmitting end and a receiving end, both of which include a MAC layer, a FlexE shim, and a physical layer.

[0181] As shown in Figure 9, the FlexE shim of the transmitting end includes an OH processing module, a time slot allocation scheduler, p idle addition and deletion modules, multiple FlexE instances, multiple interleaving modules, and multiple pad processing modules, where p is a positive integer. The OH processing module, the p idle addition and deletion modules, and the multiple FlexE instances are respectively connected to the time slot allocation scheduler, and the OH processing module is respectively connected to the multiple FlexE instances, each interleaving module is connected to at least two FlexE instances, different interleaving modules are connected to different FlexE instances, and the multiple interleaving modules are connected to the multiple pad processing modules in a one-to-one correspondence. In addition, the pad processing module of the transmitting end is connected to the PHY interface of the transmitting end. For example, the multiple pad processing modules of the transmitting end are connected to the multiple PHY interfaces of the transmitting end in a one-to-one correspondence.

[0182] As shown in Figure 9, the FlexE shim at the receiving end includes an OH processing module, a time slot allocation scheduler, p idle addition and deletion modules, multiple FlexE instances, multiple deinterleaving modules, and multiple pad processing modules. The OH processing module, the p idle addition and deletion modules, and the multiple FlexE instances are respectively connected to the time slot allocation scheduler, and the OH processing module is respectively connected to the multiple FlexE instances. Each deinterleaving module in the multiple deinterleaving modules is connected to at least two FlexE instances, and different deinterleaving modules are connected to different FlexE instances. The multiple pad processing modules are connected one-to-one with the multiple deinterleaving modules. In addition, the pad processing module in the FlexE shim at the receiving end is connected to the PHY interface of the receiving end. For example, the multiple pad processing modules at the receiving end are connected one-to-one with the multiple PHY interfaces of the receiving end.

[0183] As shown in FIG9 , the multiple PHY interfaces of the transmitting end are connected to the multiple PHY interfaces of the receiving end in a one-to-one correspondence.

[0184] As shown in FIG9 , FlexE clients 1 to p are p data flows exchanged between the MAC layer and the FlexE shim. The p data flows are all 64B / 66B encoded data flows, and each of the p data flows includes multiple 66-bit code blocks.

[0185] Referring to Figure 9, the processing flow of the transmitting end includes: the MAC layer obtains p data streams (i.e., FlexE clients 1~p) and sends the p data streams to the FlexE shim; the FlexE shim processes the p data streams and sends the processed data streams to the physical layer; the physical layer performs some physical layer processing on the data stream sent by the FlexE shim (such as inserting AM code blocks into the data stream), and sends the processed data stream to the receiving end through the PHY interface.

[0186] 9 , the processing process of the FlexE shim at the sending end is as follows.

[0187] Each of the p idle addition and deletion modules is configured to receive a data stream (FlexE client) sent by the MAC layer, perform idle addition and deletion on the data stream (adding idle code blocks or deleting some code blocks from the data stream), and send the idle addition and deletion data stream to the timeslot allocation scheduler. This idle addition and deletion of the data stream enables the data stream rate to adapt to the timeslot allocation scheduler rate.

[0188] The timeslot allocation scheduler is configured to receive p data streams sent by the p idle add / drop modules, perform timeslot mapping on the p data streams in a TDM manner to obtain a multi-channel data stream mixed with code blocks of the p data streams, insert OH code blocks into each of the multi-channel data streams under the control of the OH processing module, and send the multi-channel data streams after the OH code blocks are inserted to the multiple FlexE instances in a one-to-one correspondence.

[0189] Each of the multiple FlexE instances is configured to receive a data stream sent by the timeslot allocation scheduler, perform sub-timeslot mapping on the data stream in a TDM manner, insert an OH code block into the data stream under the control of the OH processing module, and send the data stream with the OH code block inserted to the corresponding interleaving module. The FlexE instance is also referred to as a sub-timeslot allocation scheduler and can be a 100GE FlexE instance, which is not limited in this embodiment of the present application.

[0190] Each of the multiple interleaving modules is configured to receive multiple data streams sent by corresponding multiple FlexE instances, interleave the multiple data streams to obtain an interleaved data stream, and send the interleaved data stream to a corresponding pad processing module.

[0191] Each of the multiple pad processing modules is configured to receive a data stream sent by a corresponding interleaving module, periodically insert a padding sequence into the data stream, and transmit the data stream with the padding sequence inserted to the physical layer. The padding sequence includes n consecutive padding code blocks, where n is an integer greater than or equal to 16 for the application scenario shown in FIG9 .

[0192] Referring to Figure 9, the processing flow at the receiving end includes: the physical layer receives the data stream through the PHY interface, the physical layer performs some physical layer processing on the data stream (such as deleting the AM code block in the data stream, etc.), and sends the processed data stream to the FlexE shim; the FlexE shim processes the data stream to obtain p-way data streams (i.e., FlexE clients 1~p), and sends the p-way data streams to the MAC layer.

[0193] 9 , the processing process of the receiving-end FlexE shim is as follows.

[0194] Each of the multiple pad processing modules is configured to receive a data stream transmitted by the physical layer, search for and remove a padding sequence from the data stream, and transmit the data stream after the padding sequence is removed to a corresponding deinterleaving module. The padding sequence includes n consecutive padding code blocks, where n is an integer greater than or equal to 16 for the application scenario shown in FIG9 .

[0195] Each of the multiple deinterleaving modules is configured to receive a data stream sent by a corresponding pad processing module, deinterleave the data stream to obtain multiple data streams, and send the multiple data streams to the corresponding multiple FlexE instances in a one-to-one correspondence.

[0196] Each of the multiple FlexE instances is configured to receive a data stream sent by a corresponding deinterleaving module, search for and delete the OH code blocks in the data stream under the control of the OH processing module, perform sub-timeslot demapping on the data stream in a TDM manner, and send the demapped data stream to the timeslot allocation scheduler. The FlexE instance is also referred to as a sub-timeslot allocation scheduler and can be a 100GE FlexE instance, which is not limited in this embodiment of the present application.

[0197] The timeslot allocation scheduler is used to receive multiple data streams sent by multiple FlexE instances, search for and delete OH code blocks in the multiple data streams under the control of the OH processing module, perform timeslot demapping on the multiple data streams in a TDM manner to obtain p data streams, and send the p data streams to p idle add / delete modules in a one-to-one correspondence.

[0198] Each of the p idle addition and deletion modules is configured to receive a data stream sent by the time slot allocation scheduler, perform idle addition and deletion on the data stream (add idle code blocks in the data stream or delete some code blocks) to obtain a FlexE client, and send the FlexE client to the MAC layer.

[0199] Comparing Figures 8 and 9, it can be seen that in the application scenario shown in Figure 8, at the transmitting end, the processing flow of the pad processing module (specifically, the pad insertion module) precedes the processing flow of the interleaving module, and at the receiving end, the processing flow of the deinterleaving module precedes the processing flow of the pad processing module (specifically, the pad deletion module). In the application scenario shown in Figure 9, at the transmitting end, the processing flow of the interleaving module precedes the processing flow of the pad processing module (specifically, the pad insertion module), and at the receiving end, the processing flow of the pad processing module (specifically, the pad deletion module) precedes the processing flow of the deinterleaving module. For the application scenario shown in Figure 8, at the transmitting end, different pad processing modules connected to the same interleaving module can insert different padding sequences into the data stream, such as the structure and period of the padding sequences. For example, different pad insertion modules can insert padding sequences into the data stream using different insertion methods provided in the various embodiments of the present application (such as the insertion methods provided in the method embodiments below, such as the insertion methods provided in Figures 15 to 21). As a result, the padding sequences included in the multiple data streams interleaved by the interleaving module can be different. For the application scenario shown in FIG9 , at the transmitting end, different pad processing modules connected to different interleaving modules may insert different padding sequences into the data stream, and the padding sequence period, etc. For example, different pad processing modules may use different insertion methods among the multiple insertion methods provided in the embodiments of the present application to insert the padding sequence into the data stream. It can be seen that the embodiments of the present application support the insertion of differentiated padding sequences, thereby allowing some pad processing modules to reduce the complexity of the padding sequence insertion function, while other pad processing modules introduce slightly higher complexity in the padding sequence insertion function to improve performance. The embodiments of the present application do not limit this.

[0200] It should be noted that the transmitting end and the receiving end in the embodiment of the present application both support the FlexE function. For example, the transmitting end and the receiving end are both forwarding devices, user terminal devices or server devices that support the FlexE function. The forwarding device may be a router or a switch. For example, the transmitting end and the receiving end are both forwarding devices, user terminal devices or server devices in a slicing packet network (SPN). In some embodiments, the transmitting end is also referred to as a transmitting end device, and the receiving end is also referred to as a receiving end device. In addition, the transmitting end and the receiving end are relative. In some embodiments, the transmitting end in the embodiment of the present application can also be used as a receiving end, and the receiving end in the embodiment of the present application can also be used as a transmitting end. The above description of the transmitting end and the receiving end is merely exemplary. The transmitting end and the receiving end may also have other structures and / or functions not shown and / or described above. The embodiment of the present application does not limit this and will not be elaborated here. In addition, the application scenarios shown above are only examples of application scenarios of the embodiment of the present application and are not used to limit the application scenarios of the embodiment of the present application. The application scenarios of the embodiment of the present application can be flexibly adjusted as the business develops.

[0201] The above is an introduction to the application scenario of this application. The following introduces the method embodiment of this application.

[0202] Please refer to Figure 10, which shows a flow chart of a data processing method provided in an embodiment of the present application. The data processing method is applied to FlexE. The data processing method is executed by the FlexE shim in the transmitting end, specifically by the pad processing module in the FlexE shim. Optionally, the FlexE shim in the transmitting end includes multiple pad processing modules, and the data processing method is executed by any pad processing module of the multiple pad processing modules. For example, the data processing method shown in Figure 10 is executed by any pad processing module in the FlexE shim in the transmitting end shown in Figure 8. Referring to Figure 10, the data processing method includes the following steps S1001 to S1002.

[0203] S1001. Receive an initial data stream sent by a FlexE instance.

[0204] In the FlexE shim at the transmitting end, the FlexE instance can send a data stream to the pad processing module, and the pad processing module receives the data stream sent by the FlexE instance. For ease of distinction, in this embodiment, the data stream sent by the FlexE instance to the pad processing module is referred to as the initial data stream.

[0205] S1002. Periodically insert a filling sequence into the initial data stream to obtain a first data stream, the first data stream including the periodically appearing filling sequence, the filling sequence including n consecutive filling code blocks, where n is an integer greater than or equal to 4.

[0206] In the FlexE shim at the transmitting end, the pad processing module periodically inserts a padding sequence into the initial data stream. Specifically, the pad processing module inserts a padding sequence into the initial data stream every certain number of code blocks. The first data stream includes the periodic padding sequence. The periodicity of the padding sequence in the first data stream can be set based on actual conditions and is not limited in this embodiment of the present application.

[0207] In an embodiment of the present application, the padding sequence that periodically appears in the first data stream includes n consecutive padding code blocks. The n padding code blocks are all code blocks using 64B / 66B encoding, and the length of the n padding code blocks is 66 bits. In an optional embodiment, the n padding code blocks include a first padding code block and a second padding code block. The first padding code block is a globally unique control code block in the first data stream. The second padding code block is an error code block. For example, the first padding code block is the P1 code block shown in Figure 5, and the second padding code block is the P2 code block shown in Figure 6.

[0208] In an optional embodiment, the n filling code blocks further include at least one third filling code block, and the third filling code block is a data code block.

[0209] In an optional embodiment, the third filling code block includes at least one code block identifier, and the code block identifier included in any third filling code block is used to uniquely identify the third filling code block, and the code block identifier included in any third filling code block is used for the pad processing module in the FlexE shim of the receiving end to identify (or detect, find) the third filling code block. The code block identifier may include a combination of one or more of the American Standard Code for Information Interchange (ASCII) of numbers, English letters, and Chinese characters. For example, the code block identifier can be a number such as 1, 2, 3, 4, or a letter such as A, B, C, D, or an ASCII of Chinese characters such as Jia, Yi, Bing, Ding. The code block identifier can be a sequence number. Optionally, for any third filling code block, when the third filling code block includes multiple code block identifiers, the number of the multiple code block identifiers can be an odd number or an even number, and the multiple code block identifiers can be the same or different, and the embodiment of the present application does not limit this. In the embodiment of the present application, the third padding code block is configured to include multiple code block identifiers, which can prevent the pad processing module in the FlexE shim at the receiving end from being unable to recognize the third padding code block due to errors in one or more code block identifiers in the third padding code block during transmission of the third padding code block. For example, if the third padding code block only includes one code block identifier and an error occurs in the code block identifier during transmission of the third padding code block, the pad processing module in the FlexE shim at the receiving end will not be able to recognize the code block identifier and thus will not be able to recognize the third padding code block. However, if the third padding code block includes multiple code block identifiers, as long as there is a code block identifier in the third padding code block that has not experienced an error during transmission of the third padding code block, the pad processing module in the FlexE shim at the receiving end can recognize the code block identifier that has not experienced an error, and identify the third padding code block based on the code block identifier that has not experienced an error.

[0210] In an optional embodiment, the third filling code block also includes at least one check identifier. That is, the third filling code block includes at least one code block identifier and at least one check identifier, and the at least one check identifier is used to verify the correctness of the at least one code block identifier. The check identifier can be a cyclic redundancy check code (CRC), or it can be a bit-flipped code of the code block identifier (that is, the check identifier can be obtained by bit-flipping the code block identifier). For example, the code block identifier is a sequence number, and the bit-flipped code of the code block identifier is a bit-reversed sequence number. Optionally, for any third filling code block, when the third filling code block includes multiple check identifiers, the number of the multiple check identifiers can be an odd number or an even number, and the multiple check identifiers can be the same or different, and this embodiment of the present application does not limit this. In the embodiment of the present application, the third padding code block includes multiple check identifiers. This can prevent the padding processing module in the FlexE shim at the receiving end from being unable to verify the correctness of the code block identifiers in the third padding code block due to errors in one or more check identifiers in the third padding code block during transmission of the third padding code block. For example, if the third padding code block includes only one check identifier and an error occurs in the check identifier during transmission of the third padding code block, the pad processing module in the FlexE shim at the receiving end will not be able to recognize the check identifier and thus will not be able to verify the correctness of the code block identifiers in the third padding code block. However, if the third padding code block includes multiple check identifiers, as long as there is a check identifier in the third padding code block that has not experienced an error during transmission of the third padding code block, the pad processing module in the FlexE shim at the receiving end can recognize the check identifier that has not experienced an error and verify the correctness of the code block identifiers in the third padding code block based on the check identifier that has not experienced an error.

[0211] In an optional embodiment, for any third padding code block, when the third padding code block includes at least one code block identifier and at least one check identifier: the number of the at least one code block identifier is equal to the number of the at least one check identifier, for example, the number of the at least one code block identifier and the number of the at least one check identifier are both 1, 2, 3, or 4. Alternatively, the sum of the number of the at least one code block identifier and the number of the at least one check identifier is an odd number, for example, the sum of the number of the at least one code block identifier and the number of the at least one check identifier is 3, 5, 7, etc. In this embodiment of the present application, setting the number of code block identifiers in the third padding code block to be equal to the number of check identifiers, or setting the sum of the number of code block identifiers and the number of check identifiers to an odd number, can facilitate the pad processing module in the FlexE shim at the receiving end to identify the third padding code block. For example, for any third padding code block, if the number of code block identifiers in the third padding code block is equal to the number of check identifiers, the code block identifiers in the third padding code block correspond one-to-one to the check identifiers, and each check identifier is used to verify the correctness of the corresponding code block identifier. If the pad processing module in the FlexE shim at the receiving end successfully verifies at least one code block identifier in the third padding code block, the pad processing module in the FlexE shim at the receiving end deems that the at least one code block identifier is correct, and the pad processing module deems that the third padding code block has been successfully identified, that is, the pad processing module has found the third padding code block. It can be seen that if the number of code block identifiers in the third padding code block is equal to the number of check identifiers, the pad processing module in the FlexE shim at the receiving end can easily identify the third padding code block. For another example, for any third padding code block, if the sum of the number of code block identifiers and the number of check identifiers in the third padding code block is an odd number, during the process of identifying (or detecting or searching for) the third padding code block by the pad processing module in the FlexE shim at the receiving end, if the pad processing module determines that the sum of the number of correct code block identifiers and the number of correct check identifiers in the third padding code block exceeds half of the sum of the number of code block identifiers and the number of check identifiers in the third padding code block, the pad processing module deems that the third padding code block has been successfully identified, that is, the pad processing module has found the third padding code block. It can be seen that if the sum of the number of code block identifiers and the number of check identifiers in the third padding code block is an odd number, the pad processing module in the FlexE shim at the receiving end can easily identify the third padding code block.Optionally, when the sum of the number of code block identifiers and the number of check identifiers in the third filling code block is an odd number, half of the sum of the number of code block identifiers and the number of check identifiers in the third filling code block is not an integer. In this case, half of the sum of the number of code block identifiers and the number of check identifiers in the third filling code block can be rounded up for identification and judgment. This embodiment of the present application does not limit this.

[0212] In an optional embodiment, in the third filling code block, the length of the code block identifier is equal to the length of the check identifier. For example, the length of the code block identifier and the length of the check identifier are both 8 bits.

[0213] As an example, please refer to Figure 11, which shows a schematic diagram of a third padding code block provided in an embodiment of the present application. The length of the third padding code block is 66 bits. The first and second bits in the third padding code block indicate the type of the third padding code block, and the value "10" of the first and second bits indicates that the third padding code block is a data code block. The third to tenth bits in the third padding code block indicate the code block identifier of the third padding code block. The 59th to 66th bits in the third padding code block are the check identifier, which is a CRC code. The portion between the code block identifier and the check identifier (i.e., bits 11 to 58) is a reserved field. The CRC code (i.e., the check identifier) ​​is obtained by performing a CRC calculation based on the code block identifier. Since the check identifier is a CRC code, it is convenient for the pad processing module in the FlexE shim at the receiving end to use an encoder and circuit to verify the correctness of the code block identifier in the third padding code block based on the CRC code.

[0214] As another example, please refer to Figure 12, which shows a schematic diagram of another third padding code block provided in an embodiment of the present application. The length of the third padding code block is 66 bits. The first and second bits in the third padding code block indicate the type of the third padding code block, and the value "10" of the first and second bits indicates that the third padding code block is a data code block. The third to tenth bits, the eleventh to eighteenth bits, and the nineteenth to twenty-sixth bits in the third padding code block all represent the code block identifier of the third padding code block. The third padding code block includes three code block identifiers, each of which is eight bits long, and the three code block identifiers can be the same or different. The 27th to 66th bits in the third padding code block are reserved fields. In this example, setting the third padding code block to include an odd number of code block identifiers can avoid the situation where, during the transmission of the third padding code block, one or more code block identifiers in the third padding code block have errors, resulting in the pad processing module in the FlexE shim at the receiving end being unable to recognize the third padding code block. For example, when the pad processing module in the FlexE shim at the receiving end identifies (or detects, searches for) the third filling code block, if the pad processing module determines that the number of correct code block identifiers in the third filling code block exceeds half of the total number of code block identifiers in the third filling code block, the pad processing module deems that the third filling code block has been successfully identified, that is, the pad processing module has found the third filling code block. It can be seen that even if some code block identifiers in the third filling code block have errors, the pad processing module can still find the third filling code block. Optionally, in the case where the number of code block identifiers in the third filling code block is an odd number, half of the number of code block identifiers in the third filling code block is not an integer. The pad processing module in the FlexE shim at the receiving end can round up half of the number of code block identifiers in the third filling code block for identification and judgment, which is not limited in this embodiment of the present application.

[0215] As another example, please refer to Figure 13, which shows a schematic diagram of another third filling code block provided by an embodiment of the present application. The length of the third filling code block is 66 bits. The first and second bits in the third filling code block represent the type of the third filling code block, and the value "10" of the first and second bits indicates that the third filling code block is a data code block. The third to tenth bits, the 11th to 18th bits, the 19th to 26th bits and the 27th to 34th bits in the third filling code block all represent the code block identifier of the third filling code block. The 35th to 42nd bits, the 43rd to 50th bits, the 51st to 58th bits and the 59th to 66th bits in the third filling code block all represent the check mark, which is a bit flip code of the code block identifier. The third filling code block shown in Figure 13 includes 4 code block identifiers and 4 check marks. The length of each code block identifier is 8 bits, and the 4 code block identifiers can be the same or different. The length of each check identifier is 8 bits, and the four check identifiers can be the same or different. The number of code block identifiers in the third filling code block shown in Figure 13 is equal to the number of check identifiers. Optionally, the four code block identifiers correspond one-to-one to the four code block identifiers, each check identifier is a bit flip code of the corresponding code block identifier, and each check identifier is used to verify the correctness of the corresponding code block identifier. When the pad processing module in the FlexE shim at the receiving end successfully verifies at least one of the four code block identifiers, the pad processing module in the FlexE shim at the receiving end considers that the at least one code block identifier is correct, and the pad processing module considers that the third filling code block is successfully identified, that is, the pad processing module finds the third filling code block. It can be seen that the number of code block identifiers in the third filling code block is equal to the number of check identifiers, which facilitates the pad processing module in the FlexE shim at the receiving end to identify the third filling code block.

[0216] As another example, please refer to Figure 14, which shows a schematic diagram of another third filler code block provided in an embodiment of the present application. The length of the third filler code block is 66 bits. The first and second bits in the third filler code block indicate the type of the third filler code block. The value "10" of the first and second bits indicates that the third filler code block is a data code block. The third to tenth bits, the eleventh to eighteenth bits, and the nineteenth to twenty-sixth bits in the third filler code block each represent the code block identifier of the third filler code block. The twenty-seventh to thirty-fourth bits and the thirty-fifth to forty-second bits in the third filler code block each represent a check mark, which is a bit-flip code for the code block identifier. Bits 43rd to 66th bits in the third filler code block are reserved fields. The third filler code block shown in Figure 14 includes three code block identifiers and two check marks. Each code block identifier is eight bits long, and the three code block identifiers can be the same or different. Each check mark is eight bits long, and the two check marks can be the same or different. The sum of the number of code block identifiers and the number of check identifiers in the third padding code block shown in FIG14 is an odd number, which can facilitate the pad processing module in the FlexE shim at the receiving end to easily identify (or detect, find) the third padding code block. Specifically, during the process of identifying the third padding code block, if the pad processing module in the FlexE shim at the receiving end determines that the sum of the number of correct code block identifiers and the number of correct check identifiers in the third padding code block exceeds half of the sum of the number of code block identifiers and the number of check identifiers in the third padding code block, the pad processing module deems that the third padding code block has been successfully identified, that is, the pad processing module has found the third padding code block. It can be seen that even if some code block identifiers and / or check identifiers in the third padding code block have errors, the pad processing module can still find the third padding code block. Optionally, when the sum of the number of code block identifiers and the number of check identifiers in the third filling code block is an odd number, half of the sum of the number of code block identifiers and the number of check identifiers in the third filling code block is not an integer. The pad processing module in the FlexE shim at the receiving end can round up half of the sum of the number of code block identifiers and the number of check identifiers in the third filling code block for identification and judgment. This embodiment of the present application is not limited to this.

[0217] It should be noted that the bits in the third filling code block are described above in order from high to low, and the bits in the third filling code block can also be described in order from low to high. Regardless of the order in which the bits in the third filling code block are described, the meaning of the various fields in the third filling code block is not affected. In addition, Figures 11 to 14 only illustrate the third filling code block of an embodiment of the present application. The third filling code block can also be other code blocks. The positions of the various fields in the third filling code block can be flexibly adjusted, and the embodiments of the present application do not limit this. In some embodiments, the third filling code block is also called a P3 code block, and the embodiments of the present application do not limit the name of the third filling code block.

[0218] In conjunction with the above description, the following describes the padding sequence that periodically appears in the first data stream in an embodiment of the present application. As previously described, the padding sequence includes n consecutive padding code blocks. In one possible scenario of the embodiment of the present application, the n padding code blocks include x first padding code blocks and y second padding code blocks, where x + y = n, and x and y are both positive integers. That is, the n padding code blocks include only the first and second padding code blocks, and do not include the third padding code block. In other words, the padding sequence consists of the first and second padding code blocks. In another possible scenario of the embodiment of the present application, the n padding code blocks include x first padding code blocks, y second padding code blocks, and z third padding code blocks, where x + y + z = n, and x, y, and z are all positive integers. That is, the n padding code blocks include the first, second, and third padding code blocks. In other words, the padding sequence consists of the first, second, and third padding code blocks.

[0219] In an optional embodiment, the first data stream satisfies any one of the following six implementation methods.

[0220] First implementation: The first data stream includes a periodically occurring padding sequence, the padding sequence comprising n consecutive padding code blocks, the n padding code blocks comprising x first padding code blocks and y second padding code blocks, where x=1 and y=n-1, the y second padding code blocks being located after the x first padding code blocks, the y second padding code blocks being consecutive, and the y second padding code blocks being consecutive to the x first padding code blocks. That is, the n padding code blocks comprising one first padding code block and n-1 second padding code blocks, the n-1 second padding code block being located after the one first padding code block, the n-1 second padding code blocks being consecutive, and the n-1 second padding code blocks being consecutive to the one first padding code block.

[0221] For example, the first padding code block is a P1 code block, the second padding code block is a P2 code block, and the first data stream is shown in Figure 15. Referring to Figure 15, every w code blocks in the first data stream (the w code blocks are referred to as data code blocks in Figure 15) have a padding sequence, and each padding sequence includes one P1 code block and n-1 P2 code blocks, the n-1 P2 code blocks are located after the one P1 code block, the n-1 P2 code blocks are continuous, and the n-1 P2 code blocks are continuous with the one P1 code block.

[0222] Second implementation: The first data stream includes a periodically occurring padding sequence, the padding sequence including n consecutive padding code blocks, the n padding code blocks including x first padding code blocks and y second padding code blocks, where n is an even number, x=y=n / 2, the y second padding code blocks are located after the x first padding code blocks, the x first padding code blocks are continuous, the y second padding code blocks are continuous, and the y second padding code blocks are continuous with the x first padding code blocks. That is, the n padding code blocks include n / 2 first padding code blocks and n / 2 second padding code blocks, the n / 2 second padding code blocks are located after the n / 2 first padding code blocks, the n / 2 first padding code blocks are continuous, the n / 2 second padding code blocks are continuous, and the n / 2 second padding code blocks are continuous with the n / 2 first padding code blocks.

[0223] For example, the first padding code block is a P1 code block, the second padding code block is a P2 code block, and the first data stream is shown in Figure 16. Referring to Figure 16, every w code blocks in the first data stream (the w code blocks are referred to as data code blocks in Figure 16) have a padding sequence, and each padding sequence includes n / 2 P1 code blocks and n / 2 P2 code blocks, the n / 2 P2 code blocks are located after the n / 2 P1 code blocks, the n / 2 P1 code blocks are continuous, the n / 2 P2 code blocks are continuous, and the n / 2 P2 code blocks are continuous with the n / 2 P1 code blocks.

[0224] A third implementation method: The first data stream includes a periodically occurring padding sequence, which includes n consecutive padding code blocks, wherein the n padding code blocks include x first padding code blocks and y second padding code blocks, where n is an even number, x = y = n / 2. The padding sequence includes n / 2 code block groups, each of which includes a first padding code block and a second padding code block. In each code block group, the second padding code block follows the first padding code block and is continuous with the first padding code block, and the padding code blocks in the n / 2 code block groups are continuous. That is, the n padding code blocks include n / 2 first padding code blocks and n / 2 second padding code blocks, with the first padding code blocks and the second padding code blocks arranged alternately. In other words, the n padding code blocks are arranged in the order of first padding code block, second padding code block, first padding code block, second padding code block, and so on.

[0225] For example, the first padding code block is a P1 code block, the second padding code block is a P2 code block, and the first data stream is shown in Figure 17. Referring to Figure 17, every w code blocks in the first data stream (the w code blocks are referred to as data code blocks in Figure 17) have a padding sequence, each padding sequence includes n / 2 P1 code blocks and n / 2 P2 code blocks, and each padding sequence includes n / 2 code block groups, each code block group includes one P1 code block and one P2 code block, the P2 code block is located after the P1 code block and is continuous with the P1 code block, and the padding code blocks in the n / 2 code block groups are continuous. In other words, the n padding code blocks in the padding sequence are arranged in the order of P1 code block, P2 code block, P1 code block, P2 code block, etc.

[0226] The fourth implementation method: the first data stream includes a periodically appearing filling sequence, the filling sequence includes n consecutive filling code blocks, the n filling code blocks include x first filling code blocks and y second filling code blocks, the x first filling code blocks include x1 first filling code blocks and x2 first filling code blocks, the y second filling code blocks are located between the x1 first filling code blocks and the x2 first filling code blocks, the x1 first filling code block, the y second filling code blocks and the x2 first filling code blocks are consecutive, x1+x2=x, x+y=n.

[0227] For example, the first padding code block is a P1 code block, the second padding code block is a P2 code block, and the first data stream is shown in Figure 18. Referring to Figure 18, every w code blocks in the first data stream (the w code blocks are referred to as data code blocks in Figure 18) have a padding sequence, and each padding sequence includes x P1 code blocks, y P2 code blocks, and x2 P1 code blocks, where the y P2 code blocks are located between the x1 P1 code blocks and the x2 P1 code blocks, and the x1 P1 code blocks, the y P2 code blocks, and the x2 P1 code blocks are consecutive.

[0228] A fifth implementation: The first data stream includes a periodically occurring padding sequence, the padding sequence comprising n consecutive padding blocks, the n padding blocks comprising x first padding blocks, y second padding blocks, and z third padding blocks, where x + y + z = n, the y second padding blocks being located after the x first padding blocks and before the z third padding blocks, and the x first padding blocks, the y second padding blocks, and the z third padding blocks being consecutive. That is, the n padding blocks are arranged in the order of x first padding blocks, y second padding blocks, and z third padding blocks.

[0229] For example, the first padding code block is a P1 code block, the second padding code block is a P2 code block, and the third padding code block is a P3 code block. The first data stream is shown in Figure 19. Referring to Figure 19, every w code blocks in the first data stream (the w code blocks are referred to as data code blocks in Figure 19) have a padding sequence. Each padding sequence includes x P1 code blocks, y P2 code blocks, and z P3 code blocks. The y P2 code blocks are located after the x P1 code blocks and before the z P3 code blocks. The x P1 code blocks, the y P2 code blocks, and the z P3 code blocks are consecutive. That is, the n padding code blocks in the padding sequence are arranged in the order of x P1 code blocks, y P2 code blocks, and z P3 code blocks.

[0230] A sixth implementation: The first data stream includes a periodically occurring padding sequence, the padding sequence comprising n consecutive padding code blocks, the n padding code blocks including x first padding code blocks, y second padding code blocks, and z third padding code blocks, where x + y + z = n, the z third padding code blocks being located after the x first padding code blocks and before the y second padding code blocks, and the x first padding code blocks, the z third padding code blocks, and the y second padding code blocks being consecutive. That is, the n padding code blocks are arranged in the order of x first padding code blocks, z third padding code blocks, and y second padding code blocks.

[0231] For example, the first filling code block is a P1 code block, the second filling code block is a P2 code block, and the third filling code block is a P3 code block. The first data stream is shown in Figure 20. Referring to Figure 20, every w code blocks in the first data stream (the w code blocks are referred to as data code blocks in Figure 20) have a filling sequence, and each filling sequence includes x P1 code blocks, y P2 code blocks, and z P3 code blocks. The z P3 code blocks are located after the x P1 code blocks and before the y P2 code blocks. The x P1 code blocks, the z P3 code blocks, and the y P2 code blocks are continuous. That is, the n filling code blocks in the filling sequence are arranged in the order of x P1 code blocks, z P3 code blocks, and y P2 code blocks. As an example, x=1, y=1, z=n-2, and the first data stream is shown in Figure 21.

[0232] It should be noted that in the first to fourth implementations described above, since the filling sequence only includes the first filling code block (i.e., the P1 code block) and the second filling code block (i.e., the P2 code block), the first to fourth implementations inherit the pad encapsulation format of the current FlexE standard to the greatest extent, and are simple to implement. In the fifth to sixth implementations described above, the filling sequence includes the first filling code block (i.e., the P1 code block), the second filling code block (i.e., the P2 code block), and the third filling code block (i.e., the P3 code block). On the one hand, the third filling code block can include a code block identifier, thereby simplifying the process of the pad processing module in the FlexE shim at the receiving end identifying (or detecting, searching for) the third filling code block. On the other hand, the fifth to sixth implementations can inherit the pad encapsulation format of the current FlexE standard and achieve smooth evolution of the FlexE standard. Moreover, in the sixth implementation method mentioned above, the z third filling code blocks are arranged between the x first filling code blocks and the y second filling code blocks. Since the first filling code blocks and the second filling code blocks are both control code blocks, and the third filling code block is a data code block, this arrangement method makes the third filling code block not adjacent to the actual data code blocks in the first data stream, thereby avoiding confusion between the third filling code block and the actual data code blocks in the first data stream, and avoiding contamination of the actual data code blocks in the first data stream by the third filling code block.

[0233] It should be noted that Figures 15 to 21 are merely examples of the first data stream in the embodiments of the present application and are not intended to limit the first data stream. The structure of the filling sequence in the first data stream may also be other structures. The structure of the filling sequence and the number of filling code blocks in the filling sequence (i.e., the value of n) can be flexibly set and adjusted. The period in which the filling sequence appears in the first data stream can be flexibly set and adjusted. That is, the value of w involved in the description of Figures 15 to 21 can be flexibly adjusted. In addition, for different implementations in Figures 15 to 21, the value of w can be the same or different, and the value of n can be the same or different, and the embodiments of the present application do not limit this. For example, the value of n is 2 to the power of i, where i is an integer greater than or equal to 2. For example, the value of n is 4, 8, 16, 32, 64, and the like.

[0234] In the embodiment shown in Figure 10, after the pad processing module in the FlexE shim at the transmitting end obtains the first data stream, the pad processing module sends the first data stream to the interleaving module in the FlexE shim. After the interleaving module receives multiple data streams, including the first data stream, sent by multiple pad processing modules, the interleaving module interleaves the multiple data streams to obtain an interleaved data stream. The interleaving module sends the interleaved data stream to the physical layer of the transmitting end. After the physical layer of the transmitting end performs physical layer-related processing on the data stream (for example, inserting AM code blocks into the data stream), it sends the processed data stream to the receiving end via the PHY interface of the transmitting end.

[0235] In summary, in the data processing method provided by the embodiment of the present application, the pad processing module in the FlexE shim at the transmitting end periodically inserts a padding sequence into the initial data stream sent by the FlexE instance to obtain a first data stream. The padding sequence includes n consecutive padding code blocks, where n is an integer greater than or equal to 4. It can be seen that the embodiment of the present application provides a FlexE-oriented method for inserting a large number of padding code blocks into a data stream. The method is applicable to higher-speed PHY interfaces such as 800GE PHY interfaces and 1.6TE PHY interfaces, and can adapt to the evolution of Ethernet standards.

[0236] Please refer to Figure 22, which shows a flowchart of another data processing method provided in an embodiment of the present application. The data processing method is applied to FlexE. The data processing method is executed by the FlexE shim in the receiving end, specifically by the pad processing module in the FlexE shim. Optionally, the FlexE shim in the receiving end includes multiple pad processing modules, and the data processing method is executed by any pad processing module of the multiple pad processing modules. For example, the data processing method shown in Figure 22 is executed by any pad processing module in the FlexE shim in the receiving end shown in Figure 8. Referring to Figure 22, the data processing method includes the following steps S2201 to S2203.

[0237] S2201. Obtain a first data stream, where the first data stream is one of the multiple data streams obtained by deinterleaving, and the first data stream includes a periodically appearing filling sequence, where the filling sequence includes n consecutive filling code blocks, where n is an integer greater than or equal to 4.

[0238] Optionally, in the FlexE shim at the receiving end, the pad processing module receives a first data stream sent by the deinterleaving module, where the first data stream is one of the multiple data streams obtained by the deinterleaving module deinterleaving one data stream. For example, the first data stream is any one of the multiple data streams. It should be noted that the first data stream in the embodiment shown in Figure 22 is the same data stream as the first data stream in the embodiment shown in Figure 10, but the first data stream in the embodiment shown in Figure 22 may have bit errors compared to the first data stream in the embodiment shown in Figure 10. For the description of the first data stream, please refer to the embodiment shown in Figure 10 and will not be repeated here.

[0239] Optionally, in the FlexE shim at the receiving end, a deinterleaving module is connected to multiple pad processing modules. The deinterleaving module receives a data stream sent by the physical layer of the receiving end, deinterleaves the data stream to obtain multiple data streams, and sends the multiple data streams to the multiple pad processing modules in a one-to-one correspondence. The data stream received by one of the multiple pad processing modules from the deinterleaving module is the first data stream. The data stream sent by the physical layer of the receiving end to the deinterleaving module is the data stream after the physical layer performs physical layer-related processing (e.g., deleting AM code blocks) on the data stream received by the PHY interface of the receiving end.

[0240] S2202. Search for a filling code block in the first data stream to find a filling sequence.

[0241] In an embodiment of the present application, a first data stream includes a periodically occurring padding sequence, which includes n consecutive padding code blocks. Optionally, the n padding code blocks include x globally unique first padding code blocks. At the receiving end, a pad processing module first searches for the first padding code block in the first data stream. After the pad processing module finds the first padding code block in the first data stream, the pad processing module locks the found first padding code block. The pad processing module searches for the padding sequence in the first data stream based on the first padding code block found in the first data stream.

[0242] In one embodiment, the pad processing module determines n-1 code blocks following the first first padding code block found in the first data stream, where the n-1 code blocks are continuous and the n-1 code blocks are continuous with the first first padding code block. The pad processing module searches for the padding code block in the n-1 code blocks by detecting the n-1 code blocks. The pad processing module detects the n-1 code blocks, that is, the pad processing module detects whether each code block in the n-1 code blocks is a padding code block. In other words, the pad processing module detects the correctness of each code block in the n-1 code blocks (that is, detects whether each code block is a correct padding code block). For code blocks in the n-1 code blocks that include a code block identifier, the pad processing module detects whether the code block is a padding code block based on the code block identifier in the code block. Moreover, if the code block also includes a check mark, the pad processing module verifies the correctness of the code block identifier in the code block based on the check mark in the code block.

[0243] In an optional embodiment, after the pad processing module finds the first first filling code block in the first data stream, the pad processing module obtains the first first filling code block and the n-1 code blocks after the first first filling code block, and the pad processing module maps the first first filling code block and the n-1 code blocks to (or sets) a code block bitmap, and the pad processing module detects the n-1 code blocks based on the code block bitmap to find the filling code block in the n-1 code blocks. The code block bitmap can be located in the pad processing module. For example, Figure 23 shows a schematic diagram of the code block bitmap in the pad processing module, and the code block bitmap includes n code block positions. The pad processing module maps the first first filling code block and each code block in the n-1 code blocks to a code block position, and the pad processing module maps different code blocks to different code block positions. In one example, the n code block positions are arranged in sequence, the pad processing module maps the first first filling code block to the first code block position among the n code block positions (for example, the code block position marked as 1 in Figure 23), and the pad processing module maps the n-1 code blocks one-to-one to the remaining n-1 code block positions (that is, the 2nd to nth code block positions) according to the arrangement order of the n-1 code blocks.

[0244] In an optional embodiment, the n padding code blocks include x first padding code blocks, y second padding code blocks, and z third padding code blocks, and the third padding code blocks include at least one code block identifier. After the pad processing module obtains the first first padding code block and the n-1 code blocks after the first first padding code block found in the first data stream, for each code block in the n-1 code blocks, the pad processing module detects whether the code block includes a code block identifier. If the code block includes a code block identifier, the pad processing module maps the code block to the code block bitmap based on the code block identifier. After the pad processing module maps all code blocks in the n-1 code blocks that include code block identifiers to the code block bitmap, the pad processing module randomly maps the first first padding code block and the code blocks in the n-1 code blocks that do not include code block identifiers to the remaining positions in the code block bitmap.

[0245] In an optional embodiment, the third filling code block also includes at least one check mark. That is, the third filling code block includes at least one code block identifier and at least one check mark. After the pad processing module obtains the first first filling code block found in the first data stream and the n-1 code blocks after the first first filling code block, for the code block in the n-1 code blocks that includes the code block identifier, the pad processing module further detects whether the code block includes the check mark. If the code block includes the check mark, the pad processing module verifies the correctness of the code block identifier in the code block based on the check mark. After the verification is successful, the pad processing module maps the code block to the code block bitmap based on the code block identifier in the code block. Optionally, if the pad processing module successfully verifies the code block identifier in the code block, the pad processing module determines that the code block is the third filling code block, that is, the pad processing module identifies the third filling code block. In other words, the pad processing module finds the third filling code block. For each code block mapped to the code block bitmap and not including a code block identifier, the pad processing module detects whether the code block is a padding code block based on the 66 bits of the code block. Optionally, if the pad processing module determines that the number of bits in the 66 bits that match the padding code block exceeds a target number, the pad processing module determines that the code block is a padding code block, that is, the pad processing module successfully detects the code block and finds the padding code block. If the number of bits in the 66 bits that match the padding code block does not exceed the target number, the pad processing module determines that the code block is not a padding code block, that is, the pad processing module fails to detect the code block.

[0246] In one embodiment, the check identifier included in the third padding code block is a CRC code, which is obtained by performing a CRC calculation on the code block identifier in the third padding code block. For example, the third padding code block is shown in Figure 11. For each code block including a code block identifier in the n-1 code blocks after the first first padding code block found in the first data stream, the pad processing module detects whether the code block includes a CRC code. If the code block includes a CRC code, the pad processing module verifies the correctness of the code block identifier in the code block based on the CRC code. Specifically, the pad processing module obtains the code block identifier and CRC code in the code block, and performs a CRC calculation on the code block identifier in the code block to obtain a CRC calculation result. The pad processing module determines whether the CRC calculation result matches the CRC code (for example, they are the same or the number of the same bits reaches a certain number). If the CRC calculation result matches the CRC code, the pad processing module determines that the code block identifier is successfully verified and the pad processing module determines that the code block identifier is correct. In the case that the CRC calculation result does not match the CRC code, the pad processing module determines that the check of the code block identifier has failed, and the pad processing module determines that the code block identifier is incorrect.

[0247] In another embodiment, the check mark included in the third padding code block is a bit-flip code of the code block identifier included in the third padding code block, for example, the third padding code block is shown in Figure 13 or 14. For each code block including a code block identifier in the n-1 code blocks after the first first padding code block found in the first data stream, the pad processing module detects whether the code block includes a check mark. If the code block includes a check mark, the pad processing module verifies the correctness of the code block identifier in the code block based on the check mark. Specifically, the pad processing module performs a bit-flip on the code block identifier in the code block to obtain a bit-flip code for the code block identifier. The pad processing module determines whether the bit-flip code of the code block identifier matches the check mark (for example, they are the same or the number of bits that are the same reaches a certain number). If the bit-flip code of the code block identifier matches the check mark, the pad processing module determines that the check of the code block identifier is successful, and the pad processing module determines that the code block identifier is correct. In the case that the bit flip code of the code block identifier does not match the check identifier, the pad processing module determines that the check of the code block identifier fails, and the pad processing module determines that the code block identifier is wrong.

[0248] In an optional embodiment, for each code block in the n-1 code blocks that includes a code block identifier and a check identifier, the pad processing module detects the correctness of the check identifier in the code block. If the check identifier in the code block is determined to be correct, the pad processing module verifies the correctness of the code block identifier in the code block based on the check identifier in the code block. In one embodiment, the code block includes multiple code block identifiers and multiple check identifiers, and the number of the multiple code block identifiers is equal to or unequal to the number of the multiple check identifiers, for example, the number of the multiple code block identifiers and the number of the multiple check identifiers are an odd number. The pad processing module detects the correctness of the multiple check identifiers and verifies the correctness of the multiple code block identifiers based on the correct check identifiers among the multiple check identifiers. In another embodiment, the code block includes multiple code block identifiers and multiple check identifiers, and the multiple code block identifiers correspond one-to-one to the multiple check identifiers. The pad processing module detects the correctness of the multiple check identifiers and verifies the correctness of the corresponding code block identifiers among the multiple code block identifiers based on the correct check identifiers among the multiple check identifiers.

[0249] In an optional embodiment, for each code block in the n-1 code blocks that includes multiple code block identifiers and multiple check identifiers, the number of the multiple code block identifiers is equal to or unequal to the number of the multiple check identifiers, for example, the sum of the number of the multiple code block identifiers and the number of the multiple check identifiers is an odd number. The pad processing module detects the correctness of the multiple code block identifiers and the multiple check identifiers. Based on the detection result, the pad processing module determines the sum of the number of correct code block identifiers in the multiple code block identifiers and the number of correct check identifiers in the multiple check identifiers. If the sum of the number of correct code block identifiers in the multiple code block identifiers and the number of correct check identifiers in the multiple check identifiers exceeds half of the sum of the number of the multiple code block identifiers and the number of check identifiers, the pad processing module determines that the code block is a third padding code block. If the sum of the number of correct code block identifiers in the multiple code block identifiers and the number of correct check identifiers in the multiple check identifiers does not exceed half of the sum of the number of the multiple code block identifiers and the number of check identifiers, the pad processing module determines that the code block is not the third padding code block. Optionally, when the sum of the number of the multiple code block identifiers and the number of the multiple check identifiers is an odd number, half of the sum of the number of the multiple code block identifiers and the number of the multiple check identifiers is not an integer, the pad processing module may round up half of the sum of the number of the multiple code block identifiers and the number of the multiple check identifiers for identification and judgment, and the embodiments of the present application are not limited to this.

[0250] The above embodiment uses the example of the pad processing module jointly identifying (or searching for) the third filler code block based on the code block identifier and the check identifier. When the third filler code block includes multiple code block identifiers, the pad processing module can identify (or search for) the third filler code block based on the multiple code block identifiers. In one embodiment, for each code block that includes multiple code block identifiers among the n-1 code blocks following the first first filler code block found in the first data stream, the pad processing module detects the correctness of the multiple code block identifiers. The pad processing module determines the number of correct code block identifiers among the multiple code block identifiers. If the number of correct code block identifiers among the multiple code block identifiers exceeds half of the number of the multiple code block identifiers, the pad processing module determines that the code block is the third filler code block. If the number of correct code block identifiers among the multiple code block identifiers does not exceed half of the number of the multiple code block identifiers, the pad processing module determines that the code block is not the third filler code block. Optionally, when the number of the multiple code block identifiers is an odd number, half of the number of the multiple code block identifiers is not an integer. The pad processing module can round up half of the number of the multiple code block identifiers for identification and judgment. This embodiment of the present application does not limit this.

[0251] Based on the above description, it can be seen that in the embodiment of the present application, the third padding code block is configured to include multiple code block identifiers and / or multiple check identifiers. Even if some of the multiple code block identifiers and / or the multiple check identifiers have errors, the pad processing module in the FlexE shim at the receiving end can still identify the third padding code block. This can avoid errors in the code block identifier and / or check identifier in the third padding code block, which can cause the pad processing module in the FlexE shim at the receiving end to be unable to identify the third padding code block, thereby improving the fault tolerance of the pad processing module in finding the third padding code block. In addition, the pad processing module in the FlexE shim at the receiving end only needs to identify the code block identifier and / or check identifier in the third padding code block to identify the third padding code block, and may not need to identify the entire content of the third padding code block. In other words, the pad processing module only needs to detect the correctness of the code block identifier and / or check identifier in the third padding code block to achieve the effect of identifying the third padding code block. Therefore, the process of the pad processing module finding the third padding code block can be simplified. The embodiment of the present application reduces the dependency between the filling code blocks by setting the third filling code block to include a code block identifier. Even if some filling code blocks are erroneous, it does not affect the pad processing module's search for the filling sequence in the first data stream.

[0252] S2203. Determine that a filling sequence is found when multiple filling code blocks found continuously in the first data stream meet a preset condition, where the preset condition includes: the number of the multiple filling code blocks is greater than a preset threshold and the number of the multiple filling code blocks is less than or equal to n.

[0253] During a search for padding blocks in a first data stream by a pad processing module in a FlexE shim at a receiving end, the pad processing module determines whether the number of padding blocks found consecutively in the first data stream is greater than a preset threshold and less than or equal to n. If the pad processing module determines that the number of padding blocks found consecutively is greater than the preset threshold and less than or equal to n, the pad processing module determines that the padding blocks meet a preset condition, and then the pad processing module determines that a padding sequence has been found. If the pad processing module determines that the number of padding blocks is not greater than the preset threshold, the pad processing module determines that the padding blocks do not meet the preset condition, and the pad processing module continues searching for padding blocks in the first data stream until multiple padding blocks found consecutively meet the preset condition. Optionally, the padding blocks found consecutively in the first data stream by the pad processing module include the first first padding block found consecutively by the pad processing module in the first data stream and the padding blocks found by the pad processing module n-1 blocks after the first first padding block.

[0254] In an optional embodiment, the pad processing module performs at least one search process on the first data stream to search for a padding sequence in the first data stream. During each search process, the pad processing module searches for a first padding code block in the first data stream. After the pad processing module finds the first first padding code block in the first data stream, the pad processing module searches for a padding code block in the n-1 code blocks after the first first padding code block. Furthermore, the pad processing module determines whether the number of padding code blocks found in the n code blocks (including the first first padding code block and the n-1 code blocks) is greater than a preset threshold. If the pad processing module determines that the number of padding code blocks found in the n code blocks is greater than the preset threshold, the pad processing module determines that the multiple padding code blocks found continuously meet the preset condition, and then the pad processing module determines that the padding sequence is found. The pad processing module determines that this search process is successful, and the pad processing module ends the search process. When the pad processing module determines that the number of padding code blocks found in the n code blocks is not greater than the preset threshold, the pad processing module determines that multiple padding code blocks found continuously meet the non-preset condition, the pad processing module determines that the current search process has failed, and the pad processing module performs the next search process. Optionally, in the first search process, the pad processing module starts searching for the first padding code block from the starting position of the first data stream. In each subsequent search process, the pad processing module starts searching for the first padding code block from the end position of the previous search process (specifically, the next code block of the n code blocks detected in the previous search process), which is not limited in this embodiment of the present application.

[0255] It should be noted that the above-mentioned preset threshold can be set flexibly according to the circumstances, and the embodiment of the present application does not limit the specific value of the preset threshold. The embodiment of the present application takes the preset condition for finding a filling sequence as an example, including that the number of multiple filling code blocks found continuously in the first data stream is greater than the preset threshold and less than or equal to n. In some embodiments, the preset condition for finding a filling sequence includes: the number of multiple filling code blocks found continuously in the first data stream is greater than or equal to the preset threshold and less than or equal to n. How the preset condition is specifically set may be related to the preset threshold. In one example, when n is 8 and the preset threshold is 6, the preset condition may be: the number of multiple filling code blocks found continuously in the first data stream is greater than the preset threshold and less than or equal to n; when n is 8 and the preset threshold is 7, the preset condition may be: the number of multiple filling code blocks found continuously in the first data stream is greater than or equal to the preset threshold and less than or equal to n. In another example, when n is 16 and the preset threshold is 13, the preset condition may be: the number of padding blocks found consecutively in the first data stream is greater than the preset threshold and less than or equal to n; when n is 16 and the preset threshold is 14, the preset condition may be: the number of padding blocks found consecutively in the first data stream is greater than or equal to the preset threshold and less than or equal to n. In yet another example, when n is 32 and the preset threshold is 28, the preset condition may be: the number of padding blocks found consecutively in the first data stream is greater than the preset threshold and less than or equal to n; when n is 32 and the preset threshold is 29, the preset condition may be: the number of padding blocks found consecutively in the first data stream is greater than or equal to the preset threshold and less than or equal to n. In another example, when n is 64 and the preset threshold is 60, the preset condition may be: the number of multiple padding code blocks found consecutively in the first data stream is greater than the preset threshold and less than or equal to n; when n is 64 and the preset threshold is 61, the preset condition may be: the number of multiple padding code blocks found consecutively in the first data stream is greater than or equal to the preset threshold and less than or equal to n. It can be seen that whether the preset condition includes the case where the number of multiple padding code blocks found consecutively is equal to the preset threshold depends on the setting of the preset threshold, and the scope of the preset condition can be flexibly set based on the preset threshold.

[0256] After finding the padding sequence in the first data stream, the pad processing module in the FlexE shim at the receiving end can delete the padding sequence in the first data stream. Optionally, the pad processing module deletes the padding sequence in the first data stream based on the first padding sequence found in the first data stream and the period at which the padding sequence appears in the first data stream. In one embodiment, there is a padding sequence every w code blocks in the first data stream. The pad processing module first deletes the first padding sequence found in the first data stream, and then deletes n code blocks every w code blocks (the pad processing module considers these n code blocks to be n padding code blocks, that is, padding sequences).

[0257] In the embodiment shown in Figure 22, after the pad processing module in the FlexE shim at the receiving end deletes the padding sequence in the first data stream, the pad processing module sends the data stream after the padding sequence is deleted (for example, the data stream after the padding sequence is deleted is the initial data stream described in S1001) to the corresponding FlexE instance, so that the FlexE instance processes the initial data stream. The initial data stream is processed by the FlexE instance, the timeslot allocation scheduler, and the idle addition and deletion module in sequence to restore the FlexE client data stream. The FlexE shim at the receiving end sends the FlexE client data stream to the MAC layer for processing.

[0258] In summary, the data processing method provided in the embodiments of the present application, because the first data stream includes a periodically occurring padding sequence, the padding sequence includes n consecutive padding blocks, where n is an integer greater than or equal to 4. Therefore, the embodiments of the present application provide a FlexE-oriented method for inserting a large number of padding blocks into a data stream. This method is applicable to higher-speed PHY interfaces such as 800GE PHY interfaces and 1.6TE PHY interfaces, and is adaptable to the evolution of Ethernet standards. The pad processing module in the FlexE shim at the receiving end determines that the padding sequence has been found when the number of padding blocks found consecutively in the first data stream is greater than a preset threshold and less than or equal to n. The number of padding blocks found consecutively does not necessarily need to be equal to n, that is, it is not necessary for all padding blocks in the padding sequence to be correctly detected. Therefore, the embodiments of the present application provide a method for finding the padding sequence using a soft decision approach. The pad processing module in the FlexE shim at the receiving end has a relatively relaxed process for finding the padding sequence, has better fault tolerance for finding the padding sequence, and can maintain the probability of successfully finding the padding sequence.

[0259] Please refer to Figure 24, which shows a flowchart of another data processing method provided in an embodiment of the present application. The data processing method is applied to FlexE. The data processing method is executed by the FlexE shim in the transmitting end, specifically by the pad processing module in the FlexE shim. Optionally, the FlexE shim in the transmitting end includes multiple pad processing modules, and the data processing method is executed by any pad processing module of the multiple pad processing modules. For example, the data processing method shown in Figure 24 is executed by any pad processing module in the FlexE shim in the transmitting end shown in Figure 9. Referring to Figure 24, the data processing method includes the following steps S2401 to S2402.

[0260] S2401. Receive an initial data stream, where the initial data stream is obtained by interleaving multiple data streams sent by multiple FlexE instances.

[0261] In the transmitting FlexE shim, the interleaving module can send data streams to the pad processing module, which then receives the data streams sent by the interleaving module. For ease of distinction, in this embodiment, the data stream sent by the interleaving module to the pad processing module is referred to as the initial data stream. This initial data stream is generated by the interleaving module interleaving multiple data streams sent to it by multiple FlexE instances.

[0262] S2402. Periodically insert a filling sequence into the initial data stream to obtain a first data stream, the first data stream including the periodically appearing filling sequence, the filling sequence including n consecutive filling code blocks, where n is an integer greater than or equal to 16.

[0263] For the implementation process of S2402, please refer to the implementation process of S1002. For the description of the first data stream in this embodiment, please refer to the embodiment shown in Figure 10, which will not be repeated here. It should be noted that, unlike the embodiment shown in Figure 10, in this embodiment, n is an integer greater than or equal to 16.

[0264] In this embodiment, after the pad processing module at the transmitting end obtains the first data stream, the pad processing module sends the first data stream to the physical layer of the transmitting end. The physical layer performs physical layer-related processing on the first data stream (for example, inserting AM code blocks into the first data stream) and then sends the processed data stream to the receiving end through the PHY interface of the transmitting end.

[0265] In summary, in the data processing method provided in the embodiment of the present application, the pad processing module in the FlexE shim at the transmitting end periodically inserts a padding sequence into the initial data stream to obtain a first data stream. The padding sequence includes n consecutive padding code blocks, where n is an integer greater than or equal to 16. It can be seen that the embodiment of the present application provides a FlexE-oriented method for inserting a large number of padding code blocks into a data stream. This method is applicable to higher-speed PHY interfaces such as 800GE PHY interfaces and 1.6TE PHY interfaces, and can adapt to the evolution of Ethernet standards.

[0266] Please refer to Figure 25, which shows a flowchart of another data processing method provided in an embodiment of the present application. The data processing method is applied to FlexE. The data processing method is executed by the FlexE shim in the receiving end, specifically by the pad processing module in the FlexE shim. Optionally, the FlexE shim in the receiving end includes multiple pad processing modules, and the data processing method is executed by any pad processing module of the multiple pad processing modules. For example, the data processing method shown in Figure 25 is executed by any pad processing module in the FlexE shim in the receiving end shown in Figure 9. Referring to Figure 25, the data processing method includes the following steps S2501 to S2503.

[0267] S2501. Obtain a first data stream. The first data stream is obtained by periodically inserting a padding sequence into an initial data stream. The initial data stream is obtained by interleaving multiple data streams sent by multiple FlexE instances. The first data stream includes the periodically appearing padding sequence. The padding sequence includes n consecutive padding code blocks, where n is an integer greater than or equal to 16.

[0268] Optionally, in the FlexE shim at the receiving end, the pad processing module receives the first data stream sent by the physical layer. The first data stream is the data stream after the physical layer performs physical layer related processing (such as deleting AM code blocks) on the data stream received by the PHY interface of the receiving end. In addition, the first data stream is the data stream obtained by the pad processing module in the FlexE shim at the transmitting end periodically inserting a padding sequence into the initial data stream, and the initial data stream is obtained by the interleaving module in the FlexE shim at the transmitting end interleaving multiple data streams sent by multiple FlexE instances in the FlexE shim. It should be noted that the first data stream in the embodiment shown in Figure 25 is the same data stream as the first data stream in the embodiment shown in Figure 24, but the first data stream in the embodiment shown in Figure 25 may have bit errors compared to the first data stream in the embodiment shown in Figure 24. For the description of the first data stream in the embodiment shown in Figure 25, please refer to the embodiment shown in Figure 10, which will not be repeated here. Unlike the embodiment shown in Figure 10, in the embodiment shown in Figure 25, n is an integer greater than or equal to 16.

[0269] S2502. Search for a filling code block in the first data stream to find a filling sequence.

[0270] S2503. Determine that a filling sequence is found when multiple filling code blocks found continuously in the first data stream meet preset conditions. The preset conditions include: the number of the multiple filling code blocks is greater than a preset threshold and the number of the multiple filling code blocks is less than or equal to n.

[0271] The implementation process of S2502 to S2503 can refer to the implementation process of S2202 to S2203, and will not be repeated here.

[0272] It should be noted that the value of the preset threshold in S2503 is different from the value of the preset threshold in S2203, and the preset threshold in S2503 is usually greater than the preset threshold in S2203. Similar to S2203, the preset threshold in S2503 can be flexibly set according to the situation, and the embodiment of the present application does not limit the specific value of the preset threshold. In addition, the embodiment of the present application takes the preset condition for finding a filling sequence as an example, including the number of multiple filling code blocks found continuously in the first data stream being greater than the preset threshold and less than or equal to n. In some embodiments, the preset condition for finding a filling sequence includes: the number of multiple filling code blocks found continuously in the first data stream is greater than or equal to the preset threshold and less than or equal to n. How the preset condition is specifically set may be related to the preset threshold. In one example, when n is 16 and the preset threshold is 13, the preset condition may be: the number of padding blocks found consecutively in the first data stream is greater than the preset threshold and less than or equal to n; when n is 16 and the preset threshold is 14, the preset condition may be: the number of padding blocks found consecutively in the first data stream is greater than or equal to the preset threshold and less than or equal to n. In another example, when n is 32 and the preset threshold is 28, the preset condition may be: the number of padding blocks found consecutively in the first data stream is greater than the preset threshold and less than or equal to n; when n is 32 and the preset threshold is 29, the preset condition may be: the number of padding blocks found consecutively in the first data stream is greater than or equal to the preset threshold and less than or equal to n. In another example, when n is 64 and the preset threshold is 60, the preset condition may be: the number of multiple padding blocks found consecutively in the first data stream is greater than the preset threshold and less than or equal to n; when n is 64 and the preset threshold is 61, the preset condition may be: the number of multiple padding blocks found consecutively in the first data stream is greater than or equal to the preset threshold and less than or equal to n. In another example, when n is 128 and the preset threshold is 120, the preset condition may be: the number of multiple padding blocks found consecutively in the first data stream is greater than the preset threshold and less than or equal to n; when n is 128 and the preset threshold is 121, the preset condition may be: the number of multiple padding blocks found consecutively in the first data stream is greater than or equal to the preset threshold and less than or equal to n. It can be seen that whether the preset condition includes the situation where the number of multiple padding blocks found consecutively is equal to the preset threshold depends on the setting of the preset threshold, and the range of the preset condition can be flexibly set according to the preset threshold.

[0273] In this embodiment, after the pad processing module in the FlexE shim at the receiving end finds the padding sequence in the first data stream, the pad processing module deletes the padding sequence in the first data stream. The pad processing module sends the data stream after deleting the padding sequence (for example, the data stream after deleting the padding sequence is the initial data stream described in S2201) to the corresponding deinterleaving module in the receiving end. The deinterleaving module deinterleaves the initial data stream to obtain multiple data streams. The deinterleaving module sends the multiple data streams one by one to multiple FlexE instances in the receiving end so that the multiple FlexE instances process the multiple data streams. The initial data stream is processed by the deinterleaving module, the FlexE instance, the time slot allocation scheduler and the idle addition and deletion module in sequence to restore the FlexE client data stream. The FlexE shim at the receiving end sends the FlexE client data stream to the MAC layer for processing.

[0274] In summary, the data processing method provided in the embodiments of the present application provides a FlexE-oriented method for inserting a large number of padding blocks into a data stream, as the first data stream includes a periodically occurring padding sequence comprising n consecutive padding blocks, where n is an integer greater than or equal to 16. The method is applicable to higher-speed PHY interfaces such as 800GE PHY interfaces and 1.6TE PHY interfaces, and is adaptable to the evolution of Ethernet standards. The pad processing module in the FlexE shim at the receiving end determines that the padding sequence has been found when the number of padding blocks found consecutively in the first data stream is greater than a preset threshold and less than or equal to n. The number of padding blocks found consecutively does not necessarily need to be equal to n, i.e., it is not necessary for all padding blocks in the padding sequence to be correctly detected. Therefore, the embodiments of the present application provide a method for finding the padding sequence using a soft decision approach. The pad processing module in the FlexE shim at the receiving end has a relatively relaxed process for finding the padding sequence, has better fault tolerance for finding the padding sequence, and can maintain a stable probability of successfully finding the padding sequence.

[0275] The above is an introduction to the method embodiments of the present application. The following describes the device embodiments of the present application. The device of the present application can be used to perform the method of the present application. For details not disclosed in the device embodiments of the present application, please refer to the method embodiments.

[0276] Please refer to Figure 26, which shows a schematic diagram of a data processing device 600 provided in an embodiment of the present application. The data processing device 600 is applied to FlexE. For example, the data processing device 600 is a FlexE shim in the transmitting end, and specifically can be a pad processing module in the FlexE shim. The data processing device 600 is used to execute the method provided in the embodiments shown in Figures 10 and 24. As shown in Figure 26, the data processing device 600 includes a transceiver unit 610 and a processing unit 620. The transceiver unit 610 is used to perform the transceiver operations in the method embodiments shown in Figures 10 and 24, and the processing unit 620 is used to perform operations other than the transceiver operations in the method embodiments shown in Figures 10 and 24.

[0277] In one implementation: a transceiver unit 610 is used to receive an initial data stream sent by a FlexE instance; a processing unit 620 is used to periodically insert a padding sequence into the initial data stream to obtain a first data stream, wherein the first data stream includes the periodically appearing padding sequence, and the padding sequence includes n consecutive padding code blocks, where n is an integer greater than or equal to 4.

[0278] In another implementation: the transceiver unit 610 is used to receive an initial data stream, which is obtained by interleaving multiple data streams sent by multiple FlexE instances; the processing unit 620 is used to periodically insert a padding sequence into the initial data stream to obtain a first data stream, wherein the first data stream includes the periodically appearing padding sequence, and the padding sequence includes n consecutive padding code blocks, where n is an integer greater than or equal to 16.

[0279] Optionally, in the above two implementations, the n filling code blocks include x first filling code blocks and y second filling code blocks, the first filling code block is a globally unique control code block in the first data stream, the second filling code block is an error code block, x is a positive integer, and y is a positive integer.

[0280] Optionally, in the above two implementations, the x first filling code blocks and the y second filling code blocks satisfy any one of the following conditions:

[0281] x=1, y=n-1, the y second filling code blocks are located after the first filling code block, and the y second filling code blocks are continuous with the first filling code block; or,

[0282] n is an even number, x=y=n / 2, the y second padding code blocks are located after the x first padding code blocks, and the y second padding code blocks are continuous with the x first padding code blocks; or,

[0283] n is an even number, x=y=n / 2, the padding sequence includes n / 2 code block groups, each code block group includes one first padding code block and one second padding code block, in each code block group, the second padding code block is located after the first padding code block and is continuous with the first padding code block, and the padding code blocks in the n / 2 code block groups are continuous; or

[0284] The x first filling code blocks include x1 first filling code blocks and x2 first filling code blocks, the y second filling code blocks are located between the x1 first filling code blocks and the x2 first filling code blocks, the x1 first filling code blocks, the y second filling code blocks and the x2 first filling code blocks are continuous, x1+x2=x, x1 and x2 are both positive integers.

[0285] Optionally, in the above two implementations, the n filling code blocks also include z third filling code blocks, where z is a positive integer; the y second filling code blocks are located after the x first filling code blocks and before the z third filling code blocks, and the x first filling code blocks, the y second filling code blocks and the z third filling code blocks are continuous; or, the z third filling code blocks are located after the x first filling code blocks and before the y second filling code blocks, and the x first filling code blocks, the z third filling code blocks and the y second filling code blocks are continuous.

[0286] Optionally, in the above two implementations, the third filling code block is a data code block.

[0287] Optionally, in the above two implementations, the third filling code block includes at least one code block identifier.

[0288] Optionally, in the above two implementations, the third filling code block further includes at least one verification identifier, and the at least one verification identifier is used to verify the correctness of the at least one code block identifier.

[0289] Optionally, in the above two implementations, the number of the at least one code block identifier is equal to the number of the at least one check identifier; or the sum of the number of the at least one code block identifier and the number of the at least one check identifier is an odd number.

[0290] In summary, the technical solution provided by the embodiment of the present application is that the data processing device (i.e., the FlexE shim in the transmitting end) periodically inserts a padding sequence into the initial data stream, which includes n consecutive padding code blocks, where n is an integer greater than or equal to 4, or n is an integer greater than or equal to 16. It can be seen that the embodiment of the present application can insert more padding code blocks into the data stream for FlexE, and can be applied to higher-speed PHY interfaces such as 800GE PHY interfaces and 1.6TE PHY interfaces, and can adapt to the evolution of Ethernet standards.

[0291] Please refer to Figure 27, which shows a schematic diagram of another data processing device 700 provided in an embodiment of the present application. The data processing device 700 is applied to FlexE. For example, the data processing device 700 is a FlexE shim in the receiving end, and specifically can be a pad processing module in the FlexE shim. The data processing device 700 is used to execute the method provided in the embodiments shown in Figures 22 and 25. As shown in Figure 27, the data processing device 700 includes a transceiver unit 710 and a processing unit 720, the transceiver unit 710 is used to perform the transceiver operations in the method embodiments shown in Figures 22 and 25, and the processing unit 720 is used to perform operations other than the transceiver operations in the method embodiments shown in Figures 22 and 25.

[0292] In one implementation: a transceiver unit 710 is used to obtain a first data stream, where the first data stream is one of the multiple data streams obtained by deinterleaving, and the first data stream includes a periodically appearing filling sequence, where the filling sequence includes n consecutive filling code blocks, where n is an integer greater than or equal to 4; a processing unit 720 is used to search for filling code blocks in the first data stream to find the filling sequence; and to determine that the filling sequence is found when multiple filling code blocks found consecutively in the first data stream meet a preset condition, where the preset condition includes: the number of the multiple filling code blocks is greater than a preset threshold and the number of the multiple filling code blocks is less than or equal to n.

[0293] In another implementation: the transceiver unit 710 is used to obtain a first data stream, which is obtained by periodically inserting a filling sequence into an initial data stream, and the initial data stream is obtained by interleaving multiple data streams sent by multiple FlexE instances. The first data stream includes the periodically appearing filling sequence, and the filling sequence includes n consecutive filling code blocks, where n is an integer greater than or equal to 16; the processing unit 720 is used to search for filling code blocks in the first data stream to find the filling sequence; and to determine that the filling sequence is found when multiple filling code blocks found continuously in the first data stream meet a preset condition, and the preset condition includes: the number of the multiple filling code blocks is greater than a preset threshold and the number of the multiple filling code blocks is less than or equal to n.

[0294] Optionally, in the above two implementations, the n filling code blocks include x first filling code blocks and y second filling code blocks, the first filling code block is a globally unique control code block in the first data stream, the second filling code block is an error code block, x is a positive integer, and y is a positive integer.

[0295] Optionally, in the above two implementations, the x first filling code blocks and the y second filling code blocks satisfy any one of the following conditions:

[0296] x=1, y=n-1, the y second filling code blocks are located after the first filling code block, and the y second filling code blocks are continuous with the first filling code block; or,

[0297] n is an even number, x=y=n / 2, the y second padding code blocks are located after the x first padding code blocks, and the y second padding code blocks are continuous with the x first padding code blocks; or,

[0298] n is an even number, x=y=n / 2, the padding sequence includes n / 2 code block groups, each code block group includes a first padding code block and a second padding code block, in each code block group, the second padding code block is located after the first padding code block and is continuous with the first padding code block, and the padding code blocks in the n / 2 code block groups are continuous; or

[0299] The x first filling code blocks include x1 first filling code blocks and x2 first filling code blocks, the y second filling code blocks are located between the x1 first filling code blocks and the x2 first filling code blocks, the x1 first filling code blocks, the y second filling code blocks and the x2 first filling code blocks are continuous, x1+x2=x, x1 and x2 are both positive integers.

[0300] Optionally, in the above two implementations, the n filling code blocks also include z third filling code blocks, where z is a positive integer; the y second filling code blocks are located after the x first filling code blocks and before the z third filling code blocks, and the x first filling code blocks, the y second filling code blocks and the z third filling code blocks are continuous; or, the z third filling code blocks are located after the x first filling code blocks and before the y second filling code blocks, and the x first filling code blocks, the z third filling code blocks and the y second filling code blocks are continuous.

[0301] Optionally, in the above two implementations, the third filling code block is a data code block.

[0302] Optionally, in the above two implementations, the third filling code block includes at least one code block identifier.

[0303] Optionally, in the above two implementations, the third filling code block further includes at least one verification identifier, and the at least one verification identifier is used to verify the correctness of the at least one code block identifier.

[0304] Optionally, in the above two implementations, the number of the at least one code block identifier is equal to the number of the at least one check identifier; or the sum of the number of the at least one code block identifier and the number of the at least one check identifier is an odd number.

[0305] Optionally, in the above two implementations, the n filling code blocks include x first filling code blocks, the first filling code block is a globally unique control code block in the first data stream, x is a positive integer, and the processing unit 720 is used to: search for the first filling code block in the first data stream; and search for the filling sequence in the first data stream based on the first filling code block found in the first data stream.

[0306] Optionally, in the above two implementations, the processing unit 720 is used to: determine the n-1 code blocks after the first first filling code block found in the first data stream, the n-1 code blocks are continuous, and the n-1 code blocks are continuous with the first first filling code block; and detect the n-1 code blocks to find the filling code block in the n-1 code blocks.

[0307] Optionally, in the above two implementations, the processing unit 720 is used to: map the first first filling code block and the n-1 code blocks into a code block bitmap; and detect the n-1 code blocks based on the code block bitmap to search for the filling code block in the n-1 code blocks.

[0308] Optionally, in the above two implementations, the n filling code blocks include a third filling code block, and the third filling code block includes at least one code block identifier. The processing unit 720 is used to map the third filling code block to the code block bitmap based on the code block identifier in the third filling code block.

[0309] Optionally, in the above two implementations, the third filling code block also includes at least one check identifier, and the processing unit 720 is used to: verify the correctness of the at least one code block identifier based on the at least one check identifier; and map the third filling code block to the code block bitmap based on the correct code block identifier in the at least one code block identifier.

[0310] In summary, the technical solution provided by the embodiment of the present application is that since the first data stream includes a periodically appearing filling sequence, the filling sequence includes n consecutive filling code blocks, n is an integer greater than or equal to 4, or n is an integer greater than or equal to 16, so the present application can be oriented to FlexE to insert more filling code blocks in the data stream, and can be applicable to higher-speed PHY interfaces such as 800GE PHY interface and 1.6TE PHY interface, and can adapt to the evolution of Ethernet standards. The data processing device (that is, the FlexE shim at the receiving end) determines that the filling sequence is found when the number of multiple filling code blocks found continuously in the first data stream is greater than a preset threshold and less than or equal to n, and the number of multiple filling code blocks found continuously does not need to be equal to n, that is, it is not necessary for all filling code blocks in the filling sequence to be detected correctly, so the process of finding the filling sequence is relatively relaxed, the fault tolerance of finding the filling sequence is better, and the probability of successfully finding the filling sequence can be maintained without degradation.

[0311] The data processing device provided in the embodiments of the present application may also be implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD may be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. The data processing method provided in the above method embodiments may also be implemented using software. When the data processing method provided in the above method embodiments is implemented using software, each module in the data processing device may also be a software module.

[0312] An embodiment of the present application provides a data processing device, which is applied to FlexE. The data processing device can be a transmitting end or a functional component within the transmitting end, or the receiving end or a functional component within the receiving end. The data processing device includes a memory and a processor. The memory is configured to store a computer program. The processor is configured to execute the computer program stored in the memory, causing the data processing device to perform all or part of the steps of the data processing method provided in the above method embodiment.

[0313] In one embodiment, please refer to Figure 28, which shows a schematic diagram of another data processing device 800 provided in an embodiment of the present application. The data processing device 800 can be a transmitting end or a functional component in the transmitting end, and the data processing device 800 can also be a receiving end or a functional component in the receiving end. The data processing device 800 can implement the method embodiments shown in Figures 10, 22, 24 or 25. The data processing device 800 includes a main control board 810, an interface board 830 and an interface board 840. In the case of multiple interface boards, a switching network board (not shown in Figure 28) is also included, and the switching network board is used to complete data exchange between interface boards (interface boards are also called line cards or service boards).

[0314] The main control board 810 performs functions such as system management, device maintenance, and protocol processing. The interface boards 830 and 840 provide various service interfaces and implement service forwarding. These service interfaces include POS interfaces, GE PHY interfaces, TE PHY interfaces, and asynchronous transfer mode (ATM) interfaces. The main control board 810 primarily includes three functional units: a system management and control unit, a system clock unit, and a system maintenance unit. The main control board 810, interface boards 830, and interface boards 840 are interconnected via a system bus and the system backplane. The interface board 830 includes one or more processors 831. Processors 831 control and manage the interface board 830 and communicate with the central processing unit 812 on the main control board 810. The memory 832 on the interface board 830 stores forwarding table entries. The interface board 830 also includes one or more network interfaces 833 for transmitting and receiving. The main control board 810 also includes a memory 814, which is used to store system management information, protocols, etc., which is not limited in this embodiment of the present application.

[0315] As shown in FIG28 , this embodiment includes multiple interface boards and employs a distributed forwarding mechanism. Under this mechanism, the operations on the interface board 840 are substantially similar to those on the interface board 830. For example, the interface board 840 includes one or more network interfaces 843 for transmitting and receiving packets, includes a memory 842 for storing forwarding table entries, and includes a processor 841 for controlling and managing the interface board 840 and communicating with the central processing unit 812 on the main control board 810.

[0316] In FIG28 , the processor 831 in interface board 830 and / or the processor 841 in interface board 840 can be dedicated hardware or chips, such as a network processor or an application-specific integrated circuit, to implement the aforementioned functions. This implementation is commonly referred to as utilizing dedicated hardware or chips for forwarding plane processing. In other embodiments, the processor 831 in interface board 830 and / or the processor 841 in interface board 840 can also be a general-purpose processor, such as a general-purpose central processing unit (CPU).

[0317] There may be one or more main control boards, and when there are multiple boards, they may include a primary main control board and a backup main control board. There may be one or more interface boards. The stronger the data processing capability of a device (such as a transmitter, receiver, etc.), the more interface boards are provided. In the case of multiple interface boards, the multiple interface boards can communicate with each other through one or more switching network boards. When there are multiple boards, they can jointly achieve load sharing and redundant backup. In a centralized forwarding architecture, the device may not require a switching network board, and the interface board is responsible for processing the service data of the entire system. In a distributed forwarding architecture, the device includes multiple interface boards, and data exchange between multiple interface boards can be achieved through the switching network board, providing large-capacity data exchange and processing capabilities. Therefore, the data access and processing capabilities of devices with a distributed architecture are greater than those of devices with a centralized architecture. The specific architecture to be adopted depends on the network deployment scenario and is not limited here.

[0318] In an optional embodiment, the memory 832 and / or the memory 842 is a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, an optical disc storage (including a compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited to these. The memory 832 can be independent and connected to the processor 831 via a communication bus, or it can be integrated with the processor 831. The memory 842 can be independent and connected to the processor 841 via a communication bus, or it can be integrated with the processor 841.

[0319] The memory 832 is used to store program code (i.e., computer program) and is controlled by the processor 831 to execute part or all of the steps of the data processing method provided in the above embodiment. The processor 831 is used to execute the program code stored in the memory 832. The program code may include one or more software units. These one or more software units may be the functional units provided in the embodiment shown in Figure 26 or Figure 27 above. The memory 842 may also be used to store program code and be controlled by the processor 841 to execute part or all of the steps of the data processing method provided in the above embodiment. Similarly, the memory 814 may also be used to store program code and be controlled by the central processing unit 812 to execute part or all of the steps of the data processing method provided in the above embodiment.

[0320] Optionally, the network interfaces 833 and 843 use devices such as transceivers for communicating with other devices or networks, such as Ethernet, radio access networks (RAN), wireless local area networks (WLAN), etc.

[0321] In another embodiment, please refer to Figure 29, which shows a schematic diagram of another data processing device 900 provided in an embodiment of the present application. Data processing device 900 can be a transmitting end or a functional component within the transmitting end, or a receiving end or a functional component within the receiving end. Data processing device 900 can implement the method embodiments of Figures 10, 22, 24, or 25.

[0322] As shown in FIG29 , the data processing device 900 includes a processor 902, a memory 904, a communication interface 906, and a bus 908. The processor 902, the memory 904, and the communication interface 906 are communicatively connected via the bus 908. The connection method between the processor 902, the memory 904, and the communication interface 906 shown in FIG29 is merely exemplary. During implementation, the processor 902, the memory 904, and the communication interface 906 may also be connected using a connection method other than the bus 908, and this embodiment of the present application is not limited thereto.

[0323] Memory 904 is used to store computer programs 9042, which may include instructions and data. Memory 904 may be various types of storage media, such as RAM, ROM, non-volatile RAM (NVRAM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), flash memory, optical storage, and registers.

[0324] Among them, the processor 902 can be a general-purpose processor or a special-purpose processor. A general-purpose processor is a processor that performs specific steps and / or operations by reading and executing a computer program (e.g., computer program 9042) stored in a memory (e.g., memory 904). The general-purpose processor may use data stored in the memory (e.g., memory 904) in the process of performing the above steps and / or operations. The stored computer program can be executed to implement the relevant functions of the aforementioned processing unit 620, and the general-purpose processor can be a CPU. A special-purpose processor is a processor specially designed to perform specific steps and / or operations, and the special-purpose processor can be a digital signal processor (DSP), ASIC, or FPGA, etc. The processor 902 can also be a combination of multiple processors, such as a multi-core processor. The processor 902 includes at least one circuit to perform all or part of the steps of the above-mentioned method embodiment.

[0325] The communication interface 906 includes input / output (I / O) interfaces, physical interfaces, and logical interfaces, which are used to interconnect devices within the data processing device 900, as well as interfaces for interconnecting the data processing device 900 with other devices. The physical interface can be a GE PHY interface or a TE PHY interface, which is used to interconnect the data processing device 900 with other devices. The logical interface is an interface within the data processing device 900, which is used to interconnect devices within the data processing device 900. The communication interface 906 can be used for the data processing device 900 to communicate with other devices, and the communication interface 906 can implement the relevant functions of the aforementioned transceiver unit 610 and transceiver unit 710. The communication interface 906 can also include a transceiver for transceiver transmission, and the transceiver can also implement the relevant functions of the transceiver unit 610 and transceiver unit 710.

[0326] Bus 908 is any type of communication bus used to interconnect processor 902, memory 904, and communication interface 906. Bus 908 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, for example. Bus 908 may be classified as an address bus, a data bus, a control bus, and the like. For ease of illustration, FIG29 shows only one thick line, but this does not imply that there is only one bus or only one type of bus.

[0327] The above-mentioned devices can be provided on separate chips, or at least partially or entirely on the same chip. Whether to provide each device independently on different chips or to integrate them on one or more chips often depends on the product design requirements. The embodiments of this application do not limit the specific implementation of the above-mentioned devices.

[0328] The data processing device 900 shown in FIG29 is merely exemplary. During implementation, the data processing device 900 may also include other components, which are not listed here. The data processing device 900 shown in FIG29 inserts a padding sequence into a data stream or deletes a padding sequence from a data stream by executing all or part of the steps of the data processing method provided in the above embodiment.

[0329] Based on the same inventive concept, an embodiment of the present application provides a communication system, comprising a transmitting end and a receiving end. The transmitting end includes a data processing device as shown in Figure 26, Figure 28, or Figure 29. The receiving end includes a data processing device as shown in Figure 27, Figure 28, or Figure 29. For example, the communication system is shown in any of Figures 7 to 9.

[0330] Based on the same inventive concept, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed (for example, by a data processing device, a FlexE shim, a pad processing module in the FlexE shim, one or more processors, etc.), it implements all or part of the steps of the method provided in the above method embodiment.

[0331] Based on the same inventive concept, an embodiment of the present application provides a computer program product, which includes a program or code. When the program or code is executed (for example, by a data processing device, FlexE shim, a pad processing module in the FlexE shim, one or more processors, etc.), it implements all or part of the steps of the method provided in the above method embodiment.

[0332] Based on the same inventive concept, an embodiment of the present application provides a chip, which includes a programmable logic circuit and / or program instructions. When the chip is running, it is used to implement all or part of the steps of the method provided in the above method embodiment.

[0333] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product, which includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center to another website, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium, or a semiconductor medium (e.g., a solid-state hard disk).

[0334] It should be understood that the term "at least one" in this application refers to one or more, and "a plurality of" refers to two or more. In this application, unless otherwise specified, the symbol " / " generally means or, for example, A / B can mean A or B. The term "and / or" in this application is merely a description of the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, for the sake of clarity of description, this application uses words such as "first", "second", and "third" to distinguish between identical or similar items with basically the same functions and effects. Those skilled in the art will understand that words such as "first", "second", and "third" do not limit the quantity and execution order.

[0335] Different types of embodiments, such as method embodiments and device embodiments, provided in the embodiments of the present application can refer to each other. The order of operations of the method embodiments can be appropriately adjusted, and the operations can be increased or decreased in response to the situation. Any technician familiar with this technical field can easily think of different methods within the technical scope disclosed in this application, and they should all be covered within the scope of protection of this application, so they will not be repeated here.

[0336] In the corresponding embodiments provided in this application, it should be understood that the disclosed devices, etc. can be implemented through other structural methods. For example, the device embodiments described above are merely illustrative. For example, the division of modules and / or units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple modules, units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices, modules or units can be electrical or other forms. The modules and / or units described as separate components may be physically separated or not physically separated. The components described as modules and / or units may be physical modules and / or physical units or not physical modules and / or physical units, and may be located in one place or distributed on multiple devices. Some or all of the modules and / or units can be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0337] The above description is merely an exemplary embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A data processing method, characterized in that: Applied to Flexible Ethernet FlexE, the method comprises: Receive the initial data stream sent by the FlexE instance; A filling sequence is periodically inserted into the initial data stream to obtain a first data stream, wherein the first data stream includes the filling sequence that appears periodically, and the filling sequence includes n consecutive filling code blocks, where n is an integer greater than or equal to 4.

2. A data processing method, characterized in that: Applied to Flexible Ethernet FlexE, the method comprises: receiving an initial data stream, where the initial data stream is obtained by interleaving multiple data streams sent by multiple FlexE instances; A filling sequence is periodically inserted into the initial data stream to obtain a first data stream, wherein the first data stream includes the filling sequence that appears periodically, and the filling sequence includes n consecutive filling code blocks, where n is an integer greater than or equal to 16.

3. The method according to claim 1 or 2, characterized in that: The n filling code blocks include x first filling code blocks and y second filling code blocks, the first filling code block is a globally unique control code block in the first data stream, the second filling code block is an error code block, x is a positive integer, and y is a positive integer.

4. The method according to claim 3, characterized in that The x first filling code blocks and the y second filling code blocks satisfy any one of the following conditions: x=1, y=n-1, the y second filling code blocks are located after the first filling code block, and the y second filling code blocks are continuous with the first filling code block; or, The n is an even number, x=y=n / 2, the y second filling code blocks are located after the x first filling code blocks, and the y second filling code blocks are continuous with the x first filling code blocks; or, n is an even number, x=y=n / 2, the filling sequence includes n / 2 code block groups, each code block group includes one first filling code block and one second filling code block, in each code block group, the second filling code block is located after the first filling code block and is continuous with the first filling code block, and the filling code blocks in the n / 2 code block groups are continuous; or The x first filling code blocks include x1 first filling code blocks and x2 first filling code blocks, the y second filling code blocks are located between the x1 first filling code blocks and the x2 first filling code blocks, the x1 first filling code blocks, the y second filling code blocks and the x2 first filling code blocks are continuous, x1+x2=x, and the x1 and x2 are both positive integers.

5. The method according to claim 3, characterized in that: The n padding code blocks further include z third padding code blocks, where z is a positive integer; The y second filling code blocks are located after the x first filling code blocks and before the z third filling code blocks, and the x first filling code blocks, the y second filling code blocks and the z third filling code blocks are continuous; or, The z third filling code blocks are located after the x first filling code blocks and before the y second filling code blocks, and the x first filling code blocks, the z third filling code blocks and the y second filling code blocks are continuous.

6. The method according to claim 5, characterized in that The third filling code block is a data code block.

7. The method according to claim 5 or 6, characterized in that: The third filling code block includes at least one code block identifier.

8. The method according to claim 7, characterized in that The third filling code block further includes at least one verification mark, and the at least one verification mark is used to verify the correctness of the at least one code block mark.

9. The method according to claim 8, characterized in that The number of the at least one code block identifier is equal to the number of the at least one check identifier; or, The sum of the number of the at least one code block identifier and the number of the at least one check identifier is an odd number.

10. A data processing method, characterized in that: Applied to Flexible Ethernet FlexE, the method comprises: Acquire a first data stream, where the first data stream is one of the multiple data streams obtained by deinterleaving, and the first data stream includes a periodically appearing filling sequence, where the filling sequence includes n consecutive filling code blocks, where n is an integer greater than or equal to 4; Searching for a filling code block in the first data stream to find the filling sequence; The filling sequence is determined to be found when a plurality of filling code blocks found continuously in the first data stream meet a preset condition, wherein the preset condition includes: the number of the plurality of filling code blocks is greater than a preset threshold and the number of the plurality of filling code blocks is less than or equal to n.

11. A data processing method, characterized in that: Applied to Flexible Ethernet FlexE, the method comprises: Acquire a first data stream, where the first data stream is obtained by periodically inserting a padding sequence into an initial data stream, where the initial data stream is obtained by interleaving multiple data streams sent by multiple FlexE instances, where the first data stream includes the padding sequence that appears periodically, where the padding sequence includes n consecutive padding code blocks, where n is an integer greater than or equal to 16; Searching for a filling code block in the first data stream to find the filling sequence; The filling sequence is determined to be found when a plurality of filling code blocks found continuously in the first data stream meet a preset condition, wherein the preset condition includes: the number of the plurality of filling code blocks is greater than a preset threshold and the number of the plurality of filling code blocks is less than or equal to n.

12. The method according to claim 10 or 11, characterized in that: The n filling code blocks include x first filling code blocks and y second filling code blocks, the first filling code block is a globally unique control code block in the first data stream, the second filling code block is an error code block, x is a positive integer, and y is a positive integer.

13. The method according to claim 12, characterized in that The x first filling code blocks and the y second filling code blocks satisfy any one of the following conditions: x=1, y=n-1, the y second filling code blocks are located after the first filling code block, and the y second filling code blocks are continuous with the first filling code block; or, The n is an even number, x=y=n / 2, the y second filling code blocks are located after the x first filling code blocks, and the y second filling code blocks are continuous with the x first filling code blocks; or, n is an even number, x=y=n / 2, the filling sequence includes n / 2 code block groups, each code block group includes one first filling code block and one second filling code block, in each code block group, the second filling code block is located after the first filling code block and is continuous with the first filling code block, and the filling code blocks in the n / 2 code block groups are continuous; or The x first filling code blocks include x1 first filling code blocks and x2 first filling code blocks, the y second filling code blocks are located between the x1 first filling code blocks and the x2 first filling code blocks, the x1 first filling code blocks, the y second filling code blocks and the x2 first filling code blocks are continuous, x1+x2=x, and the x1 and x2 are both positive integers.

14. The method according to claim 12, characterized in that The n padding code blocks further include z third padding code blocks, where z is a positive integer; The y second filling code blocks are located after the x first filling code blocks and before the z third filling code blocks, and the x first filling code blocks, the y second filling code blocks and the z third filling code blocks are continuous; or, The z third filling code blocks are located after the x first filling code blocks and before the y second filling code blocks, and the x first filling code blocks, the z third filling code blocks and the y second filling code blocks are continuous.

15. The method according to claim 14, characterized in that The third filling code block is a data code block.

16. The method according to claim 14 or 15, characterized in that The third filling code block includes at least one code block identifier.

17. The method according to claim 16, characterized in that The third filling code block further includes at least one verification mark, and the at least one verification mark is used to verify the correctness of the at least one code block mark.

18. The method according to claim 17, characterized in that The number of the at least one code block identifier is equal to the number of the at least one check identifier; or, The sum of the number of the at least one code block identifier and the number of the at least one check identifier is an odd number.

19. The method according to any one of claims 10 to 18, characterized in that The n filling code blocks include x first filling code blocks, the first filling code block is a globally unique control code block in the first data stream, and x is a positive integer. The step of searching for a filling code block in the first data stream to find the filling sequence comprises: searching for the first filler code block in the first data stream; The filling sequence is searched for in the first data stream based on the first filling code block found in the first data stream.

20. The method according to claim 19, characterized in that The searching for the filling sequence in the first data stream based on the first filling code block found in the first data stream comprises: Determine n-1 code blocks after the first first filling code block found in the first data stream, wherein the n-1 code blocks are continuous and the n-1 code blocks are continuous with the first first filling code block; The n-1 code blocks are detected to find a filling code block in the n-1 code blocks, wherein the multiple filling code blocks found continuously in the first data stream include the first first filling code block and the filling code block found in the n-1 code blocks.

21. A data processing device, characterized in that: Applied to Flexible Ethernet FlexE, the device comprises: A transceiver unit, configured to perform the transceiver operation in the method according to any one of claims 1 to 9; A processing unit, configured to perform operations other than the sending and receiving operations in the method according to any one of claims 1 to 9.

22. A data processing device, characterized in that: Applied to Flexible Ethernet FlexE, the device comprises: A transceiver unit, configured to perform the transceiver operation in the method according to any one of claims 10 to 20; A processing unit, configured to perform operations other than the sending and receiving operations in the method according to any one of claims 10 to 20.

23. A data processing device, characterized in that: including memory and processor; The memory is used to store computer programs; The processor is configured to execute the computer program stored in the memory so as to enable the data processing device to perform the method according to any one of claims 1 to 20.

24. A communication system, characterized in that: It comprises a sending end and a receiving end, the sending end comprises the data processing device as claimed in claim 21 or 23, and the receiving end comprises the data processing device as claimed in claim 22 or 23.

25. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed, the method according to any one of claims 1 to 20 is implemented.

26. A computer program product, characterized in that The computer program product comprises a program or a code, and when the program or the code is executed, the method according to any one of claims 1 to 20 is implemented.

27. A chip, characterized in that: The chip implements the method according to any one of claims 1 to 20 when running.

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