Multiplication circuit, arithmetic circuit, and electronic apparatus

Abstract

Provided is a multiplication circuit with reduced power consumption. The multiplication circuit has a first cell and a second cell. Each of the first cell and the second cell has a function for serving as a current source circuit. The first cell has a function that generates a first current corresponding to the gate-source voltage of a first transistor, and the second cell has a function that generates a reference current corresponding to the gate-source voltage of a second transistor. The multiplication circuit has a function for amplifying the first current to a third current in accordance with the ratio between the reference current and a second current, such amplification performed by changing the reference current of the second cell to the second current. In order to hold the gate-source voltage of each of the first transistor and the second transistor, each of the first cell and the second cell includes a switch unit. Each switch unit includes: transistors in series; and a capacitive element connected between the transistors.

Description

Multiplication circuit, arithmetic circuit and electronic device

[0001] One embodiment of the present invention relates to a multiplier circuit, an arithmetic circuit, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, an operating method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices (including liquid crystal display devices), light-emitting devices, power storage devices, imaging devices, memory devices, processing devices, signal processing devices, sensors, arithmetic devices (including processors), electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof.

[0003] Currently, the development of integrated circuits that mimic the workings of the human brain is actively progressing. Such integrated circuits incorporate the workings of the brain as electronic circuits, and have circuits that mimic the "neurons" and "synapses" of the human brain. For this reason, such integrated circuits are sometimes called "neuromorphic," "brainmorphic," or "brain-inspired." Such integrated circuits have a non-von Neumann architecture, and are expected to be able to perform parallel processing with extremely low power consumption compared to von Neumann architectures, which consume more power as processing speed increases.

[0004] An information processing model that mimics a neural network having "neurons" and "synapses" is called an artificial neural network (ANN, which may be simply referred to as a neural network in this specification). For example, Non-Patent Documents 1 and 2 disclose a computing device that configures an artificial neural network using an SRAM (Static Random Access Memory).

[0005] There are also attempts to use a computing device that configures an artificial neural network, for example, to correct an image displayed on a display device. For example, Patent Document 1 discloses a display device that uses a computing circuit that configures an artificial neural network to adjust the brightness, color tone, etc. of a displayed image to suit the preferences of the viewer.

[0006] JP 2018-36639 A

[0007] M. Kang et al. , “IEEE Journal Of Solid-State Circuits”, 2018, Volume 53, No. 2, p. 642-655. J. Zhang et al. , “IEEE Journal Of Solid-State Circuits”, 2017, Volume 52, No. 4, p. 915-924.

[0008] The arithmetic circuits that make up an artificial neural network mainly include circuits that enable product-sum operations. In particular, multilayered artificial neural networks, such as multilayer perceptrons, require many multipliers and adders because they frequently perform product-sum operations between weight coefficients and input data for neurons. Furthermore, in general computers, the results of operations performed by multipliers or adders are written to a memory device and then read out for the next operation. Therefore, memory accesses are frequent during operations in artificial neural networks. Therefore, it is preferable that the product-sum operation circuits be provided with in-memory storage circuits for storing input data, such as multipliers and multiplicands, or operation results.

[0009] One example of such a memory circuit is an SRAM, which has a fast access speed, but is a volatile memory and therefore consumes a lot of power to retain data. Another example of such a memory circuit is a gain cell-type memory circuit, but because data is retained by a switching element and a capacitive element, the data retention time depends on the characteristics of the switching element. For example, the larger the off-current of the switching element, the faster the data degradation due to charge leakage. On the other hand, by reducing the off-current of the switching element, the data degradation can be suppressed. For this reason, it is considered preferable for an in-memory multiply-accumulate circuit to include a memory circuit that consumes low power and can retain data for a long time.

[0010] An object of one embodiment of the present invention is to provide a multiplication circuit with reduced power consumption.An object of one embodiment of the present invention is to provide a multiplication circuit with a small circuit area.An object of one embodiment of the present invention is to provide a multiplication circuit that can retain data for a long period of time.An object of one embodiment of the present invention is to provide a novel multiplication circuit.An object of one embodiment of the present invention is to provide an arithmetic circuit including the above-described multiplication circuit.An object of one embodiment of the present invention is to provide an electronic device including the above-described arithmetic circuit.

[0011] Note that the problem of one embodiment of the present invention is not limited to the above problem. The above problem does not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the above problem and other problems, and does not necessarily solve all of the above problem and other problems.

[0012] (1) One aspect of the present invention is a multiplication circuit including a first cell and a second cell. The first cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitance element, and a second capacitance element. The second cell includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a third capacitance element, and a fourth capacitance element.

[0013] One of the source and drain of the first transistor is electrically connected to one of the source and drain of the second transistor and the first terminal of the first capacitor. The other of the source and drain of the second transistor is electrically connected to the gate of the third transistor and the first terminal of the second capacitor. One of the source and drain of the third transistor is electrically connected to one of the source and drain of the fourth transistor. One of the source and drain of the fifth transistor is electrically connected to one of the source and drain of the sixth transistor and the first terminal of the third capacitor. The other of the source and drain of the sixth transistor is electrically connected to the gate of the seventh transistor and the first terminal of the fourth capacitor. One of the source and drain of the seventh transistor is electrically connected to one of the source and drain of the eighth transistor. The other of the source and drain of the first transistor and the other of the source and drain of the fourth transistor are each electrically connected to a first wiring. The other of the source and drain of the fifth transistor, the other of the source and drain of the eighth transistor, the second terminal of the first capacitance element, the second terminal of the second capacitance element, the second terminal of the third capacitance element, and the second terminal of the fourth capacitance element are electrically connected to the second wiring. The gates of the first transistor, the second transistor, the fifth transistor, and the sixth transistor are electrically connected to the third wiring.

[0014] (2) Another aspect of the present invention is a multiplication circuit different from the multiplication circuit described above in (1), including a first cell and a second cell. The first cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitance element, and a second capacitance element. The second cell includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a third capacitance element, and a fourth capacitance element.

[0015] One of the source and drain of the first transistor is electrically connected to one of the source and drain of the second transistor and the first terminal of the first capacitor. The other of the source and drain of the second transistor is electrically connected to the gate of the third transistor and the first terminal of the second capacitor. One of the source and drain of the third transistor is electrically connected to one of the source and drain of the fourth transistor. One of the source and drain of the fifth transistor is electrically connected to one of the source and drain of the sixth transistor and the first terminal of the third capacitor. The other of the source and drain of the sixth transistor is electrically connected to the gate of the seventh transistor and the first terminal of the fourth capacitor. One of the source and drain of the seventh transistor is electrically connected to one of the source and drain of the eighth transistor. The other of the source and drain of the first transistor and the other of the source and drain of the fourth transistor are each electrically connected to a first wiring. The other of the source and drain of the fifth transistor, the other of the source and drain of the eighth transistor, the second terminal of the first capacitance element, the second terminal of the second capacitance element, the second terminal of the third capacitance element, and the second terminal of the fourth capacitance element are electrically connected to the second wiring. The gate of the first transistor and the gate of the fifth transistor are electrically connected to the third wiring. The gate of the second transistor and the gate of the sixth transistor are electrically connected to the fourth wiring.

[0016] (3) Alternatively, according to one aspect of the present invention, in the above (1) or (2), the capacitance value of the second capacitance element may be larger than the capacitance value of the first capacitance element, and the capacitance value of the fourth capacitance element may be larger than the capacitance value of the third capacitance element.

[0017] (4) Alternatively, in one embodiment of the present invention, in the above-described (3), each of the first to eighth transistors may contain an oxide semiconductor in a channel formation region.

[0018] The oxide semiconductor preferably contains one or more elements selected from indium, zinc, and an element M. The element M is one or more elements selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony.

[0019] (5) Alternatively, in one aspect of the present invention, in the circuit of (4), the second cell may have a function of maintaining a potential of the gate of the seventh transistor so that a reference current flows between the source and drain of the seventh transistor, and the first cell may have a function of maintaining a potential of the gate of the third transistor so that a first current flows between the source and drain of the third transistor. In particular, it is preferable that the first cell has a function of amplifying the first current flowing between the source and drain of the third transistor to a third current in accordance with a ratio between the reference current and the second current by changing the potential of the gate of the seventh transistor through capacitive coupling by the fourth capacitive element, thereby changing the reference current flowing between the source and drain of the seventh transistor to a second current.

[0020] (6) Another aspect of the present invention is an arithmetic circuit including a plurality of multiplication circuits according to (5), a first circuit, a second circuit, and a third circuit, wherein each of the plurality of multiplication circuits is electrically connected to the same first wiring and each of the plurality of multiplication circuits is electrically connected to a different second wiring.

[0021] The first circuit has a function of generating a first current according to first data and inputting the first current to one selected from the plurality of multiplication circuits via a first wiring. The second circuit has a function of generating a second current according to second data and inputting the second current to a multiplication circuit electrically connected to one of the plurality of second wirings. The third circuit has a function of calculating a nonlinear function using, as an input value, the sum of third currents flowing through the first wiring in each of the plurality of multiplication circuits, and outputting the result.

[0022] (7) Another embodiment of the present invention is an electronic device including the arithmetic circuit and a housing described in (6).

[0023] (8) Another aspect of the present invention is a multiplication circuit different from the above-described (1) and (2), including a first cell and a second cell. The first cell includes K (K is an integer of 3 or greater) first transistors, second transistors, and third transistors, and K-1 first and second capacitive elements. The second cell includes L (L is an integer of 3 or greater) fourth transistors, fifth transistors, and sixth transistors, and L-1 third and fourth capacitive elements.

[0024] The K first transistors are electrically connected in series, and each of the connection points between two successive first transistors in the K first transistors is electrically connected to a first terminal of a first capacitance element.

[0025] One of the two ends of the K first transistors electrically connected in series is electrically connected to the gate of the second transistor and the first terminal of the second capacitance element. One of the source and drain of the second transistor is electrically connected to one of the source and drain of the third transistor. L fourth transistors are electrically connected in series. In the L fourth transistors electrically connected in series, each of the connection points between two consecutive fourth transistors is electrically connected to a first terminal of the third capacitance element. One of the two ends of the L fourth transistors electrically connected in series is electrically connected to the gate of the fifth transistor and the first terminal of the fourth capacitance element. One of the source and drain of the fifth transistor is electrically connected to one of the source and drain of the sixth transistor. The other of the two ends of the K first transistors electrically connected in series and the other of the source and drain of the third transistor are electrically connected to a first wiring. The other of the two ends of the L fourth transistors electrically connected in series, the other of the source and drain of the eighth transistor, each of the second terminals of the K-1 first capacitance elements, the second terminal of the second capacitance element, each of the second terminals of the L-1 third capacitance elements, and the second terminal of the fourth capacitance element are electrically connected to a second wiring. The gates of the K first transistors and the gates of the L fourth transistors are electrically connected to a third wiring.

[0026] (9) Alternatively, in one embodiment of the present invention, in the above-described (8), each of the first to sixth transistors may contain an oxide semiconductor in a channel formation region.

[0027] The oxide semiconductor preferably contains one or more elements selected from indium, zinc, and an element M. The element M is one or more elements selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony.

[0028] (10) Alternatively, in one aspect of the present invention, in the circuit of (9), the second cell may have a function of maintaining a potential of the gate of the fifth transistor so that a reference current flows between the source and drain of the fifth transistor, and the first cell may have a function of maintaining a potential of the gate of the second transistor so that a first current flows between the source and drain of the second transistor. In particular, it is preferable that the first cell has a function of amplifying the first current flowing between the source and drain of the second transistor to a third current in accordance with a ratio between the reference current and the second current by changing the potential of the gate of the fifth transistor through capacitive coupling by a fourth capacitive element, thereby changing the reference current flowing between the source and drain of the fifth transistor to a second current.

[0029] (11) Another embodiment of the present invention is an arithmetic circuit including a plurality of multiplier circuits according to (10), a first circuit, a second circuit, and a third circuit, wherein each of the plurality of multiplier circuits is electrically connected to the same first wiring, and each of the plurality of multiplier circuits is electrically connected to a plurality of different second wirings.

[0030] The first circuit has a function of generating a first current according to first data and inputting the first current to one selected from the plurality of multiplication circuits via a first wiring. The second circuit has a function of generating a second current according to second data and inputting the second current to a multiplication circuit electrically connected to one of the plurality of second wirings. The third circuit has a function of calculating a nonlinear function using, as an input value, the sum of third currents flowing through the first wiring in each of the plurality of multiplication circuits, and outputting the result.

[0031] (12) Another embodiment of the present invention is an electronic device including the arithmetic circuit and a housing described in (11).

[0032] According to one embodiment of the present invention, a multiplication circuit with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a multiplication circuit with a small circuit area can be provided. Alternatively, according to one embodiment of the present invention, a multiplication circuit capable of retaining data for a long period of time can be provided. Alternatively, according to one embodiment of the present invention, a novel multiplication circuit can be provided. Alternatively, according to one embodiment of the present invention, an arithmetic circuit including the above-described multiplication circuit can be provided. Alternatively, according to one embodiment of the present invention, an electronic device including the above-described arithmetic circuit can be provided.

[0033] Note that the effects of one embodiment of the present invention are not limited to the above-described effects. The above-described effects do not preclude the existence of other effects. Furthermore, the other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. Note that one embodiment of the present invention has at least one of the above-described effects and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases.

[0034] 1A and 1B are circuit diagrams showing an example of the configuration of a multiplication circuit. FIG. 2 is a circuit diagram showing an example of the configuration of a multiplication circuit. FIGS. 3A and 3B are circuit diagrams showing an example of the configuration of a multiplication circuit. FIGS. 4A and 4B are circuit diagrams showing an example of the configuration of a multiplication circuit. FIG. 5 is a circuit diagram showing an example of the configuration of an arithmetic circuit. FIGS. 6A to 6C are circuit diagrams illustrating an example of the configuration of a circuit included in an arithmetic circuit. FIGS. 7A to 7D are circuit diagrams illustrating an example of the configuration of a circuit included in an arithmetic circuit. FIGS. 8A to 8C are block diagrams illustrating an example of the configuration of a circuit included in an arithmetic circuit. FIGS. 9A to 9C are diagrams illustrating a neural network. FIGS. 10A and 10B are block diagrams illustrating an example of the configuration of a circuit included in an arithmetic circuit. FIG. 11 is a block diagram illustrating an example of the configuration of an arithmetic device. FIGS. 12A and 12B are block diagrams illustrating an example of the configuration of a circuit included in an arithmetic device. FIGS. 13A and 13B are block diagrams illustrating an example of the configuration of a circuit included in an arithmetic device. FIG. 14A is a block diagram illustrating an example of the configuration of a circuit included in the arithmetic device, and FIGS. 14B and 14C are circuit diagrams illustrating an example of the configuration of a memory cell. FIGS. 15A to 15C are circuit diagrams illustrating an example of the configuration of a circuit included in the arithmetic device. FIG. 16 is a diagram illustrating an example of a convolutional neural network. FIG. 17 is a diagram illustrating an example of convolution processing. FIG. 18 is a diagram illustrating an example of convolution processing. FIG. 19 is a timing chart illustrating an example of the operation of convolution processing in the arithmetic device. FIGS. 20A and 20B are diagrams illustrating an example of pooling processing. FIGS. 21A and 21B are block diagrams illustrating an example of the configuration of a circuit included in the arithmetic device. FIG. 22 is a schematic perspective view illustrating an example of the configuration of a arithmetic device. FIG. 23 is a block diagram illustrating an example of the configuration of a arithmetic device. FIG. 24 is a block diagram illustrating an example of the configuration of a arithmetic device. FIG. 25 is a schematic cross-sectional view illustrating an example of the configuration of a arithmetic device. FIGS. 26A and 26B are schematic perspective views illustrating an example of the configuration of a transistor. 27A and 27B are schematic perspective views showing an example of the configuration of a transistor, Fig. 28A is a schematic plan view showing an example of the configuration of a transistor, and Figs. 28B to 28D are schematic cross-sectional views showing an example of the configuration of a transistor.29A and 29B are perspective schematic views showing an example of a transistor configuration. FIGS. 30A to 30C are cross-sectional schematic views showing an example of a transistor configuration. FIG. 31A is a plan schematic view showing an example of a transistor configuration, and FIGS. 31B to 31D are cross-sectional schematic views showing an example of a transistor configuration. FIGS. 32A and 32B are perspective schematic views showing an example of a transistor configuration. FIG. 33 is a cross-sectional schematic view showing an example of a computing device configuration. FIG. 34A is a plan schematic view showing an example of a computing device configuration, and FIG. 34B is a plan schematic view showing an example of a computing device configuration. FIG. 35 is a cross-sectional schematic view showing an example of a computing device configuration. FIG. 36 is a perspective schematic view showing an example of a computing device configuration. FIGS. 37A and 37B are diagrams showing various memory devices by layer. FIGS. 38A to 38D are diagrams showing an example of an electronic component. FIGS. 39A and 39B are diagrams showing an example of an electronic device, and FIG. 39C is a diagram showing an example of a mainframe computer. Fig. 40 is a diagram showing an example of space equipment. Fig. 41 is a diagram showing an example of a storage system applicable to a data center. Figs. 42A and 42B are circuit diagrams showing a circuit model used in a simulation described in an example. Fig. 43 is a graph showing the potential retention time, which is the result of a simulation described in an example. Fig. 44 is a circuit diagram showing a circuit model used in a simulation described in an example. Figs. 45A and 45B are graphs showing the potential retention time, which is the result of a simulation described in an example. Figs. 46A1 to 46A7 and 46B1 to 46B6 are circuit diagrams for explaining electrical connections.

[0035] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (for example, a transistor, a diode, and a photodiode), or a device having such a circuit. A semiconductor device also refers to any device that can function by utilizing semiconductor characteristics. An example of a semiconductor device is an integrated circuit. Another example of a semiconductor device is a chip equipped with an integrated circuit, and another example of a semiconductor device is an electronic component in which a chip is housed in a package. For example, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be a semiconductor device or may include a semiconductor device.

[0036] In this specification, "connection" includes, for example, "electrical connection."

[0037] When expressing "electrical connection" to define the connection relationship between circuit elements as a physical entity, "electrical connection" includes, for example, "direct connection" and "indirect connection." "A and B are directly connected" refers to a case where A and B are connected without a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" refers to a case where A and B are connected via one or more circuit elements.

[0038] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, such a circuit can be defined as an entity, and "A and B are indirectly connected." Note that even if there is a time when electrical signal transmission or potential interaction does not occur between A and B, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when a power supply voltage is not supplied to a circuit and the circuit is not operating, the circuit can be defined as an entity, and "A and B are indirectly connected" (however, for example, this is limited to the case where electrical signal transmission or potential interaction occurs between A and B during the operation of the circuit when a power supply voltage is supplied to the circuit and the circuit is operating).

[0039] Specific examples of "indirect connection" are shown below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in FIGS. 46A1 and 46A2. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," it is assumed that, assuming the circuit is operating, there is at least one time when one transistor between A and B is in the on state, conductive state, or state in which current can flow. Note that "A and B are indirectly connected" also includes cases where one transistor between A and B is in the off state or non-conductive state. When "A and B are indirectly connected," if multiple transistors are connected between A and B, it is assumed that, assuming the circuit is operating, each of the multiple transistors between A and B is in the on state, conductive state, or state in which current can flow at least one time. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases in which the multiple transistors between A and B are in an off state or a non-conductive state at the same time or at different times. As another example, as shown in FIG. 46A3, when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply, GND, or the like, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0040] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in FIG. 46A4. Another example of a case where A and B are connected via an insulator is when a gate insulating film of a transistor is interposed between A and B, as shown in FIG. 46A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0041] Another example of a case where it cannot be said that "A and B are indirectly connected" is a case where there is no timing when an electrical signal is exchanged or when potential interaction occurs between A and B. An example of this is when, as shown in Figures 46A6 and 46A7, multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." In addition, in Figure 46A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, etc., the relationship will be the same as in Figures 46A6 and 46A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected," or "B and C are indirectly connected."

[0042] Although an example of "indirect connection" has been given above, as an example, the definition of "indirect connection" is included in the definition of "electrical connection," so if "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0043] Next, specific examples of "direct connection" are shown. Examples of "A and B are directly connected" include cases where A and B are connected without any circuit elements between them, as shown in FIGS. 46B1, 46B2, and 46B3. When A and B are connected to a power supply that supplies a constant potential V or to GND without any circuit elements between them, as shown in FIGS. 46B4 and 46B5, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." It can also be said that "A and B are directly connected," even when A (or B) is connected to a constant potential V via the source and drain of a transistor, as shown in FIG. 46B6. Because A and V or B and V are connected via the source and drain of a transistor, they cannot be said to be directly connected, but rather that "A and V are indirectly connected" or "B and V are indirectly connected."

[0044] Although an example of "direct connection" has been given above, as an example, the definition of "direct connection" is included in the definition of "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0045] In addition, in this specification, the expression "multiple circuit elements connected in series" includes the case where multiple circuit elements are connected in series by connecting the terminals of two adjacent circuit elements. This connection also includes "electrical connection."

[0046] For example, the phrase "K (here, K is an integer of 2 or more) resistive elements are connected in series" includes a case where one terminal of a first resistive element is connected to one terminal of a second resistive element, the other terminal of a k (here, k is an integer of 2 or more and K-1 or less) resistive element is connected to one terminal of a k+1th resistive element, and the other terminal of a K-1th resistive element is connected to one terminal of a Kth resistive element. Furthermore, the phrase "K (here, K is an integer of 2 or more and K-1 or less) transistors are connected in series" includes a case where one of the source or drain of a first transistor is connected to one of the source or drain of a second transistor, the other of the source or drain of a k (here, k is an integer of 2 or more and K-1 or less) transistor is connected to one of the source or drain of a k+1th transistor, and the other of the source or drain of a K-1th transistor is connected to one of the source or drain of a Kth transistor.

[0047] Note that even when independent components are shown as being connected to each other in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both a wiring and an electrode. Therefore, in this specification, the term "connection" also includes such cases where one conductive film has the functions of multiple components.

[0048] Furthermore, in this specification, a "resistance element" can be, for example, a circuit element having a resistance value higher than 0Ω, or a wiring having a resistance value higher than 0Ω. Therefore, in this specification, a "resistance element" includes a wiring having a resistance value, a transistor in which a current flows between a source and a drain, a diode, or a coil. Therefore, the term "resistance element" can sometimes be replaced with the terms "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" can sometimes be replaced with the term "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value can be, for example, 1 Ω or more and 1×10 ９ It may be set to Ω or less.

[0049] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a wiring region having a capacitance value higher than 0 F, a parasitic capacitance, or a gate capacitance of a transistor. The terms "capacitive element," "parasitic capacitance," and "gate capacitance" can sometimes be replaced with the term "capacitance." Conversely, the term "capacitance" can sometimes be replaced with the terms "capacitive element," "parasitic capacitance," and "gate capacitance." A "capacitive element" (including a "capacitive element" with three or more terminals) includes an insulator and a pair of conductors sandwiching the insulator. Therefore, the term "pair of conductors" in "capacitance" can be replaced with "pair of electrodes," "pair of conductive regions," "pair of regions," or "pair of terminals." The terms "one of the pair of terminals" and "the other of the pair of terminals" may be referred to as a first terminal and a second terminal, respectively. The capacitance value can be, for example, 0.05 fF to 10 pF. It may also be, for example, 1 pF to 10 μF.

[0050] In this specification, a switch refers to a device that can be turned on or off and has the function of controlling whether or not a current flows, or a device that has the function of selecting and switching a path through which a current flows.

[0051] In this specification, a "conductive state" refers to a state in which a current can flow between two input / output terminals, and a "non-conductive state" refers to a state in which the two input / output terminals are considered to be electrically disconnected. In this specification, the on state of a switch falls under the category of a "conductive state," and the off state of a switch falls under the category of a "non-conductive state." Therefore, in this specification, the "conductive state" and the "on state" of a switch are interchangeable, and the "non-conductive state" and the "off state" are interchangeable.

[0052] Furthermore, the switch may have two or more terminals for passing current in addition to the control terminal. For example, an electrical switch, a mechanical switch, or the like may be used. In other words, the switch is not limited to a specific type as long as it has the function of controlling current.

[0053] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits combining these. When a transistor is used as a switch, the "conductive state" or "on state" of the transistor refers to a state in which a current can flow between the source electrode and the drain electrode of the transistor. The "non-conductive state" or "off state" of the transistor refers to a state in which the source electrode and the drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0054] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls the conductive and non-conductive states.

[0055] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls switching between a conductive state and a non-conductive state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms "source" and "drain" may be interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source and the drain" and "the other of the source and the drain" are used. In this specification, one of the source and the drain may be referred to as a "first electrode of the transistor" or a "first terminal of the transistor," and the other of the source and the drain may be referred to as a "second electrode of the transistor" or a "second terminal of the transistor." Note that, depending on the structure of a transistor, a backgate may be provided in addition to the three terminals described above. In this case, in this specification, one of the gate or back gate of the transistor may be referred to as a first gate, and the other of the gate or back gate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, when a transistor has three or more gates, in this specification, the respective gates may be referred to as a first gate, a second gate, a third gate, etc.

[0056] For example, in this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used as an example of a transistor. With a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the breakdown voltage (reliability) of the transistor. Alternatively, when operating in the saturation region, the multi-gate structure can provide voltage-current characteristics with a flat slope, such that the current between the drain and source does not change significantly even when the voltage between the drain and source changes. By utilizing voltage-current characteristics with a flat slope, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0057] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a circuit diagram shows one resistor, this includes two or more resistors connected in series. For example, when a circuit diagram shows one capacitance element, this includes two or more capacitance elements connected in parallel. For example, when a circuit diagram shows one transistor, this includes two or more transistors connected in series, with the gates of the transistors connected to each other. Similarly, when a circuit diagram shows one switch, this includes two or more transistors connected in series or in parallel, with the gates of the transistors connected to each other.

[0058] Furthermore, in this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration and device structure. Furthermore, a terminal, a wiring, etc. can be referred to as a node.

[0059] Furthermore, in this specification and the like, a selector may refer to, for example, a circuit having multiple input terminals and one output terminal, selecting one of the multiple input terminals, and establishing a conductive state between the selected input terminal and the one output terminal. In other words, a selector may refer to a circuit that selects one of the input signals input to each of the multiple input terminals and outputs the selected input signal to the output terminal. Alternatively, a selector may refer to, for example, a circuit having multiple output terminals and one input terminal, selecting one of the multiple output terminals, and establishing a conductive state between the selected output terminal and the one input terminal. In other words, a selector may refer to a circuit that selects one of the multiple output terminals and outputs an input signal input to the input terminal to the selected output terminal. In other words, a selector may refer to a multiplexer or a demultiplexer. In particular, when inputting or outputting an analog potential or an analog current, a selector may refer to an analog multiplexer or an analog demultiplexer.

[0060] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0061] Furthermore, in this specification and the like, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials applied to both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials applied to both wirings do not have to be equal to each other.

[0062] Furthermore, "current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. Examples of carriers here include electrons, holes, anions, cations, and complex ions, and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, and vacuum). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification, unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), the statement "current flows from element A to element B" can be rephrased as "current flows from element B to element A." Furthermore, the statement "current is input to element A" can be rephrased as "current is output from element A."

[0063] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0064] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing by 180 degrees.

[0065] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B above insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B below insulating layer A" does not require that electrode B be formed in direct contact below insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0066] Furthermore, in this specification, terms such as "row" and "column" may be used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and may be rephrased appropriately depending on the situation. For example, the expression "row direction" may be rephrased as "column direction" by rotating the orientation of the drawing by 90 degrees.

[0067] Furthermore, in this specification and the like, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to the term "insulating layer." Or, in some cases or depending on the situation, the terms "film" and "layer" may not be used and may be replaced with other terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor." Or, for example, the term "insulating layer" or "insulating film" may be changed to the term "insulator."

[0068] Furthermore, in this specification and the like, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, terms such as "electrode" or "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where one or more selected from "electrode," "wiring," and "terminal" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, the terms "electrode," "wiring," and "terminal" may be replaced with the term "region" in some cases.

[0069] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" or "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, a term such as "signal line" may be changed to the term "power line." Furthermore, a term such as "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, a term such as "signal" may be changed to the term "potential."

[0070] In addition, timing charts may be used in this specification and the like to explain an operation method of a semiconductor device. The timing charts used in this specification and the like illustrate ideal operation examples, and the periods, magnitudes, and timings of signals (e.g., potentials or currents) described in the timing charts are not limited unless otherwise specified. The magnitudes and timings of signals (e.g., potentials or currents) input to each wiring (including nodes) in the timing charts described in this specification and the like can be changed depending on the situation. For example, even if two periods are shown at equal intervals in a timing chart, the lengths of the two periods may be different. For example, even if one period is shown as long and the other period is shown as short, the lengths of the two periods may be equal, or one period may be short and the other period may be long.

[0071] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is contained in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be referred to as a transistor including a metal oxide or an oxide semiconductor.

[0072] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0073] In this specification and the like, the term "impurities" in a semiconductor refers to, for example, elements other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities may cause one or more of the following: an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.

[0074] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0075] In this specification and the like, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.

[0076] In addition, the content (part or all of the content) described in one embodiment can be applied, combined, or replaced with at least one of another content (part or all) described in that embodiment and another content (part or all) described in one or more other embodiments.

[0077] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0078] Furthermore, a figure (part or all) described in one embodiment can be combined with another part of that figure, another figure (part or all) described in that embodiment, and at least one figure (part or all) described in one or more other embodiments to form even more figures.

[0079] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0080] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m, n]" may be added to the reference numeral. Also, when an identification symbol such as "_1", "[n]", "[m, n]" is added to the reference numeral in the drawings, etc., the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0081] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0082] Embodiment 1 In this embodiment, a multiplier circuit, which is a semiconductor device of one embodiment of the present invention, will be described.

[0083] <Conventional Multiplication Circuit> First, a multiplication circuit with a conventional structure will be described.

[0084] 2 is a circuit configuration of a multiplication circuit MP including a multiplication cell IM and a driver cell IMD. The multiplication cell IM includes transistors F1, F2, and F5, and a capacitance element C5, and the driver cell IMD includes transistors F1D, F2D, and F5D, and a capacitance element C5D.

[0085] In the multiplication cell IM, the first terminal of transistor F1 is connected to the gate of transistor F2 and the first terminal of capacitor C5, and the gate of transistor F1 is connected to wiring WSL. The first terminal of transistor F2 is connected to wiring VE0, and the second terminal of transistor F2 is connected to the first terminal of transistor F5. The second terminal of capacitor C5 is connected to wiring XCL. The second terminal of transistor F1 and the second terminal of transistor F5 are connected to wiring WCL. The gate of transistor F5 is connected to wiring VE1.

[0086] In the driving cell IMD, the first terminal of the transistor F1D is connected to the gate of the transistor F2D and the first terminal of the capacitance element C5D, and the gate of the transistor F1D is connected to the wiring WSL. The first terminal of the transistor F2D is connected to the wiring VE0, and the second terminal of the transistor F2D is connected to the first terminal of the transistor F5D. The second terminal of the capacitance element C5D is connected to the wiring XCL. The second terminal of the transistor F1 and the second terminal of the transistor F5 are connected to the wiring XCL. The gate of the transistor F5 is connected to the wiring VE1.

[0087] In addition, in Figure 2, the connection point between the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitance element C5 is described as node N, and the connection point between the first terminal of transistor F1D, the gate of transistor F2D, and the first terminal of capacitance element C5D is described as node ND.

[0088] In particular, the transistors F1 and F1D function as switching transistors. The transistor F1 may be referred to as a write transistor in the multiplication cell IM, and the transistor F1D may be referred to as a write transistor in the driver cell IMD. The transistors F2 and F2D operate in the subthreshold region.

[0089] Furthermore, the transistor F5 functions as a clamp transistor (sometimes referred to as a clamp FET) for preventing drain-induced barrier lowering (DIBL) in the transistor F2. Similarly, the transistor F5D functions as a clamp transistor for preventing DIBL in the transistor F2D. Therefore, a fixed potential within a range in which the transistors F5 and F5D function as clamp transistors is input to the gates of the transistors F5 and F5D, respectively. In other words, the wiring VE1 functions as a wiring for applying the fixed potential.

[0090] The multiplication cell IM functions as a current generating circuit that generates a subthreshold current. For example, the fixed potential applied by the wiring VE0 is set to the ground potential (GND). After applying a high-level potential to the wiring WSL to turn on the transistor F1, a subthreshold current is passed through the wiring WCL, and the subthreshold current then flows through the transistors F5 and F2 to the wiring VE0. Since the transistor F1 is on, the gate-source voltage of the transistor F2 becomes a voltage corresponding to the amount I of the subthreshold current. Specifically, since the source potential of the transistor F2 is set to the ground potential, the gate potential is uniquely determined so that the amount of the source-drain current of the transistor F2 becomes the amount I of the subthreshold current. Thereafter, by applying a low-level potential to the wiring WSL and turning off the transistor F1, the gate potential of the transistor F2 is held at the first terminal of the capacitance element C5, and the gate-source voltage of the transistor F2 is fixed, so that the multiplication cell IM becomes a current generating circuit that generates a subthreshold current of an amount I flowing from the wiring WCL to the wiring VE0. Note that in this specification, such an operation is referred to as "setting (programming) the amount of current flowing between the source and drain of the transistor F2 of the multiplication cell IM to I" or the like.

[0091] Similarly to the multiplication cell IM, the driver cell IMD also functions as a current generating circuit that generates a subthreshold current. For example, the fixed potential applied by the wiring VE0 is set to the ground potential (GND). After applying a high-level potential to the wiring WSL to turn on the transistor F1D, a subthreshold current is passed through the wiring XCL, and the subthreshold current then flows through the transistors F5D and F2D to the wiring VE0. Since the transistor F1D is turned on, the gate-source voltage of the transistor F2D becomes a voltage corresponding to the amount I of the subthreshold current. Specifically, since the source potential of the transistor F2D is set to the ground potential, the gate potential is uniquely determined so that the source-drain current of the transistor F2D becomes the amount I of the subthreshold current. Thereafter, by applying a low-level potential to the wiring WSL and turning off the transistor F1D, the gate potential of the transistor F2D is held at the first terminal of the capacitance element C5D and the gate-source voltage of the transistor F2D is fixed, so that the amount of current flowing between the source and drain of the transistor F2D is set to I in the driver cell IMD, and the driver cell IMD becomes a current generating circuit that flows a subthreshold current of the amount I. At this time, the potentials of the node ND and the wiring XCL become approximately equal.

[0092] Here, the operation of multiplying w and x (where w and x are positive numbers including 0) in the multiplication circuit MP shown in FIG. 2 will be described. First, I is set as the amount of subthreshold current in the transistor F2D of the driving cell IMD. ｒｅｆ０ Then, the amount of subthreshold current in the transistor F2 of the multiplication cell IM is set to wI ｒｅｆ０ Let us consider the case where I ｒｅｆ０ is the amount of reference current that flows when the transistor F2 and the transistor F2D operate in the subthreshold region. ｒｅｆ０ xI ｒｅｆ０As the potential of the wiring XCL increases or decreases, the potential of the wiring XCL also fluctuates, and the potential of the node N also fluctuates due to the capacitive coupling of the capacitive element C5 of the multiplier cell IM. At this time, the gate-source voltage of the transistor F2 of the multiplier cell IM also fluctuates, and the current flowing between the source and drain of the transistor F2 is expressed as w×I ｒｅｆ０ That is, the multiplication cell IM passes a current proportional to the product of w and x from the wiring WCL to the wiring VE0. This allows the multiplication circuit MP shown in FIG. 2 to perform the multiplication of w and x.

[0093] In the multiplication cell IM, a potential corresponding to the amount of subthreshold current flowing between the source and drain of transistor F2 is maintained at the first terminal (node ​​N) of capacitance element C5. If the amount of leakage current of transistor F1 increases when transistor F1 is off, the potential of the first terminal (node ​​N) of capacitance element C5 fluctuates, which changes the amount of subthreshold current flowing between the source and drain of transistor F2, potentially affecting the multiplication result. Furthermore, the leakage current flows through wiring WCL or wiring VE0, which may also affect the multiplication result.

[0094] Similarly, in the driver cell IMD, a potential corresponding to the amount of subthreshold current flowing between the source and drain of the transistor F2D is held at the first terminal (node ​​N) of the capacitance element C5D. If the amount of leakage current of the transistor F1D increases when the transistor F1D is in the off state, the potential of the first terminal (node ​​N) of the capacitance element C5D fluctuates, which in turn changes the potential of the line XCL, which may affect the result of the multiplication in the multiplication cell IM.

[0095] <Multiplier Circuit of the Present Invention> A semiconductor device of one embodiment of the present invention is a multiplier circuit developed in consideration of the above-described problems, and can prevent fluctuations in the potentials of the nodes N and ND due to leakage of electric charge.

[0096] The multiplication circuit MPA shown in Figure 1A is a semiconductor device according to one embodiment of the present invention, and is a circuit obtained by modifying the configuration of the multiplication circuit shown in Figure 2. The multiplication circuit MPA in Figure 1 differs from the multiplication circuit MP in Figure 2 in that a switch unit SF1 is provided in the multiplication cell IM and a switch unit SF1D is provided in the driver cell IMD. Note that the multiplication cell IM in Figure 1A can be said to have a configuration in which the transistor F1 of the multiplication cell IM in Figure 2 is replaced with the switch unit SF1, and the driver cell IMD in Figure 1A can be said to have a configuration in which the transistor F1D of the driver cell IMD in Figure 2 is replaced with the switch unit SF1D.

[0097] 1A, the switch unit SF1 included in the multiplier cell IM has a capacitance element C4, a transistor F1a, and a transistor F1b. The switch unit SF1D included in the driver cell IMD has a capacitance element C4D, a transistor F1Da, and a transistor F1Db. For this reason, in this specification, the switch unit SF1 may be referred to as the write switch in the multiplier cell IM, and the switch unit SF1D may be referred to as the write switch in the driver cell IMD.

[0098] The first terminal of transistor F1a is connected to the first terminal of transistor F1b and the first terminal of capacitor C4. The gates of transistor F1a and F1b are connected to wiring WSL. The second terminal of transistor F1a is connected to the second terminal of transistor F5 and wiring WCL. The second terminal of transistor F1b is connected to the gate of transistor F2 and the first terminal of capacitor C5. In other words, the second terminal of transistor F1a can be substituted for the second terminal of transistor F1 in FIG. 2, the second terminal of transistor F1b can be substituted for the first terminal of transistor F1 in FIG. 2, and the gates of transistors F1a and F1b can be substituted for the gate of transistor F1 in FIG. 2.

[0099] The second terminal of the capacitance element C4 is connected to the line XCL, similarly to the second terminal of the capacitance element C5.

[0100] The first terminal of transistor F1Da is connected to the first terminal of transistor F1Db and the first terminal of capacitor C4D. The gates of transistor F1Da and transistor F1Db are connected to wiring WSL. The second terminal of transistor F1Da is connected to the second terminal of transistor F5D and wiring XCL. The second terminal of transistor F1Db is connected to the gate of transistor F2D and the first terminal of capacitor C5D. In other words, the second terminal of transistor F1Da can be replaced with the second terminal of transistor F1D in FIG. 2, the second terminal of transistor F1Db can be replaced with the first terminal of transistor F1D in FIG. 2, and the gates of transistor F1Da and transistor F1Db can be replaced with the gate of transistor F1D in FIG. 2.

[0101] The second terminal of the capacitance element C4D is connected to the line XCL, similarly to the second terminal of the capacitance element C5D.

[0102] 1A, the connection point between the first terminal of the transistor F1a, the first terminal of the transistor F1b, and the first terminal of the capacitance element C4 is denoted as a node NS, and the connection point between the first terminal of the transistor F1Da, the first terminal of the transistor F1Db, and the first terminal of the capacitance element C4D is denoted as a node NSD.

[0103] Each of the switch units SF1 and SF1D has a configuration in which two transistors are connected in series, and the gates of these transistors are connected to the same wiring. In other words, the two transistors included in each of the switch units SF1 and SF1D essentially function as one transistor. Furthermore, by connecting the two transistors in series, the channel length of the essentially single transistor can be increased. By increasing the channel length, the off current of the essentially single transistor can be reduced, thereby reducing the leakage current that flows when the switch unit SF1 or SF1D is in the off state.

[0104] As described above, the switch section SF1 also includes the capacitance element C4. In particular, the first terminal of the capacitance element C4 is connected to the first terminal of the transistor F1a and the first terminal of the transistor F1b. Therefore, when the transistors F1a and F1b are both in the on state, the potential of the second terminal of the transistor F1a or the second terminal of the transistor F1b can be written to the first terminal of the capacitance element C4. Furthermore, by transitioning the transistors F1a and F1b from the on state to the off state, the potential can be held at the first terminal of the capacitance element C4.

[0105] For example, by inputting a high-level potential to the gates of the transistors F1a and F1b from the wiring WSL, the transistors F1a and F1b can be turned on, and the potential of the wiring WCL can be written to the first terminal (node ​​N) of the capacitor C5 and the first terminal (node ​​NS) of the capacitor C4. Furthermore, by holding a potential not only at the first terminal of the capacitor C5 but also at the first terminal of the capacitor C4, fluctuations in the potential held at the node N can be prevented, for example, even if the off-current of the transistor F1b increases due to a malfunction. When the off-current of the transistor F1b increases, charge sharing occurs between the first and second terminals of the transistor F1b. However, because the first terminal (node ​​NS) of the capacitor C4 holds substantially the same potential as the first terminal (node ​​N) of the capacitor C5, charge sharing can be minimized, and as a result, fluctuations in the potential of the node N can be reduced.

[0106] Similarly, in the switch section SF1D, the first terminal of the capacitance element C4D is connected to the first terminal of the transistor F1Da and the first terminal of the transistor F1Db, so that when the transistors F1Da and F1Db are both on, the potential of the second terminal of the transistor F1Da or the second terminal of the transistor F1Db can be written to the first terminal of the capacitance element C4D. Furthermore, by transitioning the transistors F1Da and F1Db from the on state to the off state, the potential can be held at the first terminal of the capacitance element C4D.

[0107] Because the switch unit SF1D has the same configuration as the switch unit SF1, the switch unit SF1D can achieve the same effects as the switch unit SF1. In the case of the switch SF1D, by turning on each of the transistors F1Da and F1db, the potential of the wiring XCL can be written to each of the first terminal (node ​​N) of the capacitance element C5 and the first terminal (node ​​NS) of the capacitance element C4. Furthermore, even if the off-current of the transistor F1Db increases due to a malfunction, for example, the first terminal (node ​​NSD) of the capacitance element C4D holds substantially the same potential as the first terminal (node ​​ND) of the capacitance element C5D, so fluctuations in the potential held at the node ND can be prevented.

[0108] In particular, it is preferable to use OS transistors as the transistors F1a and F1b included in the switch portion SF1 and the transistors F1Da and F1Db included in the switch portion SF1D. Examples of metal oxides included in the channel formation regions of the OS transistors include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably includes one or more elements selected from indium, element M, and zinc. The element M is one or more elements selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and antimony. In particular, it is preferable that the element M is one or more elements selected from aluminum, gallium, yttrium, and tin.

[0109] In particular, as the metal oxide used for the semiconductor layer, an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) is preferably used. Alternatively, an oxide containing indium, tin, and zinc (also referred to as ITZO (registered trademark)) is preferably used. Alternatively, an oxide containing indium, gallium, tin, and zinc is preferably used. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as IAZO) is preferably used. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also referred to as IAGZO) is preferably used. Note that an OS transistor will be described in detail in Embodiment 5.

[0110] Furthermore, the metal oxide included in the channel formation region of the OS transistor preferably has a stacked structure of multiple oxide layers with different chemical compositions. For example, consider a two-layer oxide layer structure consisting of a first layer and a second layer located immediately above the first layer. The atomic ratio of the element M to the main metal element in the metal oxide used for the first layer is preferably larger than the atomic ratio of the element M to the main metal element in the metal oxide used for the second layer. Furthermore, the atomic ratio of the element M to In in the metal oxide used for the first layer is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the second layer. This structure can suppress diffusion of impurities and oxygen from structures formed below the first layer into the second layer.

[0111] In the metal oxide used for the second layer, the atomic ratio of In to the element M is preferably larger than that of In to the element M in the metal oxide used for the first layer. With this structure, the OS transistor can have large on-state current and high frequency characteristics.

[0112] Specifically, for example, the metal oxide used in the first layer may have a composition of In:M:Zn = 1:3:2 [atomic ratio] or a composition thereabout, In:M:Zn = 1:3:4 [atomic ratio] or a composition thereabout, or In:M:Zn = 1:1:0.5 [atomic ratio] or a composition thereabout. Furthermore, the metal oxide used in the second layer may have a composition of In:M:Zn = 1:1:1 [atomic ratio] or a composition thereabout, In:M:Zn = 1:1:1.2 [atomic ratio] or a composition thereabout, In:M:Zn = 1:1:2 [atomic ratio] or a composition thereabout, or In:M:Zn = 4:2:3 [atomic ratio] or a composition thereabout. Note that a composition thereabout includes a range of ±30% of the desired atomic ratio.

[0113] Incidentally, in order to reduce the off-state current of a transistor, it is preferable to use, for example, an oxide containing indium (In), gallium (Ga), and zinc (Zn) as the metal oxide used in the semiconductor layer of the transistor. When the semiconductor layer of the transistor contains an oxide containing indium (In), gallium (Ga), and zinc (Zn), the amount of current flowing between the source and drain of the transistor when the gate-source voltage is 0 V is 1×10 per 1 μm of channel width at room temperature (for example, 1° C. or higher and 30° C. or lower). −２０ A or less, 1 x 10 at 85°C −１８ A or less, or 1 x 10 at 125°C −１６ In this specification, the state in which the amount of current flowing between the source and drain when the gate-source voltage of a transistor is 0 V is extremely small is referred to as normally-off.

[0114] In this way, by using OS transistors for the transistors F1a and F1b included in the switch unit SF1, it is possible to reduce the leakage current that flows when the switch unit SF1 is in an off state. Furthermore, even if the off-state current of the transistor F1b increases, the charge held in the first terminal (node ​​NS) of the capacitor C4 can suppress fluctuations in the potential of the first terminal (node ​​N) of the capacitor C5.

[0115] Similarly, by using OS transistors for the transistors F1Da and F1Db included in the switch unit SF1D, it is possible to reduce leakage current that flows when the switch unit SF1D is in an off state. Furthermore, even if the off-state current of the transistor F1Db increases, the charge stored in the first terminal (node ​​NSD) of the capacitor C4D can suppress fluctuations in the potential of the first terminal (node ​​ND) of the capacitor C5D.

[0116] Furthermore, as will be described in detail in the Examples, in the multiplication cell IM, the potential of the first terminal (node ​​N) of the capacitive element C5 is maintained by a switch unit SF1 including transistors F1a, F1b, and capacitive element C4. Therefore, when transistors F1a and F1b are simultaneously turned off, the drop in the potential of node N can be delayed relative to the drop in the potential of node NS. In other words, the potential of node N can be maintained longer than the potential of node NS. From the results of the Examples ( FIGS. 45A and 45B ), it can be said that the greater the capacitance value of capacitive element C4 is compared to the capacitance value of capacitive element C5, the longer the retention time of the potential of node N. Therefore, by making the capacitance value of capacitive element C4 greater than the capacitance value of capacitive element C5, a multiplication cell capable of maintaining the potential of node N for a long period of time can be fabricated. While the above description has been given of the multiplication cell IM, the same effect can also be achieved with the driver cell IMD.

[0117] Furthermore, by reducing the leakage currents of the switch sections SF1 and SF1D, it is possible to reduce the number of refresh operations for the potentials of the nodes N and ND. Furthermore, by reducing the number of refresh operations, it is possible to reduce the power consumption of the multiplication circuit.

[0118] Furthermore, as the temperature of a transistor increases, the characteristics of the transistor tend to deteriorate. However, by using an OS transistor for each of the transistors F1a, F1b, F1Da, and F1Db, as described above, for example, when the temperature of the transistor is 125° C. and the gate-source voltage of the transistor is 0 V, the current flowing between the source and drain can be reduced to 1×10 −１６ A or less. That is, since an OS transistor can be said to have high temperature resistance, the multiplication circuit MPA including an OS transistor can operate stably even at high temperatures.

[0119] The above-described OS transistors can also be used for the transistors F2, F5, F2D, and F5D. By using OS transistors as the transistors included in the multiplication circuit MPA, the transistors F1a, F1b, F2, F5, F1Da, F1Db, F2D, and F5D can be simultaneously manufactured in the same process, thereby reducing the takt time of the multiplication circuit MPA.

[0120] In particular, by using an OS transistor for one or both of the transistors F2 and F2D, the transistors can operate over a wide current range in the subthreshold region, which can lead to a reduction in current consumption and an expansion of the range of values ​​of the multiplication result that can be calculated.

[0121] One or more selected from the transistors F1a, F1b, F2, F5, F1Da, F1Db, F2D, and F5D may be transistors other than OS transistors. For example, a transistor having silicon in a channel formation region (hereinafter referred to as a Si transistor) may be used as a transistor other than an OS transistor. Examples of silicon include single crystal silicon, amorphous silicon, microcrystalline silicon, and polycrystalline silicon (including low temperature polysilicon (LTPS)).

[0122] Examples of transistors other than OS transistors and Si transistors include a transistor including germanium in a channel formation region, a transistor including a compound semiconductor such as zinc selenide, cadmium sulfide, gallium arsenide, indium phosphide, gallium nitride, or silicon germanium in a channel formation region, a transistor including a carbon nanotube in a channel formation region, and a transistor including an organic semiconductor in a channel formation region.

[0123] 1 are n-channel transistors, but may be p-channel transistors in some cases. That is, the polarity of each of the transistors listed above can be selected as either an n-channel or p-channel type. In this specification, the transistors F1a, F1b, F2, F5, F1Da, F1Db, F2D, and F5D are described as n-channel transistors. However, if one or more of the transistors listed above are changed to p-channel transistors, the potential input to the multiplication circuit MPA must be appropriately changed so that the multiplication circuit MPA operates normally.

[0124] The above-described changes in transistor polarity are not limited to transistors F1a, F1b, F2, F5, F1Da, F1Db, F2D, and F5D, but also apply to transistors described elsewhere in the specification or illustrated in other drawings.

[0125] <Modification Example 1 of Multiplication Circuit> The arithmetic circuit of one embodiment of the present invention may be modified to the configuration shown in Fig. 1B instead of the configuration shown in Fig. 1A. The multiplication circuit MPA shown in Fig. 1B is a modification example of the multiplication circuit MPA shown in Fig. 1A, and the wiring WSL includes wirings WSLa and WSLb.

[0126] 1B, the gates of the transistor F1a of the switch section SF1 and the transistor F1Da of the switch section SF1D are connected to a wiring WSLa. The gates of the transistor F1b of the switch section SF1 and the transistor F1Db of the switch section SF1D are connected to a wiring WSLb. In FIG. 1B, the wirings WSLa and WSLb are collectively referred to as wiring WSL.

[0127] By providing the wirings WSLa and WSLb, the operation timing of the set of the transistors F1a and F1Da and the set of the transistors F1b and F1Db can be made different from each other.

[0128] For example, in a room temperature environment where the off-state current is small, by always keeping transistors F1b and F1Db in the on state and using transistors F1a and F1Da as switching transistors that switch between the on state and the off state, switch unit SF1 can maintain the potentials of nodes N and NS, and switch unit SF1D can maintain the potentials of nodes ND and NSD. Note that at this time, switch unit SF1 establishes a conductive state between nodes N and NS, and the capacitance values ​​of capacitive elements C4 and C5 are combined, so the potentials held at nodes N and NS can be maintained for a longer period of time. The same applies to switch unit SF1D.

[0129] Furthermore, for example, in a high temperature environment where the off-state current is large, as described above, the off-state current of the switch SF1 can be reduced by simultaneously switching the transistors F1a and F1b between the on state and the off state in the switch section SF1. The same applies to the switch SF1D.

[0130] <Modification Example 2 of Multiplication Circuit> The arithmetic circuit of one embodiment of the present invention may be modified to the configuration shown in Fig. 3A instead of the configuration shown in Fig. 1A . The multiplication circuit MPA shown in Fig. 3A is a modification of the multiplication circuit MPA shown in Fig. 1A , and has a configuration in which the transistors F1a, F1b, F1Da, and F1Db each have a back gate.

[0131] Specifically, the transistors F1a, F1b, F1Da, and F1Db shown in FIG. 3A are each, for example, a transistor having a structure in which a channel is located between two gates facing each other, and the transistors F1a, F1b, F1Da, and F1Db each have a gate (sometimes referred to as a first gate) and a back gate (sometimes referred to as a second gate). Note that the terms "gate" and "back gate" are interchangeable. Therefore, in this specification, the term "gate" can be interchanged with the term "back gate." Similarly, the term "back gate" can be interchanged with the term "gate." As a specific example, a connection configuration in which "the gate is connected to a first wiring and the back gate is connected to a second wiring" can be replaced with a connection configuration in which "the back gate is connected to the first wiring and the gate is connected to the second wiring."

[0132] In the multiplication circuit MPA of FIG. 3A , the gates and back gates of transistors F1a, F1b, F1Da, and F1Db are connected to each other. That is, the transistors listed above are configured such that the potential input to the gate of a transistor is also input to the back gate of that transistor. By using transistors with their gates and back gates connected in this manner, the on-current of the transistors can be increased and the off-current of the transistors can be reduced. For example, increasing the on-current of a transistor can speed up charge accumulation at node N (node ​​ND), thereby increasing the speed at which a potential can be written to the multiplication cell IM (driver cell IMD). Furthermore, for example, reducing the off-current of a transistor can reduce charge leakage from node N (node ​​ND), thereby lengthening the retention time of the potential in the multiplication cell IM (driver cell IMD).

[0133] The multiplication circuit MPA of Fig. 3A can be modified to have a configuration as shown in Fig. 3B. The multiplication circuit MPA of Fig. 3B differs from the multiplication circuit MPA of Fig. 3A in that the back gates of the transistors F1a, F1b, F1Da, and F1Db are connected to the wiring BGE rather than to the gates of the transistors themselves.

[0134] By connecting wiring BGE to the back gates of transistors F1a, F1b, F1Da, and F1Db, a potential different from the potential provided by wiring WSL can be provided to the back gates of transistors F1a, F1b, F1Da, and F1Db by wiring BGE.

[0135] For example, by connecting an external circuit that outputs a predetermined potential to the wiring BGE, the potential can be applied to the back gates of the transistors F1a, F1b, F1Da, and F1Db. Furthermore, by adjusting the potential, the threshold voltages of the transistors F1a, F1b, F1Da, and F1Db can be varied. Specifically, by outputting a low-level potential, a negative potential, or the like from the external circuit to the wiring BGE, the threshold voltages of the transistors F1a, F1b, F1Da, and F1Db can be increased. Furthermore, the potential applied from the wiring WSL can switch the transistors F1a, F1b, F1Da, and F1Db between an on state and an off state. Alternatively, by outputting a high-level potential, a positive potential, or the like from the external circuit to the wiring BGE, the threshold voltages of the transistors F1a, F1b, F1Da, and F1Db can be lowered, and the potential applied from the wiring WSL can switch the on and off states of the transistors F1a, F1b, F1Da, and F1Db.

[0136] Note that examples of modifying transistors to have a back gate are not limited to transistors F1a, F1b, F1Da, and F1Db. For example, transistors F2, F5, F2D, and F5D shown in FIGS. 1A, 1B, 3A, and 3B may also be modified to have a back gate. Similarly, transistors described elsewhere in the specification or illustrated in other drawings may also be modified to have a back gate. Furthermore, transistors with a back gate described elsewhere in the specification may also be modified to transistors without a back gate.

[0137] <Modification 3 of Multiplication Circuit> Furthermore, the arithmetic circuit of one embodiment of the present invention may be modified to the configuration shown in Fig. 4A instead of the configuration shown in Fig. 1A. In the multiplication circuit MPA shown in Fig. 4A, each of the switch unit SF1 and the switch unit SF1D has k transistors connected in series (where k is an integer greater than or equal to 3) instead of two transistors connected in series. Furthermore, in the switch unit SF1 and the switch unit SF1D of Fig. 4A, a capacitor is provided between the two transistors connected in series. In other words, each of the switch unit SF1 and the switch unit SF1D has k-1 capacitors.

[0138] 4A includes transistors F1[1] to F1[k] and capacitors C4[1] to C4[k-1]. Also, the switch portion SF1D includes transistors F1D[1] to F1D[k] and capacitors C4D[1] to C4D[k-1].

[0139] In the switch unit SF1, the transistors F1[1] to F1[k] are connected in series. A wiring WSL is connected to the gates of the transistors F1[1] to F1[k]. A first terminal of a capacitor C4[p] is connected between two consecutive transistors F1[p] (p is an integer between 1 and k-1) and the transistor F1[p+1]. A wiring XCL is connected to the second terminals of the capacitors C4[1] to C4[k-1].

[0140] Similarly, in the switch unit SF1D, the transistors F1D[1] to F1D[k] are connected in series. A wiring WSL is connected to the gates of the transistors F1D[1] to F1D[k]. A capacitor C4D[p] is connected between two consecutive transistors F1D[p] and F1D[p+1]. A wiring XCL is connected to the second terminals of the capacitors C4D[1] to C4D[k-1].

[0141] As shown in Figure 4A, by connecting three or more transistors in series in the switch unit SF1, the channel length can be substantially longer than that of the switch unit SF1 shown in Figure 1A, thereby reducing the leakage current in the off state. Furthermore, since a capacitance element is provided between two consecutive transistors, the first terminals of each capacitance element can be maintained at approximately the same potential. As a result, even if the off current of one or more of the transistors increases, almost no charge is distributed through that transistor, so the potential of the node N held by the switch unit SF1 can be maintained for a long period of time. The same applies to the switch unit SF1D.

[0142] 4A , the number of transistors in the switch unit SF1 and the number of transistors in the switch unit SF1D are equal, but in some cases, the number of transistors in the switch unit SF1 and the number of transistors in the switch unit SF1D may be different. For example, if the multiplier held in the multiplier cell IM is frequently rewritten, in other words, if the multiplier does not need to be held as a potential in the multiplier cell IM for a long period of time, the number of transistors in the switch unit SF1 included in the multiplier cell IM may be less than the number of transistors in the switch unit SF1D included in the driver cell IMD. On the other hand, if the potential corresponding to the reference current does not need to be rewritten in the driver cell IMD, it is preferable for the driver cell IMD to hold the potential for a long period of time. Therefore, it is preferable that the number of transistors in the switch unit SF1D included in the driver cell IMD be greater than the number of transistors in the switch unit SF1 included in the driver cell IM.

[0143] Furthermore, by reducing the number of transistors included in either the multiplication cell IM or the driver cell IMD, the area occupied by the multiplication circuit MPA can be reduced.

[0144] The multiplication circuit MPA of Figure 4A can be modified to have a configuration similar to that of the multiplication circuit MPA shown in Figure 4B. The multiplication circuit MPA of Figure 4B differs from the multiplication circuit MPA of Figure 4A in that wirings WSLa and WSLb are provided as the wirings WSL, that wirings WSLa are connected to the gates of transistors F1[d] (d is an odd number between 1 and k) and F1D[d], and that wirings WSLb are connected to the gates of transistors F1[e] (e is an even number between 2 and k) and F1D[e]. Note that in Figure 4B, k is an even number, as an example.

[0145] Like the multiplication circuit of FIG. 1B, the multiplication circuit MPA of FIG. 4B can differentiate the operation timing of the pair of transistor F1[d] and transistor F1D[d] from the pair of transistor F1[e] and transistor F1D[e].

[0146] As a result, for example, in a room temperature environment where the off-state current is small, by always keeping transistor F1[e] and transistor F1D[e] in the on state and using transistor F1[d] and transistor F1D[d] as switching transistors that switch between the on state and the off state, the potential of node N can be maintained by switch unit SF1, and the potential of node ND can be maintained by switch unit SF1D.

[0147] Furthermore, for example, in a high temperature environment where the off-state current is large, as described above, the off-state current of the switch SF1 can be reduced by simultaneously switching the transistor F1[d] and the transistor F1[e] between the on state and the off state in the switch section SF1. The same applies to the switch SF1D.

[0148] Although the present embodiment deals with a multiplication circuit, the multiplication circuit can also be used for purposes other than multiplication. Examples of circuits other than multiplication circuits include an addition circuit and a division circuit. As another example, the multiplication circuit can also be used in a memory circuit, a pixel circuit, an amplifier circuit, a conversion circuit, a function circuit, and the like.

[0149] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0150] Embodiment Mode 2 In this embodiment mode, a configuration example of an arithmetic circuit using the multiplication circuit MPA described in the above embodiment mode will be described.

[0151] <Configuration Example of Arithmetic Circuit> The arithmetic circuit ANP shown in Fig. 5 has a cell array CA, a circuit WSD, a circuit WCS, a circuit XCS, and a circuit ITS. In particular, Fig. 5 shows the circuit configurations of the cell array CA, the circuit WCS, the circuit XCS, and the circuit ITS.

[0152] As an example, the cell array CA includes multiplication cells IM[1,1] to IM[m,n] (where m and n are each an integer of 1 or greater) and driver cells IMD_1 to IMD_m. The driver cells IMD_1 to IMD_m and the multiplication cells IM[1,1] to IM[m,n] are arranged in a matrix within the cell array CA. Specifically, the driver cells IMD_1 to IMD_m are arranged in order in the column direction, and the multiplication cells IM[1,1] to IM[m,n] are arranged in a matrix of m rows and n columns.

[0153] In the i-th row (i is an integer of 1 to m), the driver cell IMD_i and any one of the multiplication cells IM[i,1] to IM[i,n] can be the multiplication circuit MPA described in Embodiment 1. In the cell array CA, by using one driver cell IMD_i, multiplication can be performed in each of the multiplication cells IM[i,1] to IM[i,n] arranged in the same i-th row.

[0154] In this embodiment, for the sake of simplicity, the configurations of the multiplication cells IM[1,1] to IM[m,n] are assumed to be identical to each other. Therefore, in the multiplication cells IM[1,1] to IM[m,n], the common contents may be referred to as the multiplication cell IM without the address notation. Similarly, the configurations of the driving cells IMD_1 to IMD_m are assumed to be identical to each other, and in the driving cells IMD_1 to IMD_m, the common contents may be referred to as the driving cell IMD without the address notation.

[0155] 5, the cell array CA has a function of performing a multiply-and-accumulate operation on each of a plurality of first data written to a plurality of multiplication cells IM and each of a plurality of second data transmitted from the circuit XCS to a plurality of arithmetic cells. Note that in the arithmetic circuit ANP shown in FIG. 5, each of the first data and each of the second data is a positive value or "0."

[0156] The multiplication cell IM functions as a cell that performs multiplication, for example. The driving cell IMD has a function of holding a potential corresponding to reference data in order to perform calculations in the multiplication cell IM, for example. The multiplication cell IM is the multiplication cell IM described in the first embodiment, and the driving cell IMD is the driving cell IMD described in the first embodiment. The reference data is the amount of reference current I described in the first embodiment. ｒｅｆ０ This is data for generating the above, and details will be described later.

[0157] The multiplication cell IM includes, for example, a switch unit SF1, a transistor F2, a transistor F5, and a capacitance element C5, and the drive cell IMD includes, for example, a switch unit SF1D, a transistor F2D, a transistor F5D, and a capacitance element C5D.

[0158] For the switch unit SF1 included in the multiplication cell IM and the switch unit SF1D included in the driver cell IMD, the descriptions of the switch unit SF1 and the switch unit SF1D described in the first embodiment can be referred to.

[0159] The structures (e.g., channel length, channel width, shape, etc.) of the transistors F2 included in each of the multiplication cells IM[1,1] to IM[m,n] are preferably identical to each other, and the structures of the transistors F5 included in each of the multiplication cells IM[1,1] to IM[m,n] are preferably identical to each other. The structures of the transistors F2D included in each of the driver cells IMD_1 to IMD_m are preferably identical to each other, and the structures of the transistors F5D included in each of the driver cells IMD_1 to IMD_m are preferably identical to each other. The structures of the transistors F2 and F2D are preferably identical to each other, and the structures of the transistors F5 and F5D are preferably identical to each other.

[0160] By making the structures of the transistors equal to each other, the electrical characteristics of each transistor can be made approximately equal. Therefore, by making the structure of the transistor F2 included in each of the multiplication cells IM[1,1] to IM[m,n] equal and making the structure of the transistor F5 included in each of the multiplication cells IM[1,1] to IM[m,n] equal, each of the multiplication cells IM[1,1] to IM[m,n] can perform approximately the same operation under the same conditions. Here, the same conditions refer to, for example, the potentials applied to the source, drain, and gate of each transistor F2, the potentials applied to the source, drain, and gate of each transistor F5, and the potentials input to the multiplication cells IM[1,1] to IM[m,n]. Similarly, by making the structure of the transistor F2D included in each of the driver cells IMD_1 to IMD_m the same and by making the structure of the transistor F5D included in each of the driver cells IMD_1 to IMD_m the same, each of the driver cells IMD_1 to IMD_m can perform approximately the same operation under the same conditions, which here refer to, for example, the potentials applied to the source, drain, and gate of each of the transistors F2D, the potentials applied to the source, drain, and gate of each of the transistors F5D, and the voltages input to the driver cells IMD_1 to IMD_m.

[0161] Unless otherwise specified, the transistors F2 and F2D are considered to operate in the subthreshold region (i.e., in the transistor F2 or F2D, the gate-source voltage is lower than the threshold voltage, more preferably, the drain current increases exponentially with the gate-source voltage). That is, the gate voltage, source voltage, and drain voltage of each of the above-described transistors are considered to be appropriately biased to voltages within the range in which they operate in the subthreshold region. Therefore, the transistors F2 and F2D also include a case in which they operate such that an off-state current flows between the source and the drain.

[0162] Furthermore, transistors F5 and F5D function as clamp transistors, for example. Therefore, it is preferable that a fixed potential be applied to the gates of transistors F5 and F5D. Furthermore, as will be described in detail later, providing transistor F5 can prevent DIBL in transistor F2. Similarly, providing transistor F5D can prevent DIBL in transistor F2D.

[0163] On the other hand, if the DIBL in the transistor F2 can be ignored, the multiplication cell IM may be configured without the transistor F5. Similarly, if the DIBL in the transistor F2D can be ignored, the driver cell IMD may be configured without the transistor F5D.

[0164] Note that for transistors that can be used as the transistors F2, F5, F2D, and F5D, refer to the descriptions of the transistors F2, F5, F2D, and F5D in Embodiment 1.

[0165] In the multiplication cell IM shown in FIG. 1 , the second terminal of transistor F1b is connected to the gate of transistor F2. The first terminal of transistor F2 is connected to wiring VE0. The first terminal of capacitance element C5 is connected to the gate of transistor F2. The second terminal of transistor F2 is connected to the first terminal of transistor F5. The second terminal of transistor F5 is connected to the second terminal of transistor F1a, and the gate of transistor F5 is connected to wiring VE1. The first terminal of transistor F1a and the first terminal of transistor F1b are connected to the first terminal of capacitance element C4.

[0166] 1, the second terminal of the transistor F2 and the wiring WCL are connected in series via the first and second terminals of the transistor F5, which prevents a high-level potential from the wiring WCL from being directly applied to the second terminal of the transistor F2, thereby preventing DIBL in the transistor F2.

[0167] In the multiplication cell IM, when the second terminal of the transistor F2 is directly connected to the wiring WCL (i.e., when the transistor F5 is not provided), a high-level potential is directly applied to the second terminal of the transistor F2 from the wiring WCL, which may cause DIBL in the transistor F2. When DIBL occurs in the transistor F2, the threshold voltage of the transistor F2 decreases, which may change the voltage range of the subthreshold region of the transistor F2. Therefore, when the multiplication cell IM is configured without the transistor F5, variations may occur in the current in the subthreshold region flowing through the transistor F2.

[0168] 2, the second terminal of the transistor F1Db is connected to the gate of the transistor F2D. The first terminal of the transistor F2D is connected to the wiring VE0. The first terminal of the capacitance element C5D is connected to the gate of the transistor F2D. The second terminal of the transistor F2D is connected to the first terminal of the transistor F5D. The second terminal of the transistor F5D is connected to the second terminal of the transistor F1Da, and the gate of the transistor F5D is connected to the wiring VE1. The first terminal of the transistor F1Da and the first terminal of the transistor F1Db are connected to the first terminal of the capacitance element C4D.

[0169] The transistor F5D in the driver cell IMD also plays a role in preventing DIBL in the transistor F2D, similar to the transistor F5 in the multiplication cell IM.

[0170] The wiring VE0 functions as a wiring for passing a current between the first terminal and the second terminal of the transistor F2 of the multiplier cell IM. The wiring VE0 also functions as a wiring for passing a current between the first terminal and the second terminal of the transistor F2D of the driver cell IMD. As an example, the wiring VE0 functions as a wiring for supplying a fixed potential. The fixed potential can be, for example, a low-level potential or a ground potential.

[0171] The wiring VE1 functions as a wiring for applying a potential to the gate of the transistor F5 of the multiplication cell IM and the gate of the transistor F5D of the driver cell IMD, respectively. Note that the potential is preferably set to a range in which the transistors F5 and F5D function as clamp transistors.

[0172] In the cell array CA of FIG. 5 , when the multiplication cell IM of FIG. 1A is applied to the multiplication cell IM[i,j] (not shown) located in the i-th row and j-th column, the second terminal of the transistor F1a and the second terminal of the transistor F5 are connected to the wiring WCL_j, and the gates of the transistors F1a and F1b are connected to the wiring WSL_i. The second terminal of the capacitance element C5 is connected to the wiring XCL_i. In FIG. 5 , the connection point of the switch unit SF1 (the second terminal of the transistor F1b in FIG. 1A ), the gate of the transistor F2, and the first terminal of the capacitance element C5 in the multiplication cell IM[i,j] is designated as the node N[i,j].

[0173] 1A is applied to a driver cell IMD_i (not shown) located in the i-th row of the cell array CA in FIG. 5 , the second terminal of the transistor F1Da and the second terminal of the transistor F5D are connected to the wiring XCL_i, and the gate of the transistor F1Da and the transistor F1Db are connected to the wiring WSL_i. The second terminal of the capacitance element C5D is also connected to the wiring XCL_i. In FIG. 5 , the node ND[i] is defined as the connection point between the switch unit SF1 (the second terminal of the transistor F1Db in FIG. 1A ), the gate of the transistor F2D, and the first terminal of the capacitance element C5D in the driver cell IMD_i.

[0174] Nodes N[i,j] and ND[i] function as holding nodes for the respective cells. Nodes N[1,1], N[1,n], N[m,1], N[m,n], ND[1], and ND[m] are selectively shown in FIG.

[0175] [Circuit WSD] For example, when writing first data, the circuit WSD has a function of selecting a row of the cell array CA in which the multiplication cell IM to be written is arranged. When writing the first data, the circuit WSD also selects a drive cell IMD in the same row, and writes reference data for generating a reference current into the drive cell IMD.

[0176] 5, the circuit WSD supplies a high-level potential to the wiring WSL_1 and a low-level potential to the wirings WSL_2 (not shown) to WSL_m, thereby turning on the transistors F1a, F1b, F1Da, and F1Db having gates connected to the wiring WSL_1 and turning off the transistors F1a, F1b, F1Da, and F1Db having gates connected to the wirings WSL_2 to WSL_m, respectively. That is, the write switches of the multiplication cell IM and the driver cell IMD arranged in the first row of the cell array CA1 can be turned on.

[0177] [Circuit WCS] The circuit WCS has a function of, for example, acquiring first data, which is digital data acquired from an external device, converting the first data into analog data (amount of current), and supplying the converted analog data to the multiplication cells IM included in the cell array CA. For example, when the circuit WCS writes the first data to the multiplication cells IM[i,j] included in the cell array CA, the circuit WSD selects the multiplication cells IM[i,1] to IM[i,n] in the i-th row of the cell array CA, and then the circuit WCS supplies the first data to the arithmetic cells in the first column of the cell array CA via the wiring WCL_j.

[0178] The circuit WCS includes, for example, a circuit SWCA and circuits WCSa_1 to WCSa_n.

[0179] The circuit SWCA has a function of controlling switching between a conductive state and a non-conductive state between a wiring WCL_j (not shown) and a circuit WCSa_j (not shown), for example.

[0180] The circuit SWCA includes, for example, switches SA_1 to SA_n.

[0181] A first terminal of the switch SA_j (not shown) is connected to the wiring WCL_j, a second terminal of the switch SA_j is connected to the circuit WCSa_j, and a control terminal of the switch SA_j is connected to the wiring SWLA.

[0182] Each of the switches SA_1 to SA_n can be, for example, an electrical switch such as an analog switch or a transistor. In particular, the above-described transistors are preferably used as the electrical switches for each of the switches SA_1 to SA_n, and OS transistors are more preferably used. Note that when electrical switches are used for each of the switches SA_1 to SA_n, the electrical switches can be, for example, Si transistors other than OS transistors. Furthermore, each of the switches SA_1 to SA_n can be, for example, a mechanical switch.

[0183] In this specification, each of the switches SA_1 to SA_n shown in FIG. 5 is turned on when a high-level potential is applied to the control terminal, and turned off when a low-level potential is applied to the control terminal.

[0184] For example, the wiring SWLA functions as a wiring for switching the on and off states of the switches SA_1 to SA_n. Therefore, a high-level potential or a low-level potential is supplied to the wiring SWLA.

[0185] The circuit WCSa_1 is connected to the wiring IWL_1, and the circuit WCSa_n is connected to the wiring IWL_n.

[0186] For example, the circuit WCSa_j (not shown) has a function of acquiring first data from a wiring IWL_j (not shown) and supplying a signal corresponding to the first data to the wiring WCL_j. Specifically, when the switch SA_j is on, the circuit WCSa_j supplies the first data to be stored in one of the multiplication cells IM[1,j] to IM[m,j] arranged in the jth column of the cell array CA. Note that in the case of the cell array CA of FIG. 5, the signal is preferably analog data (amount of current).

[0187] For example, the circuit WCSa_j can have the configuration shown in Fig. 6A. Note that Fig. 6A also illustrates the circuit SWCA, the switch SA_j, the wiring SWLA, and the wiring WCL_j in order to show the connection of the circuit WCSa_j to peripheral circuits.

[0188] 6A is any one of the switches SA_1 to SA_n included in the circuit SWCA in Fig. 5. Similarly, the wiring WCL_j is any one of the wirings WCL_1 to WCL_n extending to the cell array CA in Fig. 5.

[0189] That is, the wiring WCL_j is connected to the circuit WCSa_j via the switch SA_j.

[0190] 6A includes a switch SWW, as an example. A first terminal of the switch SWW is connected to a second terminal of the switch SA_j, and the second terminal of the switch SWW is connected to a wiring VINIL1. The wiring VINIL1 functions as a wiring that applies an initialization potential to the wiring WCL_j, and the initialization potential can be a ground potential (GND), a low-level potential, or a high-level potential. Note that the switch SWW is turned on only when an initialization potential is applied to the wiring WCL_j, and is turned off otherwise.

[0191] For example, an electrical switch (for example, an analog switch or a transistor) can be applied to the switch SWW. When a transistor is applied as the switch SWW, the transistor can have the same structure as the transistor F1 or the transistor F2. In addition to an electrical switch, a mechanical switch may also be applied.

[0192] 6A includes a plurality of current sources CS. Ｍ In this case, the circuit WCSa_j has a function of outputting the first data of 2 ＭThe circuit WCSa_j has, for example, one current source CS that outputs the value of the 0th bit as a current, two current sources CS that output the value of the 1st bit as a current, and two current sources CS that output the value of the (M-1)th bit as a current. Ｍ−１ There are individual ones.

[0193] 6A, each current source CS has a terminal U1 and a terminal U2. The terminal U1 of each current source CS is connected to the second terminal of the switch SA_j of the circuit SWCA. The terminal U2 of one current source CS is connected to the wiring DW[0], and each of the terminals U2 of the two current sources CS is connected to the wiring DW[1]. Ｍ−１ Each of the terminals U2 of the current sources CS is connected to a wiring DW[M-1].

[0194] The multiple current sources CS included in the circuit WCSa_j each have the same amount I Ｗｕｔ In practice, during the manufacturing stage of the arithmetic circuit ANP, errors may occur due to variations in the electrical characteristics of the transistors included in each current source CS. Therefore, the amount of constant current I output from each terminal U1 of the multiple current sources CS is Ｗｕｔ The error is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, the amount of constant current I output from the terminal U1 of each of the multiple current sources CS included in the circuit WCSa_j is Ｗｕｔ The following explanation will be given assuming that there is no error.

[0195] The wirings DW[0] to DW[M-1] can be the wirings IWL_j described above, and function as wirings that acquire first data, which is digital data, from the outside. Specifically, the wirings DW[0] to DW[M-1] acquire the quantity I from the current source CS connected thereto. Ｗｕｔ For example, when a high-level potential is applied to the wiring DW[0], the current source CS connected to the wiring DW[0] outputs a constant current of I Ｗｕｔflows to the second terminal of the switch SA_j, and when a low-level potential is applied to the wiring DW[0], the current source CS connected to the wiring DW[0] flows as follows: Ｗｕｔ For example, when a high-level potential is applied to the wiring DW[1], the two current sources CS connected to the wiring DW[1] output a total of 2I Ｗｕｔ When a constant current of 2I flows through the second terminal of the switch SA_j and a low-level potential is applied to the wiring DW[1], the current source CS connected to the wiring DW[1] has a total of 2I Ｗｕｔ For example, when a high-level potential is applied to the wiring DW[M-1], the constant current of the second Ｍ−１ The current sources CS are a total of 2 Ｍ−１ I Ｗｕｔ When a constant current of a total amount flows to the second terminal of the switch SA_j and a low-level potential is applied to the wiring DW[M-1], the current source CS connected to the wiring DW[M-1] has a total of 2 Ｍ−１ I Ｗｕｔ It does not output a constant current of this magnitude.

[0196] One current source CS connected to the wiring DW[0] has a function of passing the value of the 0th bit as a current, two current sources CS connected to the wiring DW[1] have a function of passing the value of the 1st bit as a current, and two current sources CS connected to the wiring DW[M-1] have a function of passing the value of the 1st bit as a current. Ｍ−１ The current sources CS have the function of flowing the value of the (M-1)th bit as a current. Here, consider the circuit WCSa_j when M is 2. For example, when the value of the 0th bit is "1" and the value of the 1st bit is "0", a high level potential is applied to the wiring DW[0] and a low level potential is applied to the wiring DW[1]. At this time, a quantity I Ｗｕｔ A constant current of 2I flows from the circuit WCSa_j to the second terminal of the switch SA_j of the circuit SWCA. In addition, for example, when the value of the 0th bit is "0" and the value of the 1st bit is "1", a low level potential is applied to the wiring DW[0] and a high level potential is applied to the wiring DW[1]. At this time, a constant current of 2I flows from the circuit WCSa_j to the second terminal of the switch SA_j of the circuit SWCA. ＷｕｔA constant current of 3I flows from the circuit WCSa_j to the second terminal of the switch SA_j of the circuit SWCA. Ｗｕｔ A constant current of 1 flows. Furthermore, for example, when the value of the 0th bit is "0" and the value of the 1st bit is "0", a low-level potential is applied to the wiring DW[0] and the wiring DW[1]. At this time, no constant current flows from the circuit WCSa_j to the second terminal of the switch SA_j of the circuit SWCA.

[0197] 6A illustrates the circuit WCSa_j when M is an integer of 3 or more, but when M is 1, it is preferable that the circuit WCSa_j in FIG. 6A does not include a current source CS connected to the wirings DW[1] to DW[M-1]. When M is 2, it is preferable that the circuit WCSa_j in FIG. 6A does not include a current source CS connected to the wirings DW[2] (not shown) to DW[M-1].

[0198] Next, a specific example of the configuration of the current source CS will be described.

[0199] The current source CS1 shown in FIG. 7A is a circuit that can be applied to the current source CS included in the circuit WCSa_j in FIG. 6A, and the current source CS1 has a transistor Tr1 and a transistor Tr2.

[0200] A first terminal of the transistor Tr1 is connected to the wiring VDDL, and a second terminal of the transistor Tr1 is connected to the gate of the transistor Tr1, the back gate of the transistor Tr1, and the first terminal of the transistor Tr2. A second terminal of the transistor Tr2 is connected to the terminal U1, and a gate of the transistor Tr2 is connected to the terminal U2. The terminal U2 is also connected to the wiring DW.

[0201] The wiring DW is any one of the wirings DW[0] to DW[M-1] in FIG. 6A.

[0202] The wiring VDDL functions as a wiring that applies a fixed potential. The fixed potential can be, for example, a high-level potential.

[0203] When the fixed potential provided by the wiring VDDL is set to a high-level potential, the high-level potential is input to the first terminal of the transistor Tr1. The potential of the second terminal of the transistor Tr1 is set to a potential lower than the high-level potential. In this case, the first terminal of the transistor Tr1 functions as a drain, and the second terminal of the transistor Tr1 functions as a source. Since the gate of the transistor Tr1 and the second terminal of the transistor Tr1 are connected, the gate-source voltage of the transistor Tr1 is 0 V. Therefore, when the threshold voltage of the transistor Tr1 is within an appropriate range, a current (drain current) in the subthreshold current range flows between the first and second terminals of the transistor Tr1. When the transistor Tr1 is an OS transistor, the amount of the current is, for example, 1.0×10 −８ A or less, and 1.0 × 10 −１２ A or less is more preferable, and 1.0 × 10 −１５ It is more preferable that the current is equal to or less than 1 A. Furthermore, for example, it is more preferable that the current is in a range that increases exponentially with respect to the gate-source voltage. In other words, the transistor Tr1 functions as a current source for supplying a current in the current range when operating in the subthreshold region. Note that the current is the above-mentioned I Ｗｕｔ Or I, which will be described later Ｘｕｔ It can be said that:

[0204] The transistor Tr2 functions as a switching element. When the potential of the first terminal of the transistor Tr2 is higher than the potential of the second terminal of the transistor Tr2, the first terminal of the transistor Tr2 functions as a drain, and the second terminal of the transistor Tr2 functions as a source. The back gate of the transistor Tr2 and the second terminal of the transistor Tr2 are connected, so the back gate-source voltage is 0 V. Therefore, when the threshold voltage of the transistor Tr2 is within an appropriate range, a high-level potential input to the gate of the transistor Tr2 turns the transistor Tr2 on, and a low-level potential input to the gate of the transistor Tr2 turns the transistor Tr2 off. Specifically, when the transistor Tr2 is on, a current in the subthreshold region flows from the second terminal of the transistor Tr1 to the terminal U1. When the transistor Tr2 is off, the current does not flow from the second terminal of the transistor Tr1 to the terminal U1.

[0205] Note that a circuit applicable to the current source CS included in the circuit WCSa_j of FIG. 6A is not limited to the current source CS1 of FIG. 7A. For example, while the current source CS1 is configured such that the back gate of transistor Tr2 is connected to the second terminal of transistor Tr2, the back gate of transistor Tr2 may be connected to a separate wiring. An example of such a configuration is shown in FIG. 7B. In the current source CS2 shown in FIG. 7B, the back gate of transistor Tr2 is connected to wiring VTHL. By connecting wiring VTHL to an external circuit or the like, the current source CS2 can apply a predetermined potential to wiring VTHL via the external circuit, thereby applying the predetermined potential to the back gate of transistor Tr2. This allows the threshold voltage of transistor Tr2 to be varied. In particular, increasing the threshold voltage of transistor Tr2 can reduce the off-state current of transistor Tr2.

[0206] Further, for example, the current source CS1 has a configuration in which the back gate of the transistor Tr1 is connected to the second terminal of the transistor Tr1. However, a configuration in which a voltage is held between the back gate and the second terminal of the transistor Tr2 by a capacitive element may also be employed. Such a configuration example is shown in FIG. 7C. The current source CS3 shown in FIG. 7C includes, in addition to the transistors Tr1 and Tr2, a transistor Tr3 and a capacitive element C7. The current source CS3 differs from the current source CS1 in that the second terminal of the transistor Tr1 is connected to the back gate of the transistor Tr1 via the capacitive element C7, and the back gate of the transistor Tr1 is connected to the first terminal of the transistor Tr3. Also, the current source CS3 has a configuration in which the second terminal of the transistor Tr3 is connected to the wiring VTL and the gate of the transistor Tr3 is connected to the wiring VWL. The current source CS3 can make the connection between the wiring VTL and the back gate of the transistor Tr1 conductive by applying a high-level potential to the wiring VWL to turn on the transistor Tr3. At this time, a predetermined potential can be input from the wiring VTL to the back gate of the transistor Tr1. Then, by applying a low-level potential to the wiring VWL to turn off the transistor Tr3, the voltage between the second terminal of the transistor Tr1 and the back gate of the transistor Tr1 can be held by the capacitive element C7. That is, by determining the voltage applied by the wiring VTL to the back gate of the transistor Tr1, the threshold voltage of the transistor Tr1 can be varied, and the threshold voltage of the transistor Tr1 can be fixed by the transistor Tr3 and the capacitive element C7.

[0207] Further, for example, the circuit configuration applicable to the current source CS included in the circuit WCSa_j of FIG. 6A may be the current source CS4 shown in FIG. 7D. The current source CS4 has a configuration in which, in the current source CS3 of FIG. 7C, the back gate of the transistor Tr2 is connected not to the second terminal of the transistor Tr2 but to the wiring VTHL. That is, similar to the current source CS2 of FIG. 7B, the current source CS4 can vary the threshold voltage of the transistor Tr2 according to the potential applied by the wiring VTHL.

[0208] In the current source CS4, when a large current flows between the first and second terminals of the transistor Tr1, it is necessary to increase the on-current of the transistor Tr2 in order to pass the current from the terminal U1 to the outside of the current source CS4. In this case, the current source CS4 applies a high-level potential to the wiring VTHL to lower the threshold voltage of the transistor Tr2 and increase the on-current of the transistor Tr2, thereby allowing the large current flowing between the first and second terminals of the transistor Tr1 to flow from the terminal U1 to the outside of the current source CS4.

[0209] 6A is replaced with any one of the current sources CS1 to CS4 shown in FIGS. 7A to 7D, allowing the circuit WCSa_j to output a current corresponding to M bits of first data. The amount of the current can be, for example, the amount of current flowing between the first terminal and the second terminal when the transistor F1 operates in the subthreshold region.

[0210] 6A may be replaced by the circuit WCSa_j shown in FIG. 6B. The circuit WCSa_j in FIG. 6B has a configuration in which the current source CS in FIG. 7A is connected to each of the wirings DW[0] to DW[M-1]. When the channel width of the transistor Tr1[0] is w[0], the channel width of the transistor Tr1[1] is w[1], and the channel width of the transistor Tr1[M-1] is w[M-1], the ratio of the channel widths is w[0]:w[1]:w[M-1]=1:2:2. Ｍ−１ Since the current flowing between the source and drain of a transistor operating in the subthreshold region is proportional to the channel width, the circuit WCSa_j shown in FIG. 6B can output a current corresponding to the M-bit first data, similar to the circuit WCSa_j in FIG. 6A.

[0211] Note that the transistor Tr1 (including transistors Tr1[0] to Tr1[M-1]), the transistor Tr2 (including transistors Tr2[0] to Tr2[M-1]), and the transistor Tr3 can be, for example, a transistor that can be used as the transistor F1a, the transistor F1b, the transistor F2, the transistor F5, the transistor F1Da, the transistor F1Db, the transistor F2D, or the transistor F5D. In particular, the transistor Tr1 (including transistors Tr1[0] to Tr1[M-1]), the transistor Tr2 (including transistors Tr2[0] to Tr2[M-1]), and the transistor Tr3 are preferably OS transistors.

[0212] [Circuit XCS] The circuit XCS has a function of, for example, acquiring second data, which is digital data, from the outside via a wiring IXL_i (not shown in FIG. 5 ), converting the second data into analog data (amount of current), and further supplying the second data to the arithmetic cells included in the cell array CA. For example, when the circuit XCS supplies the second data to the multiplication cells IM[i,1] to IM[i,n] in the i-th row included in the cell array CA, the circuit XCS supplies the second data to the arithmetic cells in the i-th row of the cell array CA via the wiring XCL_i.

[0213] The circuit XCS includes, for example, circuits XCSa_1 to XCSa_m.

[0214] The circuit XCSa_1 is connected to the wiring IXL_1, and the circuit XCSa_m is connected to the wiring IXL_m.

[0215] The wirings IXL_1 to IXL_m function as wirings for transmitting second data, which is digital data, from the outside to the circuits XCSa_1 to XCSa_m, respectively.

[0216] For example, each of the circuits XCSa_1 to XCSa_m has a function of acquiring reference data (described later) from the wirings IXL_1 to IXL_m and supplying a signal corresponding to the reference data to the wirings XCL_1 to XCL_m. Alternatively, for example, each of the circuits XCSa_1 to XCSa_m has a function of acquiring second data from the wirings IXL_1 to IXL_m and supplying a signal corresponding to the second data. Note that in the case of the cell array CA in FIG. 5, the above-described signals are preferably analog data (amount of current).

[0217] 6C is a block diagram showing an example of a circuit XCSa_i (i is an integer of 1 to m) that can be applied to the circuit XCS in FIG. 5. Note that FIG. 6C shows the circuit XCSa_i as one of the circuits XCSa_1 to XCSa_m. Furthermore, FIG. 6C also shows a wiring XCL_i to show electrical connection between the circuit XCS and peripheral circuits. Therefore, the wiring XCL_i is connected to the circuit XCSa_i.

[0218] The circuit XCSa_i shown in FIG. 6C includes, as an example, a switch SWX. A first terminal of the switch SWX is connected to the wiring XCL_i, and a second terminal of the switch SWX is connected to the wiring VINIL2. The wiring VINIL2 functions as a wiring that applies an initialization potential to the wiring XCL_i. The initialization potential can be a ground potential (GND), a low-level potential, or a high-level potential. The initialization potential applied by the wiring VINIL2 may be equal to the potential applied by the wiring VINIL1. Note that the switch SWX is turned on only when the initialization potential is applied to the wiring XCL_i, and is turned off otherwise.

[0219] The switch SWX may be, for example, a switch applicable to the switch SWW.

[0220] 6C can be configured to have substantially the same configuration as the circuit WCSa_j in FIG. 6A. Specifically, the circuit XCSa_i has a function of outputting reference data as a current amount and a function of outputting L bits (2Ｌ In this case, the circuit XCSa_i has a function of outputting second data of a value (L is an integer of 1 or more) as a current amount. Ｌ The circuit XCSa_i has one current source CS that outputs the value of the 0th bit as a current, two current sources CS that output the value of the 1st bit as a current, and two current sources CS that output the value of the (L-1)th bit as a current. Ｌ−１ There are individual ones.

[0221] Incidentally, the reference data output as a current by the circuit XCSa_i can be, for example, information in which the value of the 0th bit is "1" and the values ​​of the 1st and subsequent bits are "0".

[0222] In FIG. 6C, the terminal U2 of one current source CS is connected to the wiring DX[0], and each of the terminals U2 of the two current sources CS is connected to the wiring DX[1]. Ｌ−１ Each of the terminals U2 of the current sources CS is connected to the wiring DX[L-1].

[0223] The multiple current sources CS included in the circuit XCSa_i each have the same amount I Ｘｕｔ The wirings DX[0] to DX[L-1] can be the wiring IXL_i described above, and function as wirings for acquiring reference data or second data, which are digital data from the outside. Specifically, the wirings DX[0] to DX[L-1] are connected to the current source CS and the wirings DX[0] to DX[L-1], respectively. Ｘｕｔ That is, the circuit XCSa_i has a function of causing the amount of current corresponding to L-bit information transmitted from the wirings DX[0] to DX[L-1] to flow to the wiring XCL_i.

[0224] Specifically, consider the circuit XCSa_i when L is set to 2. For example, when the value of the 0th bit is "1" and the value of the 1st bit is "0", a high-level potential is applied to the wiring DX[0] and a low-level potential is applied to the wiring DX[1]. At this time, a quantity I ＸｕｔFurthermore, for example, when the value of the 0th bit is "0" and the value of the 1st bit is "1", a low level potential is applied to the wiring DX[0] and a high level potential is applied to the wiring DX[1]. At this time, a constant current of 2I flows from the circuit XCSa_i to the wiring XCL_i. Ｘｕｔ Furthermore, for example, when the value of the 0th bit is "1" and the value of the 1st bit is "1", a high-level potential is applied to the wiring DX[0] and the wiring DX[1]. At this time, a constant current of 3I flows from the circuit XCSa_i to the wiring XCL_i. Ｘｕｔ A constant current of 0 flows. Also, for example, when the value of the 0th bit is "0" and the value of the 1st bit is "0", a low-level potential is applied to the wiring DX[0] and the wiring DX[1]. At this time, no constant current flows from the circuit XCSa_i to the wiring XCL_i. Note that in this specification and the like, this may be rephrased as a current of 0 flowing from the circuit XCSa_i to the wiring XCL_i. Also, when the current of 0, I output from the circuit XCSa_i is Ｘｕｔ , 2I Ｘｕｔ , 3I Ｘｕｔ etc. can be the second data output by the circuit XCSa_i, and in particular, the amount of current I Ｘｕｔ can be the reference data output by the circuit XCSa_i.

[0225] In addition, when an error occurs due to variations in the electrical characteristics of the transistors included in each current source CS of the circuit XCSa_i, the amount of constant current I output from each of the terminals U1 of the multiple current sources CS may be Ｘｕｔ The error is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, the amount of constant current I output from the terminal U1 of each of the multiple current sources CS included in the circuit XCSa_i is Ｘｕｔ The following explanation will be given assuming that there is no error.

[0226] 7A to 7D can be used as the current source CS of the circuit XCSa_i, similar to the current source CS of the circuit WCSa_j. In this case, the wirings DW[0] to DW[M-1] shown in FIGS. 7A to 7D can be replaced with wirings DX[0] to DX[L-1]. This allows the circuit XCSa_i to pass a current in the subthreshold current range to the wiring XCL_i as reference data or L-bit second data.

[0227] 6C can be applied to the circuit XCSa_i in Fig. 6C. In this case, the circuit WCSa_j in Fig. 6B can be replaced with the circuit XCSa_i, the wiring IWL_j with the wiring IXL_i, the wiring DW[0] with the wiring DX[0], the wiring DW[1] with the wiring DX[1], the wiring DW[M-1] with the wiring DX[L-1], the switch SWW with the switch SWX, and the wiring VINIL1 with the wiring VINIL2.

[0228] [Circuit ITS] The circuit ITS includes, for example, a circuit that performs a calculation of a function system (e.g., a nonlinear function system) and an analog-to-digital conversion circuit. In particular, the circuit that performs the calculation of the function system preferably has a function of, for example, performing the calculation of the function system using a value corresponding to the amount of input current as an input value, and outputting digital data (voltage) corresponding to the result of the calculation.

[0229] 8A shows an example of a circuit configuration of the circuit ITS. The circuit ITS shown in FIG. 8A is an example of a circuit that can be applied to the circuit ITS shown in FIG. 5. Note that FIG. 8A also shows a wiring WCL_j to show electrical connection of the circuit ITS with peripheral circuits. The wiring WCL_j is any one of the wirings WCL_1 to WCL_n shown in FIG. 5, and the switch SB_j is any one of the switches SB_1 to SB_n included in the circuit SWCB shown in FIG. 5.

[0230] The switch SB_j can be, for example, a switch that can be applied to the switches SA_1 to SA_n shown in Fig. 5. For example, the switch SB_j can be an electrical switch or a mechanical switch.

[0231] 8A includes a circuit SWCB and circuits ITSa_1 to ITSa_n. Note that only one of the circuits ITSa_1 to ITSa_n, i.e., a circuit ITSa_j, is illustrated in FIG. 8A. The circuit ITSa_j also includes a conversion circuit RL_j and an analog-to-digital conversion circuit ADC.

[0232] Furthermore, the conversion circuit RL_j has a terminal RTi_j and a terminal RTo_j.

[0233] A first terminal of the switch SB_j is connected to the wiring WCL_j, a second terminal of the switch SB_j is connected to the terminal RTi_j of the conversion circuit RL_j, and a control terminal of the switch SB_j is connected to the wiring SWLB. In addition, a terminal RTo_j of the conversion circuit RL_j is connected to the input terminal of the analog-to-digital conversion circuit ADC, and an output terminal of the analog-to-digital conversion circuit ADC is connected to the wiring OL_j.

[0234] For example, the wiring SWLB functions as a wiring for switching the on and off states of the switches SB_1 to SB_n. Therefore, a high-level potential or a low-level potential is supplied to the wiring SWLB.

[0235] The wiring OL_j (wirings OL_1 to OL_n in FIG. 5) functions as a wiring for outputting the result of the arithmetic operation performed in the arithmetic circuit ANP to the outside as digital data.

[0236] The conversion circuit RL_j may be the above-described function-based arithmetic circuit. The function-based arithmetic circuit may be, for example, a nonlinear function arithmetic circuit such as a sigmoid function, a tanh function, a softmax function, a ReLU function, or a threshold function. The conversion circuit RL_j may also include a circuit that performs pooling processing instead of a function-based arithmetic circuit. In the configuration of FIG. 8A , the conversion circuit RL_j is preferably configured to output a voltage from the terminal RTo_j.

[0237] The conversion circuit RL_j may be a current-voltage conversion circuit.

[0238] When the conversion circuit RL_j is a current-voltage conversion circuit, it is preferable that the conversion circuit RL_j is configured to generate an analog voltage corresponding to the current input from the wiring WCL_j to the terminal RTi_j of the conversion circuit RL_j via the switch SB_j, and output it to the terminal RTo_j of the conversion circuit RL_j.

[0239] Furthermore, the analog-to-digital converter circuit ADC preferably converts an analog voltage supplied from the terminal RTo_j of the converter circuit RL_j into a digital signal and outputs the digital signal to the wiring OL_j.

[0240] 8B shows a configuration example of the circuit ITS when the conversion circuit RL_j is a current-voltage conversion circuit. The conversion circuit RL_j shown in FIG. 8B includes, as an example, a load LE and an operational amplifier OP.

[0241] The inverting input terminal of the operational amplifier OP is connected to the first terminal of the load LE and the second terminal of the switch SB_j. The non-inverting input terminal of the operational amplifier OP is connected to the wiring VRL. The output terminal of the operational amplifier OP is connected to the second terminal of the load LE and the terminal RTo_j.

[0242] The wiring VRL functions as a wiring that applies a fixed potential, which may be, for example, a ground potential (GND) or a low-level potential.

[0243] In particular, by setting the fixed potential provided by the wiring VRL to the ground potential (GND), the inverting input terminal of the operational amplifier OP becomes a virtual ground, and therefore the analog voltage output to the wiring OL_j can be a voltage based on the ground potential (GND).

[0244] 8B , the circuit ITS can output, as an analog voltage to the terminal RTo_j, a value corresponding to the amount of current flowing from the wiring WCL_j to the terminal RTi_j of the conversion circuit RL_j via the switch SB_j. The analog voltage can be converted into a digital signal by the analog-to-digital conversion circuit ADC and output to the wiring OL_j.

[0245] Note that when the circuit ITS outputs an analog voltage rather than a digital signal to the wiring OL_j, the circuit ITSa_j does not need to include an analog-to-digital conversion circuit ADC, as in the circuit ITS shown in FIG. 8C . Also, in FIG. 8C , the conversion circuit RL_j preferably performs a function calculation using a value corresponding to the amount of current flowing through the terminal RTi_j as an input value, and outputs the result of the calculation as an analog current to the terminal RTo_j. In this case, the circuit ITS shown in FIG. 8C is effective, for example, when the calculation result of the circuit ITS is not stored in the memory circuit unit ME11 but is directly input to an analog arithmetic circuit that performs calculations on the next fully connected layer.

[0246] <Example of Operation of Arithmetic Circuit> Next, an example of operation of the arithmetic circuit ANP will be described.

[0247] First, first data, which is digital data, is input from the outside to the wirings IWL_1 to IWL_n.

[0248] 5 is the circuit WCS shown in FIG. 6A, each of the circuits WCSa_1 to WCSa_n generates a current of an amount corresponding to the value of the digital data transmitted to each of the wirings IWL_1 to IWL_n. When each of the switches SA_1 to SA_n of the circuit SWCA is on, the current generated by each of the circuits WCSa_1 to WCSa_n flows to the wirings WCL_1 to WCL_n.

[0249] 5, for example, by selecting the i-th row in the cell array CA, current flows from the wirings WCL_1 to WCL_n to the multiple multiplication cells IM[i,1] to IM[i,n] arranged in the i-th row. Here, by holding the potential of the gate of the transistor F2 of each of the multiplication cells IM[i,1] to IM[i,n], the amount of current flowing between the source and drain of the transistor F2 can be set.

[0250] Further, while currents from the wirings WCL_1 to WCL_n flow through each of the multiplication cells IM[i,1] to IM[i,n] arranged in the i-th row of the cell array CA, the circuit XCS supplies a reference current I ｒｅｆ０ This allows the amount of current flowing between the source and drain of the transistor F2d of the driving cell IMD_i to be kept at I ｒｅｆ０ The amount of current to the driving cell IMD of the cell array CA is set together with the amount of current to the multiplication cell IM.

[0251] The reference current I ｒｅｆ０ The amount of current flowing through the line XCL when the second data transmitted to the multiplication cell IM is "1", for example.

[0252] From the above, the amount of current I flowing through the transistor F2 of the multiplication cell IM[i,j] ０ [i, j] is as shown in the following formula (2.1).

[0253]

[0254] Here, w[i,j] is the first data written to the multiplication cell IM[i,j]. When the arithmetic circuit ANP performs calculations on a neural network of a fully connected layer, the first data can be rephrased as a weight coefficient (sometimes called connection strength). Also, w[i,j] is defined as in the following formula (2.2). Also, I ｒｅｆ０ is expressed as the following equation (2.3).

[0255]

[0256] In addition, V ｇ [i,j] is the gate-source voltage of transistor F2 of multiplication cell IM[i,j], and V ｔｈ [i, j] is the threshold voltage of the transistor F2 of the multiplication cell IM[i, j]. ｇｍ [i] is the gate-source voltage of the transistor F2D of the driving cell IMD_i, and V ｔｈｍ [i] is the threshold voltage of the transistor F2 of the driving cell IMD_i. ａ is V ｇｍ [i] is V ｔｈｍ [i], when I ｒｅｆ０ where J is a correction coefficient determined by temperature, device structure, etc.

[0257] Next, second data, which is digital data, is input from the outside to the wirings IXL_1 to IXL_m.

[0258] 5 is replaced with the circuit XCS shown in FIG. 6C, each of the circuits XCSa_1 to XCSa_m generates a current of an amount corresponding to the value of the digital data transmitted to each of the wirings IXL_1 to IXL_m. As a result, the currents generated by the circuits XCSa_1 to XCSa_m flow through the wirings XCL_1 to XCL_m.

[0259] The potential of each of the wirings XCL_1 to XCL_m is determined by the amount of current flowing through the wiring. When the potential of each of the wirings XCL_1 to XCL_m changes, the potential of the gate (node ​​N) of the transistor F2 of each of the multiplication cells IM[1,1] to IM[m,n] changes. At this time, the amount of current I １ [i, j] is as shown in the following equation (2.4).

[0260]

[0261] Here, x[i] is the second data transmitted from the circuit XCSa_i to the wiring XCL_i. Note that when the arithmetic circuit ANP performs a fully connected layer neural network operation, the second data can be rephrased as the input signal of the neuron. Also, x[i] is expressed by the following equation (2.5):

[0262]

[0263] ΔV[i] is the amount of current flowing through the wiring XCL_i. ｒｅｆ０ The graph shows the change in the potential of the wiring XCL_i when the current amount changes from ≡p to ≡p [i]. Also, p is the coupling capacitance coefficient between the first terminal and the second terminal of the capacitance element C1 of the multiplication cell IM[i,j].

[0264] Here, the circuit ITS included in the arithmetic circuit ANP in FIG. 5 is the circuit ITS shown in FIG. 8A. At this time, the switches SA_1 to SA_n of the circuit SWCA included in the circuit WCS are each turned off, and the switches SB_1 to SB_n of the circuit SWCB included in the circuit ITS are each turned on. As a result, in the j-th column of the cell array CA, the sum of the amounts of current flowing through the multiplication cells IM[1,j] to IM[m,j] is input to the circuit ITSa_j. At this time, the amount of current I input to the circuit ITSa_j is ＳＵＭ [j] is as follows:

[0265]

[0266] That is, the amount of current flowing through the circuit ITSa_j is I ＳＵＭ [j] is determined according to the result of multiplying and accumulating the first data and the second data.

[0267] In the circuit ITSa_j, the terminal RTi_j of the conversion circuit RL_j receives the result of the above sum of products I ＳＵＭ [j] is input. As a result, the conversion circuit RL_j receives I ＳＵＭ A function system operation is performed using [j] as an input value. The conversion circuit RL_j outputs the operation result of the function system as an analog potential to the terminal RTo_j, which inputs the result to the analog-digital conversion circuit ADC. The analog-digital conversion circuit ADC converts the analog potential into digital data. The digital data is output to the outside via the wiring OL_j. This allows the arithmetic circuit ANP to perform a product-sum operation and a function system operation.

[0268] In particular, the arithmetic circuit ANP is suitable for performing calculations on a fully connected layer neural network. For example, by storing a weight coefficient as first data in the multiplication cell IM of the cell array CA of the arithmetic circuit ANP and inputting the value of the neuron's input signal as second data to the wiring XCL, a product-sum operation can be performed on the weight coefficient and the neuron's input signal. Furthermore, by using the circuit ITSa_j as an operation circuit for an activation function adopted in the fully connected layer neural network, the value of the activation function can be output using the result of the product-sum operation as an input value. This value can then be input to the next hidden layer, output layer, etc.

[0269] By performing analog operations on the fully connected layer using the arithmetic circuit ANP of the arithmetic unit CDV, it is possible to perform large-scale operations such as the sum-of-products operations in the fully connected layers FC6 to FC8 included in the AlexNet of FIG. 16 described in embodiment 4. Specifically, since a subthreshold current flows through the transistor F2 of each of the multiplication cells IM[1,1] to IM[m,n] included in the cell array CA, the power consumption per multiplication cell IM can be reduced. Therefore, the number of multiplication cells IM included in the cell array CA can be increased, and the sum-of-products operations of the fully connected layer can be performed using a single cell array CA.

[0270] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0271] Third Embodiment In this embodiment, an operation method for reducing the overall amount of calculations when performing calculations of a multilayer neural network (for example, a multilayer perceptron) in the semiconductor device described in the above embodiments will be described.

[0272] 9A to 9C are schematic diagrams illustrating an example of a lightweight multilayer neural network model. Using these diagrams, an example of applying the lightweight multilayer neural network model to the arithmetic circuit ANP of FIG. 5 described in the above embodiment will be described.

[0273] 9A to 9C, the multilayer neural network is composed of arithmetic circuits ANP[1] to ANP[4]. In Figures 9A to 9C, the polarity (positive or negative) and magnitude of the weighting coefficients are represented by the line type (solid or dotted) and thickness of the net.

[0274] 9A to 9C include a plurality of neurons. Each neuron can be one column of multiplication cells IM[1,j] to IM[m,j] and a circuit ITSa_j in the arithmetic circuit ANP shown in FIG. 5. In FIG. 9A to 9C, the multiplication cells IM[1,1] to IM[m,1] and the circuit ITSa_1 of the arithmetic circuit ANP[1] can be shown as an arithmetic unit ANPa_1, and the multiplication cells IM[1,n] to IM[m,n] and the circuit ITSa_n of the arithmetic circuit ANP[1] can be shown as an arithmetic unit ANPa_n.

[0275] First, a general deep neural network (DNN) as shown in FIG. 9A is subjected to bit reduction to reduce the number of bits of the weight coefficients. This results in a neural network as shown in FIG. 9B (the bit-reduced network is shown thinner in the figure) that has undergone bit reduction. Bit reduction increases the proportion of weight coefficients that are 0. For example, bit reduction may reduce the weight coefficients to 1 bit. By reducing the weight coefficients to 1 bit, for example, a multiplication circuit can be replaced with an addition circuit, thereby reducing the circuit size.

[0276] Next, pruning is performed on the neural network that has undergone bit reduction as shown in FIG. 9B, and nets that become 0 are removed (sometimes referred to as "pruning"). This results in the neural network that has undergone bit reduction and pruning as shown in FIG. 9C (the pruned nets are removed from the figure). The bit reduction increases the proportion of weight coefficients that become 0, and therefore the number of nets that become 0, i.e., the number of nets that can be pruned, also increases.

[0277] The neural network with bit reduction and pruning illustrated in FIG. 9C can be configured by appropriately setting the first data to 0 in each of the multiple arithmetic circuits ANP (arithmetic circuits ANP[1] through ANP[4]). In this neural network, for example, if the weighting coefficient held by the arithmetic unit ANPa_1 of the arithmetic circuit ANP[1] is 0, the first data (weighting coefficient) can be set to 0 by setting the amount of current set in the multiplication cell IM of the arithmetic unit ANPa_1 to 0. Furthermore, for example, by setting the second data (neuron output signal) input to the multiplication cell IM of the arithmetic unit ANPa_1 of the arithmetic circuit ANP[1] to 0, the result of the multiplication of the first data and the second data can be set to 0.

[0278] Therefore, for example, when all of the second data (neuron output signals) input to the calculation unit ANPa_1 included in the calculation circuit ANP[1] are set to 0, the power consumption of the circuit ITSa_1 of the calculation unit ANPa_1 included in the calculation circuit ANP can be reduced to approximately 0. Furthermore, for example, when at least one of the first data and the second data is 0 in the calculation circuit ANP[1], the power consumption of the multiplication cells IM[1,1] to IM[m,n] that multiply the first data and the second data in each of the calculation units ANPa_1 to ANPa_n included in the calculation circuit ANP[1] can be reduced to approximately 0.

[0279] In other words, a neural network constructed using the arithmetic circuit ANP can achieve the same low power consumption effect as pruning and zero skipping, without having to delete the nets removed by pruning circuitry or without having to provide a separate circuit to determine whether data is zero by zero skipping.

[0280] Note that bit reduction and pruning may result in a decrease in the inference accuracy of the neural network. To compensate for the decrease in inference accuracy, for example, all of the circuits ITSa_1 to ITSa_n in the arithmetic circuit ANP may perform calculations of any function (e.g., a sigmoid function, a tanh function, a softmax function, a ReLU function, or a threshold function).

[0281] As described in the second embodiment, each of the arithmetic units ANPa_1 to ANPa_n included in each of the arithmetic circuits ANP[1] to ANP[4] is capable of multi-bit calculations. Therefore, the neural network configured with the arithmetic circuits ANP[1] to ANP[4] can improve inference accuracy without optimizing the nonlinear function. For example, it is possible to improve the inference accuracy of a neural network that has undergone pruning by re-learning it with 8-bit weight coefficients.

[0282] The power consumption of the multiplication cell IM included in each of the arithmetic circuits ANP[1] to ANP[4] is proportional to the multiplication of the first current amount corresponding to the first data and the second current amount corresponding to the second data. Therefore, the closer each of the first data and the second data is to 0, the lower the power consumption. Therefore, the neural network configured by the arithmetic circuits ANP[1] to ANP[4] can reduce power consumption by, for example, distributing the weight coefficients more near 0 through weight decay.

[0283] A specific example of the above will be described with reference to FIGS. 10A and 10B.

[0284] 10A and 10B show the multiplication cell IM[1,j], the multiplication cell IM[m,j], and the circuit ITSa_j located in the j-th column, which are extracted from the arithmetic circuit ANP in Fig. 5. Also shown in Fig. 10A and 10B are the circuit WCS, the circuit XCS, and the control unit CTL.

[0285] The control unit CTL has a function of reading a model of the neural network on which pruning has been performed, and inputting the first data Dw[1] to Dw[m] to the arithmetic circuit ANP so that the weighting coefficient corresponding to the pruned net becomes 0. In other words, the control unit CTL has a function of setting at least one of the first data Dw[1] to Dw[m] in the arithmetic circuit ANP to 0 by pruning.

[0286] Figure 10A shows an example of pruning a portion of a net between a neuron in the previous layer and a neuron in the next layer, in which the control unit CTL writes 0 (Dw[m]="0") as the first data Dw[m] to the multiplication cell IM corresponding to the net to be pruned (in Figure 10A, the multiplication cell IM[m, j] is used as an example).

[0287] 10B shows an example in which all nets between neurons in the previous layer and neurons in the next layer are pruned by pruning, in which the control unit CTL writes 0 as the first data Dw[1] to Dw[m] to each of multiplication cells IM[1,j] to IM[m,j] via the circuit WCS. In particular, in this case, the result of the product-sum operation of all input signals input from neurons in the next layer to each neuron in the layer after next and the weighting coefficients is 0 (ΣDw[i]×Dx[i]=0).

[0288] The control unit CTL may have a function of performing, for example, learning, bit reduction, pruning, zero skipping, function optimization, weight decay, or re-learning on the arithmetic circuit ANP.

[0289] By providing a control unit CTL in the arithmetic circuit ANP and setting at least one of the first data Dw[1] to the first data Dw[m] to 0, it is possible to obtain the same low power consumption effect as pruning and zero skipping without having to delete the nets removed by pruning circuitry or providing a separate circuit to determine whether the data is zero by zero skipping.

[0290] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0291] Embodiment 4 In this embodiment, an arithmetic device according to one embodiment of the present invention will be described.

[0292] <Configuration Example of Arithmetic Device> FIG. 11 illustrates a configuration example of a calculation device CDV according to one embodiment of the present invention.

[0293] The computing unit CDV functions as an accelerator to execute a program (e.g., a kernel program). The program is called from a host program stored in a storage device external to the computing unit CDV. The computing unit CDV can perform, for example, parallel processing of matrix operations in graphics processing, parallel processing of multiply-and-accumulate operations in neural networks, or parallel processing of floating-point operations in scientific and technological calculations.

[0294] In particular, the calculation unit CDV can perform calculations on a model of a convolutional neural network. A convolutional neural network has, for example, a convolutional layer, a pooling layer, and a fully connected layer, and by inputting an image into a multilayer structure that combines these layers, feature extraction and recognition can be performed on the image.

[0295] The arithmetic device CDV includes, for example, an arithmetic circuit DGP, an arithmetic circuit ANP, and a memory circuit MEM.

[0296] The arithmetic circuit DGP is a digital arithmetic circuit that performs an arithmetic operation when digital input data is input and outputs the result of the arithmetic operation as digital data. Specifically, the arithmetic circuit DGP has a function of performing a product-sum operation in a convolution layer of a convolutional neural network, for example, and outputting the result of the product-sum operation as digital data.

[0297] The arithmetic circuit ANP is the arithmetic circuit ANP described in embodiment 2, and is an analog arithmetic circuit that performs an arithmetic operation by inputting digital input data and outputs analog data as the result of the arithmetic operation. Specifically, the arithmetic circuit ANP has a function of performing a product-sum operation in a fully connected layer of a convolutional neural network, for example, and outputting the result of the product-sum operation as analog data.

[0298] The memory circuit MEM functions as a memory circuit that stores input data for performing calculations in the calculation circuit DGP or the calculation circuit ANP, for example. The memory circuit MEM also functions as a memory circuit that stores output data that is the result of calculations performed in the calculation circuit DGP or the calculation circuit ANP, for example. In this embodiment, the memory circuit MEM is described as a memory circuit that holds digital data. When the calculation results output from the calculation circuit ANP are stored in the memory circuit MEM, the analog data that is the output data of the calculation circuit ANP is converted into digital data by a digital-to-analog conversion circuit or the like, and the digital data is stored in the memory circuit MEM.

[0299] The arithmetic circuit DGP includes, for example, a switching unit D10, an arithmetic unit D20, and a processing unit D30.

[0300] The memory circuit MEM includes, for example, memory circuit units ME11 to ME13.

[0301] The arithmetic circuit ANP includes, for example, a cell array CA, a circuit WCS, a circuit XCS, and a circuit ITS.

[0302] An input terminal TM1i of the switching unit D10 is connected to the wiring ILA, an input terminal TM2i of the switching unit D10 is connected to the wiring ILB, and an output terminal TMo of the switching unit D10 is connected to the wiring MLA.

[0303] An input terminal TN1i of the operation unit D20 is connected to a wiring MLA, an input terminal TN2i of the operation unit D20 is connected to a wiring MLB, and an output terminal TNo of the operation unit D20 is connected to a wiring CNL.

[0304] The processing unit D30 is connected to the wiring POL.

[0305] The memory circuit unit ME11 is connected to the wiring ILB. The memory circuit unit ME11 is also connected to the wiring CNL. The memory circuit unit ME11 is also connected to the wiring POL. The memory circuit unit ME11 is also connected to the wirings IXL_1 to IXL_m (m is an integer of 1 or more). The memory circuit unit ME12 is also connected to the wiring MLB. The memory circuit unit ME13 is also connected to the wirings IWL_1 to IWL_n (n is an integer of 1 or more).

[0306] Note that the wirings IXL_1 to IXL_m and the wirings IWL_1 to IWL_n are described in Embodiment 2 and are connected to the arithmetic circuit ANP in FIG. 5 .

[0307] The wirings IWL_1 to IWL_n are connected to the input terminals of the circuit WCS, respectively. The wirings WCL_1 to WCL_n are connected to the output terminals of the circuit WCS, respectively.

[0308] The wirings IXL_1 to IXL_m are connected to the input terminals of the circuit XCS, respectively. The wirings XCL_1 to XCL_m are connected to the output terminals of the circuit XCS, respectively.

[0309] 11, the wirings WCL_1 to WCL_n extend in the column direction of the cell array CA, and the wirings XCL_1 to XCL_m extend in the row direction of the cell array CA.

[0310] The cell array CA has a plurality of arithmetic cells, which are arranged in a matrix within the cell array CA. As will be described in detail later, the arithmetic cell in the i-th row and j-th column of the cell array CA (i is an integer of 1 to m, and j is an integer of 1 to n) is connected to a wiring WCL_j and a wiring XCL_i.

[0311] The wirings WCL_1 to WCL_n are connected to the input terminals of the circuit ITS, respectively. The wirings OL_1 to OL_n are connected to the output terminals of the circuit ITS, respectively.

[0312] The wiring ILA functions as, for example, a wiring for inputting input data from outside the arithmetic unit CDV to the input terminal TM1i of the switching unit D10. The input data here may be, for example, an image. In addition, in FIG. 11, the input data is an image P ｉｎ The following is stated.

[0313] For example, the wiring ILB functions as a wiring for inputting input data read from the memory circuit unit ME11 to the input terminal TM2i of the switching unit D10. Note that the input data here may be, for example, data that has been subjected to convolution processing or data that has been subjected to pooling processing. In addition, in FIG. 11, the input data is represented by "P Ｃｉｎ or P Ｐｉｎ " and P Ｃｉｎ represents the convolved data, and P Ｐｉｎ Let represent the pooled data.

[0314] The wiring MLA functions as, for example, a wiring for inputting digital data output from the output terminal TMo of the switching unit D10 to the input terminal TN1i of the calculation unit D20. In FIG. 11, the digital data is represented by "P ｉｎ , P Ｃｉｎ , or P Ｐｉｎ " it states.

[0315] For example, the wiring MLB functions as a wiring for inputting digital data read from the memory circuit unit ME12 to the input terminal TN2i of the calculation unit D20. Note that the digital data here may be, for example, a filter value for performing a convolution operation in the calculation unit D20. In addition, in FIG. 11, the filter value is denoted as K.

[0316] For example, the wiring CNL functions as a wiring for inputting digital data output from the output terminal TNo of the calculation unit D20 to the memory circuit unit ME13. Note that the digital data here may be, for example, data resulting from a convolution process performed in the calculation unit D20. In addition, in FIG. 11, the data is represented by P Ｃｏｕｔ It states:

[0317] The wiring POL functions as, for example, a wiring for inputting digital data read from the memory circuit unit ME11 to the processing unit D30. The digital data here can be, for example, data to be subjected to pooling processing in the processing unit D30. In addition, in FIG. 11, the data is represented by P Ｃ It states:

[0318] Moreover, the wiring POL may also function as a wiring for transmitting digital data processed by the processing unit D30 to the memory circuit unit ME11. Note that the digital data here may be data that has been subjected to pooling processing in the processing unit D30, for example. In addition, in FIG. 11, the data is represented by P Ｐｏｕｔ It states:

[0319] For example, the wiring IWL_1 functions as a wiring for inputting input data (which may be the first data described in the above embodiment) read from the memory circuit unit ME13 to the circuit WCS. Similarly, for example, the wiring IWL_n functions as a wiring for inputting input data read from the memory circuit unit ME13 to the circuit WCS. Note that the input data here may be, for example, one of a multiplier or a multiplicand for calculating the product of a product-sum operation in the fully connected layer in the cell array CA. In particular, here, one of the multiplier or the multiplicand is a weight coefficient. Also, in FIG. 11, the input data is W ｉｎ (1) and W ｉｎ (n) is written.

[0320] For example, the wiring IXL_1 functions as a wiring for inputting input data (which may be the second data described in the above embodiment) read from the memory circuit unit ME11 to the circuit XCS. Similarly, for example, the wiring IXL_m functions as a wiring for inputting input data read from the memory circuit unit ME11 to the circuit XCS. Note that the input data here may be, for example, the other of the multiplier and the multiplicand for calculating the product of the product-sum operation in the fully connected layer in the cell array CA. In particular, here, the other of the multiplier and the multiplicand is the value of the signal input to the neuron in the fully connected layer. Also, in FIG. 11 , the input data is X ｉｎ (1) and X ｉｎ (m) is written.

[0321] For example, the wiring OL_1 functions as a wiring for inputting digital data output from the output terminal of the first column of the circuit ITS to the memory circuit portion ME11. Similarly, for example, the wiring OL_n functions as a wiring for inputting digital data output from the output terminal of the nth column of the circuit ITS to the memory circuit portion ME11. Note that the digital data here is, for example, the value of a signal output from a neuron in a fully connected layer. In addition, in FIG. 11, the digital data is represented by X ｏｕｔ (1) and X ｏｕｔ (n) is written.

[0322] [Switching Unit D10] The switching unit D10 has a function of selecting one of the input terminals TM1i and TM2i, and outputting data input to the selected terminal to the output terminal TMo, for example. In other words, the switching unit D10 has a function of establishing a conductive state between one of the input terminals TM1i and TM2i and the output terminal TMo, and establishing a non-conductive state between the other of the input terminals TM1i and TM2i and the output terminal TMo.

[0323] 11 illustrates one each of the input terminal TM1i and the input terminal TM2i of the switching unit D10, the number of each of the input terminals TM1i and TM2i of the switching unit D10 may be more than one. Similarly, while FIG. 11 illustrates one output terminal TMo of the switching unit D10, the number of output terminals TMo of the switching unit D10 may be more than one.

[0324] [Calculation Unit D20] The calculation unit D20 has a function of calculating the product of digital data input to the input terminal TN1i and digital data input to the input terminal TN1i, for example. The calculation unit D20 also has a function of adding up the calculated products and outputting digital data corresponding to the value (product-sum result) to the output terminal TN No.

[0325] An example of the calculation unit D20 is shown in Fig. 12A. The calculation unit D20 shown in Fig. 12A includes a multiplication circuit MP, an addition circuit AP, and a register RG.

[0326] In the calculation unit D20, the multiplication circuit MP multiplies the digital data (for example, image P ｉｎ , Data P Ｃｉｎ Or Data P Ｐｉｎ ) and digital data (e.g., filter value K) input from wiring MLB. The calculation result of multiplication circuit MP is input to addition circuit AP, and the output result of addition circuit AP is held in register RG. When another product is calculated by multiplication circuit MP after the output result of addition circuit AP is held in register RG, the value of the product and the value held in register RG are added in addition circuit AP, and the result is input to register RG. This operation is repeated to perform a sum-of-products calculation. The result of the sum-of-products calculation is output to wiring CNL as digital data. Register RG is controlled by a clock signal input to wiring CLKL and a reset signal input to wiring RSTL.

[0327] For example, if the arithmetic unit D20 of FIG. 12A is configured to perform a multiply-and-accumulate operation on 8-bit input data, the digital data processed by the arithmetic unit D20 of FIG. 12A can be as shown in FIG. 12B. Specifically, when 8-bit digital data from wiring MLA and 8-bit digital data from wiring MLB are input to the multiplication circuit MP, the multiplication circuit MP outputs 16-bit digital data as the multiplication result. Furthermore, when the 16-bit digital data from the multiplication circuit MP and 17+α-bit digital data output from register RG are input to the addition circuit AP, the addition circuit AP outputs 17+α-bit digital data as the addition result. Note that α represents a carry that occurs when addition is performed in the addition circuit AP.

[0328] In the calculation device CDV of FIG. 11, the calculation unit D20 is configured to perform a product-sum calculation based on the data transmitted to each of the wirings MLA and MLB. For example, when performing a convolution process in the calculation unit D20, the same filter value (which may be referred to as a weighting coefficient, a multiplier, or a multiplicand) may be repeatedly used.

[0329] Therefore, a configuration will be described below in which a plurality of calculation units D20 shown in FIG. 12A are provided and a plurality of identical filter values ​​are used to simultaneously perform a plurality of product-sum calculations.

[0330] Fig. 13A is a configuration example showing an example of the switching unit D10 and the calculation unit D20 shown in Fig. 11. Note that Fig. 13A also shows the memory circuit unit ME12.

[0331] In FIG. 13A, the calculation unit D20 includes, for example, calculation units D20_1 to D20_k (where k is an integer of 1 or more).

[0332] 12A can be applied to the calculation units D20_1 to D20_k, for example. Specifically, the calculation unit D20_h (h is an integer between 1 and k) shown in FIG. 13B can be applied to the calculation units D20_1 to D20_k. For the calculation unit D20_h, the description of the calculation unit D20 in FIGS. 12A and 12B can be referred to.

[0333] For example, the wiring ILA includes wirings ILA_1 to ILA_k. For example, the wiring ILB includes wirings ILB_1 to ILB_k. For example, the wiring MLA includes wirings MLA_1 to MLA_k. For example, the wiring CNL includes wirings CNL_1 to CNL_k.

[0334] The plurality of output terminals TMo of the switching unit D10 are connected to the wirings MLA_1 to MLA_k in a one-to-one relationship.

[0335] An input terminal TN1i of the operation unit D20_1 is connected to the wiring MLA_1, an input terminal TN2i of the operation unit D20_1 is connected to the wiring MLB, and an output terminal TNo of the operation unit D20_1 is connected to the wiring CNL_1. An input terminal TN1i of the operation unit D20_k is connected to the wiring MLA_k, an input terminal TN2i of the operation unit D20_k is connected to the wiring MLB, and an output terminal TNo of the operation unit D20_k is connected to the wiring CNL_k.

[0336] In other words, the input terminals TN1i of the calculation units D20_1 to D20_k are connected one-to-one to the plurality of output terminals TNo of the switching unit D10.

[0337] The wirings ILA_1 to ILA_k are each connected to an image P ｉｎ A part of the area (described later) ｉｎ Specifically, for example, the wirings ILA_1 to ILA_k are connected to the wirings ILA_1 to ILA_k, respectively, to which the image P ｉｎA plurality of digital data contained in a part of the area is transmitted.

[0338] In addition, the wirings ILB_1 to ILB_k are connected to the data P Ｃｉｎ A plurality of digital data or data P included in a part of the area Ｐｉｎ Specifically, for example, the wirings ILB_1 to ILB_k are respectively connected to the wirings ILB_1 to ILB_k, and the wirings ILB_1 to ILB_k are respectively connected to the wirings ILB_1 to ILB_k. Ｃｉｎ A plurality of digital data or data P included in a part of the area Ｐｉｎ A plurality of digital data contained in a part of the area is transmitted.

[0339] For example, the switching unit D10 here has a function of selecting one of the input terminal TM1i connected to the wiring ILA_1 and the input terminal TM2i connected to the wiring ILB_1, and outputting data input to the selected terminal to the output terminal TMo connected to the wiring MLA_1. Similarly, for example, the switching unit D10 has a function of selecting one of the input terminal TM1i connected to the wiring ILA_k and the input terminal TM2i connected to the wiring ILB_k, and outputting data input to the selected terminal to the output terminal TMo connected to the wiring MLA_k.

[0340] As an example, the wiring MLA_1 functions as a wiring for inputting digital data output from the first output terminal TMo of the switching unit D10 to the input terminal TN1i of the calculation unit D20_1. Similarly, as an example, the wiring MLA_k functions as a wiring for inputting digital data output from the kth output terminal TMo of the switching unit D10 to the input terminal TN1i of the calculation unit D20_k. Note that in FIG. 13A, the digital data are written as A(1) and A(k), respectively. Also, A(1) and A(k) are the digital data of the image P ｉｎ Digital data included in a part of the data P Ｃｉｎ Digital data included in a part of the area, or data P Ｐｉｎ The digital data may be contained in a part of the area.

[0341] For example, the wiring CNL_1 functions as a wiring for inputting digital data output from the output terminal TNo of the arithmetic unit D20_1 to the memory circuit unit ME13. Similarly, for example, the wiring CNL_k functions as a wiring for inputting digital data output from the output terminal TNo of the arithmetic unit D20_k to the memory circuit unit ME13. Note that the digital data here may be, for example, data resulting from a convolution process performed in the arithmetic unit D20. In addition, in FIG. 13A , the data is represented by P Ｃｏｕｔ (1) and P Ｃｏｕｔ (k) is written. Ｃｏｕｔ Is, P Ｃｏｕｔ (1) and P Ｃｏｕｔ (k) can be combined.

[0342] By applying the configurations of the switching unit D10 and the calculation unit D20 shown in Fig. 13A to the calculation device CDV of Fig. 11, it is possible to input a plurality of identical filter values ​​to each of the calculation units D20_1 to D20_k, and to simultaneously perform product-sum operations in each of the calculation units D20_1 to D20_k. Note that the order in which data is input to the switching unit D10 and the calculation unit D20 shown in Fig. 13A will be described later.

[0343] [Processing Unit D30] The processing unit D30, for example, processes the data P read from the memory circuit unit ME11. Ｃ The processing unit D30 has a function of performing a pooling process on the data P Ｐｏｕｔ to the memory circuit unit ME11. In addition to the pooling process, the processing unit D30 may also have a function of performing function calculation and normalization. As an example of the function, an activation function may be used.

[0344] [Memory Circuit Units ME11 to ME13] The memory circuit unit ME11 stores input data (for example, data P Ｃｉｎ or P Ｐｉｎ) and the output data (for example, data P Ｃｏｕｔ ) and functions as a storage device for holding the input data (for example, filter value K) to be input to the calculation unit D20. The memory circuit unit ME13 also functions as a storage device for holding the input data WCS to be input to the circuit WCS. ｉｎ (1) to W ｉｎ (n) (e.g., weighting coefficients).

[0345] In particular, the memory circuit unit ME12 is preferably arranged near the calculation unit D20 in order to read out, for example, the filter value K and transmit it to the calculation unit D20. For example, the memory circuit unit ME12 is preferably stacked above or below the calculation unit D20.

[0346] Furthermore, the memory circuit unit ME13 is preferably arranged near the circuit WCS in order to read out the weight coefficients and transmit them to the circuit WCS, for example. For example, the memory circuit unit ME13 is preferably stacked above or below the circuit WCS.

[0347] The memory circuit MEX in FIG. 14A is an example of a circuit configuration that can be applied to each of the memory circuit units ME11 to ME13 that the arithmetic device CDV has.

[0348] 14A also shows a cell array MEA and memory cells MC[1,1], MC[u,1], MC[1,v], and MC[u,v] arranged in a matrix of u rows and v columns (u is an integer greater than or equal to 1, and v is an integer greater than or equal to 1) in the cell array MEA. Also, FIG. 14A shows wirings WWL_1 to WWL_u, wirings RWL_1 to RWL_u, wirings WBL_1 to WBL_v, and wirings RBL_1 to RBL_v. Also, FIG. 14A shows circuits WWD, RBD, WBD, and RBD. Also, FIG. 14A shows wirings DIL connected to the circuit WBD and wirings DOL connected to the circuit RBD.

[0349] The memory cell MC[1,1] arranged in the first row and first column is connected to the wirings WWL_1, RWL_1, WBL_1, and RBL_1. The memory cell MC[u,1] arranged in the uth row and first column is connected to the wirings WWL_u, RWL_u, WBL_1, and RBL_1. The memory cell MC[1,v] arranged in the first row and vth column is connected to the wirings WWL_1, RWL_1, WBL_v, and RBL_v. The memory cell MC[u,v] arranged in the uth row and vth column is connected to the wirings WWL_u, RWL_u, WBL_v, and RBL_v.

[0350] The circuit WWD is connected to each of the wirings WWL_1 to WWL_u. The circuit RWD is connected to each of the wirings RWL_1 to RWL_u. The circuit WBD is connected to each of the wirings WBL_1 to WBL_v. The circuit RBD is connected to each of the wirings RBL_1 to RBL_v.

[0351] For example, the circuit WWD functions as a write word line driver circuit. Furthermore, the circuit RWD functions as a read word line driver circuit. Furthermore, the circuit WBD functions as a write bit line driver circuit. Furthermore, the circuit RBD functions as a read bit line driver circuit.

[0352] The circuit WBD also has a function of receiving input data transmitted to the wiring DIL and transmitting the input data to a selected one of the wirings WBL_1 to WBL_v. The circuit WBD also has a function of selecting one of the wirings RBL_1 to RBL_v and transmitting read data from the memory cell MC flowing through the selected wiring to the wiring DOL.

[0353] For example, when the memory circuit MEX shown in Fig. 14A is applied to the memory circuit unit ME11 of Fig. 11, the wiring ILB is connected to the wiring DOL of Fig. 14A. Also, when the memory circuit MEX shown in Fig. 14A is applied to the memory circuit unit ME12 of Fig. 11, the wiring MLB is connected to the wiring DOL of Fig. 14A. Also, when the memory circuit MEX shown in Fig. 14A is applied to the memory circuit unit ME11 of Fig. 11, the wiring CNL is connected to the wiring DIL of Fig. 14A.

[0354] For example, when the memory circuit MEX shown in FIG. 14A is applied to the memory circuit portion ME13 in FIG. 11, any one of the wirings IWL_1 to IWL_n is connected to the wiring DOL in FIG. 14A. When the memory circuit MEX shown in FIG. 14A is applied to the memory circuit portion ME11 in FIG. 11, any one of the wirings IXL_1 to IXL_m is connected to the wiring DOL in FIG. 14A. When the memory circuit MEX shown in FIG. 14A is applied to the memory circuit portion ME11 in FIG. 11, the wirings OL_1 to OL_n are connected to the wiring DIL in FIG. 14A.

[0355] Next, a memory cell that can be applied to memory cells MC[1,1] to MC[u,v] will be described.

[0356] 14B is a diagram illustrating an example of a circuit configuration applicable to each of memory cells MC[1,1] to MC[u,v] of the memory circuit MEX. In FIG. 14B, the memory cell MC includes transistors M1, M2, M3, and a capacitor C1. The memory cell MC illustrated in FIG. 14B has a gain cell configuration including three transistors. In particular, when the transistors M1 and M3 are OS transistors, the memory cell MC may be called NOSRAM (registered trademark) (Nonvolatile Oxide Semiconductor Random Access Memory).

[0357] In particular, by using an OS transistor as at least one selected from the transistors M1 to M3, leakage current of the selected transistor can be suppressed, thereby reducing the power consumption of the arithmetic circuit. Specifically, when the transistor M1 is off, leakage current from a retention node (e.g., the first terminal of the transistor M1, the first terminal of the capacitor C1, and the gate of the transistor M2) to the wiring WBL can be significantly reduced, thereby reducing the number of refresh operations for the potential of the retention node. Furthermore, reducing the number of refresh operations can reduce the power consumption of the arithmetic circuit.

[0358] Furthermore, each of the circuit WWD, the circuit RWD, the circuit WBD, and the circuit RBD preferably includes a CMOS circuit. Furthermore, the CMOS circuit preferably includes a Si transistor. For example, when manufacturing a p-channel transistor, it is preferable to use a Si transistor rather than an OS transistor from the viewpoint of reliability. Therefore, it is preferable that the circuit WWD, the circuit RWD, the circuit WBD, and the circuit RBD are manufactured on a semiconductor substrate made of silicon, and the memory cell MC is manufactured above the circuit WWD, the circuit RWD, the circuit WBD, and the circuit RBD.

[0359] Incidentally, when semiconductor devices are highly integrated on a chip, the chip may generate heat due to the operation of the circuits. This heat generation increases the temperature of the transistor, which may change the characteristics of the transistor, resulting in changes in field-effect mobility and a decrease in operating frequency. OS transistors have higher heat resistance than Si transistors, and therefore are less susceptible to temperature-induced changes in field-effect mobility and a decrease in operating frequency. Furthermore, OS transistors tend to maintain the characteristic that their drain current increases exponentially with respect to the gate-source voltage, even at high temperatures. Therefore, by using OS transistors, it is easy to perform calculations and processing even in high-temperature environments. Therefore, when driver circuits such as a circuit WWD, a circuit RWD, a circuit WBD, and a circuit RBD are fabricated on a semiconductor substrate made of silicon to configure a semiconductor device that is resistant to heat generated by the driver circuits, it is preferable to use OS transistors as transistors included in the circuits provided above the driver circuits.

[0360] 14B illustrates backgates for the transistors M1 to M3. Although the connection configuration of the backgates is not illustrated, the electrical connection destination of the backgates can be determined at the design stage. For example, in a transistor having a backgate, in order to increase the on-state current of the transistor, the gate and the backgate may be connected, similar to the transistors F1a, F1b, F2, F5, F1Da, F1Db, F2D, and F5D shown in FIG. 3A. That is, for example, the gate and the backgate of the transistor M1 may be connected. Furthermore, in a transistor having a backgate, in order to change the threshold voltage of the transistor or reduce the off-state current of the transistor, similar to the transistors F1a, F1b, F2, F5, F1Da, F1Db, F2D, and F5D shown in FIG. 3B, a wiring for connecting the backgate of the transistor to an external circuit or the like may be provided, and a potential may be applied to the backgate of the transistor from the external circuit or the like.

[0361] 14B have back gates, the memory cell MC in FIG. 14B may have transistors M1 to M3 that do not have back gates, that is, single-gate transistors, similar to the transistors F1a, F1b, F2, F5, F1Da, F1Db, F2D, and F5D shown in FIG. 1A. Some of the transistors may have back gates, and other transistors may not have back gates.

[0362] 14B illustrates n-channel transistors as the transistors M1 to M3, the configuration of the memory cell MC is not limited to this. For example, the transistors M2 and M3 may be n-channel transistors, and the transistor M1 may be a p-channel transistor.

[0363] The first terminal of transistor M1 is connected to the gate of transistor M2 and the first terminal of capacitor C1, the second terminal of transistor M1 is connected to wiring WBL, and the gate of transistor M1 is connected to wiring WWL. The first terminal of transistor M2 is connected to the first terminal of transistor M3, and the second terminal of transistor M2 is connected to wiring CVLB. The second terminal of transistor M3 is connected to wiring RBL, and the gate of transistor M3 is connected to wiring RWL.

[0364] The wiring WWL shown in Fig. 14B can be any one of the wirings WWL_1 to WWL_u shown in Fig. 14A. The wiring RWL shown in Fig. 14B can be any one of the wirings RWL_1 to RWL_u shown in Fig. 14A. The wiring WBL shown in Fig. 14B can be any one of the wirings WBL_1 to WBL_v shown in Fig. 14A. The wiring RBL shown in Fig. 14B can be any one of the wirings RBL_1 to RBL_v shown in Fig. 14A.

[0365] The wiring CVLA also functions as a wiring that supplies a fixed potential. The fixed potential can be, for example, a high-level potential, a low-level potential, a ground potential, or a negative potential. Similarly, the wiring CVLB also functions as a wiring that supplies one of the fixed potentials listed above. Note that the potentials transmitted to the wirings CVLA and CVLB may not be fixed potentials but may be variable potentials (e.g., also referred to as pulse voltages or pulse signals), for example.

[0366] 14B, by using an OS transistor as the transistor M1, the current flowing between the source and drain of the transistor M1 in an off state (sometimes referred to as leakage current) can be made extremely small. In other words, by using an OS transistor as the transistor M1 and utilizing the extremely small leakage current characteristics, the memory cell MC shown in FIG. 14B can be used as a nonvolatile memory by holding charge corresponding to data in the memory circuit.

[0367] 14B, the memory cells MC[1,1] to MC[u,v] of the memory circuit MEX of FIG. 14A can be, for example, the memory cell MC shown in FIG. 14C. The memory cell MC of FIG. 14C differs from the memory cell MC of FIG. 14B in that the wiring WBL and the wiring RBL are combined into a single wiring BL. The configuration of the memory cell MC shown in FIG. 14C can reduce the number of wirings extending in the column direction compared to the configuration of the memory cell MC shown in FIG. 14B, thereby reducing the circuit area. Furthermore, in some cases, the recording density of the memory storage unit can be increased.

[0368] The circuit configuration applicable to the memory circuit MEX of FIG. 14A is not limited to the memory cell MC shown in FIGS. 14B and 14C . For example, the memory cell MC shown in FIG. 15A can be applied to the memory circuit MEX of FIG. 14A . In FIG. 15A , the memory cell MC includes a transistor M1 and a capacitor C1. The memory cell MC shown in FIG. 15A includes a single transistor. A circuit configured with a single transistor and a capacitor like this is sometimes called a DRAM (Dynamic Random Access Memory). In particular, when the transistor M1 is an OS transistor, the memory cell MC is sometimes called a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory).

[0369] In FIG. 15A, a memory cell MC having a transistor M1 and a capacitor element C1 is illustrated. Also, for the transistor M1, the above-described OS transistor can be used.

[0370] In FIG. 15A, the first terminal of the transistor M1 is connected to the first terminal of the capacitor element C1, the second terminal of the transistor M1 is connected to the wiring WBL, and the gate of the transistor M1 is connected to the wiring WWL. Also, the second terminal of the capacitor element C1 is connected to the wiring CVLA.

[0371] The wiring WWL shown in FIG. 15A functions as a write word line and a read word line. Therefore, when the memory cell MC of FIG. 15A is applied to the memory cell MC of the memory circuit MEX of FIG. 14A, it is preferable that the circuit WWD shown in FIG. 14A functions as a write word line driver circuit and a read word line driver circuit. Also, in this case, the memory circuit MEX of FIG. 14A may not be provided with the circuit RWD and the wirings RWL_1 to RWL_u.

[0372] Also, the wiring WBL shown in FIG. 15A functions as a write bit line and a read bit line. Therefore, when the memory cell MC of FIG. 15A is applied to the memory cell MC of the memory circuit MEX of FIG. 14A, each of the wirings WBL_1 to WBL_v shown in FIG. 14A is preferably connected to the circuit RBD. Also, in this case, the memory circuit MEX of FIG. 14A may not be provided with the wirings RBL_1 to RBL_v.

[0373] Also, a circuit configuration applicable to the memory circuit MEX of FIG. 14A may be, for example, a circuit configuration of a 2T (transistor) type NOSRAM as in the memory cell MC of FIG. 15B. In FIG. 15B, a memory circuit MEX having a transistor M1, a transistor M2, and a capacitor element C1 is illustrated. Also, for the transistor M1 and the transistor M2, the above-described OS transistor can be used.

[0374] 15B, the first terminal of transistor M1 is connected to the gate of transistor M2 and the first terminal of capacitor C1, the second terminal of transistor M1 is connected to wiring WBL, and the gate of transistor M1 is connected to wiring WWL. The first terminal of transistor M2 is connected to wiring RBL, and the second terminal of transistor M2 is connected to wiring SL. The second terminal of capacitor C1 is connected to wiring RWL.

[0375] The wiring WWL shown in Fig. 15B functions as a write word line, the wiring RWL shown in Fig. 15B functions as a read word line, the wiring WBL shown in Fig. 15B functions as a write bit line, and the wiring RBL shown in Fig. 15B functions as a read bit line.

[0376] 15B functions as a source line. A fixed potential or a variable potential may be applied to the wiring SL. An arbitrary amount of current may be applied to the wiring SL.

[0377] A circuit configuration applicable to the memory circuit MEX of Figure 14A may be, for example, a circuit combining NOSRAMs having three transistors, as in the memory cell MC of Figure 15C. The memory cell MC of Figure 15C has a memory cell MCP and a memory cell MCN. The memory cells MCP and MCN each hold data with different logic. In other words, the memory cells MCP and MCN function as complementary memory cells.

[0378] For the configurations of the memory cells MCP and MCN, refer to the description of the memory cell MC shown in Fig. 14B. Differences between the memory cells MCP and MCN shown in Fig. 15C and the memory cell MC shown in Fig. 14B will be described below.

[0379] The gates of the transistors M1 included in the memory cells MCP and MCN are connected to the wiring WWL. The second terminals of the capacitance elements C1 included in the memory cells MCP and MCN are connected to the wiring CVLA. The gates of the transistors M3 included in the memory cells MCP and MCN are connected to the wiring RWL. The second terminals of the transistors M2 included in the memory cells MCP and MCN are connected to the wiring CVLB.

[0380] In the memory cell MCP, the second terminal of the transistor M1 is connected to the wiring WBLP, and the second terminal of the transistor M3 is connected to the wiring RBLP.

[0381] In the memory cell MCN, the second terminal of the transistor M1 is connected to the wiring WBLN, and the second terminal of the transistor M3 is connected to the wiring RBLN.

[0382] The wirings WBLP and WBLN shown in Fig. 15C function as write bit lines, similar to the wiring WBL shown in Fig. 14A. The wirings RBLP and RBLN shown in Fig. 15C function as read bit lines, similar to the wiring RBL shown in Fig. 14A.

[0383] In particular, by using OS transistors for the transistors included in the memory cells MC shown in Figures 15A to 15C and OS transistors for the transistors included in each of the multiplier cells IM and driver cells IMD shown in Figures 1A to 4B, the cell array MEA shown in Figure 14A and the cell array CA of the arithmetic circuit ANP shown in Figure 5 can be manufactured using the same process. This reduces the number of processes required to manufacture the arithmetic unit CDV, thereby lowering production costs. Furthermore, by using OS transistors for the transistors included in each of the memory cells MC, multiplier cells IM, and driver cells IMD, the cell array MEA and the cell array CA can be overlapped. This reduces the circuit area of ​​the arithmetic unit CDV.

[0384] <Example of Operation of Calculation Device> Next, an example of operation of the calculation device CDV shown in Fig. 11 will be described. Note that the switching unit D10 and calculation unit D20 included in the calculation device CDV have the configuration shown in Fig. 13A.

[0385] Here, we will explain the operation of the calculation device CDV that performs the calculations of the AlexNet shown in Figure 16. The AlexNet in Figure 16 has an input layer INLY, convolutional layers CNV1 to CNV5, pooling layer PL1, pooling layer PL2, pooling layer PL5, and fully connected layers FC6 to FC8. Note that the AlexNet in Figure 16 is configured in the following order: input layer INLY, convolutional layer CNV1, pooling layer PL1, convolutional layer CNV2, pooling layer PL2, convolutional layer CNV3, convolutional layer CNV4, convolutional layer CNV5, pooling layer PL5, fully connected layer FC6, fully connected layer FC7, and fully connected layer FC8.

[0386] [Input Layer INLY] In the operation of the input layer INLY, an image P ｉｎ It is assumed that one pixel includes red, green, and blue sub-pixels, and the total number of sub-pixels is 3 colors (red, green, blue) x 224 x 224. ｉｎ The number of channels of the image P is three, namely red, green and blue. ｉｎ The number of image data to be input to the calculation unit CDV is 3×224×224.

[0387] In the calculation device CDV of FIG. 11, the image P ｉｎ Therefore, the image P ｉｎ is entered.

[0388] In this example, the image P ｉｎ In this case, the input value in the xth row and yth column included in the zth input channel (where z is an integer between 1 and 3) is expressed as p ｉｎ It is written as [x, y, z]. Note that x is the ｉｎ and y indicates the address of the row of the image P ｉｎThat is, in the input layer INLY, x is an integer between 1 and 224, and y is an integer between 1 and 224.

[0389] [Convolutional Layer CNV1] In the convolutional layer CNV1, the calculation unit D20 calculates the image P ｉｎ Specifically, a filter (also called a kernel) used in the convolution process CNV1 and the image P ｉｎ Region A selected from ｉｎ The image data included in is subjected to a multiplication and accumulation operation.

[0390] In the convolution layer CNV1, the filter size (also called kernel size) is 11, the number of output channels (also called kernel number) is 96, and the stride is 4. ｉｎ The convolution process is performed on the region selected from the above. The number of filter values ​​in one kernel is (filter size) ２ × (number of input channels) Image P ｉｎ Since the number of input channels is 3, the number of filter values ​​for one kernel in the convolution layer CNV1 is 11 × 11 × 3.

[0391] Here, the sth (here, s is an integer between 1 and 96) kernel in the convolution layer CNV1 is K Ｃ１ （ｓ） Also, kernel K Ｃ１ The filter values ​​contained in Ｃ１ （ｓ） It is written as [p, q, r], where p indicates the row address of the kernel, q indicates the column address of the kernel, and r indicates the ordinal number of the input channel. That is, in the convolution layer CNV1, p is an integer between 1 and 11, q is an integer between 1 and 11, and r is an integer between 1 and 3.

[0392] For example, in FIG. ｉｎ Region A selected from ｉｎ (1) and kernel K Ｃ１ （１） The multiplication and addition of the two is performed, and the resultant data p Ｃ１（１） This shows an example of outputting (1). ｉｎ The x in (x) is the image P ｉｎ The data p Ｃ１ （ｓ） The s in (x) indicates the ordinal number of the output channel. Ｃ１ （ｓ） The x in (x) is the area A ｉｎ (x) is the ordinal number x.

[0393] Also, since the stride is 4, area A ｉｎ The area shifted four positions in the row direction from (1) is area A. ｉｎ For example, in FIG. ｉｎ Region A selected from ｉｎ (2) and kernel K Ｃ１ （１） The multiplication and addition of the two is performed, and the resultant data p Ｃ１ （１） An example of outputting (2) is shown.

[0394] In addition, image P ｉｎ If the number of pixels in image P is 224x224 and the stride is 4, ｉｎ The number of regions to be selected is 3025 (=55 ２ ) In this embodiment, the area A ｉｎ (1) to area A ｉｎ It is called (3025).

[0395] As described above, depending on the number of strides, the image P ｉｎ The region selected from is shifted sequentially, and each time the region is shifted, the region and the kernel K Ｃ１ （１） By performing a product-sum operation with K, a matrix of output data with 55 rows and 55 columns is obtained. In addition, the kernel included in the convolution layer CNV1 is the kernel K Ｃ１ （１） Kernel K Ｃ１ （９６） (because the number of kernels in the convolutional layer CNV1 is 96), as a result, the convolutional layer CNV1 outputs 55 × 55 × 96 output data, P Ｃ１will be output.

[0396] In the convolution process in the convolution layer CNV1, for one kernel, ｉｎ For this reason, the calculation circuit may be configured to calculate the product of each of the filter values ​​included in one kernel and the image P ｉｎ It is preferable to simultaneously perform the multiplication of data included in each of the plurality of regions selected from .

[0397] For example, in the configuration of the arithmetic device CDV shown in FIGS. 11 and 13, the input terminal TN1i (wiring MLA_1) of the arithmetic unit D20_1 has a region A ｉｎ The data included in (1) is transmitted, and the input terminal TN1i (wiring MLA_2 (not shown)) of the calculation unit D20_2 (not shown) is connected to the area A ｉｎ The data included in (2) is transmitted, and the input terminal TN1i (wiring MLA_3 (not shown)) of the calculation unit D20_3 (not shown) is connected to the area A ｉｎ It is preferable that the data included in (3) is transmitted. Similarly, the wiring MLA_3025 (not shown) has a region A ｉｎ In this case, it is preferable that the k in each of the wiring MLA_k and the calculation unit D20_k shown in FIG.

[0398] A specific transmission order of each data is shown in the timing chart of Fig. 19. Fig. 19 is a timing chart showing data input to wirings MLA_1 to MLA_3 (input terminals TN1i of the operation unit D20), filter values ​​input to wirings MLB (input terminals TN2i of the operation unit D20), and data output to wirings CNL_1 to CNL_3 (output terminals TNo of the operation unit D20) from time T01 to time T04 and around those times. Note that the timing chart omits the illustration of data output to wirings MLA_4 to MLA_3025 and wirings CNL_4 to CNL_3025.

[0399] First, consider the period from time T01 to time T02.Ｃ１ （１） The filter value k Ｃ１ （１） When [1, 1, 1] is input (that is, when the filter value k Ｃ１ （１） When [1,1,1] is read, the wiring MLA_1 has p ｉｎ [1,1,1] is input, and p ｉｎ [1, 5, 1] ​​is input, and p ｉｎ It is preferable that [1, 9, 1] is input. In addition, the filter value input to the wiring MLB is k Ｃ１ （１） [1,1,1] to k Ｃ１ （１） When the filter value k is changed to [1, 2, 1] (i.e., when the filter value k is changed to [1, 2, 1]) Ｃ１ （１） When [1, 2, 1] is read out), the wiring MLA_1 has p ｉｎ [1, 2, 1] is input, and p ｉｎ [1,6,1] is input, and p ｉｎ Preferably, [1,10,1] is input.

[0400] Thus, area A ｉｎ (1) to area A ｉｎ (3025) and the kernel K Ｃ１ （１） By continuing the calculation of the product of the filter value included in ｉｎ (1) and kernel K Ｃ１ （１） p Ｃ１ （１） The calculation unit D20_2 outputs (1). ｉｎ (2) and kernel K Ｃ１ （１） p Ｃ１ （１） The calculation unit D20_3 outputs the signal (2) for the wiring CNL_3. ｉｎ (3) and kernel K Ｃ１（１） p Ｃ１ （１） (3) is output.

[0401] In addition, the p Ｃ１ （１） (1) to p Ｃ１ （１） (3025) is written to the memory circuit unit ME11.

[0402] Between time T02 and time T03, similarly to the period between time T01 and time T02, kernel K Ｃ１ （２） Using the above, area A ｉｎ (1) to area A ｉｎ (3025) are convolutionally processed. At this time, the obtained data (for example, p Ｃ１ （２） (1) to p Ｃ１ （２） (3025)) is written to the memory circuit unit ME11.

[0403] Also, Kernel K Ｃ１ （２） After the convolution process is completed, the kernel is Ｃ１ （３） Kernel K Ｃ１ （９５） Then, using each kernel, the area A ｉｎ (1) to area A ｉｎ (3025) are convolutionally processed. Ｃ１ （３） Kernel K Ｃ１ （９５） In each of the above, data output from the wirings CNL_1 to CNL_3025 is written to the memory circuit portion ME11 in the same manner as described above.

[0404] Between time T03 and time T04, similarly to the period between time T01 and time T02, kernel K Ｃ１ （９６） Using the above, area A ｉｎ (1) to area A ｉｎThen, the convolution process of each of the regions A and B is performed. ｉｎ (1) to area A ｉｎ (3025) and the kernel K Ｃ１ （９６） By continuing the calculation of the product of the filter value included in ｉｎ (1) and kernel K Ｃ１ （９６） p Ｃ１ （９６） The calculation unit D20_2 outputs (1). ｉｎ (2) and kernel K Ｃ１ （９６） p Ｃ１ （９６） The calculation unit D20_3 outputs the signal (2) for the wiring CNL_3. ｉｎ (3) and kernel K Ｃ１ （９６） p Ｃ１ （９６） (3) is output.

[0405] In addition, the p Ｃ１ （９６） (1) to p Ｃ１ （９６） (3025) is written to the memory circuit unit ME11.

[0406] As shown in the timing chart of FIG. 19, the calculation unit D20 sequentially transmits data included in the areas corresponding to the first terminals to each of the plurality of first terminals of the calculation unit D20, and sequentially transmits filter values ​​included in the kernel to the second terminal of the calculation unit D20. In this way, the calculation unit D20 calculates a plurality of areas (area A in the above example) in one kernel. ｉｎ (1) to area A ｉｎ (3025)) can be simultaneously performed. In addition, by sequentially switching the kernel and repeating the same calculation, P Ｃ１ can be obtained.

[0407] [Pooling Layer PL1] In the pooling layer PL1, P Ｃ１ Pooling is performed on the data. Pooling is a process in which predetermined regions are sequentially selected from the data output from the convolution layer, and predetermined processing is performed on each region to extract features, which are then arranged in a matrix.

[0408] As shown in FIG. 16, in the pooling layer PL1, the kernel size is set to 3, and the data P Ｃ１ It is assumed that pooling processing is performed on each region selected from the above. The stride is set to 2, and the pooling processing is maximum pooling.

[0409] For example, in FIG. 20A, data P Ｃ１ Region A selected from the first input channel of Ｃ１ｉｎ （１） In (1), the maximum pooling process is performed, and the processed data p ｐ１ （１） In this example, the kernel size is 3, so the area A Ｃ１ｉｎ （１） (1) contains 3x3 data.

[0410] In addition, area A Ｃ１ｉｎ （ｓ） (A) s is the data P Ｃ１ indicates the ordinal number of the input channel of area A Ｃ１ｉｎ （ｓ） The A in (A) is data P Ｃ１ indicates the ordinal number of the selected region from the data p ｐ１ （ｓ） In (A), s indicates the ordinal number of the output channel, and data p ｐ１ （ｓ） The A in (A) is area A Ｃ１ｉｎ （ｓ） (A) is the ordinal number A.

[0411] Also, since the stride is 2, area A Ｃ１ｉｎ （１） The area shifted two positions in the row direction from (1) is area A Ｃ１ｉｎ（１） For example, in FIG. 20B, data P Ｃ１ Region A selected from Ｃ１ｉｎ （１） In (2), the maximum pooling process is performed, and the processed data p ｐ１ （１） An example of outputting (2) is shown.

[0412] In addition, data P Ｃ１ The number of data is 55 × 55 × 96, and the stride is 2. Ｃ１ The number of regions to be selected is 729 (=27 ２ )

[0413] As described above, the data P Ｃ１ By sequentially performing pooling processing on the regions selected from the data P Ｃ１ The first input channel of the pooling layer PL1 is described above, but the second to 96th input channels are also pooled in the same way. As a result, the pooling layer PL1 outputs 27 x 27 x 96 output data P Ｐ１ will be output.

[0414] In the operation of the calculation device CDV shown in FIG. 11, for example, the memory circuit unit ME11 outputs P Ｃ１ Then, the processing unit D30 reads out the data P Ｐ１ In addition, the data P output from the processing unit D30 is Ｐ１ is written to the memory circuit unit ME11.

[0415] [Convolutional Layer CNV2] In the convolutional layer CNV2, the data P output by the pooling layer PL1 is Ｐ１ Specifically, the kernel used in the convolution process CNV2 and P Ｐ１ A multiplication and accumulation operation is performed on the data included in the selected area.

[0416] As shown in Figure 16, in the convolution layer CNV2, the kernel size is set to 5, the number of kernels is set to 256, and P Ｐ１ The convolution process is performed on the region selected from the above. The stride is set to 1.

[0417] As in the description of the convolutional layer CNV1, by performing convolution processing in the convolutional layer CNV2, the convolutional layer CNV2 outputs 27 × 27 × 256 output data, P Ｃ２ will be output.

[0418] In the operation of the calculation device CDV shown in FIG. 11, for example, the memory circuit unit ME11 outputs P Ｐ１ Then, the switching unit D10 switches the signal input from the wiring ILB so that it is transmitted to the wiring MLA, and P Ｐ１ Enter.

[0419] Similarly to the convolutional layer CNV1, the 256 kernels of the convolutional layer CNV2 are sequentially read out from the memory circuit unit ME12, and the P Ｐ１ In addition, the data P output from the calculation unit D20 is Ｃ２ is written to the memory circuit unit ME11.

[0420] [Pooling Layer PL2] In the pooling layer PL2, P Ｃ２ The pooling process is performed on the

[0421] As shown in FIG. 16, in the pooling layer PL2, the kernel size is set to 3, and the data P Ｃ２ It is assumed that pooling processing is performed on each region selected from the above. The stride is set to 2, and the pooling processing is maximum pooling.

[0422] As in the description of the pooling layer PL1, by performing pooling processing in the pooling layer PL2, the pooling layer PL2 outputs 13×13×256 output data, P Ｐ２will be output.

[0423] For the operation of the calculation unit CDV shown in FIG. 11 in the pooling layer PL2, the description of the operation of the calculation unit CDV in the pooling layer PL1 can be referred to.

[0424] [Convolutional Layer CNV3] In the convolutional layer CNV3, the data P output by the pooling layer PL2 is Ｐ２ Specifically, the kernel used in the convolution process CNV3 and P Ｐ２ A multiplication and accumulation operation is performed on the data included in the selected area.

[0425] As shown in FIG. 16, in the convolution layer CNV3, the kernel size is set to 3 and the number of kernels is set to 384. Ｐ２ The convolution process is performed on the region selected from the above. The stride is set to 1.

[0426] As in the description of the convolutional layer CNV1, by performing convolution processing in the convolutional layer CNV3, the convolutional layer CNV3 outputs 13 × 13 × 384 output data, P Ｃ３ will be output.

[0427] Furthermore, for the operation of the arithmetic unit CDV shown in FIG. 11 in the convolutional layer CNV3, the description of the operation of the arithmetic unit CDV in the convolutional layer CNV2 can be referred to.

[0428] [Convolutional Layer CNV4] In the convolutional layer CNV4, the data P output by the convolutional layer CNV3 is Ｃ３ Specifically, the kernel used in the convolution process CNV4 and P Ｃ３ A multiplication and accumulation operation is performed on the data included in the selected area.

[0429] As shown in FIG. 16, in the convolution layer CNV4, the kernel size is set to 3, the number of kernels is set to 384, and P Ｃ３ The convolution process is performed on the region selected from the above. The stride is set to 1.

[0430] As in the description of the convolutional layer CNV1, by performing convolution processing in the convolutional layer CNV4, the convolutional layer CNV4 outputs 13 × 13 × 384 output data, P Ｃ４ will be output.

[0431] Furthermore, for the operation of the arithmetic unit CDV shown in FIG. 11 in the convolutional layer CNV4, the description of the operation of the arithmetic unit CDV in the convolutional layer CNV2 can be referred to.

[0432] [Convolutional Layer CNV5] In the convolutional layer CNV5, the data P output from the convolutional layer CNV4 is Ｃ４ Specifically, the kernel used in the convolution process CNV5 and P Ｃ４ A multiplication and accumulation operation is performed on the data included in the selected area.

[0433] As shown in FIG. 16, in the convolution layer CNV5, the kernel size is set to 3, the number of kernels is set to 256, and P Ｃ４ The convolution process is performed on the region selected from the above. The stride is set to 1.

[0434] As in the description of the convolutional layer CNV1, by performing convolution processing in the convolutional layer CNV5, the convolutional layer CNV5 outputs 13 × 13 × 256 output data, P Ｃ５ will be output.

[0435] Furthermore, for the operation of the calculation unit CDV shown in FIG. 11 in the convolutional layer CNV5, the description of the operation of the calculation unit CDV in the convolutional layer CNV2 can be referred to.

[0436] [Pooling Layer PL5] In the pooling layer PL5, P Ｃ５ The pooling process is performed on the

[0437] As shown in FIG. 16, in the pooling layer PL5, the kernel size is set to 3, and the data P Ｃ５ It is assumed that pooling processing is performed on each region selected from the above. The stride is set to 2, and the pooling processing is maximum pooling.

[0438] As in the description of the pooling layer PL1, by performing pooling processing in the pooling layer PL5, the pooling layer PL5 outputs 6×6×256 output data, P Ｐ５ will be output.

[0439] Furthermore, for the operation of the calculation unit CDV shown in FIG. 11 in the pooling layer PL5, the description of the operation of the calculation unit CDV in the pooling layer PL1 can be referred to.

[0440] [Fully Connected Layer FC6] In the fully connected layer FC6, the arithmetic circuit ANP of the arithmetic unit CDV receives the output data P Ｐ５ The fully connected layer is operated on.

[0441] 16 , in the fully connected layer FC6, the number of input channels is 9126 (= 6 × 6 × 256) and the number of output channels is 4096. In the fully connected layer, a multiply-and-accumulate operation is performed on the data of all input channels and the corresponding weighting coefficients (first data) as one output channel, and the activation function value is calculated using the result as the input value. Therefore, the number of weighting coefficients (first data) required in the fully connected layer FC6 is 4096 × 9126.

[0442] The data to be output from the Nth (here, N is an integer between 1 and 4096) channel of the fully connected layer FC6 is z ＦＣ６ (N), then z ＦＣ６ (N) can be expressed by the following formula (4.1).

[0443]

[0444] where f is the activation function in the fully connected layer FC6. Examples of the activation function include a sigmoid function, a tanh function, a softmax function, a ReLU function, and a threshold function. ＦＣ６ (N) is as shown in the following formula (4.2).

[0445]

[0446] In addition, p ｐ５ （ｓ）(A) is the A-th data of the s-th output channel output in the pooling layer PL5. ＦＣ６（Ｎ） （ｓ） (A) shows the Nth channel of the fully connected layer FC6 and p ｐ５ （ｓ） (A) and the corresponding weighting coefficient (first data).

[0447] By using the above formulas (4.1) and (4.2), z ＦＣ６ (1) to z ＦＣ６ (4096) can be obtained.

[0448] It is preferable that the calculation of the fully connected layer FC6 be performed by the calculation circuit ANP of the calculation device CDV shown in Fig. 11. For the operation of the calculation circuit ANP, reference can be made to the second embodiment.

[0449] Specifically, first data (weighting coefficients), which are digital data, are read out from the memory circuit portion ME13 and input to wirings IWL_1 to IWL_n (where n is preferably an integer of 4096 or more, for example).

[0450] 6A, when the circuit WCS included in the arithmetic device CDV in FIG. 11 is the circuit WCS shown in FIG. 6A, each of the circuits WCSa_1 to WCSa_n generates a current of an amount corresponding to the value of digital data transmitted to each of the wirings IWL_1 to IWL_n. When each of the switches SA_1 to SA_n of the circuit SWCA is turned on, the current generated by each of the circuits WCSa_1 to WCSa_n flows to the wirings WCL_1 to WCL_n.

[0451] 5 , for example, by selecting row i in the cell array CA, current flows from the wirings WCL_1 to WCL_n to the multiple multiplication cells IM[i,1] to IM[i,n] arranged in the row i. Here, by maintaining the gate potential of the transistor F2 of each of the multiplication cells IM[i,1] to IM[i,n], the amount of current flowing between the source and drain of the transistor F2 can be set. Note that the setting of the amount of current to the multiplication cells IM of the cell array CA is performed from row 1 to row 9,126. Therefore, it is preferable that m, the number of rows in the cell array CA, be 9,126 or more.

[0452] Further, while currents from the wirings WCL_1 to WCL_n flow through each of the multiplication cells IM[i,1] to IM[i,n] arranged in the i-th row of the cell array CA, the circuit XCS supplies a reference current I ｒｅｆ０ This allows the amount of current flowing between the source and drain of the transistor F2d of the driving cell IMD_i to be kept at I ｒｅｆ０ The current amount to the driving cells IMD of the cell array CA is set together with the current amount to the multiplier cells IM. In other words, by setting the current amount to the multiplier cells IM of the cell array CA from the 1st row to the 9126th row, the current amount to the driving cells IMD from the 1st row to the 9126th row is also set at the same time. By the above operation, the first data (weight coefficients) in the fully connected layer FC6 is written to the multiplier cells IM of the cell array CA.

[0453] Next, after the currents of the multiplication cell IM and the driving cell IMD of the cell array CA are set, the memory circuit unit ME13 outputs P Ｐ５ When the circuit XCS included in the arithmetic device CDV in FIG. 11 is the circuit XCS shown in FIG. 6C, the digital data P Ｐ５As a result, the currents generated by the circuits XCSa_1 to XCSa_m flow through the wirings XCL_1 to XCL_m. Through the above operation, the multiplication cell IM and the driver cell IMD of the cell array CA are supplied with the second data (P Ｐ５ ) is entered.

[0454] By the above operation, the cell array CA stores the first data (weighting coefficient) and the second data (P Ｐ５ ) is multiplied and added, and u ＦＣ６ (1) to u ＦＣ６ (4096) is obtained. Also, by the circuit ITS of the arithmetic unit CDV shown in FIG. ＦＣ６ (1) to u ＦＣ６ The activation function is calculated using each of the input values ​​(4096), and z ＦＣ６ (1) to z ＦＣ６ (4096) is obtained. As a result, z ＦＣ６ (1) to z ＦＣ６ An output signal of (4096) is output. ＦＣ６ (1) to z ＦＣ６ (4096) is converted into digital data, output from the circuit ITS, and held in the memory circuit unit ME11.

[0455] [Fully connected layer FC7] In the fully connected layer FC7, z ＦＣ６ (1) to z ＦＣ６ The fully connected layer is calculated for (4096).

[0456] 16 , the fully connected layer FC7 has 4096 input channels and 4096 output channels. As with the fully connected layer FC6, the fully connected layer FC7 performs a multiply-and-accumulate operation on the data of all input channels and the corresponding weighting coefficients (first data) as one output channel, and calculates the value of an activation function using the result as the input value. Therefore, the number of weighting coefficients (first data) required in the fully connected layer FC7 is 4096×4096.

[0457] For the product-sum operation and activation function operation in the fully connected layer FC7, the description of the fully connected layer FC6 can be referred to.

[0458] In the fully connected layer FC7, the data of the output channel from the fully connected layer FC6, z ＦＣ６ (1) to z ＦＣ６ By inputting (4096), the data of the 1st to 4096th output channels of the fully connected layer FC7, z ＦＣ７ (1) to z ＦＣ７ (4096) is output.

[0459] Furthermore, for the operation of the arithmetic unit CDV shown in FIG. 11 in the fully connected layer FC7, the description of the operation of the arithmetic unit CDV in the fully connected layer FC6 can be referred to.

[0460] [Fully Connected Layer FC8] In the fully connected layer FC8, z ＦＣ７ (1) to z ＦＣ７ The fully connected layer is calculated for (4096).

[0461] 16 , the fully connected layer FC8 has 4096 input channels and 1000 output channels. As with the fully connected layer FC6, the fully connected layer FC8 performs a multiply-and-accumulate operation on the data of all input channels and the corresponding weighting coefficients (first data) as one output channel, and calculates the value of the activation function using the result as the input value. Therefore, the number of weighting coefficients (first data) required in the fully connected layer FC8 is 1000×4096.

[0462] For the product-sum operation and activation function operation in the fully connected layer FC8, the description of the fully connected layer FC6 can be referred to.

[0463] In the fully connected layer FC8, the data of the output channel from the fully connected layer FC7, z ＦＣ７ (1) to z ＦＣ７ By inputting (4096), the data of the 1st to 1000th output channels of the fully connected layer FC8, z ＦＣ８ (1) to z ＦＣ８ (1000) is output.

[0464] Furthermore, for the operation of the arithmetic unit CDV shown in FIG. 11 in the fully connected layer FC8, the description of the operation of the arithmetic unit CDV in the fully connected layer FC6 can be referred to.

[0465] As explained above, by using the calculation device CDV, it is possible to perform the AlexNet calculation shown in Fig. 16. Furthermore, by performing the convolution process by digital calculation using the calculation circuit DGP of the calculation device CDV, it is possible to reduce the frequency of updating the filter value compared to the conventional configuration, and therefore it is possible to reduce the power required to update the filter value.

[0466] Furthermore, by performing analog operations on the fully connected layer using the arithmetic circuit ANP of the arithmetic unit CDV, it is possible to perform large-scale operations, such as multiply-and-accumulate operations in the fully connected layers FC6 to FC8. Specifically, since a subthreshold current flows through the transistor F2 of each of the multiplication cells IM[1,1] to IM[m,n] included in the cell array CA, it is possible to reduce the power consumption per multiplication cell IM. This allows the number of multiplication cells IM included in the cell array CA to be increased, allowing the multiply-and-accumulate operations of the fully connected layer to be performed using a single cell array CA.

[0467] In this operation example, the operation of the calculation unit CDV performing the calculation of AlexNet shown in Fig. 16 is described, but the calculation model performed by the calculation unit CDV is not limited to AlexNet. For example, in the input layer INLY, an image P ｉｎ is input to the calculation unit CDV, but the image size may be determined arbitrarily. The number of kernels used in the convolutional layers CNV1 to CNV5 and the filter values ​​included therein may also be determined arbitrarily. A convolutional neural network other than the AlexNet calculation model of FIG. 16 may also be operated by the calculation unit CDV.

[0468] Note that one embodiment of the present invention is not limited to the arithmetic device CDV described in this embodiment. One embodiment of the present invention may be modified in accordance with the situation by changing the configuration of the arithmetic device CDV described in this embodiment.

[0469] For example, the arithmetic circuit DGP of the arithmetic device CDV shown in Fig. 11 may be changed to the configuration shown in Fig. 21A. The arithmetic circuit DGP shown in Fig. 21A differs from the arithmetic circuit DGP of Fig. 11 in that it does not have a switching unit D10 and in that it has multiple arithmetic units D20 and multiple processing units D30. Specifically, the arithmetic circuit DGP shown in Fig. 21A has arithmetic units D20[1] to D20[5], processing unit D30[1], processing unit D30[2], and processing unit D30[5].

[0470] The calculation units D20[1] to D20[5] can refer to the description of the calculation unit D20 described above. Also, the processing units D30[1], D30[2], and D30[5] can refer to the description of the processing unit D30 described above.

[0471] The arithmetic circuit DGP shown in FIG. 21A has a configuration including circuits corresponding to the input layer INLY, convolutional layers CNV1 to CNV5, pooling layer PL1, pooling layer PL2, and pooling layer PL5 of the convolutional neural network shown in FIG. 16. For example, the input layer INLY shown in FIG. 16 corresponds to the wiring ILA. Furthermore, for example, the convolutional layers CNV1 to CNV5 shown in FIG. 16 correspond to the arithmetic units D20[1] to D20[5], respectively. Furthermore, for example, the pooling layers PL1, PL2, and PL5 shown in FIG. 16 correspond to the processing units D30[1], D30[2], and D30[5], respectively. That is, in the arithmetic circuit DGP of FIG. 21A, between the wiring ILA and the memory circuit section ME11, the arithmetic section D20[1], processing section D30[1], arithmetic section D20[2], processing section D30[2], arithmetic section D20[3], arithmetic section D20[4], arithmetic section D20[5] and processing section D30[5] are arranged in this order.

[0472] When the arithmetic circuit DGP of the arithmetic unit CDV shown in FIG. 11 executes the arithmetic operations from the convolutional layer CNV1 to the pooling layer PL5 of the convolutional neural network in FIG. 16, these operations are performed by repeatedly operating one arithmetic unit D20 and one processing unit D30. On the other hand, when the arithmetic circuit DGP shown in FIG. 21A executes the arithmetic operations from the convolutional layer CNV1 to the pooling layer PL5 of the convolutional neural network in FIG. 16, these operations are performed by operating in order from the arithmetic unit D20 (convolutional layer CNV1) to the processing unit D30 (pooling layer PL5).

[0473] Although not shown in FIG. 21A, after the arithmetic operations of each layer, in order to temporarily store the output data of each layer, the arithmetic circuit DGP and the storage circuit MEM may be configured to store the output data in the memory circuit unit of the storage circuit MEM.

[0474] Further, for example, the arithmetic circuit ANP of the arithmetic unit CDV shown in FIG. 11 may be changed to the configuration shown in FIG. 21B. The arithmetic circuit ANP shown in FIG. 21B is different from the arithmetic circuit ANP in FIG. 11 in that a plurality of cell arrays CA, a plurality of circuits WCS, and a plurality of circuits ITS are provided. Specifically, the arithmetic circuit ANP shown in FIG. 21B includes cell arrays CA[6] to CA[8], circuits WCS[6] to WCS[8], a circuit XCS, and circuits ITS[6] to ITS[8].

[0475] For the cell arrays CA[6] to CA[8] in FIG. 21B, reference can be made to the description of the cell array CA shown in FIG. 11. Also, for the circuits WCS[6] to WCS[8] in FIG. 21B, reference can be made to the description of the circuit WCS shown in FIG. 11. Further, for the circuit XCS in FIG. 21B, reference can be made to the description of the circuit XCS shown in FIG. 11.

[0476] Also, for the circuits ITS[6] and ITS[7], the circuit ITS shown in FIG. 8C can be applied. For the circuit ITS[8], the circuit ITS shown in FIG. 8A or FIG. 8B can be applied.

[0477] The memory circuit unit ME13 is connected to the circuit WCS[6] via a wiring IWL[6]. The memory circuit unit ME13 is also connected to the circuit WCS[7] via a wiring IWL[7]. The memory circuit unit ME13 is also connected to the circuit WCS[8] via a wiring IWL[8].

[0478] Note that each of the wirings IWL[6] to IWL[8] can be a wiring group including a plurality of wirings. Specifically, for example, the wiring IWL[6] can be a wiring group including the wirings IWL_1 to IWL_n shown in FIG. 11. Similarly, the wiring IWL[7] can be a wiring group including the wirings IWL_1 to IWL_n shown in FIG. 11, and the wiring IWL[8] can be a wiring group including the wirings IWL_1 to IWL_n shown in FIG.

[0479] The memory circuit portion ME11 is connected to the circuit XCS through a wiring IXL. Note that the wiring IXL here can be a wiring group including a plurality of wirings. Specifically, for example, the wiring IXL can be a wiring group including the wirings IXL_1 to IXL_m shown in FIG. 11 .

[0480] The circuit WCS[6] is connected to the circuit ITS[6] via a wiring WCL[6]. The circuit WCS[7] is connected to the circuit ITS[7] via a wiring WCL[7]. The circuit WCS[8] is connected to the circuit ITS[8] via a wiring WCL[8].

[0481] Each of the wirings WCL[6] to WCL[8] can be a wiring group having a plurality of wirings. Specifically, for example, the wiring WCL[6] can be a wiring group that includes the wirings WCL_1 to WCL_n shown in FIG. 11. Similarly, the wiring WCL[7] can be a wiring group that includes the wirings WCL_1 to WCL_n shown in FIG. 11, and the wiring WCL[8] can be a wiring group that includes the wirings WCL_1 to WCL_n shown in FIG. 11. Furthermore, the wiring WCL[6] extends in the column direction of the cell array CA[6], the wiring WCL[7] extends in the column direction of the cell array CA[7], and the wiring WCL[8] extends in the column direction of the cell array CA[8].

[0482] The circuit XCS is connected to a wiring XCL[6]. The wiring XCL[6] can be a wiring group including a plurality of wirings. Specifically, for example, the wiring XCL[6] can be a wiring group including the wirings XCL_1 to XCL_m shown in FIG. 11. The wiring XCL[6] extends in the row direction of the cell array CA[6].

[0483] The circuit ITS[6] is connected to the wiring XCL[7]. The wiring XCL[7] can be a wiring group including a plurality of wirings. Specifically, for example, the wiring XCL[7] can be a wiring group including the wirings XCL_1 to XCL_m shown in FIG. 11. The wiring XCL[7] extends in the row direction of the cell array CA[7].

[0484] The circuit ITS[7] is connected to the wiring XCL[8]. The wiring XCL[8] can be a wiring group including a plurality of wirings. Specifically, for example, the wiring XCL[8] can be a wiring group including the wirings XCL_1 to XCL_m shown in FIG. 11. The wiring XCL[8] extends in the row direction of the cell array CA[8].

[0485] The circuit ITS[8] is connected to a wiring OL[8]. Note that the wiring OL[8] can be a wiring group including a plurality of wirings. Specifically, for example, the wiring OL[8] can be a wiring group including the wirings OL_1 to OL_n shown in FIG. 11 .

[0486] The arithmetic circuit ANP shown in Figure 21B has circuits corresponding to the fully connected layers FC6 to FC8 of the convolutional neural network shown in Figure 16. For example, the fully connected layer FC6 shown in Figure 16 corresponds to the cell array CA[6] and the circuit ITS[6]. Furthermore, for example, the fully connected layer FC7 shown in Figure 16 corresponds to the cell array CA[7] and the circuit ITS[7]. The fully connected layer FC8 shown in Figure 16 corresponds to the cell array CA[8] and the circuit ITS[8].

[0487] When the arithmetic circuit ANP of the arithmetic device CDV shown in Fig. 11 executes the operations of the fully connected layers FC6 to FC8 of the convolutional neural network of Fig. 16, the operations are performed by repeatedly operating one cell array CA, one circuit WCS, one circuit XCS, and one circuit ITS. On the other hand, when the arithmetic circuit ANP shown in Fig. 21B executes the operations of the fully connected layers FC6 to FC8 of the convolutional neural network of Fig. 16, the operations are performed by sequentially operating the cell arrays CA and circuits ITS corresponding to each fully connected layer.

[0488] The arithmetic circuit ANP shown in Figure 21B also differs from the arithmetic circuit ANP of the arithmetic unit CDV in Figure 11 in that analog-to-digital conversion is not performed in the circuit ITS[6] and the circuit ITS[7]. In other words, the arithmetic circuit ANP shown in Figure 21B is configured such that an analog-to-digital conversion circuit is not provided in either the circuit ITS[6] or the circuit ITS[7]. By not providing an analog-to-digital conversion circuit in either the circuit ITS[6] or the circuit ITS[7], it is possible to reduce the circuit area and power consumption of the arithmetic unit CDV.

[0489] Although not shown in Figure 21B, after the calculation of each layer, in order to temporarily store the output data of each fully connected layer, the calculation circuit ANP and the memory circuit MEM may be configured to store the output data in the memory circuit section of the memory circuit MEM.

[0490] Furthermore, for example, in this operation example, the pooling process has been described as maximum pooling, but depending on the situation, average pooling, Lp pooling, or the like may also be used.

[0491] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0492] Fifth Embodiment In this embodiment, a configuration example of the calculation device CDV described in the above embodiment will be described.

[0493] Fig. 22 is a perspective view schematically illustrating the arithmetic device CDV described in embodiment 4. The arithmetic device CDV shown in Fig. 22 includes, as an example, a circuit layer PHRL, a memory layer OMEL, and an arithmetic layer OMAL. The circuit layer PHRL is located below the memory layer OMEL, and the arithmetic layer OMAL is located above the memory layer OMEL. In other words, the arithmetic device CDV in Fig. 22 has a configuration in which, from bottom to top, the circuit layer PHRL, the memory layer OMEL, and the arithmetic layer OMAL are stacked.

[0494] FIG. 23 is a block diagram showing an example of the configuration of each of the circuit layer PHRL, memory layer OMEL, and arithmetic layer OMAL shown in FIG.

[0495] 23, the circuit layer PHRL has, for example, the switching unit D10, the calculation unit D20, and the processing unit D30 shown in Fig. 11. The memory layer OMEL has, for example, the memory circuit units ME11, ME12, and ME13 shown in Fig. 11. The calculation layer OMAL has, for example, a cell array CA, a circuit WCS, a circuit XCS, and a circuit ITS.

[0496] The circuit WCS, the circuit XCS, and the circuit ITS shown in Fig. 11 may be included in the circuit layer PHRL as shown in Fig. 24. Note that Fig. 24 excerpts the cell array CA, the circuit WCS, the circuit XCS, the circuit ITS, the memory circuit unit ME11, and the memory circuit unit ME13. Alternatively, one or more selected from the circuit WCS, the circuit XCS, and the circuit ITS shown in Fig. 11 may be included in the memory layer OMEL.

[0497] The circuit layer PHRL can be formed by, for example, providing circuit elements such as transistors and capacitors on a substrate. The substrate can be a semiconductor substrate (e.g., a single-crystal silicon substrate or a single-crystal germanium substrate). Other than semiconductor substrates, examples of usable substrates include an SOI (silicon-on-insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, laminated films, and base films include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Another example is a synthetic resin such as acrylic. Another example is polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Another example is polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, or paper. If the manufacturing process of the computing device CDV includes a heat treatment, it is preferable to select a material with high heat resistance for the substrate.

[0498] In this embodiment, the substrate included in the circuit layer PHRL will be described as a semiconductor substrate having silicon.

[0499] By using a semiconductor substrate made of silicon as the substrate included in the circuit layer PHRL, the transistors included in each of the switching unit D10, the calculation unit D20, and the processing unit D30 can be formed on the semiconductor substrate. In this case, the transistors are Si transistors. Si transistors have high field-effect mobility and can pass large on-state currents. This makes it possible to increase the drive speed of each of the above-mentioned circuits, widen the signal range, and so on. Furthermore, when the calculation device CDV has the configuration example shown in FIG. 24 , the transistors included in each of the circuits WCS, XCS, and ITS can also be formed on a semiconductor substrate made of silicon, making it possible to increase the drive speed, widen the signal range, and so on for each of the circuits WCS, XCS, and ITS.

[0500] The stacked structure of the circuit layer PHRL and the memory layer OMEL can be fabricated by forming the memory layer OMEL directly on the circuit layer PHRL, or by mounting the memory layer OMEL on a substrate on which circuit elements such as transistors and capacitive elements are provided.

[0501] When the memory layer OMEL is formed directly on the circuit layer PHRL, the memory layer OMEL preferably includes an OS transistor. Since the OS transistor can be formed not only on a semiconductor substrate but also on an insulating substrate, a conductive substrate, or even on a conductive film, an insulating film, or a semiconductor film, the OS transistor can be easily provided on the semiconductor substrate (on the circuit layer PHRL) on which the Si transistor is formed.

[0502] Furthermore, when circuit elements such as transistors and capacitors are formed on a substrate as the memory layer OMEL and the substrate is mounted on the circuit layer PHRL, flip-chip bonding or wire bonding can be used. Alternatively, a first bonding layer may be provided on the circuit layer PHRL side, a second bonding layer may be provided on the substrate of the memory layer OMEL, and the first and second bonding layers may be bonded together using one or both of a surface activated bonding method and a hydrophilic bonding method, thereby mounting the memory layer OMEL on the circuit layer PHRL. In particular, bonding in which copper (Cu) is used as the conductor contained in each of the first and second bonding layers and the copper (Cu) layers are bonded together is called Cu-Cu bonding.

[0503] <Cross-sectional Configuration Example 1> Next, a specific configuration example of the arithmetic unit CDV shown in Fig. 22 and Fig. 23 will be described. Fig. 25 is a schematic cross-sectional view of one example of the arithmetic unit CDV shown in Fig. 22 and Fig. 23.

[0504] Fig. 25 shows a cross-sectional schematic diagram of the circuit layer PHRL, the memory layer OMEL, and the arithmetic layer OMAL. Note that the arithmetic device CDV in Fig. 25 shows a configuration in which the memory layer OMEL is formed directly on the circuit layer PHRL, and the arithmetic layer OMAL is formed directly on the memory layer OMEL.

[0505] 25 illustrates a transistor 400 included in the circuit layer PHRL. The transistor 400 is provided over a substrate 311 and includes a conductive layer 316 functioning as a gate, insulating layers 315 and 317 functioning as gate insulating films, a semiconductor region 313 including part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions including part of the substrate. The transistor 400 can be a p-channel transistor or an n-channel transistor. The substrate 311 can be, for example, a single crystal silicon substrate.

[0506] Here, in the transistor 400 shown in FIG. 25 , a semiconductor region 313 (part of the substrate 311) where a channel is formed has a convex shape. A conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 interposed therebetween. Note that the conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 400 is also called a fin-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulating layer that is in contact with the top of the convex portion and functions as a mask for forming the convex portion may be provided. Here, the case where the convex portion is formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0507] Note that the transistor 400 illustrated in FIG. 25 is just an example, and the structure is not limited thereto. An appropriate transistor may be used depending on the circuit configuration or driving method.

[0508] Between each structure, a wiring layer provided with an interlayer film, wiring, and plugs may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Furthermore, in this specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.

[0509] For example, an insulating layer 320, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer film over the transistor 400. A conductive layer 328 and the like are embedded in the insulating layer 320. A conductive layer 330 and the like are embedded in the insulating layer 324 and the insulating layer 326. The conductive layer 328 and the conductive layer 330 function as contact plugs or wirings.

[0510] The insulating layer functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulating layer 320 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method to improve the planarity.

[0511] 25 , an insulating layer 350, an insulating layer 357, an insulating layer 352, and an insulating layer 354 are stacked in this order over the insulating layer 326 and the conductive layer 330. A conductive layer 356 is formed in the insulating layer 350, the insulating layer 357, and the insulating layer 352. The conductive layer 356 functions as a contact plug or a wiring.

[0512] An insulating layer 354 is provided on the insulating layer 352 and the conductive layer 356. Contact plugs or wiring may be embedded in the insulating layer 354 to connect to an upper circuit (e.g., a circuit included in the memory layer OMEL or a circuit included in the operational layer OMAL).

[0513] 25 illustrates a memory cell MC included in the memory layer OMEL. Specifically, FIG. 25 illustrates a transistor M1, a transistor M2, a transistor M3, and a capacitance element C1 included in the memory cell MC. Note that the memory cell MC may be the memory cell MC illustrated in FIG. 14C described in the above embodiment.

[0514] 25, the transistor M2 and the transistor M3 are formed on the insulating layer STJ1. The transistor M1 and the capacitance element C1 are formed on the insulating layer STJ2. The insulating layer STJ2 is located above the insulating layer STJ1. Therefore, the transistor M1 and the capacitance element C1 are located above the transistor M2 and the transistor M3.

[0515] 25, the transistors M2 and M3 are provided so as to share one fin-shaped semiconductor layer SC1. Specifically, the gate insulating film and gate electrode of the transistor M2 are formed so as to overlap one of two regions of the fin-shaped semiconductor layer SC1, and the gate insulating film and gate electrode of the transistor M3 are formed so as to overlap the other of the two regions of the fin-shaped semiconductor layer SC1.

[0516] A conductive layer functioning as a wiring CVLB is connected to one of the source electrode or drain electrode of the transistor M2. A conductive layer functioning as a wiring BL is connected to one of the source electrode or drain electrode of the transistor M5. The wiring CVLB and the wiring BL are, for example, extended in the channel width direction of the transistor M2 or the transistor M3. The conductive layer functioning as the wiring CVLB is formed so as to overlap with the fin-shaped semiconductor layer SC1, and the conductive layer functioning as the wiring BL is formed so as to overlap with the fin-shaped semiconductor layer SC1.

[0517] The conductive layer serving as the gate electrode of the transistor M3 extends in the direction of the channel width and also functions as the wiring RWL.

[0518] An insulating layer functioning as an interlayer film is formed between the transistor M1 and the transistors M2 and M3. The insulating layer has openings in a region overlapping with the gate electrode of the transistor M2 and a region overlapping with the wiring BL, and a conductive layer is embedded in each of the openings. One conductive layer is connected to one of the source electrode or drain electrode of the transistor M1, and the other conductive layer is connected to the other of the source electrode or drain electrode of the transistor M1.

[0519] As described above, the transistor M1 is located above the transistors M2 and M3. The transistor M1 also has a partial region of the fin-shaped semiconductor layer SC2. In addition, a partial region of the conductive layer that functions as one of the source electrode or drain electrode of the transistor M1 is formed with an insulating layer region that functions as the dielectric of the capacitance element C1, and a conductive layer that functions as the second terminal of the capacitance element C1 is formed in the insulating layer region. The conductive layer also functions as the wiring CVLA.

[0520] Further, as described in Embodiment 4, the potentials applied by the wiring CVLA and the wiring CVLB may be equal to each other. When the potentials applied by the wiring CVLA and the wiring CVLB are equal to each other, the wiring CVLA and the wiring CVLB may be connected to each other (not shown).

[0521] The gate insulating film and gate electrode of the transistor M1 are formed so as to overlap a portion of the fin-shaped semiconductor layer SC2 of the transistor M1. In particular, the conductive layer serving as the gate electrode of the transistor M1 extends in the channel width direction. This conductive layer also functions as the wiring WWL.

[0522] 25, a conductive layer functioning as a back gate may be provided below the insulating layer STJ2 in the transistor M1. Similarly, a conductive layer functioning as a back gate may be provided below the insulating layer STJ1 in each of the transistors M2 and M3. By providing a back gate in each transistor and changing the potential of the back gate, the threshold voltage of the transistor can be changed.

[0523] For example, by using a transistor with a back gate as the transistor M1, the influence of an external electric field can be reduced and the transistor M1 can be stably maintained in an off state. Therefore, data written to the first terminal of the capacitance element C1 can be stably held. By providing a back gate, the operation of the memory cell MC can be stabilized, and the reliability of the memory layer OMEL including the memory cell MC can be improved.

[0524] For the semiconductor layers in which the channels of the transistors M1, M2, and M3 are formed, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. As the semiconductor material, for example, silicon or germanium can be used as described in Embodiment 1. As another example, a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, an oxide semiconductor, or a nitride semiconductor can also be used.

[0525] Note that the transistors M1, M2, and M3 are preferably transistors (OS transistors) that use an oxide semiconductor, which is a type of metal oxide, in a semiconductor layer where a channel is formed. The oxide semiconductor has a band gap of 2 eV or more, and therefore has a significantly low off-state current. Therefore, the power consumption of the memory cell MC can be reduced. Therefore, the power consumption of the computing device CDV including the memory cell MC can be reduced.

[0526] A memory cell including an OS transistor can be called an "OS memory." A computing device CDV including the memory cell can also be called an "OS memory." In this case, the computing device CDV can be called a memory device.

[0527] Furthermore, the OS transistor operates stably even in a high-temperature environment, and its characteristics fluctuate little. For example, the off-state current hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an environment at room temperature, for example, from 30° C. to 200° C. Furthermore, the on-state current hardly decreases even in a high-temperature environment. Therefore, the OS memory operates stably even in a high-temperature environment, and high reliability is achieved.

[0528] 25 also illustrates a multiplication cell IM included in the arithmetic layer OMAL. Specifically, FIG. 25 illustrates transistors F1a, F1b, F2, F5, and capacitors C4 and C5 included in the multiplication cell IM. The multiplication cell IM may be the multiplication cell IM shown in FIG. 1A described in the above embodiment.

[0529] 25, in the arithmetic layer OMAL of the arithmetic unit CDV, transistors F2 and F5 are formed on an insulating layer STJ3. Transistors F1a and F1b, and capacitive elements C4 and C5 are formed on an insulating layer STJ4. In addition, insulating layer STJ4 is located above insulating layer STJ3. Therefore, transistors F1a and F1b, and capacitive elements C4 and C5 are located above transistors F2 and F5.

[0530] 25, the transistors F2 and F5 are provided so as to share one fin-shaped semiconductor layer SC3. Specifically, the gate insulating film and gate electrode of the transistor F2 are formed so as to overlap one of two regions of the fin-shaped semiconductor layer SC3, and the gate insulating film and gate electrode of the transistor F5 are formed so as to overlap the other of the two regions of the fin-shaped semiconductor layer SC3.

[0531] A conductive layer functioning as a wiring VE0 is connected to one of the source electrode or drain electrode of transistor F2. A conductive layer functioning as a wiring WCL is connected to one of the source electrode or drain electrode of transistor F5. The wiring VE0 and the wiring WCL are, for example, extended in the channel width direction of transistor F2 or transistor F5. The conductive layer functioning as the wiring VE0 is formed so as to overlap with the fin-shaped semiconductor layer SC3, and the conductive layer functioning as the wiring WCL is provided so as to overlap with the fin-shaped semiconductor layer SC3.

[0532] The conductive layer serving as the gate electrode of the transistor F2 extends in the direction of the channel width, and is shown as a wiring ME in FIG.

[0533] The conductive layer serving as the gate electrode of the transistor F5 extends in the direction of the channel width and also functions as the wiring VE1.

[0534] 26A and 26B are schematic perspective views of the transistor F2 and the transistor F5 as examples thereof. Note that Fig. 26B is a schematic perspective view in which the wiring VE0, the wiring WCL, some insulating layers, and some conductive layers are omitted from Fig. 26A.

[0535] 26A and 26B show two fin-shaped semiconductor layers SC3 each having a rectangular opening region. Therefore, it can be said that the semiconductor layer SC3 has a circumferential and fin-shaped structure. The opening may have a rectangular shape or a closed curve shape.

[0536] As shown in Figures 26A and 26B, the wiring ME and the wiring VE1 are formed so as to overlap with part of the side surfaces of the two fin-shaped semiconductor layers SC3. In this way, the wiring ME and the wiring VE1 are used to surround the semiconductor layer SC3 in which the channel is formed via a gate insulating film, thereby forming the transistors F2 and F5. This also prevents the electric field generated outside the transistor F2 or the transistor F5 from acting on the semiconductor in which the channel is formed. In other words, an electrostatic shielding function against static electricity can be added to the transistor F2 or the transistor F5. This prevents the electrical characteristics of the transistor from fluctuating due to the influence of external electric fields such as static electricity.

[0537] 26A, the wiring VE0 and the wiring WCL are formed so as to overlap with part of the side surfaces of the two fin-shaped semiconductor layers SC3. Furthermore, since a conductive layer is formed between the wiring VE0 or the wiring WCL and the semiconductor layer SC3 (not shown in FIGS. 26A and 26B), a current can flow between the wiring VE0 or the wiring WCL and the semiconductor layer SC3.

[0538] 27A and 27B are schematic perspective views of the transistor F1a and the transistor F1b as examples. Note that Fig. 27B is a schematic perspective view in which two wirings WSL and some insulating layers are omitted from Fig. 27A.

[0539] 27A and 27B show two fin-shaped semiconductor layers SC4 each having a rectangular opening region, similar to the semiconductor layer SC3. Therefore, the semiconductor layer SC4 can be said to have a circumferential and fin-shaped structure. The opening may have a rectangular shape or a closed curve shape.

[0540] As shown in Figures 26A and 26B, two wirings WSL are formed so as to overlap with part of the side surfaces of two fin-shaped semiconductors SC4. In this way, the two wirings WSL are used to surround the semiconductor layer SC4 in which the channel is formed via a gate insulating film, thereby forming transistors F1a and F1b. This also prevents electric fields generated outside transistor F1a or F1b from acting on the semiconductor in which the channel is formed. In other words, an electrostatic shielding function against static electricity can be added to transistor F1a or F1b. This prevents the electrical characteristics of the transistor from fluctuating due to the influence of external electric fields such as static electricity.

[0541] 27A and 27B, the wiring XCL is formed so as to overlap with part of the side surfaces of the two fin-shaped semiconductor layers SC4. An insulating layer (not shown in FIGS. 27A and 27B) that functions as a dielectric is formed between the wiring XCL and the semiconductor layer SC4, and thus a capacitance element C4 is formed in the region where the wiring XCL and the semiconductor layer SC4 overlap. The first terminal of the capacitance element C4 can be a conductive layer formed on the semiconductor layer SC4.

[0542] Furthermore, an insulating layer functioning as an interlayer film is formed between the transistors F2 and F5 and the transistors F1a and F1b. The insulating layer has openings in a region overlapping the wiring ME and a region overlapping the wiring WCL, and a conductive layer is embedded in each of the openings. One of the conductive layers is connected to one of the source electrode or drain electrode of the transistor Fa1, and the other conductive layer is connected to one of the source electrode or drain electrode of the transistor F1b.

[0543] As described above, the transistor F1 is located above the transistors F2 and F5. The transistor F1 also includes a portion of the fin-shaped semiconductor layer SC4. A portion of the conductive layer that functions as one of the source and drain electrodes of the transistor F1 includes an insulating layer that functions as a dielectric for the capacitor C5, and a conductive layer that functions as the second terminal of the capacitor C5 is formed in the insulating layer. The conductive layer also functions as the wiring XCL. The conductive layer that functions as the second terminal of the capacitor C5 and the conductive layer that functions as the second terminal of the capacitor C4 can each be the wiring XCL. For example, the respective conductive layers can be provided as the same wiring.

[0544] <<Configuration Example of Transistor>> Next, the structures of the transistors F1a, F1b, F2, F5, M1, M2, and M3 used in the cross-sectional view of FIG. 25 will be described.

[0545] 28A to 28D are schematic plan views and cross-sectional views illustrating the structure of a transistor 500mf that includes two fin-shaped, circumferentially shaped semiconductor layers, similar to the transistors described above. Note that, unlike the transistors described above, the transistor 500mf in FIGS. 28A to 28D does not share the same semiconductor layer with two or more transistors.

[0546] Fig. 28A is a schematic plan view of a transistor 500mf that can be used as each of transistors F1a, F1b, F2, F5, M1, M2, and M3 of the arithmetic unit CDV of Fig. 25, and Figs. 28B to 28D are schematic cross-sectional views of the transistor 500mf. In particular, Fig. 28B is a schematic cross-sectional view of the portion indicated by dashed-dotted line A1-A2 in Fig. 28A, and is also a schematic cross-sectional view of the transistor 500mf in the channel width direction. Fig. 28C is a schematic cross-sectional view of the portion indicated by dashed-dotted line A3-A4 in Fig. 28A, and is also a schematic cross-sectional view of the transistor 500mf in the channel width direction. Fig. 28D is a schematic cross-sectional view of the portion indicated by dashed-dotted line A5-A6 in Fig. 28A, and is also a schematic cross-sectional view of the transistor 500mf in the channel length direction. Here, the dashed-dotted line A5-A6 is perpendicular to the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4, respectively, and the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4 are parallel to each other. Note that in the plan view of FIG. 28A, some elements are omitted for clarity, and some elements are shown transparently. Also, FIGS. 29A and 29B show perspective views of the transistor 500mf of FIGS. 28A to 28D. Note that FIG. 29B is a perspective view in which the conductive layer 540a, the conductive layer 540b, some insulating layers, and some conductive layers are omitted from FIG. 29A. Also, FIG. 30A shows an enlarged view of the vicinity of the conductive layer 560 of FIG. 28D. Also, FIG. 30B shows an enlarged view of the vicinity of the semiconductor layer 530 of FIG. 28B. Also, FIG. 30C shows an enlarged view of the vicinity of the semiconductor layer 530 of FIG. 28C.

[0547] The transistor 500mf includes an insulating layer 516 over the insulating layer 514, an insulating layer 521 over the insulating layer 516, an insulating layer 522 over the insulating layer 521, a semiconductor layer 530 over the insulating layer 522, conductive layers 542a and 542b over the semiconductor layer 530 and the insulating layer 522, an insulating layer 550 over the semiconductor layer 530, and a conductive layer 560 (conductive layer 560a and conductive layer 560b) over the insulating layer 550. Note that hereinafter, the conductive layer 542a and the conductive layer 542b may be collectively referred to as the conductive layer 542.

[0548] An insulating layer 575 is provided over the conductive layer 542, and an insulating layer 580 is provided over the insulating layer 575. The insulating layer 550 and the conductive layer 560 are disposed inside openings provided in the insulating layer 580 and the insulating layer 575. The openings reach the semiconductor layer 530, and the insulating layer 550 is in contact with the semiconductor layer 530 within the openings. An insulating layer 582 is provided over the insulating layer 580 and the conductive layer 560. An insulating layer 583 is provided over the insulating layer 582.

[0549] An insulating layer 541a is provided in contact with the inner wall of an opening of the insulating layer 580 or the like, and a conductive layer 540a is provided in contact with the side surface of the insulating layer 541a. The bottom surface of the conductive layer 540a is in contact with the top surface of the conductive layer 542a. An insulating layer 541b is provided in contact with the inner wall of an opening of the insulating layer 580 or the like, and a conductive layer 540b is provided in contact with the side surface of the insulating layer 541b. The bottom surface of the conductive layer 540b is in contact with the top surface of the conductive layer 542b. Note that hereinafter, the conductive layers 540a and 540b may be collectively referred to as the conductive layer 540. The insulating layers 541a and 541b may be collectively referred to as the insulating layer 541.

[0550] For the insulating layers 541 a and 541 b, an insulating film having a function of suppressing oxygen permeation is preferably used to prevent a decrease in conductivity due to oxidation of the conductive layers 542 a and 542 b. For example, a silicon nitride film is preferably formed by a PEALD method.

[0551] The insulating layer 516, like the insulating layer 320, functions as a planarizing film that flattens steps caused by plugs and the like. For this reason, the insulating layer 516 can be made of a material that functions as a planarizing film like the insulating layer 320. Furthermore, by using a material with a low dielectric constant for the insulating layer 516, the parasitic capacitance between wirings can be reduced. From the above, the insulating layer 516 can be made of, for example, a material that can be used for the insulating layer IS1 described below.

[0552] Like the insulating layers 324 and 350, the insulating layers 521 and 522 are preferably insulating layers having a barrier property against one or more selected from hydrogen, oxygen, and water.

[0553] The semiconductor layer 530 has a region that functions as a channel formation region of the transistor 500mf. The conductive layer 560 has a region that functions as a first gate electrode (upper gate electrode) of the transistor 500mf. The insulating layer 550 has a region that functions as a first gate insulating film of the transistor 500mf.

[0554] In particular, a metal oxide functioning as an oxide semiconductor can be used for the semiconductor layer 530. In this case, the transistor 500mf is an OS transistor. Note that the semiconductor layer 530 can be any one or more of the above-described semiconductor layers SC1 to SC4.

[0555] An axial growth CAAC (AG CAAC) oxide semiconductor can be used for the semiconductor layer 530. The AG CAAC refers to an oxide semiconductor having a CAAC structure, which is produced in an oxide semiconductor layer including a first layer and a second layer having higher crystallinity than the first layer by solid-phase growth of a metal oxide included in the first layer using the second layer as a nucleus or seed.

[0556] For example, the first layer is preferably formed by atomic layer deposition (ALD) or chemical vapor deposition (CVD). A wet method may also be used. Furthermore, molecular beam epitaxy (MBE), a film formation method for growing a thin film having a crystal structure that reflects the crystal system of the substrate, may also be used. Examples of CVD methods include plasma enhanced CVD (PECVD), thermal CVD, photo-assisted CVD, and metal organic CVD (MOCVD). These film formation methods can cause less damage to the surface to be formed than sputtering.

[0557] Next, the second layer is preferably formed by sputtering or pulsed laser deposition (PLD). In particular, forming the second layer after the first layer can prevent a mixed layer from being formed at the interface between the first and second layers. Furthermore, impurities present on the surface on which the second layer is formed can be prevented from being mixed into the second layer. These factors further enhance the crystallinity of the second layer.

[0558] In addition, methods for solid-phase growth of the metal oxide contained in the first layer using the second layer as a nucleus or seed include, for example, heat treatment, plasma treatment, microwave (typically 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation treatment. Note that a plurality of these treatments may be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment may be performed simultaneously. Alternatively, microwave plasma treatment may be performed after heat treatment.

[0559] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0560] Furthermore, it is more preferable to perform the treatment for increasing the crystallinity of the oxide semiconductor layer multiple times during the formation of the oxide semiconductor layer. For example, when the oxide semiconductor layer is formed by an ALD method, it is preferable to perform microwave plasma treatment every time an atomic layer is formed. Alternatively, it is preferable to perform the treatment for increasing the crystallinity every time an oxide semiconductor layer having a thickness within a predetermined range is formed, in order to increase productivity. Specifically, it is preferable to form a first oxide semiconductor layer having a thickness of 1 nm to 10 nm, perform the first microwave plasma treatment, and then form a second oxide semiconductor layer having a thickness of 1 nm to 10 nm, and perform the second microwave plasma treatment. Note that the method for forming the first oxide semiconductor layer and the second oxide semiconductor layer is not particularly limited, and ALD or sputtering may be used, respectively. In particular, forming the first oxide semiconductor layer by the ALD method is preferable because it can prevent elements of the layers constituting the formation surface from being mixed (also referred to as mixing) into the first oxide semiconductor layer and the second oxide semiconductor layer. This is particularly suitable when the element contained in the layer constituting the formation surface inhibits crystallization of the oxide semiconductor (for example, when silicon, carbon, or the like is contained). The first oxide semiconductor layer and the second oxide semiconductor layer may have different compositions. Although a stacked structure of the first oxide semiconductor layer and the second oxide semiconductor layer is illustrated here, the present invention is not limited to this. The same treatment can be applied to a single oxide semiconductor layer or a stacked structure of three or more layers.

[0561] Treatment for increasing the crystallinity of the oxide semiconductor layer may be performed after the oxide semiconductor layer is formed. Specifically, the treatment may be performed directly on the formed oxide semiconductor layer, or may be performed through another film such as an insulating film formed on the oxide semiconductor layer. For example, microwave plasma treatment may be performed after the oxide semiconductor layer is formed, or an insulating film (e.g., a silicon nitride film, a silicon oxide film, or an aluminum oxide film) may be formed after the oxide semiconductor layer is formed, and then heat treatment or microwave plasma treatment may be performed on the oxide semiconductor layer through the insulating film.

[0562] Note that the treatment for increasing the crystallinity of the oxide semiconductor layer can also serve as treatment for removing impurities contained in the oxide semiconductor layer. For example, carbon, hydrogen, nitrogen, and the like contained in the oxide semiconductor layer can be preferably removed. Alternatively, by performing the treatment for increasing the crystallinity of the oxide semiconductor layer in an oxygen gas atmosphere, oxygen vacancies in the oxide semiconductor layer can be reduced.

[0563] When the treatment for increasing the crystallinity of the oxide semiconductor layer is performed, the temperature of the substrate is preferably set to room temperature (here, for example, 25° C.) or higher, 100° C. or higher and 600° C. or lower, or 300° C. or higher and 450° C. The temperature of the heat treatment is preferably set to 100° C. or higher and 700° C. or lower, or 300° C. or higher and 450° C.

[0564] By performing treatment to increase the crystallinity of the oxide semiconductor layer in addition to the above-described method for forming the oxide semiconductor layer, a highly reliable transistor can be provided.

[0565] 23B, the semiconductor layer 530 can have a structure including a semiconductor layer 530a, a semiconductor layer 530b in contact with the semiconductor layer 530a, and a semiconductor layer 530c in contact with the semiconductor layer 530b. In addition, the side surfaces of the semiconductor layer 530 (the semiconductor layers 530a to 530c) are preferably perpendicular or approximately perpendicular to the substrate surface.

[0566] As described above, in the cross section of the semiconductor layer 530 (semiconductor layers 530a to 530c) observed using a TEM image, it is confirmed that metal atoms are arranged in layers in a direction parallel to or substantially parallel to the formation surface. In other words, in the cross section of the semiconductor layer 530 (semiconductor layers 530a to 530c) observed using a TEM image, it is confirmed that metal atoms are arranged in layers in a direction perpendicular to or substantially perpendicular to the substrate surface. It can also be said that the c-axis of AG CAAC is substantially parallel to the normal direction to the side surface of the semiconductor layer 530.

[0567] In this way, by using the semiconductor layer 530 made of AG CAAC in the channel formation region of the transistor 500mf, a transistor with large on-state current, high field-effect mobility, a good S value, high frequency characteristics, and good reliability can be provided. Note that the S value is a subthreshold swing value, which indicates the amount of change in gate voltage in the subthreshold region required to change the drain current by one order of magnitude at a constant drain voltage. The smaller the S value, the steeper the slope of the drain current with respect to the gate voltage, resulting in better switching characteristics.

[0568] The semiconductor layers 530a to 530c can be formed, for example, by providing a pillar that functions as a sacrificial layer on the insulating layer 522, depositing a first semiconductor film that will become the semiconductor layer 530a, a second semiconductor film that will become the semiconductor layer 530b, and a third semiconductor film that will become the semiconductor layer 530c on the side surfaces of the pillar in this order, removing the first to third semiconductor films located on the top surfaces of the insulating layer 522 and the pillars, and then removing the pillars.

[0569] Furthermore, when the semiconductor layer 530 has a three-layer structure of semiconductor layers 530a to 530c as described above, the semiconductor layer 530 is formed in the order of semiconductor layer 530a, semiconductor layer 530b, and semiconductor layer 530c, with the region where the pillars were formed at the center. In other words, as shown in Fig. 28A , the semiconductor layer 530 has a structure that surrounds the region where the pillars were formed in plan view.

[0570] A channel formation region and a source region and a drain region sandwiching the channel formation region are formed in the semiconductor layer 530. At least a part of the channel formation region overlaps with the conductive layer 560. The source region overlaps with the conductive layer 542a, and the drain region overlaps with the conductive layer 542b. Note that the source region and the drain region can be interchanged.

[0571] The channel formation region has fewer oxygen vacancies or a lower impurity concentration than the source and drain regions, and is therefore a high-resistance region with a low carrier concentration. Therefore, the channel formation region can be said to be i-type (intrinsic) or substantially i-type.

[0572] The source and drain regions are low-resistance regions with high carrier concentrations due to a large number of oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements. That is, the source and drain regions are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region.

[0573] The carrier concentration in the channel formation region is 1×10 １８ cm −３ Below, 1 x 10 １７ cm −３ Less than 1 x 10 １６ cm −３ Less than 1 x 10 １５ cm −３ Less than 1 x 10 １４ cm −３ Less than 1 x 10 １３ cm −３ Less than 1 x 10 １２ cm −３ Less than 1 x 10 １１ cm −３ Less than or 1 x 10 １０ cm −３ The lower limit of the carrier concentration in the channel formation region is not particularly limited, but is preferably less than 1×10 −９ cm −３ It can be said that:

[0574] Note that when the carrier concentration of the semiconductor layer 530 is reduced, the impurity concentration in the semiconductor layer 530 is reduced to reduce the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or metal oxide). Note that an oxide semiconductor (or metal oxide) with a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or metal oxide).

[0575] In order to stabilize the electrical characteristics of the transistor 500mf, it is effective to reduce the impurity concentration in the channel formation region in the semiconductor layer 530. Furthermore, in order to reduce the impurity concentration in the semiconductor layer 530, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that the impurities in the semiconductor layer 530 refer to, for example, elements other than the main components constituting the semiconductor layer 530. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0576] Furthermore, it may be difficult to clearly detect the boundaries between regions in the semiconductor layer 530. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may vary continuously within each region, rather than varying stepwise from region to region. That is, the concentrations of metal elements and impurity elements such as hydrogen and nitrogen may decrease in regions closer to the channel formation region.

[0577] In a transistor using an oxide semiconductor for the semiconductor layer 530, impurities and oxygen vacancies are present in a region where a channel is formed in the oxide semiconductor, and the transistor's electrical characteristics are likely to fluctuate, which may result in poor reliability. Ｏ H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor is likely to be normally on. Therefore, in the channel formation region of the oxide semiconductor, impurities, oxygen vacancies, and V Ｏ It is preferable that H be reduced as much as possible. In other words, it is preferable that the carrier concentration of a channel formation region in the oxide semiconductor be reduced and that the channel formation region be i-type (intrinsic) or substantially i-type.

[0578] In response to this problem, an insulating layer containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed. This allows oxygen to be supplied from the insulating layer to the oxide semiconductor, thereby eliminating oxygen vacancies and V ＯH can be reduced. However, if an excessive amount of oxygen is supplied to the source region or drain region, the on-state current or field-effect mobility of the transistor 500 mf may decrease. Furthermore, variations in the amount of oxygen supplied to the source region or drain region within the substrate surface may cause variations in the characteristics of a semiconductor device including the transistor. Furthermore, if oxygen supplied from the insulating layer to the oxide semiconductor diffuses into a conductive layer such as a gate electrode, a source electrode, or a drain electrode, the conductive layer may be oxidized, resulting in a loss of conductivity, which may adversely affect the electrical characteristics and reliability of the transistor.

[0579] Therefore, in the oxide semiconductor, the channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, and the source and drain regions preferably have a high carrier concentration and are n-type. Ｏ It is also preferable to prevent an excessive amount of oxygen from being supplied to the source and drain regions, and to reduce V Ｏ It is preferable to prevent the amount of H from being reduced excessively. Furthermore, it is preferable to suppress a decrease in the conductivity of the conductive layer 560, the conductive layer 542a, the conductive layer 542b, and the like. For example, it is preferable to suppress oxidation of the conductive layer 560, the conductive layer 542a, the conductive layer 542b, and the like. Note that hydrogen in the oxide semiconductor is converted into V Ｏ H can be formed, so V Ｏ To reduce the amount of H, it is necessary to reduce the hydrogen concentration.

[0580] As shown in FIG. 30B , the insulating layer 550 includes an insulating layer 550a, an insulating layer 550b, an insulating layer 550c, and an insulating layer 550d. The insulating layers 550a to 550d function as part of the first gate insulating film. The insulating layers 550a to 550d are provided in an opening formed in the insulating layer 580, similar to the conductive layer 560 described later. To miniaturize the transistor 500mf, the insulating layers 550a to 550d are preferably thin. The thicknesses of the insulating layers 550a to 550d are preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, still more preferably 1.0 nm to less than 5.0 nm, and even more preferably 1.0 nm to 3.0 nm. Note that it is only necessary that at least a part of each of the insulating layers 550a to 550d has a region with the above-described thickness.

[0581] The thickness of the silicon oxide film used as the insulating layer 550 is preferably 0.7 nm to 3 nm.

[0582] In order to thin the insulating layers 550a to 550d as described above, it is preferable to form the insulating layers 550a to 550d by atomic layer deposition (ALD). Furthermore, it is preferable to form the insulating layers 550a to 550d in openings in the insulating layer 580 or the like by ALD. Examples of ALD methods include thermal ALD, in which a precursor and a reactant are reacted using only thermal energy, and PEALD, in which a plasma-excited reactant is used. The PEALD method may be preferable because it uses plasma, which enables film formation at a lower temperature.

[0583] The ALD method can deposit atoms layer by layer, and therefore has the following advantages: it is possible to form an extremely thin film, it is possible to form a film on a structure with a high aspect ratio, it is possible to form a film with few defects such as pinholes, it is possible to form a film with excellent coverage, it is possible to form a film at a low temperature, etc. Therefore, the insulating layer 550 can be formed with good coverage on the side surface of the opening formed in the insulating layer 580 and with the thin film thickness as described above.

[0584] Note that some precursors used in the ALD method contain carbon and the like. Therefore, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Note that the quantity of impurities can be determined using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0585] Although the insulating layer 550 has been described above as having a four-layer structure of insulating layers 550a to 550d, the present invention is not limited to this. The insulating layer 550 may have a structure including at least one of the insulating layers 550a to 550d. By forming the insulating layer 550 using one, two, or three of the insulating layers 550a to 550d, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0586] For example, insulating layer 550 may have a three-layer structure. In this case, insulating layer 550 preferably has a stacked structure of insulating layer 550a, insulating layer 550b on insulating layer 550a, and insulating layer 550c on insulating layer 550b. In other words, this structure is the same as the structure shown in FIG. 30A except that insulating layer 550d is removed.

[0587] It is preferable to use the ALD process two or more times in forming the insulating layer 550. For example, the insulating layer 550 preferably has a stacked structure of a plurality of insulating films, and it is preferable that two or more of the plurality of insulating films are formed using the ALD process. By forming at least two or more insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 550. Furthermore, it is possible to increase productivity by successively forming two or more different films, for example, two or more insulating films, using the ALD process.

[0588] For example, the insulating layer 550a is preferably made of aluminum oxide, which has a high ability to capture or fix hydrogen. The insulating layer 550b is preferably made of silicon oxide, which has a high dielectric strength. The insulating layer 550c is preferably made of hafnium oxide, which has a high ability to capture or fix hydrogen. The insulating layer 550d is preferably made of silicon nitride, which has a high hydrogen barrier property.

[0589] 28D and other figures show the conductive layer 560 as having a two-layer structure. Here, the conductive layer 560 preferably includes a conductive layer 560a and a conductive layer 560b disposed on the conductive layer 560a. For example, the conductive layer 560a is preferably disposed so as to surround the bottom and side surfaces of the conductive layer 560b. In this case, the conductive layer 560a is preferably made of a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion.

[0590] The conductive layer 560a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms, oxygen molecules, etc.).

[0591] Furthermore, since the conductive layer 560a has the function of suppressing oxygen diffusion, it is possible to suppress the conductive layer 560b from being oxidized by oxygen contained in the insulating layer 580 or the like, which would cause a decrease in conductivity. Examples of conductive materials that have the function of suppressing oxygen diffusion include preferably titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Furthermore, the conductive layer 560a may be made of a material that can be used for the conductive layer ME1 described above.

[0592] Furthermore, it is preferable that the conductive layer 560b be a conductive layer with high conductivity. For example, the conductive layer 560b can be made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductive layer 560b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material. The conductive layer 560b may also be made of a material that can be used for the conductive layer ME1 described above.

[0593] In the transistor 500mf, the conductive layer 560 is formed in a self-aligned manner to fill an opening formed in the insulating layer 580 or the like. Here, the side surfaces of the insulating layer 580 in the openings coincide or substantially coincide with the side surfaces of the conductive layers 542a and 542b. Therefore, the conductive layer 560 can be arranged to overlap the region between the conductive layers 542a and 542b without alignment.

[0594] The conductive layer 542a has a region functioning as one of the source electrode and drain electrode of the transistor 500mf. The conductive layer 540a functions as a plug connected to the conductive layer 542a. The conductive layer 542b has a region functioning as the other of the source electrode and drain electrode of the transistor 500mf. The conductive layer 540b functions as a plug connected to the conductive layer 542b.

[0595] For the conductive layers 542a and 542b, it is preferable to use, for example, a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layers 542a and 542b. When a conductive material containing metal and nitrogen is used for the conductive layers 542a and 542b, the conductive layers 542a and 542b become conductive layers containing at least metal and nitrogen. For example, the material used for the conductive layers 542a and 542b can be selected from the materials that can be used for the conductive layer ME1 described above, such as a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion.

[0596] The conductive layers 540a and 540b are preferably made of a conductive material containing, for example, tungsten, copper, or aluminum as a main component. The conductive layer 540 may also have a layered structure in which a first conductive layer is provided in contact with the side surface of the insulating layer 541 and a second conductive layer is provided further inside. In this case, the above-mentioned conductive material may be used as the second conductive layer. The conductive layers 540a and 540b may also be made of a material applicable to the above-mentioned conductive layer ME1. Here, the first conductive layer corresponds to the conductive layer 540a1 shown in FIG. 30A , and the second conductive layer corresponds to the conductive layer 540a2 shown in FIG. 30A .

[0597] Furthermore, when the conductive layer 540 has a stacked structure, a first conductive layer disposed near the insulating layer 583, the insulating layer 582, the insulating layer 580, and the insulating layer 575 is preferably made of a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used. Furthermore, a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a stacked layer. With such a structure, impurities such as water and hydrogen contained in layers above the insulating layer 583 can be prevented from entering the semiconductor layer 530 through the conductive layer 540a and the conductive layer 540b.

[0598] For example, the insulating layer 575 is preferably a barrier insulating film against oxygen. Examples of the barrier insulating film against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0599] For example, the insulating layer 580 preferably has a lower dielectric constant than the insulating layer 522. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance occurring between wirings can be reduced. For this reason, the insulating layer 580 preferably uses, as a material with a low dielectric constant, one or more of silicon oxide, silicon oxynitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, and silicon oxide having vacancies.

[0600] In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0601] The upper surfaces of the insulating layers 580 may be planarized, and in this case, the insulating layers 580 also function as planarizing films.

[0602] As described above, the insulating layer 580 can be formed using a material similar to that of the insulating layer 516 .

[0603] One or both of the insulating layers 582 and 583 preferably function as a barrier insulating layer that suppresses diffusion of oxygen from above the insulating layers 582 and 583 to the transistor 500mf or the like. Therefore, one or both of the insulating layers 582 and 583 can be resistant to hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (for example, copper atoms, copper molecules, etc.) (the impurities are less likely to permeate through the insulating material), or it is preferable to have an insulating material that has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate through the insulating material).

[0604] The insulating layers 582 and 583 preferably have an insulating layer that has a function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen, and can be made of, for example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, silicon nitride, or silicon nitride oxide. For example, the insulating layer 583 is preferably made of silicon nitride, which has a higher hydrogen barrier property. For example, the insulating layer 582 is preferably made of aluminum oxide, which has a high ability to capture or fix hydrogen.

[0605] The semiconductor layer 530 is formed on and in contact with the insulating layer 522. As shown in Figures 30B and 30C, the semiconductor layer 530 has a shape with a high aspect ratio when viewed cross-sectionally in the channel width direction. For this reason, the semiconductor layer 530 can also be said to have a fin-like shape.

[0606] Here, the aspect ratio of the semiconductor layer 530 in a cross-sectional view in the channel width direction refers to the ratio of the length L of the semiconductor layer 530 in the direction of the dashed dotted line A1-A2 (which can also be referred to as the width L of the semiconductor layer 530) to the length H of the semiconductor layer 530 in a direction perpendicular to the surface on which the semiconductor layer 530 is formed (e.g., the insulating layer 522) (which can also be referred to as the height H of the semiconductor layer 530). The aspect ratio of the semiconductor layer 530 is preferably as large as possible within a range in which the semiconductor layer 530 does not collapse during the manufacturing process of the transistor 500mf. In the semiconductor layer 530, the height H of the semiconductor layer 530 is at least longer than the width L of the semiconductor layer 530. The height H of the semiconductor layer 530 is preferably greater than 1 time and less than 400 times the width L of the semiconductor layer 530, more preferably between 2 times and 100 times, even more preferably between 5 times and 40 times, and even more preferably between 10 times and 20 times. Furthermore, for example, the height H may be two to ten times the width L. For example, the width L is preferably 5 nm to 100 nm, more preferably 5 nm to 50 nm, and even more preferably 10 nm to 30 nm. For example, the height H is preferably 50 nm to 2000 nm, and more preferably 100 nm to 1000 nm. For example, the height H may be 50 nm to 100 nm.

[0607] 30B , in a cross-sectional view in the channel width direction, the angle θ between the side surface of the semiconductor layer 530 and the top surface of the insulating layer 522 is preferably perpendicular or approximately perpendicular. For example, the angle θ is preferably 80° to 100°, more preferably 85° to 95°.

[0608] An insulating layer 550, a conductive layer 560, and a conductive layer 542 are provided to cover the semiconductor layer 530 having such a high aspect ratio. In the transistor 500mf, as shown in FIG. 30B , a portion of the insulating layer 550 and a portion of the conductive layer 560 are provided so as to sandwich the semiconductor layer 530 in two. As a result, in a cross-sectional view in the channel width direction, the semiconductor layer 530 and the conductive layer 560 are provided facing each other with the insulating layer 550 sandwiched between the upper portion, the side surface on the A1 side, and the side surface on the A2 side of the semiconduct...

Claims

A first cell and a second cell, the first cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitance element, and a second capacitance element; the second cell includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a third capacitive element, and a fourth capacitive element; one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and to a first terminal of the first capacitive element; the other of the source and the drain of the second transistor is electrically connected to the gate of the third transistor and to a first terminal of the second capacitive element; one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor; one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor and to a first terminal of the third capacitive element; the other of the source and the drain of the sixth transistor is electrically connected to the gate of the seventh transistor and a first terminal of the fourth capacitive element; one of a source and a drain of the seventh transistor is electrically connected to one of a source and a drain of the eighth transistor; the other of the source and the drain of the first transistor and the other of the source and the drain of the fourth transistor are each electrically connected to a first wiring; the other of the source and the drain of the fifth transistor, the other of the source and the drain of the eighth transistor, a second terminal of the first capacitance element, a second terminal of the second capacitance element, a second terminal of the third capacitance element, and a second terminal of the fourth capacitance element are electrically connected to a second wiring; a gate of the first transistor, a gate of the second transistor, a gate of the fifth transistor, and a gate of the sixth transistor are electrically connected to a third wiring; Multiplication circuit. 　 A first cell and a second cell, the first cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitance element, and a second capacitance element; the second cell includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a third capacitive element, and a fourth capacitive element; one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and to a first terminal of the first capacitive element; the other of the source and the drain of the second transistor is electrically connected to the gate of the third transistor and to a first terminal of the second capacitive element; one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor; one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor and to a first terminal of the third capacitive element; the other of the source and the drain of the sixth transistor is electrically connected to the gate of the seventh transistor and a first terminal of the fourth capacitive element; one of a source and a drain of the seventh transistor is electrically connected to one of a source and a drain of the eighth transistor; the other of the source and the drain of the first transistor and the other of the source and the drain of the fourth transistor are each electrically connected to a first wiring; the other of the source and the drain of the fifth transistor, the other of the source and the drain of the eighth transistor, a second terminal of the first capacitance element, a second terminal of the second capacitance element, a second terminal of the third capacitance element, and a second terminal of the fourth capacitance element are each electrically connected to a second wiring; a gate of the first transistor and a gate of the fifth transistor are electrically connected to a third wiring; a gate of the second transistor and a gate of the sixth transistor are electrically connected to a fourth wiring; Multiplication circuit. 　 In claim 1 or 2, a capacitance value of the second capacitance element is greater than a capacitance value of the first capacitance element; The capacitance value of the fourth capacitance element is greater than the capacitance value of the third capacitance element. Multiplication circuit. 　 In claim 3, each of the first to eighth transistors includes an oxide semiconductor in a channel formation region; the oxide semiconductor contains one or more selected from indium, zinc, and an element M; The element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony; Multiplication circuit. 　 In claim 4, the second cell has a function of holding a potential of a gate of the seventh transistor so that a reference current flows between a source and a drain of the seventh transistor; the first cell has a function of holding a potential of a gate of the third transistor so that a first current flows between a source and a drain of the third transistor; the first cell has a function of changing a potential of a gate of the seventh transistor by capacitive coupling by the fourth capacitive element to change the reference current flowing between the source and drain of the seventh transistor to a second current, thereby amplifying the first current flowing between the source and drain of the third transistor to a third current in accordance with a ratio between the reference current and the second current; Multiplication circuit. 　 A multiplication circuit according to claim 5, a first circuit, a second circuit, and a third circuit, Each of the plurality of multiplication circuits is electrically connected to the same first wiring, the plurality of multiplication circuits are electrically connected to different second wirings, the first circuit has a function of generating the first current according to first data and inputting the first current to one selected from the plurality of multiplication circuits via the first wiring; the second circuit has a function of generating the second current according to second data and inputting the second current to the multiplication circuit electrically connected to one of the plurality of second wirings; the third circuit has a function of performing a nonlinear function operation using a sum of the third currents flowing through the first wiring in each of the plurality of multiplication circuits as an input value, and outputting the result of the operation; Arithmetic circuit. 　 An electronic device comprising the arithmetic circuit according to claim 6 and a housing. 　 A first cell and a second cell, the first cell includes K (K is an integer equal to or greater than 3) first transistors, a second transistor, a third transistor, and K-1 first capacitance elements and a second capacitance element; the second cell includes L fourth transistors (L is an integer equal to or greater than 3), a fifth transistor, a sixth transistor, L-1 third capacitance elements, and a fourth capacitance element; the K first transistors are electrically connected in series; the K first transistors are electrically connected in series, and a first terminal of the first capacitance element is electrically connected to each of connection points of two adjacent first transistors; one of both ends of the K first transistors electrically connected in series is electrically connected to the gate of the second transistor and a first terminal of the second capacitive element; one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor; the L fourth transistors are electrically connected in series; the L number of the fourth transistors electrically connected in series is such that a first terminal of the third capacitance element is electrically connected to each of connection points of two successive fourth transistors, one of both ends of the L fourth transistors electrically connected in series is electrically connected to the gate of the fifth transistor and the first terminal of the fourth capacitive element; one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor; the other of both ends of the K first transistors electrically connected in series and the other of the source and drain of the third transistor are electrically connected to a first wiring; the other of both ends of the L fourth transistors electrically connected in series, the other of the source and drain of the sixth transistor, each of the second terminals of the K-1 first capacitance elements, the second terminal of the second capacitance element, each of the second terminals of the L-1 third capacitance elements, and the second terminal of the fourth capacitance element are electrically connected to a second wiring; each of the K gates of the first transistors and each of the L gates of the fourth transistors are electrically connected to a third wiring; Multiplication circuit. 　 In claim 8, each of the first to sixth transistors includes an oxide semiconductor in a channel formation region; the oxide semiconductor contains one or more selected from indium, zinc, and an element M; The element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony; Multiplication circuit. 　 In claim 9, the second cell has a function of holding a potential of a gate of the fifth transistor so that a reference current flows between a source and a drain of the fifth transistor; the first cell has a function of holding a potential of a gate of the second transistor so that a first current flows between a source and a drain of the second transistor; the first cell has a function of changing a potential of a gate of the fifth transistor by capacitive coupling by the fourth capacitive element to change the reference current flowing between the source and drain of the fifth transistor to a second current, thereby amplifying the first current flowing between the source and drain of the second transistor to a third current in accordance with a ratio between the reference current and the second current; Multiplication circuit. 　 A multiplication circuit according to claim 10, a first circuit, a second circuit, and a third circuit, Each of the plurality of multiplication circuits is electrically connected to the same first wiring, the plurality of multiplication circuits are electrically connected to the plurality of second wirings different from one another; the first circuit has a function of generating the first current according to first data and inputting the first current to one selected from the plurality of multiplication circuits via the first wiring; the second circuit has a function of generating the second current according to second data and inputting the second current to the multiplication circuit electrically connected to one of the plurality of second wirings; the third circuit has a function of performing a nonlinear function operation using a sum of the third currents flowing through the first wiring in each of the plurality of multiplication circuits as an input value, and outputting the result of the operation; Arithmetic circuit. 　 An electronic device comprising the arithmetic circuit according to claim 11 and a housing.

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