Semiconductor device

Abstract

Provided is a semiconductor device including transistors of a very small size. The semiconductor device includes first and second transistors, and first and second insulating layers. Both of the two transistors are vertical transistors, and the second transistor is provided overlapping the first transistor. One (a first conductive layer) of the source electrode and the drain electrode of the first transistor, the first insulating layer, and the other (a second conductive layer) of the source electrode and the drain electrode of the first transistor are provided in this order, and these components have an overlapping region. An opening reaching the first conductive layer is provided in the second conductive layer and the first insulating layer, and a semiconductor layer, a gate insulating layer, and a gate electrode are provided in this order in contact with the side wall and the bottom surface of the opening. The second insulating layer is provided so as to fill a recess in the gate electrode of the first transistor, and one of the source electrode and the drain electrode of the second transistor is provided on and in contact with the gate electrode.

Description

Semiconductor Devices

[0001] 1. Field of the Invention One embodiment of the present invention relates to a transistor, a semiconductor device, a display device, a display module, and an electronic device. 1. Field of the Invention One embodiment of the present invention relates to a method for manufacturing a transistor, a method for manufacturing a semiconductor device, and a method for manufacturing a display device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), an electronic device including any of these devices, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may themselves be semiconductor devices and each may have a semiconductor device.

[0004] Semiconductor devices having transistors are widely used in display devices and electronic devices, and there is a demand for semiconductor devices with higher integration and faster speeds. For example, when semiconductor devices are applied to high-resolution display devices, semiconductor devices with higher integration levels are required. As one means for increasing the integration level of transistors, development of fine-sized transistors is underway.

[0005] In recent years, there has been a demand for display devices applicable to virtual reality (VR), augmented reality (AR), substitutional reality (SR), or mixed reality (MR). VR, AR, SR, and MR are collectively referred to as XR (Extended Reality). Display devices for XR are desired to have high resolution and high color reproducibility in order to enhance the sense of realism and immersion. Examples of display devices applicable to such devices include liquid crystal display devices, organic electroluminescence (EL) devices, and light-emitting devices including light-emitting devices (also referred to as light-emitting elements) such as light-emitting diodes (LEDs).

[0006] Patent Document 1 discloses a display device for VR that uses an organic EL device (also called an organic EL element).

[0007] International Publication No. 2018 / 087625

[0008] An object of one embodiment of the present invention is to provide a semiconductor device including a micro-sized transistor and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a small-sized semiconductor device and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device including a transistor with high on-state current and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a manufacturing method of a semiconductor device with high productivity. Another object of one embodiment of the present invention is to provide a novel semiconductor device and a manufacturing method thereof.

[0009] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0010] To further increase the integration density of semiconductor devices, it is effective to miniaturize transistors included in the semiconductor device and to devise a layout for the transistors. For example, it is effective to arrange multiple transistors included in a semiconductor device by stacking them vertically with respect to a substrate surface rather than arranging them on the same plane. This allows for increased integration of semiconductor devices without increasing the area occupied by the transistors within the substrate surface. On the other hand, when transistors are stacked, if a lower transistor has a large unevenness, the surface on which the transistor is formed will also have unevenness, making it difficult to form fine transistors by stacking them. Therefore, it is preferable that the surface on which the transistor is formed be as flat as possible. Therefore, one embodiment of the present invention provides a semiconductor device including transistors whose upper surface unevenness is planarized by an insulating layer, and a manufacturing method thereof.

[0011] One embodiment of the present invention has a function as part of a sequential circuit. The sequential circuit includes a first transistor, a second transistor, a first insulating layer, a second insulating layer, and a third insulating layer. The first transistor includes a first semiconductor layer, a first conductive layer, a second conductive layer, a gate insulating layer, and a gate electrode. The second transistor includes a second semiconductor layer, a third conductive layer, and a fourth conductive layer. The first insulating layer is provided over the first conductive layer, and the second conductive layer is provided over the first insulating layer. The first insulating layer and the second conductive layer each have a first opening reaching the first conductive layer. In the first opening, the first semiconductor layer is in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, and a side surface of the second conductive layer. a gate insulating layer provided in contact with an upper surface of the first semiconductor layer; a gate electrode provided in contact with an upper surface of the gate insulating layer so as to have a region overlapping with the first opening; a second insulating layer provided on the gate electrode so as to fill the first opening; a third conductive layer provided in contact with the second insulating layer and the gate electrode; the third insulating layer provided on the third conductive layer; a fourth conductive layer provided on the third insulating layer; the third insulating layer and the fourth conductive layer each have a second opening reaching the third conductive layer; within the second opening, the second semiconductor layer provided in contact with an upper surface of the third conductive layer, a side surface of the third insulating layer, and a side surface of the fourth conductive layer; and the second insulating layer is made of an organic insulating material.

[0012] In the above, it is preferable that a fourth insulating layer is provided in an area on the gate insulating layer that does not overlap with the first opening, the third insulating layer is provided on the fourth insulating layer, and the fourth insulating layer has the same material as the second insulating layer.

[0013] In addition, in the above, it is preferable that the second insulating layer contains one or more selected from acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenolic resin, and precursors of these resins.

[0014] In the above, it is preferable that the first transistor has a back gate electrode, and that the back gate electrode is provided between the first conductive layer and the second conductive layer so as to have an area overlapping with each of the first conductive layer and the second conductive layer, and that in the first opening, one surface of the first semiconductor layer faces the gate electrode and the other surface of the first semiconductor layer faces the back gate electrode.

[0015] In the above, it is preferable that at least one of the first semiconductor layer and the second semiconductor layer contains a metal oxide, the metal oxide contains two or three selected from indium, an element M, and zinc, the element M contains one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium, and that at least one of the first insulating layer and the third insulating layer contains silicon oxide or silicon oxynitride.

[0016] Furthermore, in the above, it is preferable that the first insulating layer has a fifth insulating layer, a sixth insulating layer on the fifth insulating layer, and a seventh insulating layer on the sixth insulating layer, the third insulating layer has an eighth insulating layer, a ninth insulating layer on the eighth insulating layer, and a tenth insulating layer on the ninth insulating layer, and that the fifth insulating layer, the seventh insulating layer, the eighth insulating layer, and the tenth insulating layer each have silicon nitride, silicon nitride oxide, hafnium oxide, or aluminum oxide, and that the sixth insulating layer and the ninth insulating layer each have silicon oxide or silicon oxynitride.

[0017] Another embodiment of the present invention includes a first transistor, a second transistor, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer. The first transistor includes a first semiconductor layer, a first conductive layer, a second conductive layer, a first gate insulating layer, and a first gate electrode. The second transistor includes a second semiconductor layer, a third conductive layer, a fourth conductive layer, a second gate insulating layer, and a second gate electrode. the insulating layer is provided on the first conductive layer, the second conductive layer is provided on the first insulating layer, the first insulating layer and the second conductive layer each have a first opening reaching the first conductive layer, the first semiconductor layer is provided in the first opening in contact with an upper surface of the first conductive layer, a side surface of the first insulating layer, and a side surface of the second conductive layer, the first gate insulating layer is provided in contact with an upper surface of the first semiconductor layer, and the first gate electrode has a region overlapping with the first opening. the second insulating layer is provided on the first gate electrode so as to fill the first opening; the third insulating layer is provided in contact with the upper surface of the second insulating layer, a side surface of the first gate electrode, and the upper surface of the first gate insulating layer; the third conductive layer is provided in contact with the upper surface of the third insulating layer; the fourth insulating layer is provided on the third conductive layer; the fourth conductive layer is provided on the fourth insulating layer; The conductive layers each have a second opening reaching the third conductive layer, and within the second opening, the second semiconductor layer is provided in contact with an upper surface of the third conductive layer, a side surface of the fourth insulating layer, and a side surface of the fourth conductive layer, the second gate insulating layer is provided in contact with an upper surface of the second semiconductor layer, and the second gate electrode is provided in contact with an upper surface of the second gate insulating layer so as to have a region overlapping with the second opening, and the second insulating layer is a semiconductor device having an organic insulating material.

[0018] In the above, it is preferable that the first conductive layer and the third conductive layer are connected, the second conductive layer and the fourth conductive layer are connected, and the first gate electrode and the second gate electrode are connected.

[0019] In the above, it is preferable that the second conductive layer and the third conductive layer are connected, and the first gate electrode and the second gate electrode are connected.

[0020] In the above, it is preferable that a fifth insulating layer is provided in an area on the first gate insulating layer that does not overlap with the first opening, the fourth insulating layer is provided on the fifth insulating layer, and the fifth insulating layer has the same material as the second insulating layer.

[0021] In addition, in the above, it is preferable that the second insulating layer contains one or more selected from acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenolic resin, and precursors of these resins.

[0022] In the above, at least one of the first semiconductor layer and the second semiconductor layer preferably contains a metal oxide, the metal oxide containing two or three elements selected from indium, an element M, and zinc, the element M containing one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium, and at least one of the first insulating layer and the fourth insulating layer preferably contains silicon oxide or silicon oxynitride.

[0023] Furthermore, in the above, it is preferable that the first insulating layer has a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer, the fourth insulating layer has a ninth insulating layer, a tenth insulating layer on the ninth insulating layer, and an eleventh insulating layer on the tenth insulating layer, and that the sixth insulating layer, the eighth insulating layer, the ninth insulating layer, and the eleventh insulating layer each have silicon nitride, silicon nitride oxide, hafnium oxide, or aluminum oxide, and that the seventh insulating layer and the tenth insulating layer each have silicon oxide or silicon oxynitride.

[0024] According to one embodiment of the present invention, a semiconductor device including a micro-sized transistor and a manufacturing method thereof can be provided. Alternatively, according to one embodiment of the present invention, a small-sized semiconductor device and a manufacturing method thereof can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device including a transistor with high on-state current and a manufacturing method thereof can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics and a manufacturing method thereof can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device and a manufacturing method thereof can be provided. Alternatively, according to one embodiment of the present invention, a manufacturing method of a semiconductor device with high productivity can be provided. Alternatively, according to one embodiment of the present invention, a novel semiconductor device and a manufacturing method thereof can be provided.

[0025] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0026] FIG. 1A is a plan view illustrating an example of a semiconductor device. FIG. 1B is a cross-sectional view illustrating an example of a semiconductor device. FIG. 2A is a cross-sectional view illustrating an example of a semiconductor device. FIG. 2B is a circuit diagram illustrating a semiconductor device. FIG. 3 is a cross-sectional view illustrating an example of a semiconductor device. FIG. 4 is a cross-sectional view illustrating an example of a semiconductor device. FIG. 5 is a cross-sectional view illustrating an example of a semiconductor device. FIG. 6 is a cross-sectional view illustrating an example of a semiconductor device. FIG. 7A is a cross-sectional view illustrating an example of a semiconductor device. FIG. 7B is a circuit diagram illustrating a semiconductor device. FIG. 8A is a cross-sectional view illustrating an example of a semiconductor device. FIG. 8B is a circuit diagram illustrating a semiconductor device. FIG. 9A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 9B and 9C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 10A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 10B and 10C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 11A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 11B and 11C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 12A is a plan view illustrating an example of a manufacturing method of a semiconductor device. 12B and 12C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 13A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 13B and 13C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 14A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 14B and 14C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 15A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 15B and 15C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 16A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 16B and 16C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 17A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 17B and 17C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 18A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 18B and 18C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 19A is a plan view illustrating an example of a method for manufacturing a semiconductor device. 19B and 19C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.FIG. 20A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 20B and 20C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 21A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 21B and 21C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 22A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 22B and 22C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 23A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 23B and 23C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 24A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 24B and 24C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 25A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 25B and 25C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 26A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 26B and 26C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 27A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 27B and 27C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 28A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 28B and 28C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 29A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 29B and 29C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 30A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 30B and 30C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 31A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 31B and 31C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 32A is a diagram illustrating an example of a configuration of a sequential circuit. FIG. 32B is a circuit diagram of a shift register. FIG. 32C is a timing chart. FIGS. 33A and 33B are diagrams illustrating an example of a configuration of a sequential circuit. FIGS. 34A and 34B are diagrams illustrating an example of a configuration of a sequential circuit. 35 is a circuit diagram illustrating an example of a stacked structure of transistors included in a sequential circuit. FIG. 36 is a cross-sectional view illustrating an example of a stacked structure of transistors included in a sequential circuit. FIG. 37A to FIG. 37D are diagrams illustrating examples of electronic devices.38A to 38F are diagrams showing an example of an electronic device, and Fig. 39A to Fig. 39G are diagrams showing an example of an electronic device.

[0027] The following description of the preferred embodiments will be given in detail with reference to the accompanying drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various modifications can be made to the modes and details of the present invention without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the preferred embodiments shown below.

[0028] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0029] For ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0030] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0031] A transistor is a type of semiconductor element that can realize functions such as amplifying current or voltage, and performing a switching operation to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0032] The functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current changes during circuit operation. For this reason, the terms "source" and "drain" may be used interchangeably in this specification. Note that the names of the source and drain of a transistor may be appropriately changed to the source terminal and drain terminal, or the source electrode and drain electrode, etc., depending on the situation.

[0033] The terms "gate" and "back gate" can be interchanged. Therefore, in this specification and the like, the terms "gate" and "back gate" can be used interchangeably. Note that the names of the gate and back gate of a transistor can be appropriately changed to gate electrode and back gate electrode, etc., depending on the situation.

[0034] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as a physical entity. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements.

[0035] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an exchange of an electric signal or an interaction of electric potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no exchange of an electric signal or an interaction of electric potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an exchange of an electric signal or an interaction of electric potential occurs between A and B.

[0036] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0037] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0038] In this specification and the like, a light-emitting device has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer).

[0039] In this specification, the phrase "top surface shapes generally match" means that at least a portion of the contours of stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes generally match" may also be used.

[0040] In this specification, the top surface shape of a certain component refers to the contour shape of the component in a plan view. Furthermore, a plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0041] Furthermore, in this specification and the like, "approximately the same height" refers to a configuration in which the heights from a reference surface (for example, a flat surface such as a substrate surface) are approximately the same in a cross-sectional view. For example, when a planarization process (typically, a chemical mechanical polishing (CMP) process) is performed, the heights of the processed surfaces are approximately the same. However, even when a planarization process is performed, the heights may not strictly match depending on the film material, etc., but in this specification and the like, this case is also considered to be "approximately the same height."

[0042] Embodiment 1 In this embodiment, a transistor of one embodiment of the present invention, a manufacturing method of the transistor, and the like will be described.

[0043] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a first insulating layer, a second insulating layer, and a third insulating layer.

[0044] The first transistor and the second transistor are both vertical transistors in which the source electrode and the drain electrode are provided overlapping each other at different heights relative to the substrate surface, and the drain current flows in the height direction (vertical direction). Therefore, they can be miniaturized and occupy a smaller area than planar transistors in which the source electrode and the drain electrode are provided on the same plane. The first transistor and the second transistor have the above-mentioned structure, which allows miniaturization and high integration of the semiconductor device.

[0045] Furthermore, by using a structure in which the first transistor and the second transistor are stacked, miniaturization and higher integration of the semiconductor device can be achieved.

[0046] However, since a vertical transistor has a structure in which the source electrode, the channel formation region, and the drain electrode are provided at different heights, the vertical transistor is more likely to have large steps or unevenness in the height direction than a planar transistor. Therefore, stacking a vertical transistor on a vertical transistor is much more difficult to fabricate than stacking a planar transistor on a planar transistor.

[0047] In the vertical transistor of one embodiment of the present invention, steps or unevenness occurring in the height direction are filled with a layer having a planarization function, which allows stacking of multiple vertical transistors, thereby enabling miniaturization and high integration of semiconductor devices.

[0048] In the semiconductor device of one embodiment of the present invention, the first transistor and the second transistor are provided overlapping with each other in this order.

[0049] The first insulating layer is provided above one of the source electrode and the drain electrode of the first transistor, and the other of the source electrode and the drain electrode of the first transistor is provided on the first insulating layer. That is, the first insulating layer has a region sandwiched between the source electrode and the drain electrode of the first transistor.

[0050] The first insulating layer and the other of the source electrode or drain electrode of the first transistor each have a first opening reaching one of the source electrode or drain electrode of the first transistor. A semiconductor layer of the first transistor is provided in contact with a side surface of the first insulating layer within the first opening, a side surface of the other of the source electrode or drain electrode of the first transistor within the first opening, and an upper surface of one of the source electrode or drain electrode of the first transistor within the first opening. A gate insulating layer of the first transistor is provided in contact with the upper surface of the semiconductor layer. A gate electrode of the first transistor is provided in contact with the upper surface of the gate insulating layer so as to have a region overlapping with the first opening. The gate electrode has a shape that follows the shape of the first opening. That is, the gate electrode has a recess on its upper surface that corresponds to the shape of the first opening.

[0051] The second insulating layer is a layer having the aforementioned planarizing function. The second insulating layer is provided so as to fill a recess formed in the gate electrode of the first transistor. The upper surface of the second insulating layer has a generally flat shape. The upper surface of the second insulating layer and the upper surface of the highest region of the gate electrode of the first transistor as viewed from the substrate surface are generally the same height.

[0052] One of a source electrode and a drain electrode of a second transistor is provided in contact with a part of the top surface of the gate electrode of the first transistor.

[0053] The third insulating layer is provided above one of the source electrode and the drain electrode of the second transistor, and the other of the source electrode and the drain electrode of the second transistor is provided on the third insulating layer. That is, the third insulating layer has a region sandwiched between the source electrode and the drain electrode of the second transistor.

[0054] The third insulating layer and the other of the source electrode or drain electrode of the second transistor each have a second opening reaching one of the source electrode or drain electrode of the second transistor. A semiconductor layer of the second transistor is provided in contact with a side surface of the third insulating layer in the second opening, a side surface of the other of the source electrode or drain electrode of the second transistor in the second opening, and an upper surface of one of the source electrode or drain electrode of the second transistor in the second opening. A gate insulating layer of the second transistor is provided in contact with the upper surface of the semiconductor layer. A gate electrode of the second transistor is provided in contact with the upper surface of the gate insulating layer and has a region overlapping with the second opening.

[0055] As described above, the semiconductor device of one embodiment of the present invention includes two vertical transistors. At least one of the vertical transistors has a structure in which a step or unevenness occurring in the height direction, more specifically, a depression occurring in the gate electrode, is filled with a layer having a planarizing function. Therefore, it is easy to form another vertical transistor overlapping the vertical transistor. For example, when the semiconductor device of one embodiment of the present invention is used in a scan line driver circuit (also referred to as a gate line driver circuit or a gate driver) of a display device, vertical transistors can be used for each of a plurality of transistors constituting the scan line driver circuit, and the transistors whose electrodes (source electrode, drain electrode, or gate electrode) are connected to each other can be stacked. This can reduce the area occupied by the scan line driver circuit and narrow the frame of the display device.

[0056] Below, specific structural examples of the semiconductor device of one embodiment of the present invention will be described with reference to the drawings.

[0057] <Configuration Example 1 of Semiconductor Device> Fig. 1A shows a plan view (also referred to as a top view) of a semiconductor device 100. Fig. 1B shows a cross-sectional view taken along dashed dotted line A1-A2 shown in Fig. 1A, and Fig. 2A shows a cross-sectional view taken along dashed dotted line B1-B2 shown in Fig. 1A. Fig. 2B shows a circuit diagram illustrating the configuration of the semiconductor device 100. Note that some of the components of the semiconductor device 100 (insulating layers, etc.) are omitted in Fig. 1A. As with Fig. 1A, some of the components are omitted in plan views of semiconductor devices and the like in the following drawings.

[0058] The semiconductor device 100 is provided over a substrate 102. Although not shown in FIG. 1B and other drawings, an insulating layer functioning as a base film may be provided between the substrate 102 and the semiconductor device 100. The semiconductor device 100 includes a transistor 10_1, a transistor 10_2, an insulating layer 110_1 (insulating layer 110a1, insulating layer 110b1, and insulating layer 110c1), an insulating layer 110_2 (insulating layer 110a2, insulating layer 110b2, and insulating layer 110c2), an insulating layer 192, an insulating layer 193, and an insulating layer 194. The transistor 10_1 and the transistor 10_2 are provided overlapping each other in this order.

[0059] The transistor 10_1 includes a conductive layer 104_1, an insulating layer 106_1, a semiconductor layer 108_1, a conductive layer 112a1, and a conductive layer 112b1. The conductive layer 104_1 functions as a gate electrode. A part of the insulating layer 106_1 functions as a gate insulating layer. The conductive layer 112a1 functions as one of a source electrode and a drain electrode. The conductive layer 112b1 functions as the other of the source electrode and the drain electrode. An entire region of the semiconductor layer 108_1 that overlaps with the gate electrode with the gate insulating layer interposed therebetween functions as a channel formation region. A region of the semiconductor layer 108_1 that is in contact with the source electrode functions as a source region, and a region that is in contact with the drain electrode functions as a drain region.

[0060] The above description of transistor 10_1 can be applied to transistor 10_2 by replacing the conductive layer 104_1, the insulating layer 106_1, the semiconductor layer 108_1, the conductive layer 112a1, and the conductive layer 112b1 with the conductive layer 104_2, the insulating layer 106_2, the semiconductor layer 108_2, the conductive layer 112a2, and the conductive layer 112b2, respectively.

[0061] The detailed configuration of the semiconductor device 100 will be described.

[0062] A conductive layer 112a1 is provided over the substrate 102. An insulating layer 110a1 is provided over the conductive layer 112a1 and the substrate 102. An insulating layer 110b1 is provided over the insulating layer 110a1. An insulating layer 110c1 is provided over the insulating layer 110b1. A conductive layer 112b1 is provided over the insulating layer 110c1. Note that the insulating layer 110a1, the insulating layer 110b1, and the insulating layer 110c1 may be collectively referred to as the insulating layer 110_1.

[0063] The conductive layer 112a1, the insulating layer 110_1, and the conductive layer 112b1 overlap with each other in a region where the insulating layer 110_1 is sandwiched between the conductive layer 112a1 and the conductive layer 112b1.

[0064] The insulating layer 110_1 and the conductive layer 112b1 have an opening 143 that reaches the conductive layer 112a1.

[0065] The top surface shape of the opening 143 can be, for example, circular or elliptical. The top surface shape of the opening 143 may be a polygon such as a triangle, a quadrangle (including a rectangle, a rhombus, and a square), or a pentagon, or a polygon with rounded corners. As shown in FIG. 1A , the top surface shape of the opening 143 is preferably circular. By making the top surface shape of the opening 143 circular, the processing accuracy when forming the opening 143 can be improved, and the opening 143 can be formed with a fine size. Note that in this specification and the like, a circle is not limited to a perfect circle.

[0066] 1B and 2A show a configuration in which the thickness of the conductive layer 112a1 in the region overlapping with the opening 143 is approximately equal to the thickness of the region not overlapping with the opening 143, but this is not limited thereto. The thickness of the conductive layer 112a1 in the region overlapping with the opening 143 may be thinner than the thickness of the region not overlapping with the opening 143. In this case, the electric field from the conductive layer 104_1 (i.e., the gate electric field of the transistor 10_1) can be applied up to the channel formation region near the conductive layer 112a1. Therefore, the effect of the gate electric field on carriers in the channel formation region can be strengthened in some cases compared to when the conductive layer 112a1 has a uniform thickness.

[0067] The semiconductor layer 108_1 is provided in contact with the top surface of the conductive layer 112a1 in the opening 143, the side surface of the insulating layer 110_1 in the opening 143, the side surface of the conductive layer 112b1 in the opening 143, and the top surface of the conductive layer 112b1.

[0068] 1B and 2A show a structure in which the semiconductor layer 108_1 has a region in contact with the top surface of the conductive layer 112b1, but this is not limiting. The semiconductor layer 108_1 only needs to have a region in contact with the side surface of the conductive layer 112b1 in at least the opening 143.

[0069] For example, by configuring the entire region of the semiconductor layer 108_1 to be located within the opening 143 and the end portion of the semiconductor layer 108_1 to be in contact only with the side surface of the conductive layer 112b1 within the opening 143, it is possible to prevent the end portion of the semiconductor layer 108_1 from causing a step on the conductive layer 112b1. This can improve the coverage of a film on the top surface of the conductive layer 112b1 as a formation surface.

[0070] 1B and 2A , by configuring the semiconductor layer 108_1 so that the end portion of the semiconductor layer 108_1 extends to the outside of the opening 143 and the semiconductor layer 108_1 is in contact with not only the side surface of the conductive layer 112b1 in the opening 143 but also the top surface of the conductive layer 112b1, the contact area between the semiconductor layer 108_1 and the conductive layer 112b1 can be increased. This can prevent the semiconductor layer 108_1 from peeling off. Furthermore, the contact resistance between the semiconductor layer 108_1 and the conductive layer 112b1 can be reduced, which can increase the on-state current of the transistor 10_1 in some cases.

[0071] Here, the insulating layer 110b1 of the insulating layer 110_1 is preferably an insulating layer containing oxygen. Furthermore, it is preferably an insulating layer that releases oxygen by heating. Thus, for example, when a metal oxide is used for the semiconductor layer 108_1, oxygen contained in the insulating layer 110b1 can be supplied to the metal oxide. This can repair oxygen vacancies in the metal oxide, thereby improving the electrical characteristics and reliability of the transistor 10_1.

[0072] On the other hand, the insulating layer 110a1 and the insulating layer 110c1 of the insulating layer 110_1 preferably have a blocking property against gases such as oxygen and hydrogen. This can prevent oxygen contained in the insulating layer 110b1 from being released to the outside through the insulating layer 110a1 or the insulating layer 110c1. Furthermore, it can prevent hydrogen from diffusing from the outside of the insulating layer 110_1 into the insulating layer 110b1 through the insulating layer 110a1 or the insulating layer 110c1 and then diffusing into the semiconductor layer 108_1. For example, when a metal oxide is used for the semiconductor layer 108_1, hydrogen in the semiconductor layer 108_1 can cause deterioration of the electrical characteristics and reliability of the transistor 10_1.

[0073] An insulating layer 106_1 is provided over the semiconductor layer 108_1. The insulating layer 106_1 has a region in contact with the top surface and side surfaces of the semiconductor layer 108_1, the top surface of the conductive layer 112b1, and the top surface of the insulating layer 110c1.

[0074] The conductive layer 104_1 is provided over the insulating layer 106_1. The conductive layer 104_1 is provided to have a region overlapping with the opening 143 in a plan view. The conductive layer 104_1 has a shape that conforms to the shapes of the semiconductor layer 108_1 and the insulating layer 106_1 in the opening 143. That is, the conductive layer 104_1 has a recess in its upper surface that corresponds to the shape of the opening 143. The conductive layer 104_1 has a region that faces the semiconductor layer 108_1 with the insulating layer 106_1 interposed therebetween in the opening 143.

[0075] An insulating layer 192 is provided over the conductive layer 104_1 so as to fill the opening 143. The top surface of the insulating layer 192 has a substantially flat shape. For example, an organic insulating material is preferably used as the insulating layer 192. This allows recesses formed in the conductive layer 104_1 to be easily planarized with good productivity. The top surface of the insulating layer 192 and the top surface of the highest region of the conductive layer 104_1 as viewed from the substrate surface are preferably substantially the same height. This allows the formation surfaces of layers (e.g., the conductive layer 112a2) provided over the insulating layer 192 and the conductive layer 104_1 to be substantially flat, thereby improving the coverage of the layers.

[0076] A conductive layer 112a2 is provided over the insulating layer 192 and the conductive layer 104_1. The conductive layer 112a2 is provided to have a region overlapping with the opening 143. Ends of the conductive layer 112a2 and the conductive layer 104_1 are approximately aligned in plan view. The conductive layer 112a2 has regions in contact with the top surface of the insulating layer 192 and parts of the top surface of the conductive layer 104_1.

[0077] That is, as shown in FIG. 2B, the gate electrode (conductive layer 104_1) of the transistor 10_1 and one of the source electrode and the drain electrode (conductive layer 112a2) of the transistor 10_2 are connected to each other.

[0078] An insulating layer 193 is provided over the transistor 10_1 and the conductive layer 112a2 so as to cover them. The insulating layer 193 is preferably made of the same material as the insulating layers 110a1 and 110c1. This can prevent impurities such as hydrogen from diffusing into the transistor 10_1 from the outside of the transistor 10_1 through the insulating layer 193.

[0079] An insulating layer 194 is provided in a region of the insulating layer 193 that does not overlap with the opening 143. The insulating layer 194 has a function of filling in and planarizing steps or unevenness caused by the transistor 10_1. Therefore, the insulating layer 194 is preferably made of the same material as the insulating layer 192 described above. For example, an organic insulating material is preferably used. This allows the steps or unevenness caused by the transistor 10_1 to be easily planarized with good productivity. The heights of the top surface of the insulating layer 194 and part of the top surface of the insulating layer 193 (specifically, the top surface of the region overlapping with the conductive layer 112a2) are preferably approximately the same. This allows the formation surfaces of layers (e.g., the insulating layer 110_2) provided on the insulating layer 194 and the insulating layer 193 to be approximately flat, thereby improving the coverage of the layers.

[0080] An insulating layer 110a2 is provided over the insulating layer 194 and the insulating layer 193. An insulating layer 110b2 is provided over the insulating layer 110a2. An insulating layer 110c2 is provided over the insulating layer 110b2. A conductive layer 112b2 is provided over the insulating layer 110c2. Note that the insulating layer 110a2, the insulating layer 110b2, and the insulating layer 110c2 may be collectively referred to as insulating layer 110_2.

[0081] The insulating layers 110a2, 110b2, and 110c2 are preferably made of the same materials as the insulating layers 110a1, 110b1, and 110c1, respectively. As a result, for example, when a metal oxide is used for the semiconductor layer 108_2, oxygen contained in the insulating layer 110b2 can be supplied to the metal oxide. Furthermore, release of oxygen contained in the insulating layer 110b2 to the outside through the insulating layer 110a2 or the insulating layer 110c2 can be suppressed. Furthermore, diffusion of hydrogen from the outside of the insulating layer 110_2 into the insulating layer 110b2 through the insulating layer 110a2 or the insulating layer 110c2 to the semiconductor layer 108_2 can be suppressed.

[0082] The conductive layer 112a2, the insulating layer 193, the insulating layer 110_2, and the conductive layer 112b2 overlap with each other in a region where the insulating layer 193 and the insulating layer 110_2 are sandwiched between the conductive layer 112a2 and the conductive layer 112b2.

[0083] The insulating layer 193, the insulating layer 110_2, and the conductive layer 112b2 each have an opening 144 that reaches the conductive layer 112a2.

[0084] For the top surface shape of the opening 144, please refer to the description of the top surface shape of the opening 143. As shown in Fig. 1A, the top surface shape of the opening 144 is preferably circular.

[0085] 1B and 2A show a configuration in which the film thickness of the conductive layer 112a2 in the region overlapping with the opening 144 is approximately equal to the film thickness of the region not overlapping with the opening 144, but this is not limited thereto. As with the above description regarding the conductive layer 112a1 and the opening 143, the film thickness of the conductive layer 112a2 in the region overlapping with the opening 144 may also be thinner than the film thickness of the region not overlapping with the opening 144.

[0086] The semiconductor layer 108_2 is provided in contact with the top surface of the conductive layer 112a2 in the opening 144, the side surface of the insulating layer 193 in the opening 144, the side surface of the insulating layer 110_2 in the opening 144, the side surface of the conductive layer 112b2 in the opening 144, and the top surface of the conductive layer 112b2.

[0087] 1B and 2A show a configuration in which the semiconductor layer 108_2 has a region in contact with the top surface of the conductive layer 112b2, but this is not limited thereto. As with the above description of the semiconductor layer 108_1 and the conductive layer 112b1, the semiconductor layer 108_2 may also have at least a region in contact with the side surface of the conductive layer 112b2 in the opening 144.

[0088] An insulating layer 106_2 is provided over the semiconductor layer 108_2. The insulating layer 106_2 has a region in contact with the top surface and side surfaces of the semiconductor layer 108_2, the top surface of the conductive layer 112b2, and the top surface of the insulating layer 110c2.

[0089] The conductive layer 104_2 is provided over the insulating layer 106_2. The conductive layer 104_2 is provided to have a region overlapping with the opening 144 in a plan view. The conductive layer 104_2 has a shape that conforms to the shapes of the semiconductor layer 108_2 and the insulating layer 106_2 within the opening 144. That is, the conductive layer 104_2 has a recessed portion on its top surface that corresponds to the shape of the opening 144. The conductive layer 104_2 has a region that faces the semiconductor layer 108_2 with the insulating layer 106_2 interposed therebetween within the opening 144.

[0090] Note that the conductive layer 104_2 can also be formed to fill the opening 144. For example, depending on the diameter of the opening 144 in a plan view, the conductive layer 104_2 may be formed to fill the opening 144. In this case, a step or unevenness formed on the top surface of the conductive layer 104_2 in a region overlapping with the opening 144 is reduced, which is preferable because coverage of a layer formed thereon can be improved.

[0091] In the transistor 10_1, the source electrode and the drain electrode are located at different heights with respect to the surface of the substrate 102, which is a surface where the transistor is formed, and a drain current flows in a direction perpendicular to or approximately perpendicular to the surface of the substrate 102. Similarly, in the transistor 10_2, the source electrode and the drain electrode are located at different heights with respect to the surface of the insulating layer 192, etc., which is a surface where the transistor is formed, and a drain current flows in a direction perpendicular to or approximately perpendicular to the surface of the insulating layer 192, etc. That is, in the transistors 10_1 and 10_2, the drain current flows in the vertical direction or approximately vertically. Therefore, the transistor of one embodiment of the present invention can be called a vertical transistor, a vertical channel transistor, or a VFET (Vertical Field Effect Transistor).

[0092] Since the source electrode and the drain electrode of each of the transistors 10_1 and 10_2 can be overlapped, the transistors can be made smaller than a so-called planar transistor in which the source electrode and the drain electrode are arranged on the same plane, and the area occupied by the transistor within the substrate surface can be significantly reduced.

[0093] Furthermore, in the semiconductor device 100 of one embodiment of the present invention, the transistor 10_2 is provided so as to overlap the transistor 10_1, whose gate electrode is substantially planarized by the insulating layers 192 and 194. Therefore, the area occupied by the transistors in the substrate surface can be significantly reduced compared to a case in which these two transistors are arranged on the same plane, thereby enabling miniaturization and high integration of the semiconductor device. For example, when the semiconductor device of one embodiment of the present invention is used in a scan line driver circuit of a display device, vertical transistors can be used for each of the multiple transistors constituting the scan line driver circuit, and transistors whose electrodes (source electrode, drain electrode, or gate electrode) are connected to each other, such as the transistors 10_1 and 10_2, can be stacked. This allows the area occupied by the scan line driver circuit to be reduced, thereby realizing a display device with an extremely narrow frame.

[0094] The channel lengths and channel widths of the transistors 10_1 and 10_2 will be described below. Note that although the channel length and channel width will be described below using the transistor 10_2, the same description can be applied to the transistor 10_1, which is also a vertical transistor, by replacing each component of the transistor (for example, by replacing the number "2" at the end of each reference numeral with "1").

[0095] In the semiconductor layer 108_2, a region in contact with the conductive layer 112a2 functions as one of a source region and a drain region, a region in contact with the conductive layer 112b2 functions as the other of the source region and the drain region, and a region between the source region and the drain region functions as a channel formation region.

[0096] The channel length of the transistor 10_2 is the distance between the source region and the drain region. In FIG. 2A, the channel length L10_2 of the transistor 10_2 is indicated by a dashed double-headed arrow. In FIG. 2A, the distance along the semiconductor layer 108_2 in the region between the conductive layer 112a2 and the conductive layer 112b2 is indicated as the channel length L10_2 of the transistor 10_2.

[0097] Note that the sum of the thickness of the insulating layer 193 and the thickness of the insulating layer 110_2 in a region sandwiched between the top surface of the conductive layer 112a2 and the bottom surface of the conductive layer 112b2 (the thickness of the insulating layer 110_1 in the case of the channel length of the transistor 10_1) may be used as the channel length L10_2 of the transistor 10_2. Alternatively, the thickness of the insulating layer 110b2 (the thickness of the insulating layer 110b1 in the case of the channel length of the transistor 10_1) may be used as the channel length L10_2 of the transistor 10_2. Alternatively, the sum of the thickness of the insulating layer 193, the thickness of the insulating layer 110_2, and the thickness of the conductive layer 112b2 (the sum of the thickness of the insulating layer 110_1 and the thickness of the conductive layer 112b1 in the case of the channel length of the transistor 10_1) may be used as the channel length L10_2 of the transistor 10_2.

[0098] Here, the channel length L10_2 of the transistor 10_2 is determined by the thickness of the insulating layer 193, the thickness of the insulating layer 110_2, the thickness of the conductive layer 112b2, the angle θ110_2 between the surface where the semiconductor layer 108_2 is to be formed in the opening 144 (here, the side surface of the insulating layer 193, the side surface of the insulating layer 110_2, and the side surface of the conductive layer 112b2) and the surface where the insulating layer 193 is to be formed (here, the top surface of the conductive layer 112a2), and the like, and is not affected by the performance of the exposure apparatus used to manufacture the transistor. Therefore, the channel length L10_2 can be set to a value smaller than the limit resolution of the exposure apparatus, and a transistor with a microscopic size can be realized.

[0099] The channel length L10_2 can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and less than 2.5 μm, 10 nm or more and less than 2 μm, 10 nm or more and less than 1.5 μm, 10 nm or more and less than 1.2 μm, 10 nm or more and less than 1 μm, 10 nm or more and less than 500 nm, 10 nm or more and less than 300 nm, 10 nm or more and less than 200 nm, 10 nm or more and less than 100 nm, 10 nm or more and less than 50 nm, 10 nm or more and less than 30 nm, or 10 nm or more and less than 20 nm. For example, the channel length L10_2 can be 100 nm or more and less than 1 μm. By shortening the channel length L10_2, the on-state current of the transistor 10_2 can be increased.

[0100] The thickness of the insulating layer 110_2 (or the sum of the thickness of the insulating layer 193 and the thickness of the insulating layer 110_2) can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and less than 2.5 μm, 10 nm or more and less than 2 μm, 10 nm or more and less than 1.5 μm, 10 nm or more and less than 1.2 μm, 10 nm or more and less than 1 μm, 10 nm or more and less than 500 nm, 10 nm or more and less than 300 nm, 10 nm or more and less than 200 nm, 10 nm or more and less than 100 nm, 10 nm or more and less than 50 nm, 10 nm or more and less than 30 nm, or 10 nm or more and less than 20 nm.

[0101] The angle θ110_2 can be, for example, 30 degrees or more and less than 90 degrees, 35 degrees or more and less than 85 degrees, 40 degrees or more and less than 80 degrees, 45 degrees or more and less than 80 degrees, 50 degrees or more and less than 80 degrees, 55 degrees or more and less than 80 degrees, 60 degrees or more and less than 80 degrees, 65 degrees or more and less than 80 degrees, or 70 degrees or more and less than 80 degrees. Note that the angle θ110_2 can also be 90 degrees. The smaller the angle θ110_2, the better the coverage of the layer (such as the semiconductor layer 108_2) formed along the sidewall of the opening 144 can be. On the other hand, the closer the angle θ110_2 is to 90 degrees, the better the area occupied by the transistor on the substrate surface can be reduced.

[0102] The channel width of the transistor 10_2 is the length of the source region or the length of the drain region in a plan view ( FIG. 1A ). That is, the channel width of the transistor 10_2 is the length of the region where the semiconductor layer 108_2 and the conductive layer 112a2 are in contact with each other in a plan view or the length of the region where the semiconductor layer 108_2 and the conductive layer 112b2 are in contact with each other in a plan view. Alternatively, the channel width of the transistor 10_2 may be an intermediate value between the length of the region where the semiconductor layer 108_2 and the conductive layer 112a2 are in contact with each other in a plan view and the length of the region where the semiconductor layer 108_2 and the conductive layer 112b2 are in contact with each other in a plan view.

[0103] Here, the channel width of the transistor 10_2 is described as the perimeter of a region where the semiconductor layer 108_2 is in contact with the side surface of the conductive layer 112b2 on the opening 144 side. In Figures 1A and 2A, the channel width W10_2 of the transistor 10_2 is indicated by a dashed double-headed arrow. The channel width W10_2 can also be referred to as the perimeter of the opening 144 in a plan view (in the case of the channel width of the transistor 10_1, the perimeter of the opening 143 in a plan view).

[0104] The channel width W10_2 is determined by the top surface shape of the opening 144, etc. In FIGS. 1A and 2A, the width D144 of the opening 144 is indicated by a two-dot chain line with a double arrow. The width D144 refers to the short side of the smallest rectangle circumscribing the opening 144 in a plan view. When the opening 144 is formed using photolithography, the width D144 of the opening 144 is equal to or greater than the resolution limit of the exposure tool. The width D144 is, for example, equal to or greater than 0.20 μm and less than 5.0 μm. Note that when the top surface shape of the opening 144 is circular, the width D144 corresponds to the diameter of the opening 144, and the channel width W10_2 can be calculated as "D144 × π."

[0105] [Semiconductor Layer 108_1, Semiconductor Layer 108_2] The semiconductor material that can be used for the semiconductor layer 108_1 and the semiconductor layer 108_2 is not particularly limited. For example, an elemental semiconductor or a compound semiconductor can be used. As the elemental semiconductor, for example, silicon or germanium can be used. As the compound semiconductor, for example, gallium arsenide and silicon germanium can be used. As the compound semiconductor, an organic substance having semiconductor properties or a metal oxide having semiconductor properties (also referred to as an oxide semiconductor) can be used. Note that these semiconductor materials may contain impurities that function as dopants (for example, when silicon is used as the semiconductor material, typical examples include elements such as phosphorus and boron).

[0106] The crystallinity of the semiconductor material used for the semiconductor layer 108_1 and the semiconductor layer 108_2 is not particularly limited, and any of an amorphous semiconductor and a crystalline semiconductor (a single-crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. The use of a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0107] The semiconductor layer 108_1 and the semiconductor layer 108_2 can be formed using silicon. Examples of silicon include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS).

[0108] A transistor using amorphous silicon for the semiconductor layers 108_1 and 108_2 can be formed over a large glass substrate and can be manufactured at low cost. A transistor using polycrystalline silicon for the semiconductor layers 108_1 and 108_2 has high field-effect mobility and can operate at high speed. A transistor using microcrystalline silicon for the semiconductor layers 108_1 and 108_2 has higher field-effect mobility and can operate at high speed than a transistor using amorphous silicon.

[0109] The semiconductor layer 108_1 and the semiconductor layer 108_2 preferably contain a metal oxide (oxide semiconductor). Examples of metal oxides that can be used for the semiconductor layer 108_1 and the semiconductor layer 108_2 include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. The element M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium. In particular, the element M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin. Gallium is more preferred as the element M.

[0110] For the semiconductor layer 108_1 and the semiconductor layer 108_2, for example, indium oxide, indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium aluminum zinc oxide (In—Al—Zn oxide, also referred to as IAZO), indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In—Ga—Sn—Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In—Ga—Al—Zn oxide, also referred to as IGAZO or IAGZO), or the like can be used. Alternatively, indium tin oxide containing silicon can be used.

[0111] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). When forming a metal oxide by sputtering, the atomic ratio of the target may differ from the atomic ratio of the metal oxide. In particular, the atomic ratio of zinc in the metal oxide may be smaller than the atomic ratio of the target. Specifically, the atomic ratio of zinc in the metal oxide may be approximately 40% to 90% of the atomic ratio of zinc contained in the target.

[0112] When the semiconductor layers 108_1 and 108_2 are formed by the ALD method, it is preferable to use a film formation method such as a thermal ALD method or a PEALD (Plasma Enhanced ALD) method. The thermal ALD method is preferable because it exhibits extremely high step coverage. The PEALD method is also preferable because it exhibits high step coverage and allows low-temperature film formation.

[0113] The compositions of the metal oxides in the semiconductor layers 108_1 and 108_2 greatly affect the electrical characteristics and reliability of the transistors 10_1 and 10_2, respectively.

[0114] For example, by increasing the content of indium in the metal oxide, a transistor with a large on-state current can be realized. Furthermore, by using a metal oxide that does not contain gallium or has a low content of gallium in the semiconductor layers 108_1 and 108_2, for example, a transistor with high reliability against application of a positive bias can be obtained. Furthermore, by using a metal oxide with a low content of element M in the semiconductor layers 108_1 and 108_2, for example, a transistor with high reliability against application of a positive bias can be obtained. Furthermore, by increasing the content of element M in the metal oxide, for example, a transistor with high reliability against light can be obtained.

[0115] The composition of the metal oxide contained in the semiconductor layer 108_1 and the semiconductor layer 108_2 will be described in detail later.

[0116] It is preferable to use a crystalline metal oxide layer for the semiconductor layer 108_1 and the semiconductor layer 108_2. For example, a metal oxide layer having a CAAC (C-Axis Aligned Crystal) structure, a polycrystalline (poly-crystal) structure, a nanocrystalline (nc: nano-crystal) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer 108_1 and the semiconductor layer 108_2, the defect state density in the semiconductor layer 108_1 and the semiconductor layer 108_2 can be reduced, and a highly reliable transistor can be realized. Note that the CAAC structure is a crystal structure in which multiple microcrystals (typically, multiple IGZO microcrystals) have c-axis orientation and are connected without being oriented in the a-b plane. In the CAAC structure, crystal grain boundaries (grains) are less clearly visible in the a-b plane than in the polycrystalline structure, and therefore a highly reliable transistor can be realized.

[0117] The higher the crystallinity of the metal oxide layers used for the semiconductor layers 108_1 and 108_2, the more the density of defect states in the semiconductor layers 108_1 and 108_2 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0118] The semiconductor layer 108_1 and the semiconductor layer 108_2 may have a stacked structure of two or more metal oxide layers with different crystallinity. For example, a stacked structure of a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer can be used, and the second metal oxide layer can have a region with higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer can have a region with lower crystallinity than the first metal oxide layer. The two or more metal oxide layers included in the semiconductor layer 108_1 and the semiconductor layer 108_2 may have the same or approximately the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used to form the layers, thereby reducing manufacturing costs. For example, a stacked structure of two or more metal oxide layers with different crystallinity can be formed by using the same sputtering target and varying the ratio of the flow rate of oxygen gas to the total deposition gas used during formation (hereinafter also referred to as the oxygen flow rate ratio). Note that the two or more metal oxide layers included in the semiconductor layer 108_1 and the semiconductor layer 108_2 may have different compositions.

[0119] The thickness of each of the semiconductor layer 108_1 and the semiconductor layer 108_2 (film thickness relative to the surface on which it is formed) is preferably 3 nm or more and 100 nm or less, more preferably 5 nm or more and 100 nm or less, further preferably 10 nm or more and 100 nm or less, further preferably 10 nm or more and 70 nm or less, further preferably 15 nm or more and 70 nm or less, further preferably 15 nm or more and 50 nm or less, further preferably 20 nm or more and 50 nm or less, further preferably 20 nm or more and 40 nm or less, further preferably 25 nm or more and 40 nm or less.

[0120] Here, oxygen vacancies that can be formed in the semiconductor layer 108_1 and the semiconductor layer 108_2 will be described.

[0121] When an oxide semiconductor is used for the semiconductor layer 108_1 and the semiconductor layer 108_2, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to form water, and oxygen vacancies (V ＯFurthermore, defects in which hydrogen enters an oxygen vacancy (hereinafter referred to as V Ｏ H.) functions as a donor and generates electrons as carriers. Furthermore, some of the hydrogen atoms may bond with oxygen atoms that are bonded to metal atoms to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily mobile due to stresses such as heat and an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be reduced.

[0122] V Ｏ H can function as a donor in an oxide semiconductor. However, it is difficult to quantitatively evaluate such defects. Therefore, in an oxide semiconductor, evaluation is sometimes performed using the carrier concentration rather than the donor concentration. Therefore, in this specification and the like, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of the oxide semiconductor, rather than the donor concentration. In other words, the "carrier concentration" described in this specification and the like may be rephrased as the "donor concentration."

[0123] From the above, when an oxide semiconductor is used for the semiconductor layer 108_1 and the semiconductor layer 108_2, V Ｏ It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic. Ｏ To obtain an oxide semiconductor in which H is sufficiently reduced, impurities such as water and hydrogen are removed from the oxide semiconductor (this may be referred to as dehydration or dehydrogenation treatment), and oxygen vacancies (V Ｏ It is important to repair the Ｏ By using an oxide semiconductor in which defects such as H are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained. Ｏ ) is sometimes referred to as oxygenation treatment.

[0124] When an oxide semiconductor is used for the semiconductor layer 108_1 and the semiconductor layer 108_2, the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is 1×10 １８ cm −３ Preferably, it is 1×10 or less. １７ cm −３ More preferably, it is less than 1×10 １６ cm −３ More preferably, it is less than 1×10 １３ cm −３ More preferably, it is less than 1×10 １２ cm −３ Note that the lower limit of the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is not particularly limited, but is preferably 1×10 −９ cm −３ It can be said that:

[0125] A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has significantly higher field-effect mobility than a transistor using amorphous silicon. Furthermore, an OS transistor has significantly lower source-drain leakage current in an off state (hereinafter also referred to as an off-state current) and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, by using an OS transistor in a semiconductor device, the power consumption of the semiconductor device can be reduced.

[0126] OS transistors can be applied to display devices. To increase the light-emission luminance of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since OS transistors have a higher source-drain breakdown voltage than transistors using silicon (hereinafter referred to as Si transistors), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as a driving transistor in a pixel circuit, it is possible to increase the amount of current flowing through the light-emitting device and increase the light-emission luminance of the light-emitting device.

[0127] When a transistor operates in the saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the current flowing between the source and drain can be precisely determined by changing the gate-source voltage, and the amount of current flowing through the light-emitting device can be precisely controlled. This allows for a greater number of gray levels to be displayed in the pixel circuit.

[0128] In terms of saturation characteristics of the current that flows when a transistor operates in a saturation region, an OS transistor can pass a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be passed through a light-emitting device, even when the current-voltage characteristics of the light-emitting device vary. In other words, when an OS transistor operates in a saturation region, the source-drain current of the OS transistor remains almost unchanged even when the source-drain voltage increases, thereby stabilizing the light-emitting luminance of the light-emitting device.

[0129] As described above, by using an OS transistor for a driving transistor included in a pixel circuit, it is possible to achieve "suppression of black floating," "increase in light emission luminance," "multiple gradations," "suppression of variations in light-emitting devices," and the like.

[0130] Furthermore, OS transistors can also be applied to, for example, a scan line driver circuit of a display device. As described above, OS transistors have significantly higher field-effect mobility than transistors using amorphous silicon. Therefore, by applying OS transistors to the scan line driver circuit of a display device, a scan line driver circuit that can operate at high speed can be realized.

[0131] Furthermore, OS transistors exhibit little change in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, neutron rays, and proton rays).

[0132] In the transistor of one embodiment of the present invention, and in a semiconductor device, a display device, or the like to which the transistor of one embodiment of the present invention is applied, an inorganic insulating material or an organic insulating material can be used for the insulating layer (the insulating layer 110_1, the insulating layer 110_2, the insulating layer 106_1, the insulating layer 106_2, the insulating layer 192, the insulating layer 193, and the insulating layer 194). Alternatively, the insulating layer may have a stacked structure of an inorganic insulating material and an organic insulating material.

[0133] As the inorganic insulating material, one or more of an oxide, an oxynitride, a nitride oxide, and a nitride can be used.

[0134] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. A nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0135] For example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectrometry (XPS) can be used to analyze the oxygen and nitrogen contents. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., less than 0.5 atomic% or less than 1 atomic%). When comparing the element contents, it is more preferable to perform a combined analysis using both SIMS and XPS analytical techniques.

[0136] Furthermore, for evaluating the film density of an insulating layer or the like, for example, Rutherford Backscattering Spectrometry (RBS) or X-ray Reflection (XRR) can be used. Differences in film density can sometimes be evaluated using cross-sectional transmission electron microscopy (TEM) images. In TEM observation, a high film density results in a dense (dark) transmission electron (TE) image, whereas a low film density results in a pale (bright) transmission electron (TE) image. Even when the same material is used for the insulating layer, if the film densities are different, the boundary between these may be observed as a difference in contrast in a cross-sectional TEM image.

[0137] The nitrogen content of the insulating layer can be confirmed, for example, by energy dispersive X-ray spectrometry (EDX). For example, when silicon nitride, silicon oxynitride, or the like is used for the insulating layer, the nitrogen content can be evaluated using the ratio of the nitrogen peak height to the silicon peak height. In EDX, the peak of a certain element refers to the point at which the count number of the element reaches a maximum in a spectrum where the horizontal axis shows the energy of characteristic X-rays and the vertical axis shows the count number (detection value) of characteristic X-rays. Alternatively, the count number at the energy of characteristic X-rays specific to the element may be used to confirm the difference in nitrogen content by the ratio of the nitrogen count number to the silicon count number. For example, the count number at 1.739 keV (Si-Kα) can be used for silicon, and the count number at 0.392 keV (N-Kα) can be used for nitrogen.

[0138] The hydrogen concentration of the insulating layer can be evaluated by, for example, SIMS.

[0139] When hydrogen diffuses into the semiconductor layer 108_1 and the semiconductor layer 108_2, it reacts with oxygen atoms contained in the oxide semiconductor to form water, and oxygen vacancies (V Ｏ ) may be formed in the semiconductor layer 108_1 and the semiconductor layer 108_2. Ｏ When a blocking film that suppresses hydrogen diffusion is used as an insulating layer in contact with the semiconductor layer 108_1 or the semiconductor layer 108_2 or as an insulating layer located around the semiconductor layer 108_1 or the semiconductor layer 108_2, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0140] Oxygen vacancies (V Ｏ ) and V ＯIn particular, when the channel length is short, oxygen vacancies (V Ｏ ) and V Ｏ For example, when VH flows from the source region or drain region to the channel formation region, the influence of VH on the electrical characteristics and reliability of the transistors 10_1 and 10_2 increases. Ｏ The diffusion of H increases the carrier concentration in the channel formation region, which may cause fluctuations in the threshold voltages of the transistors 10_1 and 10_2 or reduce the reliability. Ｏ The influence of the diffusion of H on the electrical characteristics and reliability of the transistors 10_1 and 10_2 increases as the channel length decreases. Ｏ ) and V Ｏ By reducing H, it is possible to realize a transistor with a short channel length, which has good electrical characteristics and high reliability.

[0141] By using an insulating layer that releases oxygen as an insulating layer in contact with the semiconductor layer 108_1 and the semiconductor layer 108_2 (for example, the insulating layer 106_1, the insulating layer 106_2, the insulating layer 110b1, and the insulating layer 110b2), oxygen can be supplied from the insulating layer to the semiconductor layer 108_1 and the semiconductor layer 108_2. By supplying oxygen to the channel formation regions of the semiconductor layer 108_1 and the semiconductor layer 108_2, oxygen vacancies (V Ｏ ) and V Ｏ The H can be reduced, and a highly reliable transistor can be obtained, which has favorable electrical characteristics. Note that other treatments for supplying oxygen to the semiconductor layers 108_1 and 108_2 include heat treatment in an atmosphere containing oxygen, plasma treatment in an atmosphere containing oxygen, and the like.

[0142] It is preferable that an insulating layer in contact with the semiconductor layer 108_1 or 108_2, or an insulating layer located around the semiconductor layer 108_1 or 108_2, emits little impurities (for example, water and hydrogen) from itself. Note that the impurities referred to here are impurities that diffuse into the semiconductor layer 108_1 or 108_2 and cause oxygen vacancies (V Ｏ ) and V Ｏ Impurities refer to substances that can adversely affect the electrical characteristics of a transistor by, for example, generating H. Reducing the release of impurities can suppress the diffusion of the impurities into the semiconductor layers 108_1 and 108_2, thereby enabling a highly reliable transistor to exhibit favorable electrical characteristics.

[0143] Oxygen may be released from the semiconductor layers 108_1 and 108_2 due to heat applied in a process after the formation of the semiconductor layers 108_1 and 108_2. However, oxygen is supplied to the semiconductor layers 108_1 and 108_2 from an insulating layer in contact with the semiconductor layers 108_1 and 108_2, which can cause oxygen vacancies (V Ｏ ) and V Ｏ An increase in H can be suppressed. Furthermore, the degree of freedom in the process temperature can be increased in the processes after the formation of the semiconductor layers 108_1 and 108_2. Specifically, the process temperature can be increased in the processes after the formation of the semiconductor layers 108_1 and 108_2. Therefore, a transistor having good electrical characteristics and high reliability can be formed.

[0144] [Insulating Layer 110_1 and Insulating Layer 110_2] The insulating layer 110_1 (insulating layer 110a1, insulating layer 110b1, and insulating layer 110c1) and the insulating layer 110_2 (insulating layer 110a2, insulating layer 110b2, and insulating layer 110c2) can be formed using an inorganic insulating material or an organic insulating material. The insulating layer 110_1 and the insulating layer 110_2 may have a stacked structure of an inorganic insulating material and an organic insulating material.

[0145] An inorganic insulating material can be suitably used for the insulating layer 110_1 and the insulating layer 110_2. Examples of the inorganic insulating material that can be used include one or more of oxide, oxynitride, nitride oxide, and nitride. Examples of the insulating layer 110_1 and the insulating layer 110_2 that can be used include one or more of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, gallium oxide, tantalum oxide, magnesium oxide, lanthanum oxide, cerium oxide, neodymium oxide, silicon nitride, silicon nitride oxide, and aluminum nitride.

[0146] The insulating layer 110_1 and the insulating layer 110_2 may have a stacked structure of two or more layers. In FIG. 1B and other drawings, the insulating layer 110_1 has a stacked structure of an insulating layer 110a1, an insulating layer 110b1 on the insulating layer 110a1, and an insulating layer 110c1 on the insulating layer 110b1, and the insulating layer 110_2 has a stacked structure of an insulating layer 110a2, an insulating layer 110b2 on the insulating layer 110a2, and an insulating layer 110c2 on the insulating layer 110b2. The insulating layers 110a1, 110b1, 110c1, 110a2, 110b2, and 110c2 may be made of the same material or different materials.

[0147] The insulating layers 110_1 and 110_2 preferably release little impurities (for example, water and hydrogen) from themselves.

[0148] The insulating layers 110b1 and 110b2 can be thicker than the insulating layers 110a1 and 110a2 and the insulating layers 110c1 and 110c2. As described above, the insulating layers 110b1 and 110b2 are insulating layers containing oxygen to be supplied to the semiconductor layers 108_1 and 108_2, respectively. Therefore, by making the insulating layers 110b1 and 110b2 thickest among the three insulating layers constituting the insulating layer 110_1 (the insulating layer 110a1, the insulating layer 110b1, and the insulating layer 110c1) and the three insulating layers constituting the insulating layer 110_2 (the insulating layer 110a2, the insulating layer 110b2, and the insulating layer 110c2), respectively, the amount of oxygen that can be contained in the entire insulating layer 110_1 and the entire insulating layer 110_2 can be increased. The deposition rate of the insulating layers 110b1 and 110b2 is preferably faster than the deposition rate of the insulating layers 110a1 and 110a2 and the deposition rate of the insulating layers 110c1 and 110c2. By increasing the deposition rate of a thick film, productivity can be improved.

[0149] The insulating layers 110a1 and 110c1, as well as the insulating layers 110a2 and 110c2, function as blocking films that suppress gas desorption from the insulating layers 110b1 and 110b2, respectively. The insulating layers 110a1 and 110c1, as well as the insulating layers 110a2 and 110c2, are preferably made of materials that are difficult for gas to diffuse through. The insulating layers 110a1 and 110c1, as well as the insulating layers 110a2 and 110c2, preferably have regions with higher film density than the insulating layers 110b1 and 110b2, respectively. Increasing the film density of the insulating layers can improve their blocking properties against gas. Slowing the film formation rate of the insulating layers increases the film density, thereby improving their blocking properties against gas.

[0150] The insulating layers 110b1 and 110b2 are preferably formed using an oxide or an oxynitride. The insulating layers 110b1 and 110b2 are preferably formed using a film that releases oxygen when heated. The insulating layers 110b1 and 110b2 are preferably formed using, for example, silicon oxide or silicon oxynitride.

[0151] When the insulating layers 110b1 and 110b2 release oxygen, oxygen can be supplied from the insulating layer 110b1 to the semiconductor layer 108_1 and from the insulating layer 110b2 to the semiconductor layer 108_2. The insulating layers 110b1 and 110b2 preferably have a high oxygen diffusion coefficient. A high oxygen diffusion coefficient facilitates diffusion of oxygen in the insulating layers 110b1 and 110b2, allowing oxygen to be efficiently supplied to the semiconductor layers 108_1 and 108_2, respectively. Furthermore, as described above, by configuring the insulating layers 110b1 and 110b2 to be thicker than the insulating layers 110a1 and 110c1 and the insulating layers 110a2 and 110c2, respectively, more oxygen can be supplied to the semiconductor layers 108_1 and 108_2.

[0152] The insulating layers 110_1 and 110_2 are preferably formed by a film formation method such as a sputtering method, an ALD method, or a plasma CVD method.

[0153] In particular, by using a sputtering method without using a gas containing hydrogen in the deposition gas, a film with an extremely low hydrogen content can be obtained. Therefore, hydrogen supply to the semiconductor layer 108_1 and the semiconductor layer 108_2 can be suppressed, and the electrical characteristics of the transistors 10_1 and 10_2 can be stabilized. When silicon oxide is deposited by sputtering, it can be deposited using a silicon target in an atmosphere containing an oxygen gas, for example. When silicon nitride is deposited by sputtering, it can be deposited using a silicon target in an atmosphere containing nitrogen gas, for example. When aluminum oxide is deposited by sputtering, it can be deposited using an aluminum target in an atmosphere containing an oxidizing gas, for example.

[0154] Silicon oxide and silicon nitride can be formed by, for example, the PEALD method. Aluminum oxide and hafnium oxide can be formed by, for example, the thermal ALD method. By forming an insulating layer by the PEALD method and the thermal ALD method, a dense insulating film can be formed, and thus the blocking property against oxygen and hydrogen can be improved.

[0155] The insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2 can be made of a material having a higher nitrogen content than the insulating layers 110b1 and 110b2, respectively. Increasing the nitrogen content of the insulating layers can improve the blocking properties against oxygen and hydrogen.

[0156] The insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2 may each have a region with a lower hydrogen concentration than the insulating layers 110b1 and 110b2.

[0157] The insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2 are preferably impermeable to oxygen. Furthermore, the insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2 are preferably impermeable to hydrogen. The insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2 function as blocking films that suppress diffusion of hydrogen from the outside of the transistor to the semiconductor layer 108_1 and the semiconductor layer 108_2 through the insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2, respectively. The film densities of the insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2 are preferably higher than those of the insulating layers 110b1 and 110b2, respectively. Increasing the film density of the insulating layers can improve the blocking properties of oxygen and hydrogen. When silicon oxide or silicon oxynitride is used for the insulating layers 110b1 and 110b2, silicon nitride or silicon nitride oxide can be used for the insulating layers 110a1, 110c1, 110a2, and 110c2, respectively. Furthermore, hafnium oxide or aluminum oxide can be suitably used for the insulating layers 110a1, 110c1, 110a2, and 110c2.

[0158] Furthermore, the insulating layer 110a1, the insulating layer 110c1, the insulating layer 110a2, and the insulating layer 110c2 can each have a structure in which two or more materials selected from silicon nitride, silicon nitride oxide, hafnium oxide, and aluminum oxide are stacked.

[0159] If oxygen contained in the insulating layers 110b1 and 110b2 diffuses downward (toward the substrate 102) from the insulating layers 110b1 and 110b2, the amounts of oxygen supplied from the insulating layers 110b1 and 110b2 to the semiconductor layers 108_1 and 108_2, respectively, may decrease. By providing the insulating layers 110a1 and 110a2 below the insulating layers 110b1 and 110b2, respectively, it is possible to prevent the oxygen contained in the insulating layers 110b1 and 110b2 from diffusing downward from the insulating layers 110b1 and 110b2. Furthermore, by providing the insulating layers 110c1 and 110c2 on the insulating layers 110b1 and 110b2, respectively, it is possible to suppress the oxygen contained in the insulating layers 110b1 and 110b2 from diffusing upward from the insulating layers 110b1 and 110b2. Therefore, the amount of oxygen supplied from the insulating layers 110b1 and 110b2 to the semiconductor layers 108_1 and 108_2 increases, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0160] Furthermore, by providing the insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2, diffusion of hydrogen into the semiconductor layers 108_1 and 108_2 is suppressed, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0161] The insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2 preferably have a thickness that functions as a blocking film for oxygen and hydrogen. If the insulating layers are too thin, the blocking film function may be impaired. On the other hand, if the insulating layers are too thick, the regions of the semiconductor layers 108_1 and 108_2 that are in contact with the insulating layers 110b1 and 110b2, respectively, may become narrower, and the amount of oxygen supplied to the semiconductor layers 108_1 and 108_2 may become smaller. The film thickness (film thickness relative to the surface on which the insulating layer 110a1, the insulating layer 110c1, the insulating layer 110a2, and the insulating layer 110c2 are preferably 1 nm or more and 200 nm or less, 1 nm or more and 100 nm or less, 1 nm or more and 60 nm or less, 1 nm or more and 50 nm or less, 1 nm or more and 40 nm or less, 1 nm or more and 30 nm or less, 1 nm or more and 20 nm or less, 1 nm or more and 10 nm or less, 1 nm or more and 5 nm or less, or 2 nm or more and 5 nm or less, respectively.

[0162] [Insulating Layer 106_1 and Insulating Layer 106_2] The insulating layers 106_1 and 106_2, which function as gate insulating layers, preferably have a low defect density. The low defect density of the insulating layers 106_1 and 106_2 enables a transistor to exhibit favorable electrical characteristics. Furthermore, the insulating layers 106_1 and 106_2 preferably have a high withstand voltage. The high withstand voltage of the insulating layers 106_1 and 106_2 enables a highly reliable transistor.

[0163] The insulating layers 106_1 and 106_2 are preferably insulating layers containing oxygen. Furthermore, they are preferably insulating layers that release oxygen when heated. For example, when a metal oxide is used for the semiconductor layers 108_1 and 108_2, oxygen contained in the insulating layers 106_1 and 106_2 can be supplied to the metal oxide. This can repair oxygen vacancies in the metal oxide, thereby improving the electrical characteristics and reliability of the transistors 10_1 and 10_2.

[0164] The insulating layers 106_1 and 106_2 can include, for example, one or more of an oxide, an oxynitride, a nitride oxide, and a nitride having insulating properties. The insulating layers 106_1 and 106_2 can include, for example, one or more of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga—Zn oxide. The insulating layers 106_1 and 106_2 can be single layers or stacked layers. The insulating layers 106_1 and 106_2 can have, for example, a stacked structure of an oxide and a nitride.

[0165] In a miniaturized transistor, a thin gate insulating layer may result in a large leakage current. By using a material with a high dielectric constant (also referred to as a high-k material) for the gate insulating layer, a low voltage can be achieved during transistor operation while maintaining the physical film thickness. Examples of high-k materials include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

[0166] The insulating layers 106_1 and 106_2 preferably release little impurities (for example, water and hydrogen) from themselves. The small amount of impurity release from the insulating layers 106_1 and 106_2 suppresses the diffusion of the impurities into the semiconductor layers 108_1 and 108_2, respectively, and thus the transistors can have favorable electrical characteristics and high reliability.

[0167] The insulating layers 106_1 and 106_2 are preferably formed under conditions that cause little damage to the semiconductor layers 108_1 and 108_2 because they are formed over the semiconductor layers 108_1 and 108_2, respectively. For example, they are preferably formed under conditions that cause little damage to the semiconductor layers 108_1 and 108_2. For example, when the insulating layers 106_1 and 106_2 are formed by a plasma CVD method, low power consumption can reduce damage to the semiconductor layers 108_1 and 108_2.

[0168] Here, the insulating layers 106_1 and 106_2 will be specifically described using an example in which metal oxide is used for the semiconductor layers 108_1 and 108_2.

[0169] In order to improve interface characteristics with the semiconductor layer 108_1 and the semiconductor layer 108_2, it is preferable to use one or more of oxide and oxynitride on at least the side of the insulating layer 106_1 that is in contact with the semiconductor layer 108_1 and on at least the side of the insulating layer 106_2 that is in contact with the semiconductor layer 108_2. For example, one or more of silicon oxide and silicon oxynitride can be suitably used for the insulating layer 106_1 and the insulating layer 106_2. It is more preferable to use a film that releases oxygen by heating for the insulating layer 106_1 and the insulating layer 106_2.

[0170] The insulating layers 106_1 and 106_2 may have a stacked structure. The insulating layers 106_1 and 106_2 can have a stacked structure of an oxide film or oxynitride film in contact with the semiconductor layer 108_1 and the semiconductor layer 108_2, respectively, and a nitride film in contact with the conductive layer 104_1 and the conductive layer 104_2, respectively. As the oxide film or the oxynitride film, for example, one or more of silicon oxide and silicon oxynitride can be preferably used. As the nitride film, for example, silicon nitride can be preferably used.

[0171] The thickness of the insulating layer 106_1 and the insulating layer 106_2 (thickness relative to the surface where the insulating layer 106_1 and the insulating layer 106_2 are formed) is more preferably 1 nm to 100 nm. At least a part of the insulating layer 106_1 and the insulating layer 106_2 may have a region with the above thickness.

[0172] [Conductive Layer 112a1, Conductive Layer 112b1, Conductive Layer 112a2, and Conductive Layer 112b2] The conductive layers 112a1 and 112b1, and the conductive layers 112a2 and 112b2, which function as a source electrode and a drain electrode, respectively, can be formed using one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, or an alloy containing one or more of the above metals. The conductive layers 112a1 and 112b1, and the conductive layers 112a2 and 112b2 can be formed using a low-resistance conductive material containing one or more of copper, silver, gold, and aluminum. Copper and aluminum are particularly preferred because of their excellent mass productivity.

[0173] The conductive layers 112a1 and 112b1, and the conductive layers 112a2 and 112b2 can each be formed using a metal oxide film (also referred to as an oxide conductor). Examples of oxide conductors (OC) include In—Sn oxide (ITO), In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Zn oxide, In—Sn—Si oxide (ITSO), and In—Ga—Zn oxide.

[0174] Here, oxide conductors (OC) will be described. For example, when oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is added to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes more conductive and becomes an electric conductor. A metal oxide that has become an electric conductor can be called an oxide conductor.

[0175] The conductive layers 112a1 and 112b1, and the conductive layers 112a2 and 112b2 may each have a stacked structure of a conductive film containing the oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced.

[0176] The conductive layers 112a1 and 112b1, and the conductive layers 112a2 and 112b2 may each be a Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti). By using a Cu-X alloy film, it is possible to process the film by wet etching, thereby reducing manufacturing costs.

[0177] Note that the conductive layers 112a1 and 112b1 may be formed using the same material or different materials. The same applies to the conductive layers 112a2 and 112b2.

[0178] Here, the conductive layers 112a1, 112b1, 112a2, and 112b2 will be specifically described using a structure in which metal oxide is used for the semiconductor layers 108_1 and 108_2 as an example.

[0179] When an oxide semiconductor is used for the semiconductor layer 108_1 and the semiconductor layer 108_2, the conductive layer 112a1 and the conductive layer 112b1 and the conductive layer 112a2 and the conductive layer 112b2 are oxidized by oxygen contained in the semiconductor layer 108_1 and the semiconductor layer 108_2, which may result in an increase in resistance. The conductive layer 112a1 and the conductive layer 112b1 and the conductive layer 112a2 and the conductive layer 112b2 are oxidized by oxygen contained in the insulating layer 110_1 and the insulating layer 110_2, which may result in an increase in resistance. Furthermore, the conductive layer 112a1 and the conductive layer 112b1 and the conductive layer 112a2 and the conductive layer 112b2 are oxidized by oxygen contained in the semiconductor layer 108_1 and the semiconductor layer 108_2, which may result in an oxygen deficiency (V ＯWhen the conductive layers 112a1 and 112b1 and the conductive layers 112a2 and 112b2 are oxidized by oxygen contained in the insulating layers 110_1 and 110_2, the amounts of oxygen supplied from the insulating layers 110_1 and 110_2 to the semiconductor layers 108_1 and 108_2, respectively, may decrease.

[0180] The conductive layers 112a1 and 112b1, and the conductive layers 112a2 and 112b2, are preferably made of a material that is resistant to oxidation. The conductive layers 112a1 and 112b1, and the conductive layers 112a2 and 112b2, are preferably made of an oxide conductor. For example, In—Sn oxide (ITO) or In—Sn—Si oxide (ITSO) can be suitably used. The conductive layers 112a1 and 112b1, and the conductive layers 112a2 and 112b2, may each be made of a nitride conductor. Examples of nitride conductors include tantalum nitride and titanium nitride. The conductive layers 112a1 and 112b1, and the conductive layers 112a2 and 112b2 may each have a stacked structure of the above-mentioned materials.

[0181] By using a material that is difficult to oxidize for the conductive layers 112a1 and 112b1 and the conductive layers 112a2 and 112b2, it is possible to prevent oxidation due to oxygen contained in the semiconductor layer 108_1 or 108_2 or oxygen contained in the insulating layer 110_1 or 110_2, which can prevent an increase in resistance. Ｏ ) can be suppressed, and the amounts of oxygen supplied from the insulating layers 110_1 and 110_2 to the semiconductor layers 108_1 and 108_2, respectively, can be increased.

[0182] The conductive layers 104_1 and 104_2, which function as gate electrodes, can be formed using, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, and niobium, or an alloy containing one or more of the above metals. Furthermore, the conductive layers 104_1 and 104_2 can be formed using the same materials as those used for the conductive layers 112a1 and 112b1 and the conductive layers 112a2 and 112b2.

[0183] 1B and the like, the conductive layers 104_1 and 104_2 are shown as single-layer structures, but this is not limited thereto. For example, the conductive layers 104_1 and 104_2 may have a stacked structure of two or more layers. For example, when the conductive layers 104_1 and 104_2 have a two-layer stacked structure, a nitride or an oxide can be used as the first conductive layer (the conductive layer on the insulating layer 106_1 side and the conductive layer on the insulating layer 106_2 side, respectively), and a second conductive layer can be used as one or more of chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, and niobium, or an alloy containing one or more of the above metals. Furthermore, for example, when the conductive layer 104_1 and the conductive layer 104_2 have a three-layer stacked structure, the first conductive layer (the conductive layer on the insulating layer 106_1 side and the conductive layer 106_2 side, respectively) can be an alloy containing one or more of the above-mentioned metals as components, or a nitride of the metal or the alloy; the second conductive layer can be an alloy containing one or more of the above-mentioned metals as components; and the third conductive layer can be an alloy containing one or more of the above-mentioned metals as components, or a nitride of the metal or the alloy.

[0184] [Insulating Layer 192, Insulating Layer 194] The insulating layer 192 filling the opening 143 and the insulating layer 194 planarizing the top surface of the transistor 10_1 can each be made of an organic insulating material or an inorganic insulating material, or both. An organic insulating material is preferably used for the insulating layer 192 and the insulating layer 194. For example, by using an organic insulating material for the insulating layer 192 and the insulating layer 194, a film with excellent planarity can be easily formed at a relatively low temperature on a formation surface having steps.

[0185] Specific examples of organic insulating materials that can be used for the insulating layers 192 and 194 include acrylic resins, polyimide resins, epoxy resins, polyamide resins, polyimideamide resins, siloxane resins, benzocyclobutene-based resins, phenolic resins, and precursors of these resins. Photosensitive materials may also be used as the organic insulating material. Here, photosensitivity refers to the property of being sensitive to ultraviolet light, far ultraviolet light, electron beams, X-rays, and the like. This property is utilized to form a resist pattern by exposure. For exposure of silicon-containing resists, ultraviolet light, and more preferably far ultraviolet light, is primarily used. The raw material monomer used here may be aromatic, but to increase sensitivity, it is more desirable for the structure to be free of aromatic rings. For example, polyimide resins are preferably used for the insulating layers 192 and 194.

[0186] An inorganic insulating material can also be used for the insulating layer 192 and the insulating layer 194. Specific examples of the inorganic insulating material that can be used for the insulating layer 192 and the insulating layer 194 include the inorganic insulating materials that can be used for the insulating layer 110_1 and the insulating layer 110_2. For example, the insulating layer 192 and the insulating layer 194 are preferably made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like.

[0187] [Insulating Layer 193] The insulating layer 193 covering the transistor 10_1 is preferably made of an insulating material that does not easily diffuse impurities. Providing the insulating layer 193 can effectively prevent external impurities from diffusing into the transistor 10_1, thereby improving the reliability of the transistor 10_1. Examples of impurities include water and hydrogen. The insulating layer 193 can be an insulating layer containing an inorganic insulating material or an insulating layer containing an organic insulating material. The insulating layer 193 is preferably made of an inorganic insulating material. Specific examples of inorganic insulating materials that can be used for the insulating layer 193 include the inorganic insulating materials that can be used for the insulating layer 110a1, the insulating layer 110c1, the insulating layer 110a2, and the insulating layer 110c2. For example, the insulating layer 193 is preferably made of silicon nitride, silicon nitride oxide, hafnium oxide, aluminum oxide, or the like.

[0188] [Substrate 102] There are no significant limitations on the material of the substrate 102, but it is necessary that the material has at least heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or an organic resin substrate may be used as the substrate 102. Furthermore, any of these substrates on which semiconductor elements are provided may also be used as the substrate 102. The shape of the semiconductor substrate and the insulating substrate may be circular or rectangular.

[0189] A flexible substrate may be used as the substrate 102, and the semiconductor device 100 or the like may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the semiconductor device 100 or the like. The peeling layer can be used to separate a semiconductor device, after a part or all of the semiconductor device is completed thereon, from the substrate 102 and transfer the semiconductor device 100 or the like to another substrate. In this case, the semiconductor device 100 or the like can also be transferred to a substrate with poor heat resistance or a flexible substrate.

[0190] [Composition of Metal Oxide in Semiconductor Layer 108_1 and Semiconductor Layer 108_2] The composition of metal oxide in the semiconductor layer 108_1 and the semiconductor layer 108_2 will be described below.

[0191] The compositions of the metal oxides in the semiconductor layers 108_1 and 108_2 greatly affect the electrical characteristics and reliability of the transistors 10_1 and 10_2, respectively.

[0192] For example, by increasing the content of indium in the metal oxide, a transistor with a large on-state current can be realized.

[0193] When an In—Zn oxide is used for the semiconductor layers 108_1 and 108_2, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of zinc. For example, a metal oxide in which the atomic ratio of metal elements is In:Zn=1:1, In:Zn=2:1, In:Zn=3:1, In:Zn=4:1, In:Zn=5:1, In:Zn=7:1, or In:Zn=10:1, or a metal oxide in a range of these values, can be used.

[0194] When an In—Sn oxide is used for the semiconductor layers 108_1 and 108_2, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of tin. For example, a metal oxide in which the atomic ratio of metal elements is In:Sn=1:1, In:Sn=2:1, In:Sn=3:1, In:Sn=4:1, In:Sn=5:1, In:Sn=7:1, or In:Sn=10:1, or a ratio close to these, can be used.

[0195] When the semiconductor layer 108_1 and the semiconductor layer 108_2 are made of In-M-Zn oxide, a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is higher than the atomic ratio of the element M can be used. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of the element M. For example, the semiconductor layer 108_1 and the semiconductor layer 108_2 may be made of metal oxides in which the atomic ratio of metal elements is In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=5:1:9, In:M:Zn=5:1:10, In:M:Zn=5:1:11, In:M:Zn=5:1:12, In:M:Zn=5:1:13, In:M:Zn=5:1:14, In:M:Zn=5:1:15, In:M:Zn=5:1:16, In:M:Zn=5:1:17, In:M:Zn=5:1:18, In:M:Zn=5:1:19 ... Metal oxides having a ratio of In:M:Zn=6:1:6, In:M:Zn=10:1:3, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, or metal oxides having a ratio close to these can be used.

[0196] In addition, when the element M has a plurality of metal elements, the sum of the atomic ratios of the metal elements can be taken as the atomic ratio of the element M. For example, in the case of an In-Ga-Al-Zn oxide having gallium and aluminum as the element M, the sum of the atomic ratio of gallium and the atomic ratio of aluminum can be taken as the atomic ratio of the element M. Furthermore, it is preferable that the atomic ratios of indium, the element M, and zinc are within the above-mentioned range. For example, in the case of an In-Ga-Sn-Zn oxide having gallium and tin as the element M, the sum of the atomic ratio of gallium and the atomic ratio of tin can be taken as the atomic ratio of the element M. Furthermore, it is preferable that the atomic ratios of indium, the element M, and zinc are within the above-mentioned range.

[0197] It is preferable to use a metal oxide in which the ratio of the number of indium atoms to the number of atoms of metal elements contained in the metal oxide is 30 atomic % to 100 atomic %, preferably 30 atomic % to 95 atomic %, more preferably 35 atomic % to 95 atomic %, more preferably 35 atomic % to 90 atomic %, more preferably 40 atomic % to 90 atomic %, more preferably 45 atomic % to 90 atomic %, more preferably 50 atomic % to 80 atomic %, more preferably 60 atomic % to 80 atomic %, and more preferably 70 atomic % to 80 atomic %. For example, when an In—Ga—Zn oxide is used for the semiconductor layer 108_1 and the semiconductor layer 108_2, the ratio of the number of indium atoms to the total number of indium, gallium, and zinc atoms is preferably in the above-mentioned range.

[0198] In this specification and the like, the ratio of the number of indium atoms to the number of atoms of the contained metal element may be referred to as the indium content. The same applies to other metal elements.

[0199] By increasing the indium content of the metal oxide, a transistor with a large on-state current can be obtained. By applying the transistor to a transistor that requires a large on-state current, a semiconductor device with excellent electrical characteristics can be obtained.

[0200] The composition of a metal oxide can be analyzed using, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques may be used for analysis. Note that for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, or quantification may be difficult, or element M may not be detected.

[0201] In this specification, a "nearby composition" includes a range of ±30% of the desired atomic ratio. For example, when an atomic ratio is described as In:M:Zn = 4:2:3 or a composition near there, this includes a case where, when the atomic ratio of indium is 4, the atomic ratio of M is 1 to 3 and the atomic ratio of zinc is 2 to 4. Furthermore, when an atomic ratio is described as In:M:Zn = 5:1:6 or a composition near there, this includes a case where, when the atomic ratio of indium is 5, the atomic ratio of M is greater than 0.1 and less than 2 and the atomic ratio of zinc is greater than 5 and less than 7. Furthermore, when an atomic ratio is described as In:M:Zn = 1:1:1 or a composition near there, this includes a case where, when the atomic ratio of indium is 1, the atomic ratio of M is greater than 0.1 and less than 2 and the atomic ratio of zinc is greater than 0.1 and less than 2.

[0202] Here, the reliability of a transistor will be described. One of the indicators for evaluating the reliability of a transistor is a Gate Bias Temperature (GBT) stress test, in which a transistor is held at a high temperature while an electric field is applied to the gate. Among these, a test in which a positive potential (positive bias) is applied to the gate relative to the source potential and the drain potential while the transistor is held at a high temperature is called a Positive Bias Temperature (PBTS) test, and a test in which a negative potential (negative bias) is applied to the gate while the transistor is held at a high temperature is called a Negative Bias Temperature (NBTS) test. The PBTS test and the NBTS test performed under light irradiation are called a PBTIS (Positive Bias Temperature Illumination Stress) test and an NBTIS (Negative Bias Temperature Illumination Stress) test, respectively.

[0203] In an n-channel transistor, a positive potential is applied to the gate when the transistor is turned on (a state in which current flows). Therefore, the amount of change in threshold voltage in the PBTS test is one of the important items to be noted as an index of the reliability of the transistor.

[0204] By using a metal oxide that does not contain gallium or has a low gallium content for the semiconductor layer 108_1 and the semiconductor layer 108_2, a transistor with high reliability against positive bias application can be obtained. That is, a transistor with a small amount of fluctuation in threshold voltage in a PBTS test can be obtained. Furthermore, when a metal oxide containing gallium is used, it is preferable to make the gallium content lower than the indium content. This makes it possible to realize a highly reliable transistor.

[0205] One factor that causes the threshold voltage to fluctuate in the PBTS test is carrier trapping into defect levels at or near the interface between the semiconductor layer and the gate insulating layer. The greater the defect level density, the greater the number of carriers trapped in the defect levels, resulting in significant degradation in the PBTS test. By reducing the gallium content in the region of the semiconductor layer that contacts the gate insulating layer, the generation of the defect levels can be suppressed.

[0206] The following is a possible reason why using a metal oxide containing no gallium or with a low gallium content for the semiconductor layer can suppress fluctuations in threshold voltage in the PBTS test. Gallium contained in the metal oxide has the property of attracting oxygen more easily than other metal elements (e.g., indium or zinc). Therefore, it is presumed that gallium combines with excess oxygen in the gate insulating layer at the interface between the gallium-rich metal oxide and the gate insulating layer, making it easier to generate carrier (here, electron) trap sites. Therefore, when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, which is thought to cause fluctuations in threshold voltage.

[0207] More specifically, when In—Ga—Zn oxide is used for the semiconductor layers 108_1 and 108_2, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of gallium can be used for the semiconductor layers 108_1 and 108_2. It is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium. In other words, it is preferable to use a metal oxide in which the atomic ratios of metal elements satisfy In>Ga and Zn>Ga for the semiconductor layers 108_1 and 108_2.

[0208] For the semiconductor layer 108_1 and the semiconductor layer 108_2, it is preferable to use a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal element is more than 0 atomic % and 50 atomic % or less, preferably 0.1 atomic % to 40 atomic % or less, more preferably 0.1 atomic % to 35 atomic % or less, more preferably 0.1 atomic % to 30 atomic % or less, more preferably 0.1 atomic % to 25 atomic % or less, more preferably 0.1 atomic % to 20 atomic % or less, more preferably 0.1 atomic % to 15 atomic % or less, and more preferably 0.1 atomic % to 10 atomic % or less. By reducing the gallium content in the semiconductor layer, a transistor with high resistance to the PBTS test can be obtained. Note that by including gallium in the metal oxide, oxygen deficiency (V Ｏ ) is less likely to occur.

[0209] A metal oxide that does not contain gallium may be used for the semiconductor layer 108_1 and the semiconductor layer 108_2. For example, In—Zn oxide may be used for the semiconductor layer 108_1 and the semiconductor layer 108_2. In this case, increasing the atomic ratio of indium to the atomic number of metal elements contained in the metal oxide can improve the field-effect mobility of the transistor. On the other hand, increasing the atomic ratio of zinc to the atomic number of metal elements contained in the metal oxide can result in a metal oxide with high crystallinity, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving reliability. Furthermore, a metal oxide that does not contain gallium or zinc, such as indium oxide, may be used for the semiconductor layer 108_1 and the semiconductor layer 108_2. Using a metal oxide that does not contain gallium can significantly reduce fluctuations in threshold voltage, particularly in a PBTS test.

[0210] For example, an oxide containing indium and zinc can be used for the semiconductor layer 108_1 and the semiconductor layer 108_2. In this case, a metal oxide having an atomic ratio of metal elements of In:Zn=2:3 or a ratio close thereto can be used.

[0211] Although gallium has been used as a representative example, the present invention can also be applied to a case where the element M is used instead of gallium. For the semiconductor layers 108_1 and 108_2, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of the element M is preferably used. Also, a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of the element M is preferably used.

[0212] By using a metal oxide having a low content of the element M for the semiconductor layers 108_1 and 108_2, a transistor having high reliability against application of a positive bias can be obtained. By using the transistor as a transistor that is required to have high reliability against application of a positive bias, a highly reliable semiconductor device can be obtained.

[0213] Next, the reliability of the transistor against light will be described.

[0214] Light incident on a transistor may cause fluctuations in the electrical characteristics of the transistor. In particular, it is preferable that a transistor applied to a region where light may be incident exhibits small fluctuations in electrical characteristics under light irradiation and has high reliability against light. The reliability against light can be evaluated, for example, by the amount of fluctuation in threshold voltage in an NBTIS test.

[0215] Increasing the content of the element M in the metal oxide can provide a transistor with high reliability against light. That is, a transistor with a small variation in threshold voltage in an NBTIS test can be provided. Specifically, a metal oxide in which the atomic ratio of the element M is equal to or greater than the atomic ratio of indium has a larger band gap, and can reduce the variation in threshold voltage of the transistor in an NBTIS test. The band gap of the metal oxide included in the semiconductor layer 108_1 and the semiconductor layer 108_2 is preferably 2.0 eV or more, more preferably 2.5 eV or more, further preferably 3.0 eV or more, further preferably 3.2 eV or more, further preferably 3.3 eV or more, further preferably 3.4 eV or more, and further preferably 3.5 eV or more.

[0216] For example, the semiconductor layer 108_1 and the semiconductor layer 108_2 can be made of metal oxides having an atomic ratio of metal elements of In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Zn=1:3:3, or In:M:Zn=1:3:4, or metal oxides having an atomic ratio of these metal elements.

[0217] For the semiconductor layer 108_1 and the semiconductor layer 108_2, a metal oxide in which the ratio of the number of atoms of the element M to the number of atoms of the contained metal element is 20 atomic % to 70 atomic %, preferably 30 atomic % to 70 atomic %, more preferably 30 atomic % to 60 atomic %, more preferably 40 atomic % to 60 atomic %, and more preferably 50 atomic % to 60 atomic % can be suitably used.

[0218] When the semiconductor layer 108_1 and the semiconductor layer 108_2 are made of In—Ga—Zn oxide, a metal oxide having an atomic ratio of indium to gallium equal to or less than that of gallium can be used. For example, a metal oxide having an atomic ratio of metal elements of In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:1.2, In:Ga:Zn=1:3:2, In:Ga:Zn=1:3:3, or In:Ga:Zn=1:3:4, or a ratio thereof close to these, can be used.

[0219] For the semiconductor layer 108_1 and the semiconductor layer 108_2, a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal element is 20 atomic % or more and 60 atomic % or less, preferably 30 atomic % or more and 60 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, and more preferably 50 atomic % or more and 60 atomic % or less can be suitably used.

[0220] By using a metal oxide having a high content of element M for the semiconductor layers 108_1 and 108_2, a transistor with high reliability against light can be obtained. By using the transistor as a transistor that is required to have high reliability against light, a highly reliable semiconductor device can be obtained.

[0221] As described above, the electrical characteristics and reliability of a transistor differ depending on the composition of the metal oxide used for the semiconductor layer 108_1 and the semiconductor layer 108_2. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

[0222] The semiconductor layer 108_1 and the semiconductor layer 108_2 may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 108_1 and the semiconductor layer 108_2 may have the same or approximately the same composition. By using a stacked structure of metal oxide layers having the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs.

[0223] The two or more metal oxide layers included in the semiconductor layer 108_1 and the semiconductor layer 108_2 may have different compositions. For example, a stacked structure of a first metal oxide layer having an atomic ratio of In:M:Zn=1:3:4 or a composition similar thereto and a second metal oxide layer having an atomic ratio of In:M:Zn=1:1:1 or a composition similar thereto provided on the first metal oxide layer can be preferably used. Furthermore, it is particularly preferable to use gallium or aluminum as the element M. For example, a stacked structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO (registered trademark) can be used.

[0224] 3 shows a configuration example of a semiconductor device 100A having a different configuration from the semiconductor device 100 shown in FIGS. 1A to 2B. FIG. 3 is a cross-sectional view corresponding to the dashed dotted line A1-A2 in the plan view of the semiconductor device 100 shown in FIG. 1A.

[0225] The semiconductor device 100A shown in FIG. 3 is different from the semiconductor device 100 shown in FIGS. 1A to 2B mainly in that the transistor 10_1 includes a conductive layer 114_1 that functions as a second gate electrode (also referred to as a back gate electrode) and an insulating layer 110s1 that functions as a second gate insulating layer (also referred to as a back gate insulating layer), and that the insulating layer 110_1 is composed of six layers: an insulating layer 110d1, an insulating layer 110e1, an insulating layer 110f1, an insulating layer 110g1, an insulating layer 110h1, and an insulating layer 110i1.

[0226] In the semiconductor device 100A, the insulating layer 110_1 is composed of six layers: an insulating layer 110d1 on the conductive layer 112a1 and the substrate 102, an insulating layer 110e1 on the insulating layer 110d1, an insulating layer 110f1 on the insulating layer 110e1, an insulating layer 110g1 on the insulating layer 110f1, an insulating layer 110h1 on the insulating layer 110g1, and an insulating layer 110i1 on the insulating layer 110h1. A conductive layer 114_1 is provided between the insulating layer 110f1 and the insulating layer 110g1. The conductive layer 112a1, the insulating layer 110d1, the insulating layer 110e1, the insulating layer 110f1, the conductive layer 114_1, the insulating layer 110g1, the insulating layer 110h1, the insulating layer 110i1, and the insulating layer 112b1 have overlapping regions.

[0227] In the semiconductor device 100A, openings 143 reaching the conductive layer 112a1 are provided in the insulating layers 110d1, 110e1, 110f1, the conductive layer 114_1, 110g1, 110h1, 110i1, and 112b1.

[0228] An insulating layer 110s1 is provided in contact with the top surface of the conductive layer 112a1, the side surfaces of the insulating layers 110d1, 110e1, 110f1, the conductive layer 114_1, 110g1, 110h1, 110i1, and the conductive layer 112b1 within the opening 143. The upper end of the insulating layer 110s1 has a curved shape.

[0229] The semiconductor layer 108_1 is provided in contact with the top surface of the conductive layer 112a1 in the opening 143, the side surface of the insulating layer 110s1 in the opening 143, the curved portion of the insulating layer 110s1, and the top surface of the conductive layer 112b1.

[0230] In the transistor 10_1 included in the semiconductor device 100A, one surface of the semiconductor layer 108_1 in the opening 143 faces the conductive layer 104_1 with the insulating layer 106_1 interposed therebetween, and the other surface of the semiconductor layer 108_1 in the opening 143 faces the conductive layer 114_1 with the insulating layer 110s1 interposed therebetween. As described above, the conductive layer 114_1 functions as the second gate electrode of the transistor 10_1. The insulating layer 110s1 also functions as the second gate insulating layer of the transistor 10_1.

[0231] The transistor 10_1 of the semiconductor device 100A has two gate electrodes sandwiching the semiconductor layer 108_1, so that a gate electric field can be applied to carriers in the channel formation region from both sides of the semiconductor layer 108_1. Therefore, the transistor 10_1 can achieve a larger on-state current and a smaller off-state current than the transistor 10_1 of the semiconductor device 100 having only one gate electrode (conductive layer 104_1). The threshold voltage can be shifted toward the normally-off state. Furthermore, the saturation characteristics of the current flowing when the semiconductor device 100A operates in the saturation region can be improved (i.e., the magnitude of the drain current hardly changes with an increase in the drain voltage).

[0232] The insulating layer 110s1, which functions as the second gate insulating layer of the transistor 10_1, is preferably formed using a material that contains oxygen and releases oxygen by heat treatment or the like. For example, the insulating layer 110s1 can be formed using the same material as that used for the insulating layers 110b1 and 110b2. As a result, when a metal oxide is used for the semiconductor layer 108_1, for example, oxygen contained in the insulating layer 110s1 can be supplied to the metal oxide. As a result, oxygen vacancies in the metal oxide can be repaired, thereby improving the electrical characteristics and reliability of the transistor 10_1.

[0233] The conductive layer 114_1 which functions as the second gate electrode of the transistor 10_1 can be formed using the same material as that which can be used for the conductive layer 104_1 and the conductive layer 104_2.

[0234] Of the six insulating layers constituting the insulating layer 110_1, the insulating layer 110d1, the insulating layer 110f1, the insulating layer 110g1, and the insulating layer 110i1 can be made of the same materials as those used for the insulating layer 110a1, the insulating layer 110c1, the insulating layer 110a2, and the insulating layer 110c2. The insulating layer 110e1 and the insulating layer 110h1 can be made of the same materials as those used for the insulating layer 110b1 and the insulating layer 110b2.

[0235] As a result, for example, when a metal oxide is used for the semiconductor layer 108_1, oxygen contained in the insulating layers 110e1 and 110h1 can be supplied to the semiconductor layer 108_1 through the insulating layer 110s1. This can repair oxygen vacancies in the metal oxide, thereby improving the electrical characteristics and reliability of the transistor 10_1. Furthermore, oxygen contained in the insulating layer 110e1 can be prevented from diffusing to the conductive layer 112a1 through the insulating layer 110d1 and to the conductive layer 114_1 through the insulating layer 110f1. Similarly, oxygen contained in the insulating layer 110h1 can be prevented from diffusing to the conductive layer 114_1 through the insulating layer 110g1 and to the conductive layer 112b1 through the insulating layer 110i1.

[0236] Regarding the semiconductor device 100A, the contents described in the semiconductor device 100 can be referred to for the points other than those described above.

[0237] <Configuration Example 3 of Semiconductor Device> Fig. 4 shows a configuration example of a semiconductor device 100B having a different configuration from the semiconductor device 100A shown in Fig. 3. Fig. 4 is a cross-sectional view corresponding to the dashed dotted line A1-A2 in the plan view of the semiconductor device 100 shown in Fig. 1A.

[0238] 4 is different from the semiconductor device 100A shown in Fig. 3 mainly in that the transistor 10_1 includes an insulating layer 116 that covers the conductive layer 114_1 and functions as a blocking film for oxygen and hydrogen, and that the insulating layer 110_1 is composed of three layers, namely, an insulating layer 110a1, an insulating layer 110b1, and an insulating layer 110c1. Also, the shape of the insulating layer 110a1 is different from that of the semiconductor device 100 shown in Fig. 1B.

[0239] In the transistor 10_1 of the semiconductor device 100B, the end portion of the insulating layer 110a1 on the opening 143 side has a shape that protrudes further than the side surface of the insulating layer 110b1 on the opening 143 side, the side surface of the insulating layer 110c1 on the opening 143 side, and the side surface of the conductive layer 112b1 on the opening 143 side.

[0240] Furthermore, a conductive layer 114_1 is provided over the insulating layer 110a1 so as to overlap with the insulating layer 110b1, the insulating layer 110c1, and the conductive layer 112b1. An insulating layer 116 is provided in contact with the top surface and side surface of the conductive layer 114_1. An insulating layer 110s1 is provided in contact with the top surface of the insulating layer 110a1 in the opening 143, the side surface of the insulating layer 116 on the opening 143 side, the side surface of the insulating layer 110b1 on the opening 143 side, the side surface of the insulating layer 110c1 on the opening 143 side, and the side surface of the conductive layer 112b1 on the opening 143 side. The upper end of the insulating layer 110s1 has a curved shape.

[0241] The transistor 10_1 included in the semiconductor device 100B is different from the transistor 10_1 included in the semiconductor device 100A in that the insulating layer 110s1 is not in contact with the conductive layer 112a1. Therefore, it is possible to prevent problems such as a decrease in on-state current of the transistor 10_1 caused by oxygen in the insulating layer 110s1 diffusing toward the conductive layer 112a1 and oxidizing the conductive layer 112a1 to increase its resistance.

[0242] The semiconductor layer 108_1 is provided in contact with the top surface of the conductive layer 112a1 in the opening 143, the side surface of the insulating layer 110a1 on the opening 143 side, the side surface of the insulating layer 110s1 on the opening 143 side, the curved portion of the insulating layer 110s1, and the top surface of the conductive layer 112b1.

[0243] In the transistor 10_1 included in the semiconductor device 100B, one surface of the semiconductor layer 108_1 in the opening 143 faces the conductive layer 104_1 with the insulating layer 106_1 interposed therebetween, and the other surface of the semiconductor layer 108_1 in the opening 143 faces the conductive layer 114_1 with the insulating layer 110s1 and the insulating layer 116 interposed therebetween. As described above, the conductive layer 114_1 functions as a second gate electrode. The insulating layer 110s1 functions as a second gate insulating layer. The insulating layer 116 in a region sandwiched between the conductive layer 114_1 and the insulating layer 110s1 can also function as a second gate insulating layer.

[0244] The insulating layer 116 is preferably formed of a material that functions as a blocking film for oxygen and hydrogen. For example, the insulating layer 116 can be formed using the material that can be used for the insulating layer 110a1, the insulating layer 110c1, the insulating layer 110a2, and the insulating layer 110c2. By covering the top surface and side surface of the conductive layer 114_1 with the insulating layer 116 formed of such a material as shown in FIG. 4, it is possible to prevent problems, such as a decrease in the conductivity of the conductive layer 114_1 due to diffusion of oxygen contained in the insulating layer 110s1 and the insulating layer 110b1 into the conductive layer 114_1.

[0245] Here, the insulating layer 116 can be formed by a deposition method such as plasma CVD or sputtering. Alternatively, for example, the surface of the conductive layer 114_1 can be oxidized by plasma treatment or the like in an oxygen atmosphere to form the insulating layer 116 covering the top and side surfaces of the conductive layer 114_1. In this case, the insulating layer 116 having the same function as the insulating layer 110a1 and the insulating layer 110c1 can be formed without using a deposition method such as plasma CVD or sputtering. This reduces the number of times the above deposition method is applied, and may improve productivity. For example, productivity can be improved compared to the semiconductor device 100A having six insulating layers that constitute the insulating layer 110_1. In this case, it is preferable to use a material that is easily oxidized by plasma treatment or the like in an oxygen atmosphere for the conductive layer 114_1. For example, aluminum is preferable. In this case, the insulating layer 116 is an insulating layer made of an oxide of an element contained in the conductive layer 114_1. For example, when aluminum is used as the material of the conductive layer 114_1, the insulating layer 116 becomes aluminum oxide.

[0246] With respect to the semiconductor device 100B, the contents described for the semiconductor device 100 and the semiconductor device 100A can be referred to for the points other than those described above.

[0247] Although the semiconductor device 100B and the semiconductor device 100A shown in <Configuration Example 2 of Semiconductor Device> each have a configuration in which the transistor 10_1 has two gate electrodes and the transistor 10_2 has only one gate electrode, this is not limiting. For example, the transistor 10_1 may have only one gate electrode and the transistor 10_2 may have two gate electrodes.

[0248] 5 shows a configuration example of a semiconductor device 100C having a different configuration from the semiconductor device 100 shown in FIGS. 1A to 2B. FIG. 5 is a cross-sectional view corresponding to the dashed dotted line A1-A2 in the plan view of the semiconductor device 100 shown in FIG. 1A.

[0249] The semiconductor device 100C shown in FIG. 5 differs from the semiconductor device 100 shown in FIGS. 1A to 2B mainly in that it has a conductive layer 114_2 instead of the conductive layer 104_2 as a conductive layer that functions as the gate electrode of the transistor 10_2, that it has an insulating layer 110s2 that functions as a gate insulating layer, and that the insulating layer 110_2 is composed of six layers, namely, an insulating layer 110d2, an insulating layer 110e2, an insulating layer 110f2, an insulating layer 110g2, an insulating layer 110h2, and an insulating layer 110i2.

[0250] In the semiconductor device 100C, the insulating layer 110_2 is composed of six layers: an insulating layer 110d2 on the insulating layer 193 and the insulating layer 194; an insulating layer 110e2 on the insulating layer 110d2; an insulating layer 110f2 on the insulating layer 110e2; an insulating layer 110g2 on the insulating layer 110f2; an insulating layer 110h2 on the insulating layer 110g2; and an insulating layer 110i2 on the insulating layer 110h2. A conductive layer 114_2 is provided between the insulating layer 110f2 and the insulating layer 110g2. The conductive layer 112a2, the insulating layer 110d2, the insulating layer 110e2, the insulating layer 110f2, the conductive layer 114_2, the insulating layer 110g2, the insulating layer 110h2, the insulating layer 110i2, and the insulating layer 112b2 have overlapping regions.

[0251] In the semiconductor device 100C, openings 144 reaching the conductive layer 112a2 are provided in the insulating layer 193, the insulating layer 110d2, the insulating layer 110e2, the insulating layer 110f2, the conductive layer 114_2, the insulating layer 110g2, the insulating layer 110h2, the insulating layer 110i2, and the insulating layer 112b2.

[0252] An insulating layer 110s2 is provided in contact with the top surface of the conductive layer 112a2, the side surface of the insulating layer 193, the side surface of the insulating layer 110d2, the side surface of the insulating layer 110e2, the side surface of the insulating layer 110f2, the side surface of the conductive layer 114_2, the side surface of the insulating layer 110g2, the side surface of the insulating layer 110h2, the side surface of the insulating layer 110i2, and the side surface of the conductive layer 112b2, respectively, within the opening 144. The upper end of the insulating layer 110s2 has a curved shape.

[0253] The semiconductor layer 108_2 is provided in contact with the top surface of the conductive layer 112a2 in the opening 144, the side surface of the insulating layer 110s2 in the opening 144, the curved portion of the insulating layer 110s2, and the top surface of the conductive layer 112b2.

[0254] In the transistor 10_2 included in the semiconductor device 100C, the semiconductor layer 108_2 faces the conductive layer 114_2 in the opening 144 with the insulating layer 110s2 interposed therebetween.

[0255] For materials that can be used for the insulating layer 110s2 and the conductive layer 114_2, the descriptions of the insulating layer 110s1 and the conductive layer 114_1 in the semiconductor device 100A in <Configuration Example 2 of Semiconductor Device> can be referred to. For materials that can be used for the insulating layer 110d2, the insulating layer 110e2, the insulating layer 110f2, the insulating layer 110g2, the insulating layer 110h2, and the insulating layer 110i2, the descriptions of the insulating layer 110d1, the insulating layer 110e1, the insulating layer 110f1, the insulating layer 110g1, the insulating layer 110h1, and the insulating layer 110i1 in the semiconductor device 100A in <Configuration Example 2 of Semiconductor Device> can be referred to.

[0256] Here, in the semiconductor device 100 shown in Figures 1A to 2B, the semiconductor layer 108_2 of the transistor 10_2 surrounds the gate electrode (conductive layer 104_2) in a planar view, whereas in the semiconductor device 100C shown in Figure 5, the gate electrode (conductive layer 114_2) of the transistor 10_2 surrounds the semiconductor layer 108_2 in a planar view.

[0257] In the transistor 10_2 included in the semiconductor device 100C, the surface on which a channel of the semiconductor layer 108_2 is formed faces the conductive layer 114_2, which can prevent the surface from being directly affected by damage caused by deposition of a layer (e.g., the insulating layer 106_2) formed over the semiconductor layer 108_2. Therefore, the semiconductor device 100 may have a semiconductor layer 108_2 (especially a channel formation region) with fewer defects than the transistor 10_2 included in the semiconductor device 100. On the other hand, in the semiconductor device 100, the gate electrode (conductive layer 104_2) of the transistor 10_2 is provided to cover the opening 144, which can preferably reduce the step or unevenness of the transistor 10_2 compared to the transistor 10_2 included in the semiconductor device 100C.

[0258] With respect to the semiconductor device 100C, the contents described in connection with the semiconductor device 100 can be referred to for the points other than those described above.

[0259] 6 shows a configuration example of a semiconductor device 100D having a different configuration from the semiconductor device 100 shown in FIGS. 1A to 2B. FIG. 6 is a cross-sectional view corresponding to the dashed dotted line A1-A2 in the plan view of the semiconductor device 100 shown in FIG. 1A.

[0260] The semiconductor device 100D shown in FIG. 6 is different from the semiconductor device 100 shown in FIGS. 1A to 2B mainly in that both the transistor 10_1 and the transistor 10_2 have second gate electrodes.

[0261] For the transistor 10_1 in the semiconductor device 100D, the description of the transistor 10_1 included in the semiconductor device 100A in <Structure Example 2 of Semiconductor Device> can be referred to.

[0262] The transistor 10_2 in the semiconductor device 100D can be said to have a structure in which a conductive layer 104_2 is added to the transistor 10_2 included in the semiconductor device 100C shown in <Structural Example 4 of Semiconductor Device>. The conductive layer 104_2 is in contact with the top surface of the insulating layer 106_2 and is provided to have a region overlapping with the opening 144.

[0263] In the transistor 10_2 of the semiconductor device 100D, one surface of the semiconductor layer 108_2 in the opening 144 faces the conductive layer 104_2 through the insulating layer 106_2, and the other surface of the semiconductor layer 108_2 in the opening 144 faces the conductive layer 114_2 through the insulating layer 110s2.

[0264] In the transistor 10_2, the conductive layer 104_2 functions as a gate electrode, and part of the insulating layer 106_2 functions as a gate insulating layer. The conductive layer 114_2 functions as a second gate electrode, and part of the insulating layer 110s2 functions as a second gate insulating layer. Regarding the structure of the transistor 10_2 other than the conductive layer 104_2, the description of the transistor 10_2 included in the semiconductor device 100C in <Structure Example 4 of Semiconductor Device> can be referred to.

[0265] In the semiconductor device 100D, since both the transistor 10_1 and the transistor 10_2 have two gate electrodes, a larger on-state current can be achieved overall than in a semiconductor device in which one or both of the transistors have one gate electrode. Also, a smaller off-state current can be achieved overall. Furthermore, the threshold voltage of each transistor can be shifted toward the normally-off state. Furthermore, the saturation characteristics of the current flowing when each transistor operates in the saturation region can be improved.

[0266] With respect to the semiconductor device 100D, the contents described in connection with the semiconductor device 100 can be referred to for the points other than those described above.

[0267] 7A and 7B show a configuration example of a semiconductor device 200 having a different configuration from the semiconductor device 100 shown in FIGS. 1A to 2B. Fig. 7A is a cross-sectional view corresponding to the dashed dotted line A1-A2 in the plan view of the semiconductor device 100 shown in Fig. 1A. Fig. 7B is a circuit diagram illustrating the configuration of the semiconductor device 200.

[0268] In the semiconductor device 200, the transistors 10_1 and 10_2 have the same structures as the transistors 10_1 and 10_2 included in the semiconductor device 100, but are different from the semiconductor device 100 in the way the two transistors are connected.

[0269] Specifically, as shown in FIG. 2B, the semiconductor device 100 has a structure in which the gate electrode (conductive layer 104_1) of the transistor 10_1 is connected to one of the source electrode and the drain electrode (conductive layer 112a2) of the transistor 10_2.

[0270] 7B , the semiconductor device 200 has a structure in which one of the source electrodes or drain electrodes of the transistor 10_1 and the transistor 10_2 (the conductive layer 112a1 and the conductive layer 112a2) is connected to each other, the other of the source electrodes or drain electrodes (the conductive layer 112b1 and the conductive layer 112b2) is connected to each other, and the gate electrodes (the conductive layer 104_1 and the conductive layer 104_2) are connected to each other. That is, the semiconductor device 200 has a structure in which the transistor 10_1 and the transistor 10_2 are connected in parallel.

[0271] 7A , the cross-sectional view of the semiconductor device 200 taken along the dashed dotted line A1-A2 shows that the insulating layer 193 is sandwiched between the conductive layer 104_1 and the conductive layer 112a2, and the conductive layer 104_1 and the conductive layer 112a2 are not in contact with each other.

[0272] As described above, the semiconductor device of one embodiment of the present invention can also have a stacked structure of two transistors connected in a different manner from that of the semiconductor device 100. For example, as in the semiconductor device 200 described above, a stacked structure of the transistors 10_1 and 10_2 connected in parallel can also be used. In this way, a semiconductor device with high on-state current can be realized without increasing the occupation area.

[0273] 7A and 7B show a structure example in which two transistors connected in parallel (the transistor 10_1 and the transistor 10_2) are stacked, but this is not the only possible configuration. The semiconductor device of one embodiment of the present invention can also have a structure in which three or more transistors connected in parallel are stacked. The more transistors connected in parallel, the larger the on-state current of the entire semiconductor device, which is preferable.

[0274] With regard to the semiconductor device 200, the contents described for the semiconductor device 100 can be referred to for the points other than those described above.

[0275] 8A and 8B show a configuration example of a semiconductor device 300 having a different configuration from the semiconductor device 100 shown in FIGS. 1A to 2B. Fig. 8A is a cross-sectional view corresponding to the dashed dotted line A1-A2 in the plan view of the semiconductor device 100 shown in Fig. 1A. Fig. 8B is a circuit diagram illustrating the configuration of the semiconductor device 300.

[0276] In the semiconductor device 300, the transistors 10_1 and 10_2 have the same structures as the transistors 10_1 and 10_2 included in the semiconductor device 100, but are different from the semiconductor device 100 in the way the two transistors are connected.

[0277] Specifically, as shown in FIG. 2B, the semiconductor device 100 has a structure in which the gate electrode (conductive layer 104_1) of the transistor 10_1 is connected to one of the source electrode and the drain electrode (conductive layer 112a2) of the transistor 10_2.

[0278] 8B , the semiconductor device 300 has a structure in which the other of the source electrode and the drain electrode of the transistor 10_1 (conductive layer 112b1) is connected to the other of the source electrode and the drain electrode of the transistor 10_2 (conductive layer 112a2), and the gate electrode of the transistor 10_1 (conductive layer 104_1) is connected to the gate electrode of the transistor 10_2 (conductive layer 104_2). That is, the semiconductor device 300 has a structure in which the transistors 10_1 and 10_2 are connected in series.

[0279] 8A , the cross-sectional view of the semiconductor device 300 taken along the dashed dotted line A1-A2 shows that the insulating layer 193 is sandwiched between the conductive layer 104_1 and the conductive layer 112a2, and the conductive layer 104_1 and the conductive layer 112a2 are not in contact with each other.

[0280] As described above, the semiconductor device of one embodiment of the present invention can also have a stacked structure of two transistors connected in a different manner from that of the semiconductor device 100. For example, as in the semiconductor device 300 described above, a stacked structure of the transistors 10_1 and 10_2 connected in series can also be used. In this way, a semiconductor device with low off-state current can be realized without increasing the occupation area.

[0281] The two transistors connected in series can be regarded as one transistor having a long channel length, and therefore, by connecting the two transistors in series, the source-drain breakdown voltage can be increased compared to the transistor 10_1 or the transistor 10_2 alone.

[0282] 8A and 8B show a structure example in which two series-connected transistors (transistor 10_1 and transistor 10_2) are stacked, but this is not limiting. The semiconductor device of one embodiment of the present invention can also have a structure in which three or more series-connected transistors are stacked. Increasing the number of series-connected transistors is preferable because the off-state current of the entire semiconductor device can be reduced. Furthermore, when the semiconductor device is considered as one transistor, this is preferable because the source-drain withstand voltage can be increased.

[0283] With respect to the semiconductor device 300, the contents described for the semiconductor device 100 can be referred to for the points other than those described above.

[0284] <Example of Manufacturing Method of Semiconductor Device> An example of a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described below with reference to the drawings. Here, the semiconductor device 100 shown in FIGS. 1A to 2B will be described as an example.

[0285] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0286] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source; DC sputtering, which uses a direct current power supply; and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is preferably used for film formation using an insulating target. DC sputtering is mainly used when film formation is performed using a conductive target. In addition to forming conductive films, DC sputtering can also form insulating films by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used when forming films of compounds such as oxides, nitrides, and carbides by reactive sputtering.

[0287] CVD methods can be classified into plasma-enhanced CVD (PECVD) methods that utilize plasma, thermal CVD (TCVD) methods that utilize heat, photo-CVD (photo-CVD) methods that utilize light, etc. Furthermore, CVD methods can be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0288] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can reduce plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, or elements included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0289] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0290] The CVD and ALD methods differ from sputtering methods in that particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio, for example. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0291] Furthermore, the CVD method allows deposition of a film of any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film whose composition changes continuously by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0292] In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0293] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by methods such as spin coating, dipping, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife coating, slit coating, roll coating, curtain coating, and knife coating.

[0294] When processing a thin film that constitutes a semiconductor device, it can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0295] There are two typical photolithography methods: one is a method in which a resist mask is formed on a thin film to be processed, the thin film is processed by etching or the like, and the resist mask is then removed; the other is a method in which a photosensitive thin film is formed, and then the thin film is exposed to light and developed to be processed into a desired shape.

[0296] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0297] For etching the thin film, for example, dry etching, wet etching, or sandblasting can be used.

[0298] Typically, a polishing method such as CMP can be suitably used as the planarization treatment of the thin film. Alternatively, a reflow method, in which the conductive layer is subjected to a heat treatment to fluidize it, can be suitably used. Alternatively, a combination of the reflow method and CMP can be used.

[0299] Alternatively, a process may be used in which a planarizing film is formed on an uneven film surface and then highly anisotropically etched (e.g., dry etching) on ​​the planarizing film to form a film with a flat upper surface, or a process may be used in which a planarizing film and a photoresist are formed in that order on the uneven film surface and then highly anisotropically etched on the planarizing film and the photoresist to fill the recesses with only the planarizing film and flatten the entire upper surface (these processes are sometimes referred to as etch-back processes). The etch-back process does not require a high-temperature (e.g., about 800°C) heating process as in the reflow process, and therefore there is no need to worry about damage to elements during fabrication due to the heating process. Furthermore, the etch-back process is suitable because it can be applied to elements on large substrates that are difficult to process using CMP due to the effects of warping, etc.

[0300] Other examples of the planarization treatment for a thin film include dry etching and plasma treatment. The polishing, dry etching, and plasma treatment may be performed multiple times, or a combination of these may be performed. When a combination of these treatments is performed, the order of the steps is not particularly limited, and may be appropriately determined according to the unevenness of the surface to be treated.

[0301] To precisely process a thin film to a desired thickness, for example, a CMP method is used. In this method, the thin film is first polished at a constant processing speed until a portion of the top surface thereof is exposed. Then, the thin film is polished at a slower processing speed until the thin film reaches the desired thickness, thereby enabling highly precise processing.

[0302] Methods for detecting the end point of polishing include an optical method in which light is irradiated onto the surface of the surface to be treated and changes in the reflected light are detected, a physical method in which changes in the polishing resistance that the processing device receives from the surface to be treated are detected, and a method in which magnetic field lines are applied to the surface to be treated and changes in the magnetic field lines due to the eddy currents that are generated are used.

[0303] After the upper surface of the thin film is exposed, the thickness of the thin film can be controlled with high precision by performing a polishing process at a slow processing speed while monitoring the thickness of the thin film by an optical method such as a laser interferometer. If necessary, the polishing process may be performed multiple times until the thin film reaches the desired thickness.

[0304] 9A to 31C are diagrams illustrating a method for manufacturing the semiconductor device 100. In each figure, A shows a plan view corresponding to FIG. 1A. In each figure, B shows a cross-sectional view taken along dashed line A1-A2 in the plan view shown in FIG. 1A. In each figure, C shows a cross-sectional view taken along dashed line B1-B2 in the plan view shown in FIG. 1A.

[0305] First, a conductive film to be the conductive layer 112a1 is formed over the substrate 102, and then part of the conductive film is removed to form the conductive layer 112a1 (FIGS. 9A to 9C). The conductive film can be formed by, for example, a sputtering method. The conductive film can be processed by one or both of a wet etching method and a dry etching method.

[0306] Subsequently, an insulating film 110a1f, an insulating film 110b1f, and an insulating film 110c1f are formed in this order on the conductive layer 112a1 and the substrate 102.

[0307] The insulating film 110a1f can be made of any of the materials that can be used for the insulating layer 110a1 described above.

[0308] The insulating film 110a1f can be formed using, for example, silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide.

[0309] Specifically, the insulating film 110a1f can be formed by, for example, a silicon nitride film by a sputtering method, a PEALD method, or an aluminum oxide film by a sputtering method.

[0310] Alternatively, for example, a structure in which aluminum oxide and silicon nitride are stacked can be used, for example, a structure in which aluminum oxide formed by sputtering and silicon nitride formed by PEALD are stacked.

[0311] The insulating film 110b1f can be made of any of the materials that can be used for the insulating layer 110b1 described above.

[0312] For example, silicon oxide, silicon oxynitride, or the like can be suitably used as the insulating film 110b1f.

[0313] Specifically, the insulating film 110b1f can be formed by, for example, a silicon oxide film by a sputtering method, a silicon oxide film by a PECVD method, or a silicon oxynitride film by a PECVD method.

[0314] Alternatively, for example, a silicon oxide film formed by sputtering and a silicon oxide or silicon oxynitride film formed by PECVD can be stacked and used.

[0315] After the insulating film 110b1f is formed, heat treatment may be performed. By performing the heat treatment, water and hydrogen can be released from the surface and the interior of the insulating film 110b1f.

[0316] The temperature of the heat treatment is preferably 150° C. or higher and lower than the strain point of the substrate, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, and further preferably 350° C. or higher and 400° C. or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. As the nitrogen-containing atmosphere or the oxygen-containing atmosphere, dry air (CDA: Clean Dry Air) may be used. Note that the atmosphere preferably contains as little hydrogen, water, or the like as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower. Using an atmosphere containing as little hydrogen, water, or the like as possible can prevent hydrogen, water, or the like from being taken into the insulating film 110b1f as much as possible. The heat treatment can be performed using, for example, an oven or a rapid thermal annealing (RTA) device. By using an RTA device, the heat treatment time can be shortened.

[0317] After the heat treatment, a step of supplying oxygen to the insulating film 110b1f may be performed. For example, after the insulating film 110b1f is formed, a metal oxide layer may be formed over the insulating film 110b1f to supply oxygen to the insulating film 110b1f. Alternatively, heat treatment may be performed after the metal oxide layer is formed. By performing heat treatment after the metal oxide layer is formed, oxygen can be effectively supplied from the metal oxide layer to the insulating film 110b1f, and oxygen can be contained in the insulating film 110b1f. In a later step, the oxygen supplied to the insulating film 110b1f is supplied to the semiconductor layer 108_1, thereby reducing oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0318] After the metal oxide layer is formed or after the heat treatment, oxygen may be supplied to the insulating film 110b1f through the metal oxide layer. Examples of a method for supplying oxygen include ion implantation, ion doping, plasma immersion ion implantation, and plasma treatment. For the plasma treatment, an apparatus that converts oxygen gas into plasma using high-frequency power can be preferably used. Examples of apparatus that convert gas into plasma using high-frequency power include a plasma etching apparatus and a plasma ashing apparatus.

[0319] The metal oxide layer may be an insulating layer or a conductive layer, and may be, for example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO).

[0320] For the metal oxide layer, it is preferable to use an oxide material containing one or more of the same elements as those of the semiconductor layer 108_1. In particular, it is preferable to use an oxide semiconductor material applicable to the semiconductor layer 108_1. This allows the metal oxide layer to be formed using the same sputtering target as that of the semiconductor layer 108_1, thereby reducing manufacturing costs.

[0321] When a metal oxide material containing indium and gallium is used for the metal oxide layer, a material having a higher gallium content than the semiconductor layer 108_1 can be used. By using a material having a higher gallium content for the metal oxide layer, the blocking property against oxygen can be further improved. This is preferable because oxygen contained in the insulating film 110b1f can be prevented from being released to the outside.

[0322] The metal oxide layer is preferably formed in an atmosphere containing oxygen, for example. In particular, it is preferably formed by a sputtering method in an atmosphere containing oxygen. This allows oxygen to be suitably supplied to the insulating film 110b1f during the formation of the metal oxide layer.

[0323] Next, the metal oxide layer is removed, for example, by wet etching.

[0324] The process of supplying oxygen to the insulating film 110b1f is not limited to the above-described method. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, or the like may be supplied to the insulating film 110b1f by ion doping, ion implantation, plasma treatment, or the like. Alternatively, a film that suppresses oxygen desorption may be formed over the insulating film 110b1f, and then oxygen may be supplied to the insulating film 110b1f through the film. The film is preferably removed after supplying oxygen. The film that suppresses oxygen desorption may be a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, or tungsten.

[0325] The insulating film 110c1f can be made of any of the materials that can be used for the insulating layer 110c1 described above.

[0326] For the material and deposition method that can be used for the insulating film 110c1f, the above description of the material and deposition method that can be used for the insulating film 110a1f can be referred to.

[0327] Next, a conductive film 112b1f is formed over the insulating film 110c1f (FIGS. 10A to 10C). The conductive film 112b1f can be formed using any of the materials that can be used for the conductive layer 112b1 described above. The conductive film 112b1f can be formed by, for example, a sputtering method.

[0328] Next, a part of the conductive film 112b1f is removed to form a conductive layer 112b1e (FIGS. 11A to 11C). The conductive layer 112b1e may be formed by wet etching or dry etching, or both. The conductive layer 112b1e is formed to have a region overlapping with the conductive layer 112a1.

[0329] Next, a process is performed to remove parts of the conductive layer 112b1e, the insulating film 110c1f, the insulating film 110b1f, and the insulating film 110a1f, thereby forming an opening 143 that reaches the conductive layer 112a1. For example, dry etching can be suitably used for this process. By this process, the conductive layer 112b1, the insulating layer 110c1, the insulating layer 110b1, and the insulating layer 110a1, each having an opening, are formed (FIGS. 12A to 12C).

[0330] Next, a semiconductor film to be the semiconductor layer 108_1 is formed in contact with the top surface of the conductive layer 112a1 in the opening 143, the side surfaces of the insulating layer 110_1 (insulating layers 110a1, 110b1, and 110c1) in the opening 143, the side surfaces of the conductive layer 112b1 in the opening 143, and the top surface of the conductive layer 112b1. Then, a portion of the semiconductor film is removed by etching to form the semiconductor layer 108_1 ( FIGS. 13A to 13C ). The semiconductor layer 108_1 is provided to have a region overlapping with the opening 143. Furthermore, the semiconductor layer 108_1 is provided so that an end portion thereof has a region in contact with the conductive layer 112b1.

[0331] For the semiconductor film to be the semiconductor layer 108_1, any of the above-described materials that can be used for the semiconductor layer 108_1 can be used as appropriate.

[0332] The semiconductor film to be the semiconductor layer 108_1 can be formed by, for example, a sputtering method. For example, when a metal oxide is used for the semiconductor layer 108_1, the semiconductor layer 108_1 can be formed by a sputtering method using a metal oxide target. The sputtering method is preferable because a film with a low hydrogen content can be formed relatively easily.

[0333] When a metal oxide is used for the semiconductor layer 108_1, the semiconductor layer 108_1 can be formed by an ALD method using a precursor containing a constituent metal element and an oxidizing agent.

[0334] For example, when forming an In—Ga—Zn oxide, three precursors, i.e., a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, can be used, or two precursors, i.e., a precursor containing indium and a precursor containing gallium and zinc, can be used.

[0335] As the precursor containing indium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, and the like can be used.

[0336] Furthermore, examples of precursors that can be used that contain gallium include trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, and diethylchlorogallium.

[0337] Furthermore, as a precursor containing zinc, dimethyl zinc, diethyl zinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), zinc chloride, etc. can be used.

[0338] As the oxidizing agent, for example, ozone, oxygen, water, etc. can be used.

[0339] Methods for controlling the composition of the resulting film include adjusting the flow rate ratio of the source gases, the time for which the source gases are flowed, the order in which the source gases are flowed, etc. By adjusting these, it is also possible to form a film whose composition changes continuously. It is also possible to form films with different compositions successively.

[0340] The ALD method is preferably used to form the semiconductor film to be the semiconductor layer 108_1 because the semiconductor layer 108_1 can be formed with a uniform thickness on the side surface of the insulating layer 110_1.

[0341] After the semiconductor film to be the semiconductor layer 108_1 is formed, heat treatment may be performed. The heat treatment can reduce water and hydrogen contained in the semiconductor film and supply oxygen from the insulating layer 110_1 to the semiconductor film. Note that the heat treatment may be performed after the semiconductor film is processed.

[0342] The substrate temperature (stage temperature) during the formation of the semiconductor layer 108_1 is preferably from room temperature (25° C.) to 200° C., more preferably from room temperature to 130° C. By setting the substrate temperature within the above range, bending or distortion of the substrate can be suppressed when a large-area glass substrate is used.

[0343] The higher the substrate temperature during the formation of the metal oxide layer, the higher the crystallinity of the metal oxide layer that can be formed.Furthermore, the higher the oxygen flow rate ratio, the higher the crystallinity of the metal oxide layer that can be formed.

[0344] Subsequently, the insulating layer 106_1 is formed to cover the semiconductor layer 108_1, the conductive layer 112b1, and the insulating layer 110c1 (FIGS. 14A to 14C). The insulating layer 106_1 has regions in contact with the top and side surfaces of the semiconductor layer 108_1, the top and side surfaces of the conductive layer 112b1, and the top surface of the insulating layer 110c1.

[0345] The insulating layer 106_1 can be formed using any of the above-described materials as appropriate.

[0346] The insulating layer 106_1 can be formed by, for example, an ALD method. The ALD method is preferable because the insulating layer 106_1 can be formed with good coverage over the semiconductor layer 108_1 formed to cover the opening 143. Note that, if the semiconductor layer 108_1 can be sufficiently covered, a method other than the ALD method may be used to form the insulating layer 106_1. For example, a PECVD method, a sputtering method, or the like can be used. This allows the insulating layer 106_1 to be formed at a higher rate than when the ALD method is used, thereby increasing productivity.

[0347] Next, a conductive film 104_1f is formed over the insulating layer 106_1 (FIGS. 15A to 15C). The conductive film 104_1f can be formed using any of the materials that can be used for the conductive layer 104_1 described above. The conductive film 104_1f can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like, as appropriate. The conductive film 104_1f is preferably formed in contact with the insulating layer 106_1 that faces the side surface of the insulating layer 110_1 in the opening 143. Therefore, the conductive film 104_1f is preferably formed by a method that has good coverage or embedding properties, and more preferably by a CVD method, an ALD method, or the like.

[0348] Subsequently, an insulating film 192f is formed over the conductive film 104_1f. The insulating film 192f can be formed using any of the materials that can be used for the insulating layer 192 described above. The insulating film 192f is formed so as to fill the opening 143. The insulating film 192f is formed so that the height of its top surface is higher than the height of the top surface of any region of the conductive film 104_1f. For example, when an organic insulating material such as polyimide resin is used for the insulating film 192f, the insulating film 192f having a substantially flat top surface can be easily formed by a method such as spin coating.

[0349] Next, light 139 (for example, visible light or ultraviolet light) is irradiated onto the insulating film 192f through the mask 136 to expose the region of the insulating film 192f that does not overlap with the mask 136 (FIGS. 16A to 16C). Here, when a positive photosensitive resin composition such as polyimide resin is used for the insulating film 192f, the light 139 is irradiated via the mask 136 onto the region where the insulating layer 192 will not be formed in a later step.

[0350] Subsequently, the exposed region of the insulating film 192f is removed by development, thereby forming an insulating layer 192e (FIGS. 17A to 17C). The insulating layer 192e is formed in a region overlapping with the opening 143. In addition, the upper surface of the conductive film 104_1f is exposed in the region from which the insulating film 192f has been removed by development. Here, when a polyimide resin is used for the insulating film 192f, it is preferable to use an alkaline solution as the developer, such as a tetramethylammonium hydroxide (TMAH) aqueous solution.

[0351] After the development, a step of removing the residue (so-called scum) remaining after the development may be carried out. For example, the residue can be removed by ashing using oxygen plasma. A step of removing the residue may also be carried out after each of the development steps described below.

[0352] Subsequently, the insulating layer 192e is subjected to an etch-back process, which forms an insulating layer 192 having a flat upper surface and filling the entire opening 143 (FIGS. 18A to 18C).

[0353] 16A to 18C , the method of using etch-back treatment to form the insulating layer 192 is described, but this is not limited to this. In one embodiment of the present invention, the insulating layer 192 can also be formed without using etch-back treatment.

[0354] 15A to 15C, the insulating film 192f is formed over the conductive film 104_1f. Note that the thickness of the insulating film 192f is smaller than that in the case where the etch-back process is performed.

[0355] Next, as described above, the insulating film 192f is irradiated with light 139 through the mask 136, and the regions of the insulating film 192f that do not overlap with the mask 136 are exposed to light (FIGS. 19A to 19C).

[0356] Subsequently, development is performed to remove the exposed regions of the insulating film 192f, thereby forming the insulating layer 192 only in the region overlapping the opening 143 and exposing the top surface of the conductive film 104_1f in other regions (FIGS. 20A to 20C). In this way, depending on the film thickness of the insulating film 192f when it is formed, it is possible to form the insulating layer 192 without using an etch-back process, thereby reducing the number of steps. However, when this method is used, a gently convex shape is likely to be formed on the top surface of the insulating layer 192, as shown in FIGS. 20B and 20C. Therefore, if it is desired to further improve the flatness of the top surface of the insulating layer 192, it may be preferable to use the etch-back process described above.

[0357] Next, a conductive film 112a2f is formed over the insulating layer 192 and the conductive film 104_1f (FIGS. 21A to 21C). The conductive film 112a2f can be formed using any of the materials that can be used for the conductive layer 112a2 described above. The conductive film 112a2f can be formed by a sputtering method, for example.

[0358] Next, the conductive layer 112a2 and the conductive layer 104_1 are formed by removing parts of the conductive film 112a2f and the conductive film 104_1f ( FIGS. 22A to 22C ). The conductive layer 112a2 and the conductive layer 104_1 are formed to have regions overlapping with the opening 143. The ends of the conductive layer 112a2 and the conductive layer 104_1 are formed to approximately coincide with each other in a plan view. Furthermore, the top surface of the insulating layer 106_1 is exposed in the regions from which the conductive films 112a2f and 104_1f are removed. The conductive layer 112a2 and the conductive layer 104_1 may be formed by wet etching or dry etching, or both.

[0359] As a result, the transistor 10_1 is formed.

[0360] Subsequently, an insulating film 193f is formed over the conductive layer 112a2 and the insulating layer 106_1. The insulating film 193f is provided in contact with the top surface and side surfaces of the conductive layer 112a2, the side surfaces of the conductive layer 104_1, and the top surface of the insulating layer 106_1. The insulating film 193f can be formed using any of the materials that can be used for the insulating layer 193 described above. The insulating film 193f can be formed by, for example, an ALD method, a PECVD method, a sputtering method, or the like.

[0361] Next, an insulating film 194f is formed on the insulating film 193f (FIGS. 23A to 23C). The insulating film 194f can be formed using any of the materials that can be used for the insulating layer 194 described above. The insulating film 194f is formed so that its upper surface is higher than the upper surface of any region of the insulating film 193f. For example, when an organic insulating material such as polyimide resin is used for the insulating film 194f, the insulating film 194f can be easily formed with a substantially flat upper surface by a method such as spin coating.

[0362] Next, an etch-back process is performed on the insulating film 194f. The etch-back process is performed until the highest region of the insulating film 193f seen from the substrate surface (the region overlapping the conductive layer 112a2) is exposed. This process forms an insulating layer 194 having a flat upper surface and a height that is approximately the same as the upper surface of the highest region of the insulating film 193f seen from the substrate surface (FIGS. 24A to 24C).

[0363] 23A to 24C , the method of using etch-back treatment to form the insulating layer 194 is described, but this is not limited to this. In one embodiment of the present invention, the insulating layer 194 can also be formed without using etch-back treatment.

[0364] 23A to 23C, the insulating film 193f is formed, and then the insulating film 194f is formed on the insulating film 193f. However, at this time, the insulating film 194f is formed to have a thickness thinner than that in the case where the etch-back process is performed.

[0365] Next, light 139 is irradiated onto the insulating film 194f through the mask 138, and the regions of the insulating film 194f that do not overlap with the mask 138 are exposed to light (FIGS. 25A to 25C).

[0366] Subsequently, development is performed to remove the exposed areas of the insulating film 194f, thereby forming the insulating layer 194 only in the areas that do not overlap the opening 143 and exposing the top surface of the insulating film 193f in other areas (FIGS. 26A to 26C). In this way, depending on the thickness of the insulating film 194f when it is formed, it is possible to form the insulating layer 194 without using an etch-back process, thereby reducing the number of steps. However, when using this method, a gently convex shape is likely to form on the top surface of the insulating layer 194, as shown in FIGS. 26B and 26C. Therefore, if it is desired to further increase the flatness of the top surface of the insulating layer 194, it may be preferable to use the etch-back process described above.

[0367] Next, the insulating film 110a2f, the insulating film 110b2f, the insulating film 110c2f, and the conductive film 112b2f are formed in this order over the insulating layer 194 and the insulating film 193f (FIGS. 27A to 27C). For materials that can be used for the insulating film 110a2f, the insulating film 110b2f, the insulating film 110c2f, and the conductive film 112b2f, as well as their formation methods, the descriptions of the insulating film 110a1f, the insulating film 110b1f, the insulating film 110c1f, and the conductive film 112b1f can be referred to, respectively.

[0368] Next, a part of the conductive film 112b2f is removed to form a conductive layer 112b2e (FIGS. 28A to 28C). The conductive layer 112b2e may be formed by wet etching or dry etching, or both. The conductive layer 112b2e is formed to have a region overlapping with the conductive layer 112a2.

[0369] Next, a process is performed to remove parts of the conductive layer 112b2e, the insulating film 110c2f, the insulating film 110b2f, the insulating film 110a2f, and the insulating film 193f, thereby forming an opening 144 that reaches the conductive layer 112a2. For example, dry etching can be suitably used for this process. By this process, the conductive layer 112b2, the insulating layer 110c2, the insulating layer 110b2, the insulating layer 110a2, and the insulating layer 193, each having an opening, are formed ( FIGS. 29A to 29C ).

[0370] Next, a semiconductor film to be the semiconductor layer 108_2 is formed in contact with the top surface of the conductive layer 112a2 in the opening 144, the side surfaces of the insulating layer 193 in the opening 144, the side surfaces of the insulating layer 110_2 (insulating layer 110a2, insulating layer 110b2, and insulating layer 110c2) in the opening 144, the side surfaces of the conductive layer 112b2 in the opening 144, and the top surface of the conductive layer 112b2. Then, a portion of the semiconductor film is removed by etching to form the semiconductor layer 108_2 ( FIGS. 30A to 30C ). The semiconductor layer 108_2 is provided to have a region overlapping with the opening 144. The semiconductor layer 108_2 is also provided so that an end portion thereof is in contact with the conductive layer 112b2.

[0371] For materials, formation methods, and the like that can be used for the semiconductor film to be the semiconductor layer 108_2, the above description of materials, formation methods, and the like that can be used for the semiconductor film to be the semiconductor layer 108_1 can be referred to.

[0372] Next, the insulating layer 106_2 is formed to cover the semiconductor layer 108_2, the conductive layer 112b2, and the insulating layer 110c2 ( FIGS. 31A to 31C ). The insulating layer 106_2 has a region in contact with the top surface and side surfaces of the semiconductor layer 108_2, the top surface and side surfaces of the conductive layer 112b2, and the top surface of the insulating layer 110c2. For materials that can be used for the insulating layer 106_2, a formation method thereof, and the like, the above description of materials that can be used for the insulating layer 106_1, a formation method thereof, and the like can be referred to.

[0373] Next, a conductive film to be the conductive layer 104_2 is formed over the insulating layer 106_2. For materials, formation methods, and the like that can be used for the conductive film, the above description of materials, formation methods, and the like that can be used for the conductive film 104_1f can be referred to.

[0374] Next, a part of the conductive film to be the conductive layer 104_2 is removed to form the conductive layer 104_2. The conductive layer 104_2 is formed to have a region overlapping with the opening 144. In addition, the top surface of the insulating layer 106_2 is exposed in the region where the conductive film to be the conductive layer 104_2 is removed. The conductive layer 104_2 may be formed by one or both of a wet etching method and a dry etching method.

[0375] As a result, the transistor 10_2 is formed.

[0376] Through the above steps, the semiconductor device 100 can be manufactured (FIGS. 1A to 2B).

[0377] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0378] A semiconductor device according to one embodiment of the present invention can be applied to, for example, a scan line driver circuit of a display device. In this embodiment, a configuration example of the circuit, an application location of the semiconductor device in the circuit, and the like will be described.

[0379] 32A to 32C show examples of the configuration of a driver circuit to which the semiconductor device of one embodiment of the present invention can be applied. The driver circuit can function as, for example, a scan line driver circuit of a display device. Fig. 32A is an example of a sequential circuit. Fig. 32B is an example of a driver circuit including the sequential circuit shown in Fig. 32A. Fig. 32C is an example of a timing chart of the driver circuit shown in Fig. 32B.

[0380] <Configuration Example of Driver Circuit> An example of a driver circuit that is formed by connecting multiple sequential circuits in stages and functions as a shift register will be described below. As described above, the semiconductor device of one embodiment of the present invention described in the above embodiment can be applied to the driver circuit.

[0381] 32A is a diagram illustrating input / output terminals of the sequential circuit 20. The sequential circuit 20 has input terminals to which the signals LIN, RIN, RES, CLK1, CLK2, and CLK3 are respectively input, and output terminals to which the signals SROUT, OUTA, and OUTB are respectively input.

[0382] 32B shows a configuration example of the driver circuit 30. The driver circuit 30 includes a plurality of sequential circuits 20. Sequential circuits 20_1 to 20_6 are shown in FIG. 32B. Hereinafter, the n-th sequential circuit from the side closest to the input of the driver circuit 30 will be referred to as a sequential circuit 20_n (n is an integer equal to or greater than 1).

[0383] In sequential circuit 20_n, any three of signals CLK1 to CLK4 are used as signals CLK1, CLK2, and CLK3. The combinations of signals CLK1 to CLK4 are the same for every four stages. That is, the same signals are input to sequential circuit 20_n and sequential circuit 20_n+4 as signals CLK1, CLK2, and CLK3. For example, in the case of sequential circuits 20_1 to 20_6 constituting the driver circuit 30 shown in FIG. 32B , the same signals (here, signals CLK1, CLK2, and CLK3) are input to sequential circuit 20_1 and sequential circuit 20_5 as signals CLK1, CLK2, and CLK3. The sequential circuit 20_2 and the sequential circuit 20_6 receive the same signals (here, the signals CLK2, CLK3, and CLK4) as the signals CLK1, CLK2, and CLK3.

[0384] Here, a clock signal can be used as the signal CLK. The clock signal preferably has a duty ratio (the ratio of the period during which the signal is at high level potential in one cycle of the signal) of 45% or more and 55% or less. More preferably, the clock signal has a duty ratio of 50%. Note that the duty ratio of the clock signal is not limited to the above and can be changed as appropriate depending on the driving method.

[0385] In this specification, a clock signal refers to a signal in which high and low potentials are repeated, and the interval between the rising edge of one potential and the rising edge of the next potential, or the interval between the falling edge of one potential and the falling edge of the next potential, is constant. In this specification, a pulse signal refers to a signal whose potential changes over time. Pulse signals also include signals whose potential changes periodically. For example, pulse signals include signals whose potential changes periodically, such as rectangular waves, triangular waves, sawtooth waves, and sine waves. Therefore, a clock signal can also be considered one form of a pulse signal.

[0386] The sequential circuit 20_1 receives the signal SP as the signal LIN. The sequential circuit 20_n, where n is 2 or greater, receives the signal LIN from the output terminal SROUTn-1 of the preceding sequential circuit 20_n-1. The sequential circuit 20_n receives the signal RIN from the output terminal SROUTn+2 of the succeeding sequential circuit 20_n+2.

[0387] Specifically, the sequential circuit 20_1 receives the signals CLK1, CLK2, CLK3, and SP, and the signal at the output terminal SROUT3 of the sequential circuit 20_3, and outputs output signals to the output terminals SROUT1, OUTA1, and OUTB1, respectively. The sequential circuit 20_2 receives the signals CLK2, CLK3, and CLK4, the signal at the output terminal SROUT1 of the sequential circuit 20_1, and the signal at the output terminal SROUT4 of the sequential circuit 20_4, and outputs output signals to the output terminals SROUT2, OUTA2, and OUTB2, respectively.

[0388] Fig. 32C shows a timing chart relating to the driving method of the driving circuit 30. Fig. 32C shows, from the top to the bottom, the changes in potential over time for the signal SP, signals CLK1 to CLK4, signal RES, output terminals OUTA1 to OUTA6, output terminals OUTB1 to OUTB6, and output terminals SROUT1 to SROUT6.

[0389] First, at time T0, signals SP, CLK3, and CLK4 are at high potential, and signals CLK1 and CLK2 are at low potential. At this time, low potentials are output to output terminals OUTA2 through OUTA6, high potentials are output to output terminals OUTB2 through OUTB6, and low potentials are output to output terminals SROUT1 through SROUT6. Furthermore, as signal SP is at high potential, a high potential is output to output terminal OUTA1 and a low potential is output to output terminal OUTB1.

[0390] Next, at time T1, the signal CLK1 changes from low potential to high potential, and the signal CLK3 changes from high potential to low potential, so that the sequential circuit 20_1 maintains the high potential output to the output terminal OUTA1 and the low potential output to the output terminal OUTB1, and a high potential is output to the output terminal SROUT1. Also, a high potential is output to the output terminal OUTA2, and a low potential is output to the output terminal OUTB2.

[0391] Thereafter, signals CLK1 to CLK4 sequentially output high potentials to the output terminals from output terminal OUTA2 onwards, low potentials to the output terminals from output terminal OUTB2 onwards, and high potentials to the output terminals from output terminal SROUT2 onwards.

[0392] The signals CLK1 to CLK4 are clock signals that are shifted by a quarter period, respectively. Therefore, as shown in Fig. 32C, signals that are shifted by a quarter period, such as the signal CLK1, are output from the output terminals OUTA1 to OUTA6, the output terminals OUTB1 to OUTB6, and the output terminals SROUT1 to SROUT6, respectively.

[0393] The configuration of the driver circuit is not limited to this, and the signals, output terminals, etc. can be changed as appropriate to match the configuration of the sequential circuit used.

[0394] The above is a description of an example of the configuration of the drive circuit.

[0395] 33A illustrates a configuration example of a sequential circuit 20A of one embodiment of the present invention. The sequential circuit 20A includes a circuit 11 and a circuit 12. The circuit 11 includes a wiring WA connected to an output terminal OUTA and a wiring WB connected to an output terminal OUTB. The circuit 11 and the circuit 12 are connected to each other through the wiring WA and the wiring WB.

[0396] The circuit 11 includes a transistor Tr11, a transistor Tr12, a transistor Tr13, a transistor Tr14, a transistor Tr15, a transistor Tr21, a transistor Tr22, and a capacitor C21.

[0397] The circuit 12 includes a transistor Tr16, a transistor Tr20, a transistor Tr23, and a capacitor C11.

[0398] The circuit 11 and the circuit 12 are supplied with a potential VDD from a high potential power supply and a potential VSS from a low potential power supply.

[0399] The signals CLK2, CLK3, LIN, RIN, and RES are input to the circuit 11. The circuit 11 has a function of outputting a first signal to the wiring WA and an inverted second signal of the first signal to the wiring WB in accordance with the potentials of the signals CLK2, CLK3, LIN, and RIN. That is, the circuit 11 can also be called a control circuit. A signal for controlling the reset operation of the sequential circuit 20A is supplied to the signal RES.

[0400] The circuit 12 receives the signal CLK1, the first signal, and the second signal. The circuit 12 has a function of outputting one of the signal CLK1 and the potential VSS to the output terminal SROUT based on the potentials of the signal CLK1, the first signal, and the second signal. The circuit 12 outputs the signal CLK1 when the first signal is at a high potential (the second signal is at a low potential), and outputs the potential VSS when the second signal is at a high potential (the first signal is at a low potential). The circuit 12 can be called an amplifier circuit, a buffer circuit, or the like.

[0401] The sequential circuit 20A functions as a flip-flop circuit and can be used as part of a shift register circuit. For example, the sequential circuit 20A can be used as part of a drive circuit of a display device. In particular, the sequential circuit 20A can be suitably used as part of a scan line drive circuit of a display device.

[0402] When the sequential circuit 20A is applied to a scanning line driver circuit, scanning lines (also called gate lines) connected to a plurality of pixels of a display device can be connected to at least one or both of the output terminal OUTA and the output terminal OUTB. By connecting scanning lines to both the output terminal OUTA and the output terminal OUTB, it becomes possible to drive pixels with two types of scanning line signals, thereby realizing more multifunctional pixels.

[0403] The configuration of the sequential circuit 20A will be described in detail below.

[0404] In the circuit 11, the gate of the transistor Tr11 is connected to a wiring that receives a signal LIN, one of its source or drain is connected to a wiring WA and one of the source or drain of the transistor Tr21, and the other of its source or drain is connected to a wiring that receives a potential VDD. The gate of the transistor Tr12 is connected to a wiring that receives a signal CLK3, one of its source or drain is connected to one of the source or drain of the transistor Tr13, and the other of its source or drain is connected to a wiring that receives a potential VDD. The gate of the transistor Tr13 is connected to a wiring that receives a signal CLK2, and the other of its source or drain is connected to a wiring WB, one electrode of the capacitor C21, and the gate of the transistor Tr21. The gate of the transistor Tr14 is connected to a wiring that receives a signal RIN, one of its source or drain is connected to the wiring WB, and the other of its source or drain is connected to a wiring that receives a potential VDD. The transistor Tr15 has a gate connected to a wiring to which a signal RES is applied, one of a source or a drain connected to a wiring WB, and the other of a source or a drain connected to a wiring to which a potential VDD is applied. The transistor Tr21 has the other of a source or a drain connected to a wiring to which a potential VSS is applied. The transistor Tr22 has a gate connected to a wiring to which a signal LIN is applied, one of a source or a drain connected to a wiring WB, and the other of a source or a drain connected to a wiring to which a potential VSS is applied. The capacitor C21 has the other electrode connected to a wiring to which a potential VSS is applied.

[0405] In the circuit 12, the gate of the transistor Tr16 is connected to a wiring to which a potential VDD is applied, one of the source and the drain is connected to a wiring WA, and the other of the source and the drain is connected to one electrode of the capacitor C11 and the gate of the transistor Tr20. The transistor Tr20 has one of the source and the drain connected to the other electrode of the capacitor C11 and the output terminal SROUT, and the other of the source and the drain connected to a wiring to which a signal CLK1 is applied. The transistor Tr23 has a gate connected to a wiring WB, one of the source and the drain connected to the output terminal SROUT, and the other of the source and the drain connected to a wiring to which a potential VSS is applied.

[0406] The transistors Tr11 and Tr22 are turned on or off in accordance with the potential of the signal LIN, and the transistor Tr14 is turned on or off in accordance with the potential of the signal RIN.

[0407] When the signal LIN is at a high potential and the signal RIN is at a low potential, the transistors Tr11 and Tr22 are turned on, and the transistor Tr14 is turned off. Therefore, the wiring to which the potential VDD is applied is connected to the wiring WA via the transistor Tr11. Furthermore, the wiring to which the potential VSS is applied is connected to the wiring WB via the transistor Tr22. At this time, since the wiring WA is at a high potential, a high potential is also applied to the gate of the transistor Tr20 via the transistor Tr16, so that the transistor Tr20 is turned on. Therefore, the signal CLK1 is output to the output terminal SROUT via the transistor Tr20.

[0408] On the other hand, when the signal LIN is at a low potential and the signal RIN is at a high potential, the transistor Tr14 is turned on, and the transistors Tr11 and Tr22 are turned off. Therefore, the wiring to which the potential VDD is applied is connected to the wiring WB via the transistor Tr14. Furthermore, when the wiring WB is at a high potential, the transistor Tr21 is turned on. Therefore, the wiring to which the potential VSS is applied is connected to the wiring WA via the transistor Tr21. At this time, when the wiring WB is at a high potential, a high potential is also applied to the gate of the transistor Tr23, so that the transistor Tr23 is turned on. Therefore, the potential VSS is output to the output terminal SROUT via the transistor Tr23.

[0409] As described above, when a high potential is applied to the wiring WA, the transistor Tr20 is turned on. At this time, if the high potential applied to the wiring WA is equal to the potential VDD, a potential lower than the potential VDD by the threshold voltage of the transistor Tr16 is applied to the gate of the transistor Tr20. Because the output terminal SROUT and the gate of the transistor Tr20 are connected via the capacitor C11, the potential of the gate of the transistor Tr20 (the potential of the other of the source or drain of the transistor Tr16) increases as the potential of the output terminal SROUT increases due to the bootstrap effect. Since the potential of the gate of the transistor Tr20 increases to, for example, a potential nearly twice the potential VDD, the potential VDD can be output to the output terminal SROUT without being affected by the threshold voltage of the transistor Tr20. This allows the sequential circuit 20A to have high output performance without increasing the number of power supply potentials.

[0410] Thereafter, when the potential of the other of the source and drain of transistor Tr16 exceeds the potential VDD, transistor Tr16 is turned off, so that the gate of transistor Tr20 and the wiring WA are electrically disconnected, and the gate of transistor Tr23 is brought into a floating state. Furthermore, because transistor Tr16 is turned off, the potential of the wiring WA does not rise above the output potential of circuit 12, so that a potential higher than the output potential is prevented from being applied to transistors, etc. in circuit 12 via the wiring WA. This improves the reliability of sequential circuit 20A.

[0411] Each transistor included in the sequential circuit 20A is preferably an OS transistor. The leakage current flowing between the source and drain of an OS transistor in an off state is significantly smaller than that of a Si transistor. By using OS transistors in the circuits 11 and 12, the power consumption of each circuit can be significantly reduced.

[0412] FIG. 35 is a circuit diagram showing some transistors in a sequential circuit 20A. FIG. 36 is a cross-sectional view corresponding to the circuit diagram shown in FIG. Focusing on the transistors constituting the circuit 11, transistors Tr11 and Tr21 have either their source or drain connected to wiring WA, and transistors Tr14, Tr12, and Tr15 have either their source or drain connected to wiring WB. The gate of transistor Tr21 is connected to either the source or drain of transistor Tr14. The gate of transistor Tr21 is connected to either the source or drain of transistor Tr12. The gate of transistor Tr21 is connected to either the source or drain of transistor Tr15.

[0413] For example, the semiconductor device 100, the semiconductor device 100C, etc. described in the first embodiment can be applied to each of the combination of the transistors Tr21 and Tr14, the combination of the transistors Tr21 and Tr12, and the combination of the transistors Tr21 and Tr15. In this case, the transistor Tr21 corresponds to the transistor 10_1 included in the semiconductor device 100, etc., and the transistor Tr14, the transistor Tr12, or the transistor Tr15 corresponds to the transistor 10_2 included in the semiconductor device 100, etc.

[0414] That is, some transistors in the circuit 11 can be stacked. For example, as shown in FIGS. 35 and 36 , transistors Tr11, Tr21, and the like, each having a source or drain connected to a wiring WA, are formed in a first layer, and transistors Tr14, Tr12, Tr15, and the like, each having a source or drain connected to a wiring WB, are formed in a second layer. This can significantly reduce the area occupied by the circuit 11 compared to when these transistors are formed on the same plane. Furthermore, because the transistors of one embodiment of the present invention are vertical transistors, the area occupied by the circuit 11 can be further reduced compared to when planar transistors are used.

[0415] <Configuration Example 2 of Sequential Circuit> Fig. 33B shows a configuration example of a sequential circuit 20B that is different from the sequential circuit 20A shown in Fig. 33A. The sequential circuit 20B differs from the sequential circuit 20A in the configuration of transistors.

[0416] Specifically, in the sequential circuit 20B, all the transistors included in the circuit 11 and the circuit 12 are transistors having a back gate.

[0417] Of these, the back gates of the transistors Tr21 and Tr23 are connected to a wiring to which the potential VSS is applied, that is, the back gates of the transistors Tr21 and Tr23 are connected to the sources.

[0418] When the sequential circuit 20B is used in a scanning line driving circuit, the period during which the wiring WB is at a high potential is significantly longer than the period during which it is at a low potential. Therefore, the transistors Tr21 and Tr23, whose gates are connected to the wiring WB, are in an on state for a significantly longer period than the off state. Therefore, the threshold voltages of the transistors Tr21 and Tr23 are more likely to fluctuate than the other transistors. Specifically, the threshold voltages of the transistors are more likely to shift in the positive direction.

[0419] Therefore, the transistors Tr21 and Tr23 have a pair of gates that overlap with each other with a semiconductor layer sandwiched therebetween, and one of the gates is connected to a wiring to which a low potential is applied (a wiring to which the potential VSS is applied). This configuration can suitably prevent the threshold voltages of the transistors Tr21 and Tr23 from shifting in the positive direction. This can improve the reliability of the sequential circuit 20B, or a semiconductor device, a display device, an electronic device, or the like that uses the sequential circuit 20B.

[0420] Furthermore, by configuring transistors Tr21 and Tr23 so that one gate and one source are connected, it is possible to preferably prevent the threshold voltage from becoming a negative value. That is, it is easy to make transistors Tr21 and Tr23 have normally-off characteristics. Furthermore, by configuring transistors Tr21 and Tr23 so that one gate and one source are connected, it is also possible to achieve an effect of improving saturation. This simplifies the design of circuits 11 and 12 and enables the realization of circuits that can operate stably.

[0421] On the other hand, transistors other than the transistor Tr21 and the transistor Tr23 are configured with a pair of gates connected to each other. By connecting a pair of gates that overlap with each other with a semiconductor layer sandwiched therebetween, it is possible to increase the on-state current of the transistors. This makes it possible to improve the driving capability of the sequential circuit 20B.

[0422] Note that in the sequential circuit 20B, all the transistors included in the circuit 11 and the circuit 12 have a back gate; however, this is not limited thereto, and any one or more of the transistors included in the circuit 11 and the circuit 12 may have a back gate.

[0423] For example, when the transistor Tr21 included in the circuit 11 has a back gate and the transistors Tr14, Tr12, and Tr15 do not have back gates, the semiconductor device 100A, the semiconductor device 100B, or the like described in Embodiment 1 can be applied to the combination of the transistors Tr21 and Tr14, the combination of the transistors Tr21 and Tr12, or the combination of the transistors Tr21 and Tr15. In this case, the transistor Tr21 corresponds to the transistor 10_1 included in the semiconductor device 100A, or the like, and the transistor Tr14, the transistor Tr12, or the transistor Tr15 corresponds to the transistor 10_2 included in the semiconductor device 100A, or the like.

[0424] Furthermore, for example, when the transistors Tr21, Tr14, Tr12, and Tr15 included in the circuit 11 have back gates, the semiconductor device 100D described in Embodiment 1 can be applied to the combination of the transistors Tr21 and Tr14, the combination of the transistors Tr21 and Tr12, or the combination of the transistors Tr21 and Tr15. In this case, the transistor Tr21 corresponds to the transistor 10_1 included in the semiconductor device 100D, and the transistor Tr14, the transistor Tr12, or the transistor Tr15 corresponds to the transistor 10_2 included in the semiconductor device 100D.

[0425] For the sequential circuit 20B, other than the above, the description of the sequential circuit 20A can be referred to.

[0426] 34A shows a configuration example of a sequential circuit 20C that is different from the sequential circuit 20A shown in Fig. 33A. The sequential circuit 20C differs from the sequential circuit 20A in the configuration of transistors included in the circuit 12.

[0427] Specifically, in the sequential circuit 20C, the transistor corresponding to the transistor Tr20 in the sequential circuit 20A is configured with two transistors, a transistor Tr20a and a transistor Tr20b.

[0428] One of the source or drain of transistor Tr20a is connected to one of the source or drain of transistor Tr20b. The other of the source or drain of transistor Tr20a is connected to the other of the source or drain of transistor Tr20b. The gate of transistor Tr20a is connected to the gate of transistor Tr20b. In other words, transistor Tr20a and transistor Tr20b can be said to be connected in parallel with each other.

[0429] In this way, by configuring two transistors in parallel, it is possible to obtain approximately twice the on-state current compared to a configuration having only one transistor, assuming that each transistor has the same current generating capacity. Note that, although the sequential circuit 20C shows an example of a configuration in which two transistors, transistor Tr20a and transistor Tr20b, are connected in parallel, this is not limitative and a configuration in which three or more transistors are connected in parallel is also possible. Increasing the number of transistors connected in parallel is preferable because it allows for a larger overall output current.

[0430] As described above, the circuit 12 functions as an amplifier circuit and plays a role in outputting the signal generated by the circuit 11 to the output terminal SROUT. It is preferable that the circuit 12 amplifies the signal generated by the circuit 11 as much as possible and supplies the amplified signal to the output terminal SROUT. Therefore, as in the circuit 12 included in the sequential circuit 20C, it is preferable to configure the transistor located immediately before the output terminal SROUT as a plurality of transistors connected in parallel, because this allows a larger current to be supplied to the output terminal SROUT than when only one transistor is included.

[0431] Note that when multiple transistors are connected in parallel, as in the circuit 12 included in the sequential circuit 20C, the output current can be increased, but the increased number of transistors may increase the area occupied by the entire semiconductor device. However, in one embodiment of the present invention, transistors can be stacked, so the output current can be increased without increasing the area occupied by the semiconductor device. For example, the semiconductor device 200 described in Embodiment 1 can be applied to the combination of the transistor Tr20a and the transistor Tr20b included in the sequential circuit 20C. Also, FIGS. 35 and 36 show an example in which two transistors Tr20 connected in parallel are stacked in the circuit 12. 35 and 36 show an example in which a first transistor Tr20 (either the transistor Tr20a or the transistor Tr20b of the sequential circuit 20C) is formed in the first layer in which the aforementioned transistor Tr21 is formed, and a second transistor Tr20 (the other of the transistor Tr20a or the transistor Tr20b of the sequential circuit 20C) is formed in the second layer in which the aforementioned transistors Tr14, Tr12, and Tr15 are formed.

[0432] In the sequential circuit 20C, only the transistors corresponding to the transistor Tr20 in the sequential circuit 20A are connected in parallel, but this is not limited thereto, and transistors other than the transistor Tr20 may also be connected in parallel.

[0433] For the sequential circuit 20C, the description of the sequential circuit 20A can be referred to for other details.

[0434] <Configuration Example 4 of Sequential Circuit> Fig. 34B shows a configuration example of a sequential circuit 20D that is different from the sequential circuit 20A shown in Fig. 33A. The sequential circuit 20D differs from the sequential circuit 20A in the configuration of transistors.

[0435] Specifically, in sequential circuit 20D, the transistor corresponding to transistor Tr14 in sequential circuit 20A is composed of two transistors, transistor Tr14a and transistor Tr14b. Furthermore, the transistor corresponding to transistor Tr15 in sequential circuit 20A is composed of two transistors, transistor Tr15a and transistor Tr15b. Furthermore, the transistor corresponding to transistor Tr21 in sequential circuit 20A is composed of two transistors, transistor Tr21a and transistor Tr21b. Furthermore, the transistor corresponding to transistor Tr22 in sequential circuit 20A is composed of two transistors, transistor Tr22a and transistor Tr22b. Furthermore, the transistor corresponding to transistor Tr23 in sequential circuit 20A is composed of two transistors, transistor Tr23a and transistor Tr23b.

[0436] The source or drain of transistor Tr14a is connected to the source or drain of transistor Tr14b. The gate of transistor Tr14a is connected to the gate of transistor Tr14b. That is, transistor Tr14a and transistor Tr14b are connected in series. The same applies to transistors Tr15a and Tr15b, transistors Tr21a and Tr21b, transistors Tr22a and Tr22b, and transistors Tr23a and Tr23b.

[0437] In this way, by using a configuration in which two transistors are connected in series, if each transistor has the same current generating capability, the off-state current can be reduced to about half compared to a configuration having only one transistor, and the source-drain breakdown voltage can be increased.

[0438] Note that, when multiple transistors are connected in series as in the sequential circuit 20D, the off-state current can be reduced and the source-drain breakdown voltage can be improved, but the increase in the number of transistors may increase the area occupied by the entire semiconductor device. However, in one embodiment of the present invention, the transistors can be stacked, so that the off-state current can be reduced and the source-drain breakdown voltage can be improved without increasing the area occupied by the semiconductor device. For example, the semiconductor device 300 described in Embodiment 1 can be applied to the combination of two series-connected transistors included in the sequential circuit 20D.

[0439] In the sequential circuit 20D, two transistors are connected in series for the transistors corresponding to transistors Tr14, Tr15, Tr21, Tr22, and Tr23 in the sequential circuit 20A. However, this is not limited to this. Two transistors may also be connected in series for the transistors corresponding to transistors Tr11, Tr12, Tr13, Tr16, and Tr20 in the sequential circuit 20A. Furthermore, the number of transistors connected in series is not limited to two, and three or more transistors may be connected in series. Increasing the number of transistors connected in series is preferable because it reduces the overall off-state current. It is also preferable because it increases the overall source-drain breakdown voltage.

[0440] For the sequential circuit 20D, other than the above, the description of the sequential circuit 20A can be referred to.

[0441] As described above, the semiconductor device of one embodiment of the present invention has a structure in which two vertical transistors having various connection relationships (parallel connection, series connection, etc.) are stacked. Therefore, for example, by using the semiconductor device of one embodiment of the present invention in a scan line driver circuit of a display device, the area occupied by the scan line driver circuit can be reduced compared to when the transistors are provided on the same plane, and the frame of the display device can be narrowed.

[0442] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0443] Embodiment 3 In this embodiment, electronic devices of one embodiment of the present invention will be described with reference to FIGS. 37A to 39G.

[0444] The electronic devices of this embodiment include the display device of one embodiment of the present invention in their display portions. The display device of one embodiment of the present invention can easily achieve high definition and high resolution. Therefore, the display device of one embodiment of the present invention can be used in the display portions of various electronic devices.

[0445] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0446] In particular, the display device of one embodiment of the present invention can be suitably used in electronic devices having a relatively small display area because it can increase the resolution. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), and head-mounted wearable devices such as VR devices such as head-mounted displays, AR glasses-type devices, and MR devices.

[0447] The display device of one embodiment of the present invention preferably has an extremely high resolution, such as HD (1280 × 720 pixels), FHD (1920 × 1080 pixels), WQHD (2560 × 1440 pixels), WQXGA (2560 × 1600 pixels), 4K (3840 × 2160 pixels), or 8K (7680 × 4320 pixels). A resolution of 4K, 8K, or higher is particularly preferable. Furthermore, the pixel density (resolution) of the display device of one embodiment of the present invention is preferably 100 ppi or higher, more preferably 300 ppi or higher, more preferably 500 ppi or higher, more preferably 1000 ppi or higher, more preferably 2000 ppi or higher, more preferably 3000 ppi or higher, more preferably 5000 ppi or higher, and even more preferably 7000 ppi or higher. By using a display device having either or both of high resolution and high definition, it is possible to further enhance the sense of realism and depth. Furthermore, the screen ratio (aspect ratio) of the display device of one embodiment of the present invention is not particularly limited. For example, the display device can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

[0448] The electronic device of this embodiment may have a sensor (including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0449] The electronic device of the present embodiment can have various functions, such as a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, time, etc., a function of executing various software (programs), a wireless communication function, a function of reading out programs or data recorded on a recording medium, etc.

[0450] 37A to 37D , examples of wearable devices that can be worn on the head are described. These wearable devices have at least one of the functions of displaying AR content, VR content, SR content, and MR content. By having an electronic device with the function of displaying at least one of AR, VR, SR, and MR content, it is possible to enhance the sense of immersion felt by the user.

[0451] The electronic device 700A shown in Figure 37A and the electronic device 700B shown in Figure 37B each have a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.

[0452] The display device of one embodiment of the present invention can be applied to the display panel 751. Therefore, the electronic device can provide an extremely high-definition display.

[0453] The electronic device 700A and the electronic device 700B can each project an image displayed on the display panel 751 onto a display area 756 of the optical member 753. Because the optical member 753 is translucent, the user can see the image displayed in the display area superimposed on a transmitted image visually recognized through the optical member 753. Therefore, the electronic device 700A and the electronic device 700B are each electronic devices capable of AR display.

[0454] Each of electronic device 700A and electronic device 700B may be provided with a camera capable of capturing an image in front of it as an imaging unit. Furthermore, each of electronic device 700A and electronic device 700B may be provided with an acceleration sensor such as a gyro sensor, thereby detecting the orientation of the user's head and displaying an image corresponding to that orientation in display area 756.

[0455] The communication unit has a wireless communication device, and can supply a video signal, etc. Instead of or in addition to the wireless communication device, a connector to which a cable through which a video signal and a power supply potential are supplied may be provided.

[0456] The electronic device 700A and the electronic device 700B are each provided with a battery (not shown), which can be charged wirelessly and / or wired.

[0457] The housing 721 may be provided with a touch sensor module. The touch sensor module has a function of detecting a touch on the outer surface of the housing 721. The touch sensor module can detect a tap operation, a slide operation, or the like by the user and perform various processes. For example, a tap operation can perform a process such as pausing or resuming a video, and a slide operation can perform a process such as fast-forwarding or fast-rewinding. Furthermore, providing a touch sensor module on each of the two housings 721 can broaden the range of operations.

[0458] Various touch sensors can be used as the touch sensor module. For example, various types of touch sensors can be used, such as a capacitance type, a resistive film type, an infrared type, an electromagnetic induction type, a surface acoustic wave type, and an optical type. In particular, it is preferable to use a capacitance type or an optical type sensor in the touch sensor module.

[0459] When an optical touch sensor is used, a photoelectric conversion element can be used as the light receiving element. The active layer of the photoelectric conversion element can be made of either or both of an inorganic semiconductor and an organic semiconductor.

[0460] The electronic device 800A shown in Figure 37C and the electronic device 800B shown in Figure 37D each have a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.

[0461] The display device of one embodiment of the present invention can be applied to the display portion 820. Therefore, an electronic device capable of displaying images with extremely high definition can be provided. This allows a user to feel a high sense of immersion.

[0462] The display unit 820 is provided inside the housing 821 at a position where it can be viewed through the lens 832. Also, by displaying different images on the pair of display units 820, it is possible to perform three-dimensional display using parallax.

[0463] The electronic device 800A and the electronic device 800B can be said to be electronic devices for VR. A user wearing the electronic device 800A or the electronic device 800B can view an image displayed on the display unit 820 through the lens 832.

[0464] It is preferable that the electronic device 800A and the electronic device 800B each have a mechanism for adjusting the left-right positions of the lens 832 and the display unit 820 so that they are optimally positioned according to the position of the user's eyes. It is also preferable that the electronic device 800A and the electronic device 800B each have a mechanism for adjusting the focus by changing the distance between the lens 832 and the display unit 820.

[0465] The mounting unit 823 allows the user to mount the electronic device 800A or the electronic device 800B on the head. Note that in Fig. 37C and other figures, the mounting unit 823 is shaped like the temples of glasses, but is not limited to this. The mounting unit 823 may be shaped like a helmet or a band, for example, as long as it can be worn by the user.

[0466] The imaging unit 825 has a function of acquiring external information. Data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used for the imaging unit 825. Furthermore, multiple cameras may be provided to support multiple angles of view, such as telephoto and wide-angle.

[0467] Although an example including the imaging unit 825 is shown here, a distance measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object may be provided. That is, the imaging unit 825 is one aspect of the detection unit. As the detection unit, for example, an image sensor or a range image sensor such as a LIDAR (Light Detection and Ranging) can be used. By using an image obtained by the camera and an image obtained by the range image sensor, more information can be obtained, enabling more accurate gesture operations.

[0468] The electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone. For example, a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, the housing 821, and the wearing unit 823. This allows a user to enjoy video and audio simply by wearing the electronic device 800A, without the need for separate audio equipment such as headphones, earphones, or speakers.

[0469] The electronic device 800A and the electronic device 800B may each have an input terminal to which a cable can be connected for supplying a video signal from a video output device or the like, or power for charging a battery provided in the electronic device.

[0470] The electronic device of one embodiment of the present invention may have a function of wirelessly communicating with an earphone 750. The earphone 750 includes a communication unit (not shown) and has a wireless communication function. The earphone 750 can receive information (e.g., audio data) from the electronic device through the wireless communication function. For example, an electronic device 700A shown in FIG. 37A has a function of transmitting information to the earphone 750 through the wireless communication function. Furthermore, for example, an electronic device 800A shown in FIG. 37C has a function of transmitting information to the earphone 750 through the wireless communication function.

[0471] The electronic device may have an earphone unit. Electronic device 700B shown in Fig. 37B has earphone unit 727. For example, earphone unit 727 and the control unit may be configured to be connected to each other by wire. Part of the wiring connecting earphone unit 727 and the control unit may be disposed inside housing 721 or attachment unit 723.

[0472] Similarly, electronic device 800B shown in Fig. 37D has earphone unit 827. For example, earphone unit 827 and control unit 824 can be configured to be connected to each other by wire. Part of the wiring connecting earphone unit 827 and control unit 824 may be disposed inside housing 821 or wearing unit 823. Furthermore, earphone unit 827 and wearing unit 823 may have magnets. This allows earphone unit 827 to be fixed to wearing unit 823 by magnetic force, which is preferable as it makes storage easier.

[0473] The electronic device may have an audio output terminal to which earphones or headphones can be connected. The electronic device may also have one or both of an audio input terminal and an audio input mechanism. For example, a sound collection device such as a microphone can be used as the audio input mechanism. By having the audio input mechanism, the electronic device may be endowed with the functionality of a so-called headset.

[0474] As described above, as electronic devices according to one embodiment of the present invention, both glasses-type devices (such as the electronic device 700A and the electronic device 700B) and goggle-type devices (such as the electronic device 800A and the electronic device 800B) are suitable.

[0475] An electronic device according to one embodiment of the present invention can transmit information to an earphone via a wired or wireless connection.

[0476] The electronic device 6500 shown in FIG. 38A is a portable information terminal that can be used as a smartphone.

[0477] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and the like. The display portion 6502 has a touch panel function.

[0478] The display device of one embodiment of the present invention can be applied to the display portion 6502 .

[0479] FIG. 38B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.

[0480] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0481] A display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by adhesive layers (not shown).

[0482] In a region outside the display portion 6502, a part of the display panel 6511 is folded back, and an FPC 6515 is connected to the folded back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on a printed circuit board 6517.

[0483] The flexible display of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. Furthermore, since the display panel 6511 is extremely thin, the thickness of the electronic device can be reduced and a large-capacity battery 6518 can be mounted thereon. Furthermore, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the display portion 6502, an electronic device with a narrow frame can be realized.

[0484] 38C shows an example of a television set. A television set 7100 has a display portion 7000 built into a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0485] The display device of one embodiment of the present invention can be applied to the display portion 7000 .

[0486] 38C can be operated using operation switches provided on the housing 7101 and a separate remote control 7111. Alternatively, the display portion 7000 may be provided with a touch sensor, and the television set 7100 may be operated by touching the display portion 7000 with a finger or the like. The remote control 7111 may have a display portion that displays information output from the remote control 7111. Using operation keys or a touch panel provided on the remote control 7111, the channel and volume can be controlled, and an image displayed on the display portion 7000 can be controlled.

[0487] The television device 7100 is configured to include a receiver, a modem, and the like. Ordinary television broadcasts can be received using the receiver. Furthermore, by connecting to a wired or wireless communication network via the modem, it is also possible to perform one-way (from a sender to a receiver) or two-way (between a sender and a receiver, or between receivers, etc.) information communication.

[0488] 38D shows an example of a laptop personal computer 7200. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, and an external connection port 7214. The housing 7211 includes a display portion 7000.

[0489] The display device of one embodiment of the present invention can be applied to the display portion 7000 .

[0490] 38E and 38F show an example of digital signage.

[0491] 38E includes a housing 7301, a display portion 7000, a speaker 7303, and the like. The digital signage 7300 may further include an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0492] 38F shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7000 provided along the curved surface of the pillar 7401.

[0493] 38E and 38F, the display device of one embodiment of the present invention can be applied to the display portion 7000.

[0494] The larger the display unit 7000, the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it attracts people's attention, which can increase the advertising effectiveness of, for example, advertisements.

[0495] Applying a touch panel to the display unit 7000 is preferable because it not only displays images or videos on the display unit 7000 but also allows the user to intuitively operate it. Furthermore, when used to provide information such as route information or traffic information, the intuitive operation can improve usability.

[0496] 38E and 38F , the digital signage 7300 or the digital signage 7400 is preferably capable of wirelessly linking with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. Furthermore, by operating the information terminal 7311 or the information terminal 7411, the display on the display unit 7000 can be switched.

[0497] The digital signage 7300 or the digital signage 7400 can also be made to run a game using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller), thereby allowing an unspecified number of users to simultaneously participate in and enjoy the game.

[0498] The electronic device shown in Figures 39A to 39G has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays), a microphone 9008, etc.

[0499] 39A to 39G, the display device of one embodiment of the present invention can be applied to the display portion 9001.

[0500] The electronic devices shown in Figures 39A to 39G have various functions. For example, they may have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, or time, a function to control processing using various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc. Note that the functions of the electronic devices are not limited to these, and they may have various other functions. The electronic devices may have multiple display units. Furthermore, the electronic devices may have a function to include a camera or the like to capture still images or videos and store them on a recording medium (external or built-in to the camera), a function to display the captured images on a display unit, etc.

[0501] Details of the electronic device shown in Figures 39A to 39G will be described below.

[0502] FIG. 39A is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 can be used as, for example, a smartphone. Note that the mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. The mobile information terminal 9101 can display text and image information on multiple surfaces. FIG. 39A shows an example in which three icons 9050 are displayed. Information 9051, indicated by a dashed rectangle, can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming emails, SNS messages, phone calls, etc., the title of the email or SNS message, the sender's name, the date and time, the remaining battery level, and radio wave intensity. Alternatively, an icon 9050 or the like may be displayed in the position where the information 9051 is displayed.

[0503] 39B is a perspective view showing a mobile information terminal 9102. The mobile information terminal 9102 has a function of displaying information on three or more surfaces of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is stored in a breast pocket of clothes. The user can check the display without taking the mobile information terminal 9102 out of the pocket and determine, for example, whether to answer a call.

[0504] 39C is a perspective view showing a tablet terminal 9103. The tablet terminal 9103 is capable of executing various applications such as mobile phone calls, e-mail, text browsing and creation, music playback, internet communication, and computer games, for example. The tablet terminal 9103 has a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front side of a housing 9000, operation keys 9005 as operation buttons on the side of the housing 9000, and a connection terminal 9006 on the bottom.

[0505] FIG. 39D is a perspective view showing a wristwatch-type mobile information terminal 9200. The mobile information terminal 9200 can be used as, for example, a smart watch (registered trademark). The display surface of the display unit 9001 is curved, and display can be performed along the curved display surface. The mobile information terminal 9200 can also perform hands-free calling by communicating with, for example, a wirelessly capable headset. The mobile information terminal 9200 can also perform data transmission and charging with another information terminal through a connection terminal 9006. Note that charging may be performed by wireless power supply.

[0506] 39E to 39G are perspective views showing a foldable mobile information terminal 9201. Also, FIG. 39E is a perspective view of the mobile information terminal 9201 in an unfolded state, FIG. 39G is a perspective view of the mobile information terminal 9201 in a folded state, and FIG. 39F is a perspective view of a state in the process of changing from one of FIGS. 39E and 39G to the other. The mobile information terminal 9201 is highly portable when folded, and has a seamless, wide display area when unfolded, providing excellent visibility of the display. The display portion 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055. For example, the display portion 9001 can be bent with a curvature radius of 0.1 mm or more and 150 mm or less.

[0507] This embodiment mode can be combined with other embodiment modes as appropriate.

[0508] 10_1: transistor, 10_2: transistor, 11: circuit, 12: circuit, 20: sequential circuit, 20_1: sequential circuit, 20_2: sequential circuit, 20_3: sequential circuit, 20_4: sequential circuit, 20_5: sequential circuit, 20_6: sequential circuit, 20A: sequential circuit, 20B: sequential circuit, 20C: sequential circuit, 20D: sequential circuit, 30: driver circuit, 100: semiconductor device, 100A: semiconductor device, 100B: semiconductor device, 100C: semiconductor device, 100D: semiconductor device, 102: substrate, 104_1: conductive layer, 104_1f: conductive film, 104_2: conductive layer, 106_1: insulation layer, 106_2: insulating layer, 108_1: semiconductor layer, 108_2: semiconductor layer, 110_1: insulating layer, 110_2: insulating layer, 110a1: insulating layer, 110a1f: insulating film, 110a2: insulating layer, 110a2f: insulating film, 110b1: insulating layer, 110b1f: insulating film, 110b2: insulating layer, 110b2f: insulating film, 110c1: insulating layer, 110c1f: insulating film, 110c2: insulating layer, 110c2f: insulating film, 110d1: insulating layer, 110d2: insulating layer, 110e1: insulating layer, 110e2: insulating layer, 110f1: insulating layer, 110f2: insulating layer, 110g1: insulating layer , 110g2: insulating layer, 110h1: insulating layer, 110h2: insulating layer, 110i1: insulating layer, 110i2: insulating layer, 110s1: insulating layer, 110s2: insulating layer, 112a1: conductive layer, 112a2: conductive layer, 112a2f: conductive film, 112b1: conductive layer, 112b1e: conductive layer, 112b1f: conductive film, 112b2: conductive layer, 112b2e: conductive layer, 112b2f: conductive film, 114_1: conductive layer, 114_2: conductive layer, 116: insulating layer, 136: mask, 138: mask, 139: light, 143: opening, 144: opening, 192e: insulating layer, 192f: insulating film, 1 92: insulating layer, 193f: insulating film, 193: insulating layer, 194f: insulating film, 194: insulating layer, 200: semiconductor device, 300: semiconductor device, 700A: electronic device, 700B: electronic device, 721: housing, 723: wearing portion, 727: earphone portion, 750: earphone, 751: display panel, 753: optical member, 756: display area, 757: frame, 758: nose pad, 800A: electronic device, 800B: electronic device, 820: display portion, 821: housing, 822: communication portion, 823: wearing portion, 824: control portion, 825: imaging portion, 827: earphone portion, 832: lens,6500: electronic device, 6501: housing, 6502: display unit, 6503: power button, 6504: button, 6505: speaker, 6506: microphone, 6507: camera, 6508: light source, 6510: protective member, 6511: display panel, 6512: optical member, 6513: touch sensor panel, 6515: FPC, 6516: IC, 6517: printed circuit board, 6518: battery, 7000: display unit, 7100: television device, 7101: housing, 7103: stand, 7111: remote control, 7200: notebook personal computer, 7211: housing, 7212: keyboard, 7213: pointing device, 7214: external connection port, 7300: digital signage, 7301: housing, 7303: speaker, 7311: information terminal, 7400: digital signage, 7401: pillar, 7411: information terminal, 9000: housing, 9001: display unit, 9002: camera, 9003: speaker, 9005: operation keys, 9006: connection terminal, 9007: sensor, 9008: microphone, 9050: icon, 9051: information, 9052: information, 9053: information, 9054: information, 9055: hinge, 9101: mobile information terminal, 9102: mobile information terminal, 9103: tablet terminal, 9200: mobile information terminal, 9201: mobile information terminal,

Claims

It functions as part of a sequential circuit, the sequential circuit includes a first transistor, a second transistor, a first insulating layer, a second insulating layer, and a third insulating layer; the first transistor has a first semiconductor layer, a first conductive layer, a second conductive layer, a gate insulating layer, and a gate electrode; the second transistor has a second semiconductor layer, a third conductive layer, and a fourth conductive layer; the first insulating layer is provided on the first conductive layer; the second conductive layer is provided on the first insulating layer; the first insulating layer and the second conductive layer each have a first opening reaching the first conductive layer; In the first opening, the first semiconductor layer is provided in contact with an upper surface of the first conductive layer, a side surface of the first insulating layer, and a side surface of the second conductive layer; the gate insulating layer is provided in contact with an upper surface of the first semiconductor layer, the gate electrode is provided in contact with an upper surface of the gate insulating layer so as to have a region overlapping with the first opening; the second insulating layer is provided on the gate electrode so as to fill the first opening; the third conductive layer is provided on and in contact with the second insulating layer and the gate electrode; the third insulating layer is provided on the third conductive layer; the fourth conductive layer is provided on the third insulating layer; the third insulating layer and the fourth conductive layer each have a second opening reaching the third conductive layer; In the second opening, the second semiconductor layer is provided in contact with an upper surface of the third conductive layer, a side surface of the third insulating layer, and a side surface of the fourth conductive layer; the second insulating layer comprises an organic insulating material; Semiconductor device. 　 In claim 1, a fourth insulating layer is provided on the gate insulating layer in a region not overlapping with the first opening; the third insulating layer is provided on the fourth insulating layer; the fourth insulating layer has the same material as the second insulating layer; Semiconductor device. 　 In claim 1 or 2, The second insulating layer contains one or more selected from an acrylic resin, a polyimide resin, an epoxy resin, a polyamide resin, a polyimideamide resin, a siloxane resin, a benzocyclobutene-based resin, a phenolic resin, and precursors of these resins. Semiconductor device. 　 In claim 1 or 2, the first transistor has a back gate electrode; the back gate electrode is provided between the first conductive layer and the second conductive layer so as to have an area overlapping with each of the first conductive layer and the second conductive layer; In the first opening, one surface of the first semiconductor layer faces the gate electrode, and the other surface of the first semiconductor layer faces the back gate electrode. Semiconductor device. 　 In claim 1, At least one of the first semiconductor layer and the second semiconductor layer comprises a metal oxide; The metal oxide has two or three elements selected from indium, an element M, and zinc, The element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium; At least one of the first insulating layer and the third insulating layer comprises silicon oxide or silicon oxynitride. Semiconductor device. 　 In claim 5, the first insulating layer includes a fifth insulating layer, a sixth insulating layer on the fifth insulating layer, and a seventh insulating layer on the sixth insulating layer; the third insulating layer includes an eighth insulating layer, a ninth insulating layer on the eighth insulating layer, and a tenth insulating layer on the ninth insulating layer; the fifth insulating layer, the seventh insulating layer, the eighth insulating layer, and the tenth insulating layer each include silicon nitride, silicon oxynitride, hafnium oxide, or aluminum oxide; The sixth insulating layer and the ninth insulating layer each include silicon oxide or silicon oxynitride. Semiconductor device. 　 a first transistor, a second transistor, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer; the first transistor has a first semiconductor layer, a first conductive layer, a second conductive layer, a first gate insulating layer, and a first gate electrode; the second transistor has a second semiconductor layer, a third conductive layer, a fourth conductive layer, a second gate insulating layer, and a second gate electrode; the first insulating layer is provided on the first conductive layer; the second conductive layer is provided on the first insulating layer; the first insulating layer and the second conductive layer each have a first opening reaching the first conductive layer; In the first opening, the first semiconductor layer is provided in contact with an upper surface of the first conductive layer, a side surface of the first insulating layer, and a side surface of the second conductive layer; the first gate insulating layer is provided in contact with an upper surface of the first semiconductor layer; the first gate electrode is provided in contact with an upper surface of the first gate insulating layer so as to have a region overlapping with the first opening; the second insulating layer is provided on the first gate electrode so as to fill the first opening; the third insulating layer is provided in contact with an upper surface of the second insulating layer, a side surface of the first gate electrode, and an upper surface of the first gate insulating layer; the third conductive layer is provided in contact with an upper surface of the third insulating layer, the fourth insulating layer is provided on the third conductive layer; the fourth conductive layer is provided on the fourth insulating layer; the fourth insulating layer and the fourth conductive layer each have a second opening reaching the third conductive layer; In the second opening, the second semiconductor layer is provided in contact with an upper surface of the third conductive layer, a side surface of the fourth insulating layer, and a side surface of the fourth conductive layer; the second gate insulating layer is provided in contact with an upper surface of the second semiconductor layer; the second gate electrode is provided in contact with an upper surface of the second gate insulating layer so as to have a region overlapping with the second opening; the second insulating layer comprises an organic insulating material; Semiconductor device. 　 In claim 7, the first conductive layer and the third conductive layer are connected; the second conductive layer and the fourth conductive layer are connected; The first gate electrode and the second gate electrode are connected. Semiconductor device. 　 In claim 7, the second conductive layer and the third conductive layer are connected; The first gate electrode and the second gate electrode are connected. Semiconductor device. 　 In claim 7, a fifth insulating layer is provided on the first gate insulating layer in a region not overlapping with the first opening; the fourth insulating layer is provided on the fifth insulating layer; The fifth insulating layer has the same material as the second insulating layer. Semiconductor device. 　 In claim 7 or claim 10, The second insulating layer contains one or more selected from an acrylic resin, a polyimide resin, an epoxy resin, a polyamide resin, a polyimideamide resin, a siloxane resin, a benzocyclobutene-based resin, a phenolic resin, and precursors of these resins. Semiconductor device. 　 In claim 7, At least one of the first semiconductor layer and the second semiconductor layer comprises a metal oxide; The metal oxide has two or three elements selected from indium, an element M, and zinc, The element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium; At least one of the first insulating layer and the fourth insulating layer comprises silicon oxide or silicon oxynitride. Semiconductor device. 　 In claim 12, the first insulating layer includes a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer; the fourth insulating layer includes a ninth insulating layer, a tenth insulating layer on the ninth insulating layer, and an eleventh insulating layer on the tenth insulating layer; the sixth insulating layer, the eighth insulating layer, the ninth insulating layer, and the eleventh insulating layer each include silicon nitride, silicon oxynitride, hafnium oxide, or aluminum oxide; The seventh insulating layer and the tenth insulating layer each include silicon oxide or silicon oxynitride. Semiconductor device.

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