Uninterruptible power supply system and uninterruptible power supply device

Abstract

An uninterruptible power supply device (U) is provided with at least one power converter (1, 4, 5), a plurality of processors (7-12), a memory (15), and a memory access controller (13). The first processor (7) controls the at least one power converter (1, 4, 5) on the basis of information read from the memory (15), and writes control information in the memory (15). The second processor (8) measures a current and voltage input / output to / from at least one power converter (1, 3, 5), and writes measurement information in the memory (15). The third processor (9) exchanges information with other uninterruptible power supply devices and external devices, and writes reception information in the memory (15). The plurality of fourth processors (10) respectively generate a plurality of sets of trace data from the information stored in the memory (15). Trace conditions for generating corresponding trace data are set in advance in each of the plurality of fourth processors (10). Each of the plurality of fourth processors (10) stores the trace data generated according to the corresponding trace conditions in an external storage device.

Description

Uninterruptible Power Supply Systems and Uninterruptible Power Supplies

[0001] The present disclosure relates to uninterruptible power supply systems and uninterruptible power supplies.

[0002] For example, Japanese Patent Laid-Open Publication No. 2009-278755 (Patent Document 1) discloses an uninterruptible power supply that has a function of storing trace data when a state change occurs. This uninterruptible power supply includes a converter that converts AC power from a commercial AC power source into DC power, an inverter that converts DC power from the converter or a storage battery into AC power and supplies it to a load, a control circuit that controls the operation of the device, and a waveform storage circuit that stores waveforms of each part of the device.

[0003] The control circuit controls the converter and the inverter based on output signals from a plurality of detectors that detect the input current and input voltage of the converter, the input voltage and input current of the storage battery, and the output current and output voltage of the inverter.

[0004] The waveform storage circuit converts the output signals of the plurality of detectors into signals for condition monitoring and stores the converted signals as trace data in an external storage circuit. At this time, the waveform storage circuit stores the trace data from a predetermined time before the trigger signal to a predetermined time after the trigger signal in response to the trigger signal from the control circuit.

[0005] Japanese Patent Application Laid-Open No. 2009-278755

[0006] In recent years, with the expansion of the data center market, uninterruptible power supplies (UPSs) have become larger in capacity, and power supply systems that include UPSs have become more complex. To achieve this, UPSs have been configured with multiple parallel circuits of power conversion modules mounted on a single UPS, or multiple UPSs are connected in parallel. UPSs also have been configured to link with higher-level or lower-level power supply equipment.

[0007] In these configurations, the types and amount of information related to power supply increases dramatically, so that conventional tracing technology cannot store all the trace data necessary for analyzing power supply. Furthermore, conventional technology that directly inputs various information such as output signals from multiple detectors into a waveform storage circuit requires a huge number of wires to load all the information into the waveform storage circuit.

[0008] The present disclosure has been made to solve such problems, and an object of the present disclosure is to provide an uninterruptible power supply system and an uninterruptible power supply device that can easily accommodate an increase in the amount of information related to power supply.

[0009] An uninterruptible power supply system according to one aspect of the present disclosure includes a plurality of uninterruptible power supply units connected in parallel to a load. Each of the plurality of uninterruptible power supply units includes at least one power converter, a plurality of processors, a memory accessible by the plurality of processors, and a memory access controller that controls access to the memory from the plurality of processors. The plurality of processors include first to third processors and a plurality of fourth processors. The first processor controls the at least one power converter based on information read from the memory and writes control information for the at least one power converter to the memory. The second processor measures currents and voltages input and output to the at least one power converter and writes the measurement information to the memory. The third processor exchanges information with other uninterruptible power supply units and external devices and writes the received information to the memory. The plurality of fourth processors each generate a plurality of trace data from information stored in the memory. Each of the plurality of fourth processors has a predetermined trace condition for generating the corresponding trace data. Each of the plurality of fourth processors saves the trace data generated according to the corresponding trace condition in an external storage device.

[0010] According to the present disclosure, it is possible to provide an uninterruptible power supply system that can easily accommodate an increase in the amount of information related to power supply.

[0011] It is a block diagram showing a configuration of an uninterruptible power supply system according to an embodiment of the present disclosure. It is a circuit block diagram showing a configuration of a UPS. It is a diagram explaining the operation of a plurality of status recording circuits. It is a diagram showing an example of a trigger included in a trace condition. It is a diagram showing a recommended example of a trace condition.

[0012] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference numerals, and description thereof will not be repeated.

[0013] 1 is a block diagram showing the configuration of an uninterruptible power supply system according to an embodiment of the present disclosure. As shown in FIG. 1, uninterruptible power supply system 100 includes N uninterruptible power supplies (UPS) U1 to UN, N sets of switches S1 to S3, a communication line L0, a touch panel display 74, and an external storage device 75. N is an integer of 2 or greater.

[0014] Each of UPSU1 to UPSU1N includes an input terminal T1, a bypass input terminal T2, a battery terminal T3, an output terminal T4, and communication terminals T5 to T7. In the following description, UPSU1 to UPSU1N may be collectively referred to as "UPSU." N sets of switches S1 to S3 are provided corresponding to the N UPSU1 to UPSU1N, respectively.

[0015] The input terminal T1 of each UPS is connected via a corresponding set of switches S1 to a commercial AC power supply 71. The commercial AC power supply 71 supplies AC power of a commercial frequency to the uninterruptible power supply system 100.

[0016] The bypass input terminal T2 of each UPS is connected to a bypass AC power supply 72 via a corresponding set of switches S2. The bypass AC power supply 72 supplies AC power at a commercial frequency to the uninterruptible power supply system 100. The bypass AC power supply 72 may be the same as the commercial AC power supply 71, or may be a private generator.

[0017] Battery terminal T3 of UPSU1 to UPSUUN is connected to batteries B1 to BN, respectively. Batteries B1 to BN store DC power. A capacitor may be connected in place of each of batteries B1 to BN. In the following description, batteries B1 to BN may be collectively referred to as "battery B."

[0018] The output terminal T4 of each UPS is connected to a load 73 via a corresponding set of switches S3. The load 73 is driven by AC power supplied from the uninterruptible power supply system 100.

[0019] Switches S1 to S3 are turned on when the corresponding UPSU is in use and turned off when the corresponding UPSU is to be electrically disconnected from the other UPSUs. For example, if UPSU1 fails, the corresponding switches S1 to S3 are turned off to electrically disconnect it from the other UPSUs 2 to UN.

[0020] The communication terminal T6 of each UPSU is connected to an external storage device 75. The external storage device 75 is a storage medium that can be physically removed from the UPSU and read by an external tool. The external storage device 75 is, for example, a USB memory or an SD memory card. The external storage device 75 is mainly used to store trace data for status monitoring.

[0021] The communication terminal T7 of each UPS is connected to a touch panel display 74. The touch panel display 74 is installed, for example, on the front of a rectangular panel housing that houses the UPSUs 1 to UN. The touch panel display 74 includes an input device that accepts input operations by the user of the uninterruptible power supply system 100 and a display that displays various information. By operating the touch panel display 74, the user can turn the power to the uninterruptible power supply system 100 on and off and set the power supply mode of the uninterruptible power supply system 100. The user can also operate the touch panel display 74 to set various information. The various information includes trace conditions for each of the multiple status recording circuits 10 to generate trace data.

[0022] The communication terminal T5 of each UPSU is connected to the communication terminal T5 of another UPSU via a communication line L0. Each UPSU exchanges various information with the other UPSUs via the communication line L0. Based on this information, M UPSUs are selected from the N UPSUs 1 to UN required to operate the load 73. M is an integer between 1 and N.

[0023] The selected UPS executes an operation to supply power to the load 73. During operation, when AC power is being normally supplied from the commercial AC power supply 71 (when the commercial AC power supply 71 is functioning properly), the UPS converts the AC power from the commercial AC power supply 71 into DC power, converts the DC power into AC power, supplies it to the load 73, and stores it in the battery B.

[0024] Furthermore, during operation, if AC power is not being supplied normally from commercial AC power supply 71 (during a power outage of commercial AC power supply 71), the UPSU converts DC power from battery B into AC power and supplies it to load 73. Therefore, even during a power outage, operation of load 73 can continue as long as DC power is stored in battery B. A UPSU not selected to operate load 73 performs a standby operation in which it waits without supplying power to load 73.

[0025] During operation, the UPSU also performs a diagnostic operation to determine whether a specific part of the UPSU has failed. If the UPSU determines that a specific part of the UPSU has failed as a result of the diagnostic operation, the UPSU outputs information indicating this to the touch panel display 74 via the communication terminal T6. The user of the uninterruptible power supply system 100 turns off the switches S1 to S3 corresponding to the failed UPSU, and repairs the failed UPSU or replaces it with a new UPS while driving the load 73.

[0026] 2 is a circuit block diagram showing the configuration of the UPS. As shown in Fig. 2, the UPSU includes switches SW1 to SW3, current detectors CD1 to CD6, capacitors C1, C2, and C3, reactors L1 and L2, a converter 1, a DC line 2, a bidirectional chopper 4, an inverter 5, and a semiconductor switch 6.

[0027] The switch SW1 and the reactor L1 are connected in series between the input terminal T1 and the AC node of the converter 1. The switch SW1 is controlled by the control circuit 7. When the commercial AC power supply 71 is normal, the switch SW1 is turned on. When the commercial AC power supply 71 experiences a power outage, the switch SW1 is turned off. The current detector CD1 detects a current IR (converter current) flowing between the commercial AC power supply 71 and the converter 1, and outputs a signal indicating the detected value to the measurement circuit 8. The instantaneous value of the AC voltage VR (converter input voltage) appearing at the input terminal T1 is detected by the measurement circuit 8.

[0028] The capacitor C1 is connected to a node between the switch SW1 and the reactor L1. The capacitor C1 and the reactor L1 constitute an AC filter F1. The AC filter F1 is a low-pass filter that passes AC power of the commercial frequency from the commercial AC power supply 71 to the converter 1 and prevents signals of the switching frequency generated by the converter 1 from passing to the commercial AC power supply 71.

[0029] Converter 1 is a well-known device including a plurality of semiconductor switching elements and a plurality of diodes, and is controlled by control circuit 7. When commercial AC power supply 71 is operating normally, converter 1 converts AC power into DC power and outputs it to DC line 2. The output voltage of converter 1 can be controlled to a desired value. Converter 1 corresponds to one embodiment of a "first power converter."

[0030] In the event of a power outage in the commercial AC power supply 71, the operation of the converter 1 is stopped. The capacitor 3 is connected to the DC line 2 and smoothes the voltage of the DC line 2. The instantaneous value of the DC voltage VD appearing on the DC line 2 is detected by a measurement circuit 8.

[0031] When the commercial AC power supply 71 is normal, the control circuit 7 controls the converter 1 so that the DC voltage VD of the DC line 2 becomes the reference DC voltage VDR.

[0032] The DC line 2 is connected to a high-voltage side node of a bidirectional chopper 4, and the low-voltage side node of the bidirectional chopper 4 is connected to a battery terminal T3 via a switch SW2. The switch SW2 is controlled by a control circuit 7. The switch SW2 is turned on when the UPSU is in use and turned off, for example, during maintenance of the UPSU and battery B.

[0033] The bidirectional chopper 4 is a well-known device including a plurality of semiconductor switching elements and a plurality of diodes, and is controlled by the control circuit 7. When the commercial AC power supply 71 is operating normally, the bidirectional chopper 4 stores the DC power generated by the converter 1 in the battery B. When the commercial AC power supply 71 experiences a power outage, the bidirectional chopper 4 supplies the DC power of the battery B to the inverter 5 via the DC line 2. The bidirectional chopper 4 corresponds to one embodiment of a "third power converter."

[0034] The current detector CD4 detects the current IB (battery current) flowing between the bidirectional chopper 4 and the battery B, and outputs a signal indicating the detected value to the measurement circuit 8. The instantaneous value of the inter-terminal voltage VB of the battery B (battery voltage) appearing at the battery terminal T3 is detected by the measurement circuit 8.

[0035] The control circuit 7 controls the bidirectional chopper 4 so that the battery voltage VB becomes equal to the reference DC voltage VBR when the commercial AC power supply 71 is normal, and controls the bidirectional chopper 4 so that the DC voltage VD of the DC line 2 becomes equal to the reference DC voltage VDR when the commercial AC power supply 71 is in a power outage. The DC line 2 is connected to a DC node of the inverter 5.

[0036] The inverter 5 is a well-known type having a plurality of semiconductor switching elements and a plurality of diodes, and is controlled by a control circuit 7. The inverter 5 converts DC power supplied from the converter 1 or the bidirectional chopper 4 via the DC line 2 into AC power and outputs it to an output node.

[0037] That is, when the commercial AC power supply 71 is operating normally, the inverter 5 converts DC power supplied from the converter 1 via the DC line 2 into AC power, and when the commercial AC power supply 71 is in a power outage, the inverter 5 converts DC power supplied from the battery B via the bidirectional chopper 4 into AC power. The output voltage of the inverter 5 can be controlled to a desired value. The inverter 5 corresponds to one embodiment of a "second power converter."

[0038] An output node of the inverter 5 is connected to a first terminal of a switch SW3 via a reactor L2, and a second terminal of the switch SW3 is connected to an output terminal T4. A capacitor C2 is connected to a node between the reactor L2 and the switch SW3. The capacitor C2 and the reactor L2 form an AC filter F2. The AC filter F2 is a low-pass filter that passes commercial frequency AC power generated by the inverter 5 to the output terminal T4 and prevents switching frequency signals generated by the inverter 5 from passing to the output terminal T4.

[0039] The switch SW3 is controlled by the control circuit 7, and is turned on in an inverter power supply mode in which the AC power generated by the inverter 5 is supplied to the load 73, and is turned off in a bypass power supply mode in which the AC power from the bypass AC power supply 72 is supplied to the load 73.

[0040] The instantaneous value of AC voltage VA (inverter voltage) appearing at the node between reactor L2 and switch SW3 is detected by measurement circuit 8. Current detector CD2 detects current IA (inverter current) output from inverter 5 and provides a signal indicating the detected value to measurement circuit 8. Current detector CD3 detects current IA flowing between AC filter F2 and output terminal T4 and provides a signal indicating the detected value to measurement circuit 8. The instantaneous value of AC voltage VL (load voltage) appearing at output terminal T4 is detected by measurement circuit 8. Control circuit 7 controls inverter 5 so that AC voltage VL becomes a sinusoidal reference AC voltage VLR.

[0041] The semiconductor switch 6 includes a pair of thyristors connected in antiparallel to each other and is connected between the bypass input terminal T2 and the output terminal T4. The semiconductor switch 6 is controlled by the control circuit 7 and is turned off in the inverter power supply mode and turned on in the bypass power supply mode. Furthermore, if the inverter 5 fails, the semiconductor switch 6 turns on and supplies AC power from the bypass AC power supply 72 to the load 73. The instantaneous value of the AC voltage VS (bypass input voltage) appearing at the bypass input terminal T2 is detected by the measurement circuit 8. The current detector CD5 detects a current IS (bypass current) flowing between the bypass input terminal T2 and the semiconductor switch 6 and provides a signal indicating the detected value to the measurement circuit 8. The current detector CD6 detects a current IL (UPS output current) flowing between the semiconductor switch 6 or the inverter 5 and the output terminal T4 and provides a signal indicating the detected value to the measurement circuit 8.

[0042] The UPS further includes a control circuit 7 , a measurement circuit 8 , a communication circuit 9 , a plurality of status recording circuits 10 , a setting circuit 11 , a display circuit 12 , a memory access controller 13 , and a system information collection memory 15 .

[0043] In the present embodiment, the control circuit 7, the measurement circuit 8, the communication circuit 9, the plurality of status recording circuits 10, the setting circuit 11, the display circuit 12, and the memory access controller 13 are configured using a plurality of central processing units (CPUs) and / or circuits such as application specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs). In one aspect, the control circuit 7, the measurement circuit 8, the communication circuit 9, the plurality of status recording circuits 10, the setting circuit 11, the display circuit 12, and the memory access controller 13 are configured using a plurality of CPUs that are independent of one another. In another aspect, at least some of the control circuit 7, the measurement circuit 8, the communication circuit 9, the plurality of status recording circuits 10, the setting circuit 11, the display circuit 12, and the memory access controller 13 are configured using at least one FPGA.

[0044] The system information collection memory 15 is configured to be accessible by the multiple CPUs and / or FPGAs that make up the control circuit 7, the measurement circuit 8, the communication circuit 9, the multiple status recording circuits 10, the setting circuit 11, and the display circuit 12. The system information collection memory 15 is a memory that collects and collectively stores information and signals used by each of the control circuit 7, the measurement circuit 8, the communication circuit 9, the multiple status recording circuits 10, the setting circuit 11, and the display circuit 12. The memory access controller 13 is configured to control access to the system information collection memory 15 from the control circuit 7, the measurement circuit 8, the communication circuit 9, the multiple status recording circuits 10, the setting circuit 11, and the display circuit 12.

[0045] Specifically, measurement circuit 8 detects instantaneous values ​​of AC voltages VR, VS, VA, and VL, instantaneous value of DC voltage VD, and instantaneous value of battery voltage VB, and provides signals indicating the detected values ​​to memory access controller 13. Measurement circuit 8 also provides output signals of current detectors CD1 to CD6 to memory access controller 13. The instantaneous values ​​of AC voltages VR, VS, VA, and VL, instantaneous value of DC voltage VD, instantaneous value of battery voltage VB, and output signals of current detectors CD1 to CD6 correspond to an embodiment of "measurement information." Memory access controller 13 stores the measurement information from measurement circuit 8 in system information collection memory 15. Measurement circuit 8 corresponds to an embodiment of "second processor."

[0046] The communication circuit 9 exchanges various signals with the other UPSUs 2 to 1N via the communication terminal T5 and the communication line L0. The communication circuit 9 also exchanges various signals with external devices via the communication terminal T5. The external devices include a peripheral panel including N sets of switches S1 to S3, a battery panel including batteries B1 to BN, and upper or lower power supply equipment. The communication circuit 9 provides information received from the other UPSUs 2 to 1N and the external devices to the memory access controller 13. The memory access controller 13 stores the information received by the communication circuit 9 in the system information collection memory 15. The communication circuit 9 also transmits various information provided by the memory access controller 13 to the other UPSUs 2 to 1N via the communication terminal T5 and the communication line L0, and transmits the information to the external devices via the communication terminal T5. The communication circuit 9 corresponds to one embodiment of the "third processor."

[0047] The setting circuit 11 receives information set by a user of the uninterruptible power supply system 100 operating the touch panel display 74. The setting circuit 11 provides the setting information to the memory access controller 13. The memory access controller 13 stores the setting information from the setting circuit 11 in the system information collection memory 15. The setting circuit 11 corresponds to one embodiment of the "fifth processor."

[0048] The control circuit 7 accesses the system information collection memory 15 via the memory access controller 13 to read information required for controlling the UPS from the system information collection memory 15. The information required for controlling the UPS includes measurement information from the measurement circuit 8, received information from the communication circuit 9, and setting information from the setting circuit 11.

[0049] The control circuit 7 controls the entire UPSU based on information read from the system information collection memory 15. Specifically, the control circuit 7 controls the converter 1, bidirectional chopper 4, and inverter 5, and also controls the on / off of switches SW1 to SW3 and semiconductor switch 6, based on measurement information, reception information, and setting information. The control circuit 7 also provides control information related to control of the UPSU to the memory access controller 13. The control information includes control signals for controlling each of the converter 1, bidirectional chopper 4, and inverter 5, and on / off commands for switches SW1 to SW3 and semiconductor switch 6. The memory access controller 13 stores the control information from the control circuit 7 in the system information collection memory 15.

[0050] Furthermore, the control circuit 7 determines whether or not a predetermined part including the inverter 5 has failed based on the information read from the system information collection memory 15, and if a predetermined part has failed, provides a failure detection signal to the memory access controller 13. The memory access controller 13 stores the failure detection signal from the control circuit 7 in the system information collection memory 15. The control circuit 7 corresponds to one embodiment of the "first processor".

[0051] In this way, the control information of the control circuit 7, the fault detection signal, the measurement information of the measurement circuit 8, the reception information of the communication circuit 9, and the setting information of the setting circuit 11 are all stored in the system information collection memory 15. This information is written in a pre-specified data size to a pre-specified address in the system information collection memory 15. The control circuit 7 controls the entire UPSU while referring to the information written in the system information collection memory 15 via the memory access controller 13, and also stores the control information in the system information collection memory 15 via the memory access controller 13.

[0052] The control information stored in the system information collection memory 15 is constantly updated in accordance with the control cycle of the control circuit 7. Furthermore, the measurement information is constantly updated in accordance with the measurement cycle of the measurement circuit 8. Each of the multiple status recording circuits 10 generates trace data from the information in the constantly updated system information collection memory 15 in accordance with preset trace conditions. Figure 3 is a diagram explaining the operation of the multiple status recording circuits 10. In the diagram, A to G represent information or signals.

[0053] 3, the system information collection memory 15 stores control information from the control circuit 7, measurement information from the measurement circuit 8, reception information from the communication circuit 9, and setting information from the setting circuit 11. The setting information includes M trace conditions corresponding to M status recording circuits 10_1 to 10_M, where M is an integer of 2 or greater.

[0054] The trace conditions are conditions under which each status recording circuit 10 generates trace data. The trace conditions include the type of information to be recorded by the status recording circuit 10, the recording time of the information, a trigger for starting the recording of the information, and a sampling frequency. The user of the uninterruptible power supply system 100 can set the trace conditions for each status recording circuit 10 using the touch panel display 74. The set M trace conditions are stored in the system information collection memory 15 as setting information of the setting circuit 11.

[0055] The M status recording circuits 10_1 to 10M are configured using M CPUs or FPGAs that are independent of each other. The CPU or FPGA that configures each status recording circuit 10 reads information from the system information collection memory 15 in accordance with the corresponding trace conditions and generates trace data.

[0056] For example, the status recording circuit 10_1 reads information A and B set in the first trace condition from the system information collection memory 15 in accordance with the sampling frequency set in the first trace condition, and records the read information A and B as trace data. Trace data for the recording time set in the first trace condition is constantly overwritten and recorded in the status recording circuit 10_1. When a trigger set in the first trace condition occurs, the status recording circuit 10_1 stops overwriting the trace data at the time the trigger occurred or at the time when the recording time has elapsed since the trigger occurred. This allows the status recording circuit 10_1 to record trace data from before the recording time to after the recording time relative to the time the trigger occurred. The status recording circuit 10_1 saves the generated trace data in the external storage device 75.

[0057] The status recording circuit 10_2 reads information B, D, and FPGA set in the second trace condition from the system information collection memory 15 according to the sampling frequency set in the second trace condition, and records the read information B, D, and F as trace data. The status recording circuit 10_M is constantly overwritten and recorded with trace data for the recording time set in the second trace condition. When a trigger set in the second trace condition occurs, the status recording circuit 10_2 stops overwriting the trace data at the time the trigger occurs or the time when the recording time has elapsed since the trigger occurred. This allows the status recording circuit 10_2 to record trace data from before the recording time to after the recording time relative to the time the trigger occurred. The status recording circuit 10_2 saves the generated trace data in the external storage device 75. The status recording circuit 10 corresponds to an embodiment of the "fourth processor."

[0058] 4 is a diagram showing an example of triggers included in the trace conditions. A number of types of triggers are shown in FIG. 4. Each trigger is assigned a name and a setting number.

[0059] For example, the trigger for setting number 1, "major failure," is a trigger for recording trace data when a major failure occurs in the corresponding UPSU. The trigger for setting number 2, "minor failure," is a trigger for recording trace data when a minor failure occurs in the corresponding UPSU. Note that a major failure is a failure that makes it impossible to continue operating the UPSU, and a minor failure is a failure that allows the UPSU to continue operating for a while without repair.

[0060] The trigger for setting number 3, "power outage," is a trigger for recording trace data when a power outage occurs in the commercial AC power supply 71. The trigger for setting number 4, "switch," is a trigger for recording trace data when a UPS in inverter power supply mode is switched to bypass power supply mode. The trigger for setting number 5, "switch back," is a trigger for recording trace data when a UPS in bypass power supply mode is switched back to inverter power supply mode.

[0061] The trigger for setting number 6, "output monitoring," is a trigger for recording trace data when the AC voltage VL appearing at the output terminal T4 of the corresponding UPSU fluctuates. The trigger for setting number 7, "discharge start," is a trigger for recording trace data when the discharge of battery B connected to the corresponding UPSU starts. The trigger for setting number 8, "discharge end," is a trigger for recording trace data when the discharge of battery B connected to the corresponding UPSU ends.

[0062] The trigger with setting number 9, "Manual," is a trigger that is manually set by the user of the uninterruptible power supply system 100. The trigger with setting number 10, "Verification," is a trigger for recording trace data in response to the logical sum or logical product of multiple signals stored in the system information collection memory 15.

[0063] A user of the uninterruptible power supply system 100 can set a desired trigger by inputting a setting number into the touch panel display 74. However, since each status recording circuit 10 has a fixed data storage capacity, it is possible to prepare recommended examples of the type of information to be recorded as trace data, the recording time, and the sampling frequency corresponding to each of the multiple triggers shown in FIG.

[0064] Fig. 5 shows recommended examples of trace conditions. Five trace conditions are shown in Fig. 5. The five trace conditions correspond to five types of triggers, respectively. Each trace condition includes the name of the trigger, and recommended examples of the type of information to be recorded, the sampling frequency, and the recording time.

[0065] For example, the first trace condition is a recommended example of a trace condition corresponding to a "major fault" trigger. The second trace condition is a recommended example of a trace condition corresponding to a "minor fault" trigger. The third trace condition is a recommended example of a trace condition corresponding to a "switchover" trigger. The fourth trace condition is a recommended example of a trace condition corresponding to a "revert" trigger. The fifth trace condition is a recommended example of a trace condition corresponding to a "verification" trigger.

[0066] In the recommended example shown in FIG. 5 , the type of information to be recorded, the recording time, and the sampling frequency vary depending on the type of trigger. The recorded information includes measurement information from the measurement circuit 8. Specifically, among the five trace conditions, the first trace condition corresponding to a "major fault" records instantaneous values ​​of multiple currents and voltages included in the measurement information. The sampling frequency is 6 kHz, and the recording time is 0.2 seconds. This allows the status recording circuit 10 to store trace data of instantaneous values ​​of multiple currents and voltages from 0.2 seconds before to 0.2 seconds after the time of the major fault in the external storage device 75.

[0067] The second trace condition corresponding to a "minor fault" has the same recording target as the first trace condition, but has a lower sampling frequency and therefore a longer recording time than the first trace condition. As a result, when a minor fault occurs, the sampling interval is coarser than when a major fault occurs, but trace data of multiple instantaneous current and voltage values ​​for a longer period (0.4 sec) before and after the time of the fault can be stored in the external storage device 75.

[0068] The fourth trace condition, which corresponds to "output monitoring," has a higher sampling frequency than the first trace condition, and therefore a shorter recording time than the first trace condition. This allows trace data that precisely samples the sudden changes in the instantaneous values ​​of current and voltage at the moment when a fluctuation in the output voltage occurs to be stored in the external storage device 75.

[0069] 5 is presented to the user of the uninterruptible power supply system 100 via the touch panel display 74. The user of the uninterruptible power supply system 100 can set the trace conditions in each status recording circuit 10 while referring to the presented recommendation.

[0070] 3, each of the status recording circuits 10_1 to 10_M generates trace data by extracting and recording information set in the corresponding trace conditions from among the many pieces of information stored in the system information collection memory 15. Because the system information collection memory 15 stores control information, measurement information, reception information, and setting information all together, providing multiple status recording circuits 10 makes it possible to generate trace data of various information in parallel. For example, according to the examples shown in FIGS. 4 and 5, it is possible to generate trace data of different information at different times, such as when a major fault occurs, when a minor fault occurs, when the power supply mode is switched, and when a power outage occurs.

[0071] Returning to FIG. 2 , the display circuit 12 is disposed between the touch panel display 74 and the memory access controller 13. The touch panel display 74 accepts a user input specifying an address in the system information collection memory 15 and outputs information from the accepted address to the display circuit 12. The display circuit 12 accesses the system information collection memory 15 via the memory access controller 13 to read information stored at the specified address from the system information collection memory 15. The display circuit 12 provides the read information to the touch panel display 74, thereby displaying the information on the touch panel display 74. This allows instantaneous values ​​of various currents or voltages included in the measurement information to be read from the system information collection memory 15 and displayed on the touch panel display 74. Furthermore, time-series data showing changes over time in the instantaneous values ​​of various currents or voltages can be displayed on the touch panel display 74.

[0072] The display circuit 12 is further connected to the plurality of status recording circuits 10. The display circuit 12 can acquire trace data generated by the plurality of status recording circuits 10 and transfer it to the touch panel display 74, thereby displaying the trace data on the touch panel display 74. The display circuit 12 corresponds to one embodiment of the "sixth processor".

[0073] As described above, the uninterruptible power supply system according to this embodiment is configured such that the control circuit, measurement circuit, communication circuit, status recording circuit, setting circuit, and display circuit included in the uninterruptible power supply are configured with multiple independent processors, and the multiple processors are connected to the system information collection memory via a memory access controller so that they can access the system information collection memory. This allows the multiple circuits to share control information from the control circuit, measurement information from the measurement circuit, received information from the communication circuit, and setting information from the setting circuit. Furthermore, because access to the system information collection memory is performed by the memory access controller, each circuit can quickly read and use only the information it needs from the system information collection memory. This eliminates the need for each circuit to exchange information with other circuits, enabling high-speed processing. This makes it easy to accommodate an increase in the amount of information related to power supply.

[0074] Furthermore, since multiple circuits can operate in parallel, multiple status recording circuits can be provided for recording trace data. Since the multiple status recording circuits are also composed of multiple processors independent of each other, each status recording circuit can record trace data in parallel according to the corresponding trace condition.

[0075] The trace conditions of each status recording circuit are stored in the system information collection memory as setting information of the setting circuit and are shared among multiple circuits. This allows the user of the uninterruptible power supply system to access the system information collection memory via the touch panel display and appropriately change the trace conditions of each status recording circuit while referring to the setting information.

[0076] In the above-described embodiment, an uninterruptible power supply system including multiple uninterruptible power supplies connected in parallel to a load has been described. However, the present disclosure can also be applied to an uninterruptible power supply including multiple parallel circuits of power conversion modules. In this case, control information and measurement information of the multiple power conversion modules, as well as information exchanged between the multiple power conversion modules, are collectively stored in a system information collection memory. Each of the multiple state circuits then stores trace data in an external storage device according to the corresponding trace conditions.

[0077] Furthermore, in the above-described embodiment, the configuration of an uninterruptible power supply including a converter, an inverter, and a bidirectional chopper has been described, but the present disclosure can also be applied to an uninterruptible power supply including a high-speed switch connected between an AC power supply and a load, and a power converter connected between the load and a power storage device.

[0078] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0079] 1 Converter, 2 DC line, 3, C1, C2 Capacitor, 4 Bidirectional chopper, 5 Inverter, 6 Semiconductor switch, 7 Control circuit, 8 Measurement circuit, 9 Communication circuit, 10 Status recording circuit, 11 Setting circuit, 12 Display circuit, 13 Memory access controller, 15 System information collection memory, 71 Commercial AC power supply, 72 Bypass AC power supply, 73 Load, 74 Touch panel display, 75 External storage device, 100 Uninterruptible power supply system, B, B1 to BN Batteries, CD1 to CD6 Current detectors, F1, F2 AC filters, L0 Communication line, L1, L2 Reactor, S1 to S3, SW1 to SW3 Switches, T1 Input terminal, T2 Bypass input terminal, T3 Battery terminal, T4 Output terminal, T5 to T7 Communication terminals, U, U1 to UN Uninterruptible power supply.

Claims

1. An uninterruptible power supply system comprising a plurality of uninterruptible power supply devices connected in parallel to a load, each of the plurality of uninterruptible power supply devices comprising: at least one power converter; a plurality of processors; a memory configured to be accessible by the plurality of processors; and a memory access controller configured to control access from the plurality of processors to the memory, the plurality of processors including: a first processor configured to control the at least one power converter based on information read from the memory and write control information of the at least one power converter to the memory; a second processor configured to measure a current and a voltage input to and output from the at least one power converter and write measurement information to the memory; a third processor configured to exchange information with other uninterruptible power supply devices and external devices and write received information to the memory; and a plurality of fourth processors configured to generate respective plurality of trace data from information stored in the memory, wherein trace conditions for generating corresponding trace data are preset for each of the plurality of fourth processors, and each of the plurality of fourth processors stores the trace data generated according to the corresponding trace conditions in an external storage device.

2. The uninterruptible power supply system according to claim 1, further comprising an input device configured to receive user input, the plurality of processors further including a fifth processor configured to set the plurality of trace conditions corresponding to the plurality of fourth processors according to user input to the input device and write setting information to the memory, and each of the plurality of fourth processors generates the trace data based on the setting information written to the memory.

3. The uninterruptible power supply system according to claim 1 or 2, wherein the trace conditions include a type of information to be recorded, a trigger for starting recording, a recording time, and a sampling frequency.

4. The uninterruptible power supply system according to claim 1 or 2, further comprising a display for displaying various information, wherein the plurality of processors further include a sixth processor that displays the time-series data of the measurement information stored in the memory and the trace data generated by each of the fourth processors on the display.

5. The at least one power converter includes a first power converter connected between an AC power supply and a DC line, a second power converter connected between the DC line and the load, and a third power converter connected between a power storage device and the DC line. Each of the plurality of uninterruptible power supply devices further includes a bypass switch connected between the AC power supply and the load. The first processor turns on the bypass switch when the third power converter fails and writes on / off information of the bypass switch to the memory.

6. The trigger according to claim 5 includes any one of a failure of the uninterruptible power supply device, a switching of the power supply mode of the uninterruptible power supply device, and a power failure of the AC power supply.

7. An uninterruptible power supply device includes at least one power converter, a plurality of processors, a memory configured to be accessible by the plurality of processors, and a memory access controller that controls access from the plurality of processors to the memory. The plurality of processors include a first processor that controls the at least one power converter based on information read from the memory and writes control information of the at least one power converter to the memory, a second processor that measures current and voltage input to and output from the at least one power converter and writes measurement information to the memory, a third processor that exchanges information with an external device and writes received information to the memory, and a plurality of fourth processors that each generate a plurality of trace data from the information stored in the memory. Trace conditions for generating corresponding trace data are preset for each of the plurality of fourth processors, and each of the plurality of fourth processors stores the trace data generated according to the corresponding trace conditions in an external storage device.

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