Converter

Abstract

Provided is a converter that is capable of suppressing a spike current generated due to capacitors having a potential difference therebetween being connected to each other, thereby being able to reduce conduction loss of switching elements and noise generation.　The converter comprises an inductor L, a plurality of switching elements Q1-Q6, and a plurality of capacitors C1, C2, and Co connected via the switching elements Q1-Q6. A current path of an output current Io passing through the capacitors C1, C2, Co is formed by turn-on of the switching elements Q1-Q6 (complementary turn-on of the switching elements Q1, Q3, Q5 and the switching elements Q2, Q4, Q6). The converter also comprises a sub-inductor Lo inserted into the current path.

Description

converter

[0001] The present invention relates to a converter in which capacitors are connected to each other via switching elements.

[0002] Hybrid converters combining a buck converter and a switched capacitor (SC) converter have been proposed, including an always-dual-path hybrid (ADPH) DC-DC converter (see, for example, Non-Patent Document 1). The converter 1 shown in FIG. 33 is an ADPH converter, consisting of one inductor L, two capacitors C1 and C2, and six switching elements Q1 to Q6. The converter 1 operates in two modes: MODE 1 (switching elements Q1, Q3, and Q5 on; Q2, Q4, and Q6 off) and MODE 2 (switching elements Q1, Q3, and Q5 off; Q2, Q4, and Q6 on). The output current Io of the converter 1 is supplied via two paths: the inductor L and the capacitors C1 and C2, thereby reducing the DC current and conduction loss of the inductor L.

[0003] 2022 IEEE Energy Conversion Congress and Exposition (ECCE): 48 V-to-12 V Always-Dual-Path Hybrid DC-DC Converter for Inductor Current Reduction

[0004] However, in the ADPH converter, there is a path connecting the capacitors C1, C2, and Co to each other via the switching elements Q1 to Q6. Therefore, a large spike current flows due to the potential difference between the capacitors C1, C2, and Co. This spike current increases the conduction loss of the switching elements Q1 to Q6. The spike current also causes noise.

[0005] The present invention has been made in view of the above problems, and an object of the present invention is to provide a converter that can suppress spike currents that occur when capacitors having a potential difference are connected to each other.

[0006] To achieve the above object, the converter according to the present invention is configured as follows: The converter according to the present invention includes an inductor, a plurality of switching elements, and a plurality of capacitors connected via the switching elements, and a current path for an output current passing through the capacitors is formed by turning on the switching elements, and further includes a sub-inductor inserted in the current path.

[0007] The converter of the present invention can suppress spike currents that occur when capacitors having a potential difference are connected to each other, thereby achieving the effect of reducing conduction loss in switching elements and noise generation.

[0008] 1 is a block diagram showing the configuration of a first embodiment of a converter according to the present invention. FIG. 1 is a diagram showing a current path of the converter shown in FIG. 1. FIG. 2 is a diagram showing a capacitor current flowing through the capacitor shown in FIG. 1. FIG. 3 is a diagram showing a regenerative current of the sub-inductor shown in FIG. 1. FIG. 4 is a diagram showing a body diode current flowing due to the regenerative current shown in FIG. 5. FIG. 6 is a diagram showing a sequence for reducing the body diode current shown in FIG. 7. FIG. 7 is a diagram showing a regenerative current flowing in the sequence shown in FIG. 8. FIG. 9 is a diagram showing a control signal at turn-on by the control circuit shown in FIG. 1. FIG. 10 is a diagram showing a regenerative current during dead time DT2 of the converter shown in FIG. 1. FIG. 11 is a diagram showing a regenerative current during dead time DT1 of the converter shown in FIG. 1. FIG. 12 is a diagram showing a regenerative current when a sub-inductor is not inserted. FIG. 13 is a block diagram showing the configuration of a second embodiment of a converter according to the present invention. FIG. 14 is a diagram showing a current path of the converter shown in FIG. 12. FIG. 15 is a diagram showing a capacitor current flowing through the capacitor shown in FIG. 12. FIG. 16 is a diagram showing a regenerative current of the sub-inductor shown in FIG. 12. FIG. 17 is a diagram showing a body diode current flowing due to the regenerative current shown in FIG. 16. FIG. 18 is a diagram showing a sequence for reducing the body diode current shown in FIG. 17. FIG. 19 is a diagram showing a regenerative current flowing in the sequence shown in FIG. 18. FIG. 20 is a diagram showing a control signal at turn-on by the control circuit shown in FIG. 12. FIG. 21 is a diagram showing a regenerative current during dead time DT 27 is a diagram showing a regenerative current during dead time DT1 of the converter shown in FIG. 12. FIG. 28 is a block diagram showing the configuration of a third embodiment of a converter according to the present invention. FIG. 29 is a diagram showing a current path of the converter shown in FIG. 22. FIG. 30 is a diagram showing a capacitor current flowing through the capacitor shown in FIG. 22. FIG. 31 is a diagram showing a regenerative current of the sub-inductor shown in FIG. 22. FIG. 32 is a diagram showing a body diode current flowing due to the regenerative current shown in FIG. 22. FIG. 33 is a diagram showing a sequence for reducing the body diode current shown in FIG. 26. FIG. 34 is a diagram showing a regenerative current flowing in the sequence shown in FIG. 27. FIG. 35 is a diagram showing a control signal at turn-on by the control circuit shown in FIG. 22. FIG. 36 is a diagram showing a regenerative current during dead time DT2 of the converter shown in FIG. 22. FIG. 37 is a diagram showing a regenerative current during dead time DT1 of the converter shown in FIG. 22. FIG. 38 is a diagram comparing losses with and without ZVS.FIG. 1 is a block diagram showing a configuration of a conventional converter.

[0009] Preferred embodiments of the present invention will now be described with reference to the accompanying drawings.

[0010] First Embodiment Referring to FIG. 1A, a converter 10 according to a first embodiment is an always-dual-path hybrid (ADPH) converter. Referring to FIG. 1, the converter 10 includes six N-type switching elements Q1 to Q6, capacitors C1, C2, and Co, an inductor L, a control circuit 20, and a sub-inductor Lo. The converter 10 operates in two modes: MODE 1 (switching elements Q1, Q3, and Q5 on; Q2, Q4, and Q6 off) and MODE 2 (switching elements Q1, Q3, and Q5 off; Q2, Q4, and Q6 on). The output current Io of the converter 10 is supplied from two current paths, the inductor L and the capacitors C1 and C2, thereby reducing the DC current and conduction loss of the inductor L.

[0011] The switching elements Q1 to Q6 are power elements that switch the voltage applied to the high-potential side main terminal D and output it to the low-potential side main terminal S based on control signals G1 to G6 applied to the control terminal G. The switching elements Q1 to Q6 are semiconductor elements such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors). In the following description, the switching elements Q1 to Q6 are assumed to be MOSFETs.

[0012] The capacitors C1 and C2 are flying capacitors that store electric charge due to the input voltage Vin and function as temporary batteries. The capacitor Co is an output capacitor that smoothes the output voltage Vo and supplies the output current Io to the load.

[0013] The switching elements Q1, Q2, and Q3 are connected as a series circuit between the input terminal and the output terminal. The series circuit consisting of the capacitor C1 and the switching element Q4 is connected between ground and point A, which is the connection point between the switching elements Q1 and Q2. The series circuit consisting of the capacitor C2 and the switching element Q5 is connected between ground and point B, which is the connection point between the switching elements Q2 and Q3. The switching element Q6 is connected between the output terminal and the connection point between the capacitor C2 and the switching element Q5. The inductor L is connected between the output terminal and the connection point between the capacitor C1 and the switching element Q4. The capacitor Co is connected between the output terminal and ground.

[0014] The control circuit 20 controls the on / off of the switching elements Q1, Q3, and Q5 in synchronization with each other, and controls the on / off of the switching elements Q2, Q4, and Q6 in synchronization with the switching elements Q1, Q3, and Q5 in a complementary manner with dead times DT1 and DT2 sandwiched therebetween.

[0015] The voltage conversion ratio (M = Vo / Vin) of converter 10 operates at a step-down ratio of 1 / 3 or less depending on the duty cycle of switching elements Q1 to Q6. Converter 10 has two circuit states due to complementary on / off control of switching elements Q1, Q3, Q5 and switching elements Q2, Q4, Q6.

[0016] FIG. 2A shows MODE 1, in which switching elements Q1, Q3, and Q5 are on and switching elements Q2, Q4, and Q6 are off. In MODE 1, switching element Q1 is on, so capacitor C1 and capacitor Co are connected via inductor L. Therefore, capacitor current IC1 flowing through capacitor C1 flows via inductor L along the current path indicated by the dotted arrow in FIG. 2A and is determined by inductor L. Also, in MODE 1, switching elements Q3 and Q5 are on, so capacitor C2 and capacitor Co are connected via switching element Q3. Therefore, capacitor current IC2 flowing through capacitor C2 flows via switching element Q3 along the current path indicated by the solid arrow in FIG. 2A.

[0017] 2(b) shows MODE 2, in which switching elements Q1, Q3, and Q5 are off and switching elements Q2, Q4, and Q6 are on. In MODE 2, switching elements Q2 and Q6 are on, so capacitors C1 and C2 are connected in series via switching element Q2, and capacitors C2 and Co are connected via switching element Q6. Therefore, capacitor currents IC1 and IC2 are equal, and they flow via switching elements Q2 and Q6 along the current paths indicated by solid arrows in FIG. 2(b).

[0018] The sub-inductor Lo is inserted (disposed) between the switching elements Q3 and Q6, which are downstream of the switching elements Q3 and Q6, and the positive terminal of the capacitor Co. The location where the sub-inductor Lo is inserted is a current path through which the capacitor current IC2 flows in both MODE 1 and MODE 2, as shown by the solid arrows in FIG. 2(a) and FIG. 2(b).

[0019] The sub-inductor Lo is provided for one purpose: to suppress spike currents that occur when the switching elements Q1 to Q6 are turned on. Figure 3(a) is a simulated waveform diagram of the capacitor currents IC1 and IC2 when the sub-inductor Lo is not inserted. Figure 3(b) is a simulated waveform diagram of the capacitor currents IC1 and IC2 when the sub-inductor Lo is inserted.

[0020] Referring to Figure 3(a), at the timing of switching from MODE1 to MODE2 (when the switching elements Q2, Q4, and Q6 turn on), spike currents are generated in the capacitor currents IC1 and IC2. In MODE2, the capacitor current IC1 = IC2 (positive and negative are reversed in Figure 3). Also, at the timing of switching from MODE2 to MODE1 (when the switching elements Q1, Q3, and Q5 turn on), a spike current is generated in the capacitor current IC2.

[0021] 3B, it can be seen that the insertion of the sub-inductor Lo suppresses spike currents at the timing when the mode is switched. By suppressing spike currents, the converter 10 can reduce the conduction loss of the switching elements Q2 to Q6.

[0022] The sub-inductor Lo may have an inductance that is sufficiently smaller than that of the inductor L. For example, the sub-inductor Lo may use the inductance of a wiring pattern whose shape and length have been adjusted.

[0023] In the converter 10 shown in Fig. 1A, in MODE 1, the sub-inductor Lo is also arranged in the current path of the capacitor current IC1 indicated by the dotted arrow in Fig. 2A. The capacitor current IC1 in MODE 1 is determined by the inductor L. Therefore, as in the converter 10a shown in Fig. 1B, the sub-inductor Lo may be arranged in a path through which the capacitor current IC1 in MODE 1 does not flow.

[0024] Since the converter 10 has the sub-inductor Lo inserted, a regenerative current ILo is generated in the sub-inductor Lo during the dead times DT1 and DT2, as shown by the arrows in Fig. 4. Note that the regenerative current IL of the inductor L is omitted in Fig. 4.

[0025] The regenerative current ILo shown in Fig. 4 is generated during a dead time DT1 when the switching elements Q1, Q3, and Q5 are turned off, and during a dead time DT2 when the switching elements Q2, Q4, and Q5 are turned off. As shown in Fig. 4, the regenerative current ILo generates a closed loop that passes through the body diodes of the switching elements Q5 and Q6. The currents that flow through the body diodes of the switching elements Q5 and Q6 become body diode currents IBD5 and IBD6 shown in Fig. 5, which cause body diode loss and reduce efficiency.

[0026] 6, the control circuit 20 delays the turn-off of the switching element Q5 during the period when the regenerative current ILo flows in the dead time DT1, and also delays the turn-off of the switching element Q6 during the period when the regenerative current ILo flows in the dead time DT2.

[0027] By delaying the turn-off of switching element Q5 during dead time DT1, the regenerative current ILo flows through the body of switching element Q5, preventing the body diode current IBD5 from flowing, as shown in Figure 7(a). By delaying the turn-off of switching element Q6 during dead time DT2, the regenerative current ILo flows through the body of switching element Q6, preventing the body diode current IBD6 from flowing, as shown in Figure 7(b). In this way, the body diode current IBD5 does not flow during dead time DT1, and the body diode current IBD6 does not flow during dead time DT2, reducing body diode loss.

[0028] The control circuit 20 utilizes the regenerative current ILo of the sub-inductor Lo and optimizes the dead times DT1 and DT2 to cause the switching elements Q2, Q3, Q5, and Q6 to perform zero-voltage switching (hereinafter referred to as ZVS), thereby reducing switching loss and noise generation.

[0029] During the dead time DT2, the regenerative current ILo of the sub-inductor Lo discharges the charge on the output capacitance Coss of the switching element Q5, causing the body diode to conduct, as shown in FIG. 9A. When the body diode of the switching element Q5 becomes conductive, the control circuit 20 turns on the switching element Q5 using the control signal G5, as shown in FIG. 8A. When the switching element Q5 is turned on, the switching element Q5 is in a ZVS state.

[0030] Next, when the regenerative current ILo of the sub-inductor Lo decreases and becomes smaller than the regenerative current IL of the inductor L, the regenerative current IL of the inductor L discharges the charge of the output capacitance Coss of the switching element Q3, causing the body diode to conduct, as shown in FIG. 9B. At the timing when the body diode of the switching element Q3 conducts, the control circuit 20 turns on the switching elements Q1 and Q3 using the control signals G1 and G3, as shown in FIG. 8A. Turning on the switching element Q3 results in ZVS. Turning on the switching element Q1 does not result in ZVS (non-ZVS) because the regenerative currents ILo and IL do not flow. The dead time DT2 is determined by the timing when the switching elements Q1 and Q3 turn on.

[0031] During the dead time DT1, the regenerative current ILo from the sub-inductor Lo discharges the charge on the output capacitance Coss of the switching element Q6, causing the body diode to conduct, as shown in FIG. 10(a). When the body diode of the switching element Q6 becomes conductive, the control circuit 20 turns on the switching element Q6 using a control signal G6, as shown in FIG. 8(b). When the switching element Q6 is turned on, the switching element Q6 is in a ZVS state.

[0032] Furthermore, the regenerative current IL from the inductor L discharges the charge on the output capacitance Coss of the switching element Q4, causing the body diode to become conductive. When the body diode of the switching element Q4 becomes conductive, the control circuit 20 turns on the switching element Q4 using a control signal G4, as shown in FIG. 8(b). The turning on of the switching element Q4 results in ZVS. Note that the turning on of the switching elements Q4 and Q5 may be simultaneous, as shown in FIG. 8(b), or may occur at different times.

[0033] Next, when the regenerative current ILo of the sub-inductor Lo decreases and becomes smaller than the regenerative current IL of the inductor L, the regenerative current IL of the inductor L discharges the charge of the output capacitance Coss of the switching element Q2, causing the body diode to conduct, as shown in FIG. 10(b). At the timing when the body diode of the switching element Q2 conducts, the control circuit 20 turns on the switching element Q2 using the control signal G2, as shown in FIG. 8(b). The turn-on of the switching element Q2 is ZVS. The dead time DT1 is determined by the timing when the switching element Q2 turns on.

[0034] 11A shows the current paths when the switching elements Q1, Q3, and Q5 are turned on when the sub-inductor Lo is not inserted. Because a voltage is generated in the drain-source voltage Vds of the switching elements Q1, Q3, and Q5 when they are turned on, they are not in ZVS (non-ZVS). At this time, the switching elements Q1, Q3, and Q5 experience losses due to the charge of the output capacitance Coss being discharged internally, and losses due to the current flowing to charge the output capacitance Coss of the switching elements Q2, Q4, and Q6.

[0035] 11(b) shows the current paths when the switching elements Q2, Q4, and Q6 are turned on when the sub-inductor Lo is not inserted. Because a voltage is generated in the drain-source voltage Vds when the switching elements Q2 and Q6 are turned on, they are not in ZVS (non-ZVS). At this time, the switching elements Q2 and Q6 experience losses due to the charge on the output capacitance Coss being discharged internally, as well as losses due to the current flowing to charge the output capacitance Coss of the switching elements Q3 and Q5. Note that the turn-on of the switching element Q4 results in ZVS due to the regenerative current IL of the inductor L.

[0036] By inserting the sub-inductor Lo, the converter 10 can achieve ZVS turn-on of not only the switching element Q4 but also the switching elements Q2, Q3, Q5, and Q6, thereby reducing switching loss and noise generation.

[0037] The switching elements Q2, Q3, Q5, and Q6 may be turned on at a timing that is preset according to the characteristics of each element, or may be turned on by detecting the timing at which the body diode becomes conductive.

[0038] 12, in a converter 11 according to a second embodiment, a sub-inductor Lr2 is connected in series with a capacitor C2 instead of the sub-inductor Lo. Components similar to those in the first embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0039] Referring to FIGS. 13A and 13B, the sub-inductor Lr2 is inserted into the current path through which the capacitor current IC2 flows in both MODE1 and MODE2.

[0040] One of the purposes of the sub-inductor Lr2 is to suppress spike currents that occur when the switching elements Q2 to Q6 are turned on. Figure 14(a) is a simulation waveform diagram of the capacitor currents IC1 and IC2 when the sub-inductor Lr2 is not inserted. Figure 14(b) is a simulation waveform diagram of the capacitor currents IC1 and IC2 when the sub-inductor Lr2 is inserted.

[0041] 14B, it can be seen that the insertion of the sub-inductor Lr2 suppresses spike currents at the timing when the mode is switched. By suppressing spike currents, the converter 11 can reduce the conduction loss of the switching elements Q2 to Q6.

[0042] The sub-inductor Lr2 may have an inductance that is sufficiently smaller than that of the inductor L. For example, the sub-inductor Lr2 may use the inductance of a wiring pattern whose shape and length have been adjusted.

[0043] Because the sub-inductor Lr2 is inserted in the converter 11, a regenerative current ILr2 is generated in the sub-inductor Lr2 during the dead times DT1 and DT2, as shown by the arrows in Figures 15(a) and 15(b). Note that the regenerative current IL of the inductor L is omitted in Figure 15.

[0044] The regenerative current ILr2 shown in Figure 15(a) is generated during the dead time DT1 when the switching elements Q1, Q3, and Q5 are turned off. As shown in Figure 15(a), the regenerative current ILr2 forms a closed loop that passes through the body diodes of the switching elements Q2 and Q5. The currents that flow through the body diodes of the switching elements Q2 and Q5 become body diode currents IBD2 and IBD5 shown in Figure 16, which cause body diode loss and reduce efficiency.

[0045] The regenerative current ILr2 shown in FIG. 15(b) is generated during the dead time DT2 when the switching elements Q2, Q4, and Q6 are turned off. As shown in FIG. 15(b), the regenerative current ILr2 forms a closed loop that passes through the body diodes of the switching elements Q6 and Q3. The currents that flow through the body diodes of the switching elements Q6 and Q3 become body diode currents IBD6 and IBD3 shown in FIG. 16, which cause body diode loss and reduce efficiency.

[0046] 17, the control circuit 20a delays the turn-off of the switching element Q5 during the period when the regenerative current ILr2 flows in the dead time DT1, and also delays the turn-off of the switching element Q6 during the period when the regenerative current ILr2 flows in the dead time DT2.

[0047] By delaying the turn-off of switching element Q5 during dead time DT1, the regenerative current ILr2 flows through the body of switching element Q5, preventing the body diode current IBD5 from flowing, as shown in Figure 18(a). By delaying the turn-off of switching element Q6 during dead time DT2, the regenerative current ILr2 flows through the body of switching element Q6, preventing the body diode current IBD6 from flowing, as shown in Figure 18(b). In this way, the body diode current IBD5 does not flow during dead time DT1, and the body diode current IBD6 does not flow during dead time DT2, reducing body diode loss.

[0048] The control circuit 20a utilizes the regenerative current ILr2 of the sub-inductor Lr2 to optimize the dead times DT1 and DT2, thereby causing the switching elements Q2, Q3, Q5, and Q6 to operate in ZVS, thereby reducing switching loss and noise generation.

[0049] During the dead time DT2, the regenerative current ILr2 of the sub-inductor Lr2 discharges the charge on the output capacitance Coss of the switching element Q3, causing the body diode to become conductive, as shown in FIG. 20(a). When the body diode of the switching element Q3 becomes conductive, the control circuit 20a turns on the switching element Q3 using the control signal G3, as shown in FIG. 19(a). When the switching element Q3 is turned on, the switching element Q3 is in a ZVS state.

[0050] Next, when the direction of the regenerative current ILr2 through the sub-inductor Lr2 reverses, the regenerative current ILr2 discharges the charge on the output capacitance Coss of the switching element Q5, causing the body diode to conduct, as shown in FIG. 20(b). At the timing when the body diode of the switching element Q5 conducts, the control circuit 20a turns on the switching elements Q1 and Q5 using the control signals G1 and G5, as shown in FIG. 19(a). Turning on the switching element Q5 results in ZVS. Turning on the switching element Q1 does not result in ZVS (non-ZVS) because the regenerative currents ILr2 and IL do not flow. The dead time DT2 is determined by the timing when the switching elements Q1 and Q5 turn on.

[0051] During the dead time DT1, the regenerative current ILr2 from the sub-inductor Lr2 discharges the charge on the output capacitance Coss of the switching element Q2, causing the body diode to become conductive, as shown in Fig. 21(a). When the body diode of the switching element Q2 becomes conductive, the control circuit 20a turns on the switching element Q2 using a control signal G2, as shown in Fig. 19(b). When the switching element Q2 is turned on, the switching element Q2 is in a ZVS state.

[0052] Furthermore, the regenerative current IL from the inductor L discharges the charge on the output capacitance Coss of the switching element Q4, causing the body diode to become conductive. When the body diode of the switching element Q4 becomes conductive, the control circuit 20a turns on the switching element Q4 using a control signal G4, as shown in FIG. 19(b). The turning on of the switching element Q4 results in a ZVS. The turning on of the switching elements Q2 and Q4 may be simultaneous, as shown in FIG. 19(b), or may occur at different times.

[0053] Next, when the direction of the regenerative current ILr2 through the sub-inductor Lr2 reverses, the regenerative current ILr2 discharges the charge on the output capacitance Coss of the switching element Q6, causing the body diode to conduct, as shown in FIG. 21(b). When the body diode of the switching element Q6 becomes conductive, the control circuit 20a turns on the switching element Q6 using the control signal G6, as shown in FIG. 19(b). The turning-on of the switching element Q6 results in ZVS. The dead time DT1 is determined by the timing at which the switching element Q6 turns on.

[0054] By inserting the sub-inductor Lr2, the converter 11 can achieve ZVS turn-on of not only the switching element Q4 but also the switching elements Q2, Q3, Q5, and Q6, thereby reducing switching loss and noise generation.

[0055] The switching elements Q2, Q3, Q5, and Q6 may be turned on at a timing that is preset according to the characteristics of each element, or may be turned on by detecting the timing at which the body diode becomes conductive.

[0056] 22, a converter 12 according to a third embodiment includes a sub-inductor Lr1 connected in series with a capacitor C1 in addition to a sub-inductor Lr2. The same components as those in the second embodiment are denoted by the same reference numerals, and the description thereof will be omitted where appropriate.

[0057] Referring to FIGS. 23(a) and 23(b), the sub-inductor Lr1 is inserted into the current path through which the capacitor current IC1 flows in MODE1.

[0058] The sub-inductors Lr1 and Lr2 are provided for one purpose: to suppress spike currents that occur when the switching elements Q2 to Q6 are turned on. Figure 24(a) is a simulated waveform diagram of the capacitor currents IC1 and IC2 when the sub-inductors Lr1 and Lr2 are not inserted. Figure 24(b) is a simulated waveform diagram of the capacitor currents IC1 and IC2 when the sub-inductors Lr1 and Lr2 are inserted.

[0059] 24(b), it can be seen that the insertion of the sub-inductors Lr1 and Lr2 suppresses spike currents at the timing when the mode is switched. By suppressing spike currents, the converter 12 can reduce the conduction loss of the switching elements Q2 to Q6.

[0060] The sub-inductor Lr1 may have an inductance that is sufficiently smaller than that of the inductor L. For example, the sub-inductor Lr1 may use the inductance of a wiring pattern whose shape and length have been adjusted.

[0061] Since the converter 12 has the sub-inductors Lr1 and Lr2 inserted therein, regenerative currents ILr1 and ILr2 are generated in the sub-inductors Lr1 and Lr2 during the dead times DT1 and DT2, as shown by the arrows in Figures 25(a) and 25(b). Note that the regenerative current IL of the inductor L is omitted in Figure 25.

[0062] The regenerative currents ILr1 and ILr2 shown in Figure 25(a) are generated during dead time DT1 when switching elements Q1, Q3, and Q5 are turned off. As shown in Figure 25(a), the regenerative currents ILr1 and ILr2 form a closed loop that passes through the body diodes of switching elements Q2 and Q5. The currents that flow through the body diodes of switching elements Q2 and Q5 become body diode currents IBD2 and IBD5 shown in Figure 26, which cause body diode loss and reduce efficiency.

[0063] Regenerative currents ILr1 and ILr2 shown in FIG. 25(b) are generated during dead time DT2 when switching elements Q2, Q4, and Q6 are turned off. As shown in FIG. 25(b), regenerative current ILr1 forms a closed loop passing through the body diodes of switching elements Q1 and Q4. As shown in FIG. 25(b), regenerative current ILr2 forms a closed loop passing through the body diodes of switching elements Q6 and Q3. The currents flowing through the body diodes of switching elements Q1, Q3, Q4, and Q6 become body diode currents IBD1, IBD3, IBD4, and IBD6 shown in FIG. 26, which cause body diode loss and reduce efficiency.

[0064] 27, the control circuit 20b delays the turn-off of the switching element Q5 during the period when the regenerative currents ILr1 and ILr2 flow during the dead time DT1, and also delays the turn-off of the switching elements Q4 and Q6 during the period when the regenerative currents ILr1 and ILr2 flow during the dead time DT2.

[0065] By delaying the turn-off of switching element Q5 during dead time DT1, as shown in FIG. 28(a), regenerative currents ILr1 and ILr2 flow through the body of switching element Q5, preventing body diode current IBD5 from flowing. By delaying the turn-off of switching element Q4 during dead time DT2, as shown in FIG. 28(b), regenerative current ILr1 flows through the body of switching element Q4, preventing body diode current IBD4 from flowing. By delaying the turn-off of switching element Q6 during dead time DT2, as shown in FIG. 28(b), regenerative current ILr2 flows through the body of switching element Q6, preventing body diode current IBD6 from flowing. In this way, body diode current IBD5 does not flow during dead time DT1, and body diode currents IBD4 and IBD6 do not flow during dead time DT2, reducing body diode loss.

[0066] The control circuit 20b utilizes the regenerative current ILr1 of the sub-inductor Lr1 and the regenerative current ILr2 of the sub-inductor Lr2, and optimizes the dead times DT1 and DT2 to bring the switching elements Q1 to Q6 into ZVS, thereby reducing switching loss and noise generation.

[0067] During the dead time DT2, the regenerative current ILr2 of the sub-inductor Lr2 discharges the charge on the output capacitance Coss of the switching element Q3, causing the body diode to conduct, as shown in FIG. 30(a). The regenerative current ILr1 of the sub-inductor Lr1 discharges the charge on the output capacitance Coss of the switching element Q1, causing the body diode to conduct, as shown in FIG. 30(a). When the body diode of the switching element Q3 conducts, the control circuit 20b turns on the switching element Q3 using a control signal G3, as shown in FIG. 29(a). When the body diode of the switching element Q1 conducts, the control circuit 20b turns on the switching element Q1 using a control signal G1, as shown in FIG. 29(a). The switching elements Q1 and Q3 are turned on in a ZVS state. The switching elements Q1 and Q3 may be turned on simultaneously, as shown in FIG. 29(a), or at different times.

[0068] Next, when the direction of the regenerative current ILr2 through the sub-inductor Lr2 reverses, the regenerative current ILr2 discharges the charge on the output capacitance Coss of the switching element Q5, causing the body diode to conduct, as shown in FIG. 30(b). At the timing when the body diode of the switching element Q5 conducts, the control circuit 20b turns on the switching element Q5 using the control signal G5, as shown in FIG. 29(a). The turning on of the switching element Q5 results in ZVS. The dead time DT2 is determined by the timing when the switching element Q5 turns on.

[0069] During the dead time DT1, the regenerative current ILr2 from the sub-inductor Lr2 discharges the charge on the output capacitance Coss of the switching element Q2, causing the body diode to become conductive, as shown in FIG. 31(a). When the body diode of the switching element Q2 becomes conductive, the control circuit 20b turns on the switching element Q2 using a control signal G2, as shown in FIG. 29(b). When the switching element Q2 is turned on, the switching element Q2 is in a ZVS state.

[0070] Furthermore, the regenerative current IL from the inductor L discharges the charge on the output capacitance Coss of the switching element Q4, causing the body diode to become conductive. At the timing when the body diode of the switching element Q4 becomes conductive, the control circuit 20b turns on the switching element Q4 using a control signal G4, as shown in FIG. 29(b). The turning on of the switching element Q4 results in ZVS. Note that the turning on of the switching elements Q2 and Q4 may be simultaneous, as shown in FIG. 29(b), or may occur at different times.

[0071] Next, when the direction of the regenerative current ILr2 through the sub-inductor Lr2 reverses, the regenerative current ILr2 discharges the charge on the output capacitance Coss of the switching element Q6, causing the body diode to conduct, as shown in FIG. 31(b). At the timing when the body diode of the switching element Q6 conducts, the control circuit 20b turns on the switching element Q6 using the control signal G6, as shown in FIG. 29(b). The turning on of the switching element Q6 results in ZVS. The dead time DT1 is determined by the timing when the switching element Q6 turns on.

[0072] By inserting the sub-inductors Lr1 and Lr2, the converter 12 can achieve ZVS turn-on of not only the switching element Q4 but also the switching elements Q1, Q2, Q3, Q5, and Q6, thereby reducing switching loss and noise generation.

[0073] The switching elements Q1 to Q6 may be turned on at a timing that is preset according to the characteristics of each element, or may be turned on by detecting the timing at which the body diode becomes conductive.

[0074] In the converter 10 of the first embodiment, a sub-inductor Lo is inserted. In the converter 11 of the second embodiment, multiple sub-inductors Lr2 are inserted. In the converter 12 of the third embodiment, multiple sub-inductors Lr1, Lr2 are inserted. When multiple sub-inductors Lo, Lr1, and Lr2 are inserted in each combination of the sub-inductors Lo, Lr1, and Lr2, the same effects as in the first and second embodiments are obtained. Furthermore, when multiple sub-inductors Lo, Lr1 are inserted and when multiple sub-inductors Lo, Lr1, and Lr2 are inserted, the same effects as in the third embodiment are obtained.

[0075] Figure 32 compares losses with and without ZVS, using the turn-on of switching element Q2 as a representative example. Figure 33(a) shows simulated waveforms of drain-source voltage Vds, drain current Id, and loss Ploss = Vds × Id in the case of non-ZVS, which does not occur. It can be seen that losses occur when switching element Q2 is turned on when ZVS is not achieved. Figure 33(b) shows simulated waveforms of drain-source voltage Vds, drain current Id, and loss Ploss = Vds × Id in the case of ZVS. It shows that no losses occur when switching element Q2 is turned on in the case of ZVS.

[0076] As described above, this embodiment is a converter that includes an inductor L, multiple switching elements Q1 to Q6, and multiple capacitors C1, C2, and Co connected via the switching elements Q1 to Q6, and that forms a current path for an output current Io that passes through the capacitors C1, C2, and Co when the switching elements Q1 to Q6 are turned on (complementary turn-on of the switching elements Q1, Q3, and Q5 and the switching elements Q2, Q4, and Q6), and that includes sub-inductors Lo and Lr2 inserted in the current path. This configuration can suppress spike currents that are generated by connecting the capacitors Co, C1, and C2, which have a potential difference, and can therefore reduce conduction loss and noise generation in the switching elements Q1 to Q6.

[0077] Furthermore, in this embodiment, multiple current paths are provided, and the sub-inductors Lo and Lr2 are inserted at locations where two or more of the multiple current paths pass through. With this configuration, the single sub-inductor Lo or Lr2 can suppress spike currents in each of the two current paths.

[0078] Furthermore, in this embodiment, switching elements Q5 and Q6, which are disposed in the current path and allow the output current to flow when on, and are disposed at locations where the regenerative current of sub-inductors Lo and Lr2 flows through the body diodes, delay their turn-off. This configuration prevents the regenerative currents ILo and ILr2 from flowing as body diode currents IBD5 and IBD6, thereby reducing body diode loss.

[0079] Furthermore, in this embodiment, the regenerative currents ILo and ILr2 of the sub-inductors Lo and Lr2 are used to perform zero-voltage switching (ZVS) on the switching elements Q2, Q3, Q5, and Q6. This configuration enables ZVS on the switching elements Q2, Q3, Q5, and Q6, thereby reducing switching loss and noise generation.

[0080] Furthermore, in this embodiment, the switching elements Q1 to Q6 include a switching element Q1 (first switch), a switching element Q2 (second switch), a switching element Q3 (third switch), a switching element Q4 (fourth switch), a switching element Q5 (fifth switch), and a switching element Q6 (sixth switch), and the capacitors C1, C2, and Co include a capacitor C1 (first capacitor), a capacitor C2 (second capacitor), and a capacitor Co (third capacitor), and the switching elements Q1, Q2, and Q3 are connected to an input terminal as a series circuit. A series circuit consisting of capacitor C1 and switching element Q4 is connected between the connection point between switching element Q1 and switching element Q2 and ground, a series circuit consisting of capacitor C2 and switching element Q5 is connected between the connection point between switching element Q2 and switching element Q3 and ground, switching element Q6 is connected between the connection point between capacitor C2 and switching element Q5 and the output terminal, inductor L is connected between the connection point between capacitor C1 and switching element Q4 and the output terminal, and capacitor Co is connected between the output terminal and ground. This configuration in the constant dual path hybrid converter can suppress spike currents generated by connections between capacitors Co, C1, and C2 that have a potential difference, thereby reducing conduction loss and noise generation in switching elements Q2 to Q6.

[0081] Furthermore, in this embodiment, the sub-inductors Lo and Lr2 are inserted into the current path through which the output current Io flows as the capacitor current IC2 (second capacitor current) of the second capacitor. With this configuration, the single sub-inductor Lo or Lr2 can constantly suppress spike currents in the two current paths of the dual path hybrid converter.

[0082] Furthermore, in this embodiment, the dual path hybrid converter includes a sub-inductor Lr1 as the first sub-inductor and a sub-inductor Lo or Lr2 as the second sub-inductor, the first sub-inductor is inserted in a current path through which the output current Io flows as a first capacitor current (capacitor current IC1) of the first capacitor, and the second sub-inductor is inserted in a current path through which the output current Io flows as a second capacitor current (capacitor current IC2) of the second capacitor, and zero-voltage switching is performed on switching elements Q1, Q2, Q3, Q5, and Q6 using regenerative currents ILr1 and ILr2 of the first sub-inductor and second sub-inductor, respectively. With this configuration, the single sub-inductor Lo or Lr2 can constantly suppress spike currents in each of the two current paths of the dual path hybrid converter, and ZVS can be achieved for all of switching elements Q1 to Q6, thereby reducing switching loss and noise generation.

[0083] It is clear that the present invention is not limited to the above-described embodiments, and that each embodiment can be appropriately modified within the scope of the technical concept of the present invention. Furthermore, the number, position, shape, etc. of the above-described components are not limited to the above-described embodiments, and the number, position, shape, etc. can be set to be suitable for implementing the present invention. Note that the same components are denoted by the same reference numerals in each drawing.

[0084] 1, 10, 10a, 11, 12 Converter 20, 20a, 20b Control circuit C1, C2, Co Capacitor DT1, DT2 Dead time IBD1, IBD2, IBD3, IBD4, IBD5, IBD6 Body diode current IC1, IC2 Capacitor current IL, ILo, ILr1, ILr2 Regenerative current Id Drain current Io Output current L Inductor Lo, Lr1, Lr2 Sub-inductor Q1, Q2, Q3, Q4, Q5, Q6 Switching element Vin Input voltage Vo Output voltage

Claims

1. A converter comprising an inductor, a plurality of switching elements, and a plurality of capacitors connected via the switching elements, wherein a current path of an output current passing through the capacitor is formed by turning on the switching element, and the converter is characterized in that it comprises a sub-inductor inserted into the current path.

2. The converter according to claim 1, comprising a plurality of the current paths, wherein the sub-inductor is inserted at a location through which two or more of the plurality of the current paths pass.

3. The switching element disposed in the current path, flowing the output current in the on state, and disposed at a location where the regenerative current of the sub-inductor flows through the body diode, the converter according to claim 1 or 2, characterized in that it delays the turn-off.

4. The converter according to claim 1 or 2, characterized in that the switching element is zero-voltage switched using the regenerative current of the sub-inductor.

5. The converter according to claim 1 or 2, comprising a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a sixth switch as the plurality of the switching elements, and a first capacitor, a second capacitor, and a third capacitor as the plurality of the capacitors, respectively, wherein the first switch, the second switch, and the third switch are connected between an input terminal and an output terminal as a series circuit, a series circuit composed of the first capacitor and the fourth switch is connected between a connection point between the first switch and the second switch and ground, a series circuit composed of the second capacitor and the fifth switch is connected between a connection point between the second switch and the third switch and the ground, the sixth switch is connected between a connection point between the second capacitor and the fifth switch and the output terminal, the inductor is connected between a connection point between the first capacitor and the fourth switch and the output terminal, and the third capacitor is connected between the output terminal and the ground, respectively.

6. The converter according to claim 5, wherein the sub-inductor is inserted into the current path through which the output current flows as the second capacitor current of the second capacitor.

7. The sub-inductor includes a first sub-inductor and a second sub-inductor. The first sub-inductor is inserted into the current path through which the output current flows as the first capacitor current of the first capacitor. The second sub-inductor is inserted into the current path through which the output current flows as the second capacitor current of the second capacitor. The converter according to claim 5, wherein zero-voltage switching of the first switch, the second switch, the third switch, the fifth switch, and the sixth switch is performed by using the respective regenerative currents of the first sub-inductor and the second sub-inductor.

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