Semiconductor device

Abstract

Provided is a semiconductor device capable of increasing the electrostatic capacitance of a capacitance part while suppressing an increase in mounting area. The semiconductor device comprises: a semiconductor substrate having a lower surface, an upper surface disposed at a distance from the lower surface in the height direction, and a lateral surface connecting the upper surface and the lower surface; and a capacitance part disposed on the lateral surface side of the semiconductor substrate. The lower surface is the surface facing a mounting surface on which the semiconductor device is mounted. The capacitance part has a laminate structure that at least includes: a first dielectric layer disposed along the lateral surface; and a first conductive layer and a second conductive layer that face each other across the first dielectric layer. The semiconductor substrate has at least one trench part that has an opening in the lateral surface. At least a portion of the capacitance part is positioned in said at least one trench part.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] As an example of a semiconductor device having a capacitance portion, Patent Document 1 describes a semiconductor device in which a capacitance portion including a dielectric film and a conductor film is provided on a main surface of a semiconductor substrate.

[0003] International Publication No. 2019 / 208226

[0004] The semiconductor device described above can be mounted on, for example, a printed circuit board. However, the semiconductor device of Patent Document 1 has room for improvement in terms of further increasing the capacitance (capacitor capacitance) while suppressing an increase in the area (mounting area) required for mounting the semiconductor device.

[0005] SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above problems by providing a semiconductor device that can increase the capacitance of the capacitance section while suppressing an increase in the mounting area.

[0006] A semiconductor device according to one embodiment of the present invention comprises: a semiconductor substrate having a lower surface, an upper surface arranged at a distance from the lower surface in the vertical direction, and a side surface connecting the upper surface and the lower surface; and a capacitance portion arranged on the side surface of the semiconductor substrate, wherein the lower surface is a surface facing a mounting surface on which the semiconductor device is mounted, the capacitance portion has a layered structure including at least a first dielectric layer arranged along the side surface, and a first conductive layer and a second conductive layer facing each other with the first dielectric layer sandwiched therebetween, the semiconductor substrate has at least one trench portion having an opening on the side surface, and at least a portion of the capacitance portion is located inside the at least one trench portion.

[0007] According to the semiconductor device of the present invention, the capacitance of the capacitance section can be increased while suppressing an increase in the mounting area.

[0008] 1 is a schematic perspective view showing a semiconductor device of a first embodiment. FIG. 1 is a schematic cross-sectional view taken along line II-II of the semiconductor device of FIG. 1. FIG. 2 is a schematic view illustrating a circuit configuration of the semiconductor device of FIG. 1. FIG. 3 is a schematic cross-sectional view taken along line IX-IX of the semiconductor device of FIG. 8. FIG. 4 is a schematic cross-sectional view taken along line IX-IX of the semiconductor device of FIG. 9. FIG. 5 is a schematic cross-sectional view taken along line IX-IX of the semiconductor device of FIG. 10. 12 is a schematic diagram illustrating the circuit configuration of the semiconductor device of FIG. 8. A schematic top view showing a semiconductor device of Modification 1. A schematic cross-sectional view taken along line XII-XII of the semiconductor device of FIG. 11. A schematic top view showing a semiconductor device of Modification 2, which is a schematic diagram illustrating the circuit configuration of the semiconductor device of FIG. 11. A schematic cross-sectional view taken along line XV-XV of the semiconductor device of FIG. 14. A schematic cross-sectional view taken along line XVI-XVI of the semiconductor device shown in FIG. 15. A schematic cross-sectional view showing a wiring layer of a semiconductor device of Modification 3. A schematic perspective view showing a semiconductor device of a third embodiment, which is a schematic cross-sectional view taken along line XVIII-XVIII of the semiconductor device of FIG. 17. A schematic cross-sectional view showing a circuit board of a fourth embodiment. A schematic cross-sectional view showing another circuit board of the fourth embodiment.

[0009] (Findings on which the present invention is based) The present inventors have made extensive studies to increase the capacitance of a capacitor while suppressing an increase in the mounting area, and have found the following.

[0010] Conventional semiconductor devices have a capacitance section (e.g., a trench capacitor section) on the main surface of a semiconductor substrate, and are configured so that the back surface (the surface opposite the main surface) of the semiconductor substrate is mounted on a mounting substrate. With such a configuration, it can be difficult to mount a semiconductor device with a large capacitance within a limited mounting area. For example, increasing the area of ​​the main surface of the semiconductor substrate on which the capacitance section is formed in order to increase the capacitance of the capacitor increases the chip area and the mounting area. On the other hand, it is possible to increase the effective area of ​​the capacitance section while maintaining the mounting area by arranging trenches more densely or by deepening each trench. However, there are limitations to such trench processing. For example, even if the semiconductor substrate is thickened (i.e., the chip thickness is increased), it may be difficult to form a trench deep enough to accommodate the increased thickness. The term "mounting area" refers to the area required to mount a semiconductor device on a mounting substrate, e.g., the area in a plane (XY plane) perpendicular to the thickness (height) of the semiconductor device.

[0011] Therefore, the inventors have conducted extensive research and found that by providing a trench portion and a capacitance portion on the side surface of the semiconductor substrate, it is possible to increase the capacitance of the capacitor while suppressing an increase in the mounting area. Based on this novel finding, the inventors have arrived at the following invention.

[0012] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that the present disclosure is not limited to these embodiments. For reference, the drawings may schematically show mutually orthogonal X-, Y-, and Z-axes. Furthermore, substantially identical components in the drawings are given the same reference numerals, and redundant explanations are omitted as appropriate. For illustrative purposes, the dimensions of each element in the drawings may be exaggerated and are not necessarily drawn to scale.

[0013] In addition, for the sake of convenience, the following uses terms indicating directions such as "upper," "lower," and "side," assuming a state during normal use, but this does not mean to limit the state of use of the semiconductor device according to the present disclosure.

[0014] First Embodiment Fig. 1 is a schematic perspective view showing a first embodiment of a semiconductor device. Fig. 2 is a schematic cross-sectional view of the semiconductor device taken along line II-II of Fig. 1. Fig. 3 is a schematic diagram showing an example of the circuit configuration of the semiconductor device of Fig. 1.

[0015] 1, the semiconductor device 100 has, for example, a substantially rectangular parallelepiped shape. In this example, for ease of understanding, the width, depth, and height of the rectangular parallelepiped semiconductor device 100 are shown as being parallel to the X-axis, Y-axis, and Z-axis, respectively. The semiconductor device 100 is mounted so that the bottom surface of the semiconductor device 100 faces the mounting surface of a mounting board. The Z-axis corresponds to the height direction (thickness direction) of the semiconductor device in the mounted state, and is, for example, perpendicular to the mounting surface.

[0016] There is no particular limitation on the size of the semiconductor device 100. For example, the height (thickness) h of the semiconductor device 100 is 1.0 mm, and the width wx in the X direction and the width wy in the Y direction are each 0.5 mm. The mounting area is, for example, 0.5 mm x 0.5 mm.

[0017] As shown in FIGS. 1 and 2, the semiconductor device 100 includes a semiconductor substrate 10 , a capacitor 30 , electrode layers 51 and 52 , and an insulating layer 41 .

[0018] The semiconductor substrate 10 has, for example, a substantially rectangular parallelepiped shape. The semiconductor substrate 10 has a bottom surface 11, a top surface 12 disposed at a distance from the bottom surface 11 in the Z direction (height direction), and side surfaces connecting the bottom surface 11 and the top surface 12. The bottom surface 11 is disposed so as to face the mounting surface. The side surfaces of the semiconductor substrate 10 include a first surface s1 and a second surface s2 disposed at a distance in a direction intersecting the first surface s1 (here, the X direction).

[0019] The semiconductor substrate 10 is, for example, a Si substrate. In this embodiment, a Si substrate having a conductive low-resistance portion 14 is used as the semiconductor substrate 10. The low-resistance portion 14 is a semiconductor portion made of a low-resistance semiconductor (e.g., n-type Si, p-type Si, etc.).

[0020] The semiconductor substrate 10 has trenches 16 each having an opening on a side surface (here, the first surface s1). The trenches 16 are, for example, holes with bottoms. In this embodiment, the openings of the trenches 16 are spaced apart from one another on the first surface s1.

[0021] The depth direction of the trench portion 16 (the direction from the opening of the trench portion 16 toward the bottom surface of the trench portion 16) is, for example, parallel to the mounting surface (here, the XY plane). In the example shown in FIG. 2, the depth direction of the trench portion 16 is parallel to the normal direction (X direction) of the first surface s1. "Parallel" means that the trench portion 16 is configured to be roughly parallel, and misalignment due to processes such as trench processing may occur. As an example, the depth along the X direction from the opening of the trench portion 16 to the bottom surface is, for example, 30 μm. Note that in FIG. 2, the cross-sectional shape of the trench portion 16 along the depth direction is a rectangle that is long in the X direction, but it may also be a triangle or trapezoid whose trench width gradually decreases toward the bottom surface. Also, although FIG. 2 shows multiple trench portions 16 formed on the first surface s1, it is sufficient that at least one trench portion 16 is formed.

[0022] The capacitance section 30 is disposed on the side surface (here, the first surface s1 side) of the semiconductor substrate 10. The capacitance section 30 has a laminated structure including at least a dielectric layer d1 disposed along the side surface, and a conductive layer m1 and a conductive layer m2 opposed to each other across the dielectric layer d1 in the thickness direction of the dielectric layer d1.

[0023] In this embodiment, the capacitor 30 includes a conductive layer m1, a dielectric layer d1, a conductive layer m2, a dielectric layer d2, and a conductive layer m3 stacked in this order. The dielectric layer d1 and the two conductive layers m1 and m2 sandwiching the dielectric layer d1 form a first capacitor Ca1. The dielectric layer d2 and the two conductive layers m2 and m3 sandwiching the dielectric layer d2 form a second capacitor Ca2.

[0024] There is no particular limitation on the number of layers in the layered structure of the capacitance section 30. The layered structure of the capacitance section 30 may include one or more sets (two sets in FIG. 2 ) of capacitance formation structures each consisting of a conductive layer-dielectric layer-conductive layer. The capacitance section 30 may have a structure in which, for example, one or more sets of dielectric layers and conductive layers are alternately stacked on the conductive layer m1.

[0025] The dielectric layers d1 and d2 are made of an insulating material, such as SiO ２ membrane, HfO ２ The dielectric layers d1 and d2 may be, for example, a TiN film (thickness: for example, 20 nm) or an AlO film. The thickness of the dielectric layers d1 and d2 is, for example, 10 nm. The conductive layers m2 and m3 include a conductor. The conductive layers m2 and m3 may be, for example, a TiN film (thickness: for example, 20 nm) or a polysilicon film (thickness: for example, 1000 nm).

[0026] 2, the conductive layer m1 is formed of the low-resistance portion 14 of the semiconductor substrate 10. Note that, in cases where the semiconductor substrate 10 does not have a low-resistance portion exposed on the inner surface of the trench portion 16, the conductive layer m1 may also be a conductive film separately formed on the first surface s1, similar to the conductive layers m2 and m3.

[0027] At least a portion of the capacitance portion 30 is located inside the trench portion 16. This increases the effective area of ​​the capacitance portion 30. In this embodiment, the capacitance portion 30 is formed along the first surface s1 including the trench portion 16, and extends into the trench portion 16 and a portion of the first surface s1 located around the trench portion 16.

[0028] The electrode layers 51 and 52 include a conductor. The electrode layers 51 and 52 are metal layers such as Al or Cu. The electrode layers 51 and 52 are electrically connected to the capacitance section 30. In this embodiment, the electrode layer 51 is electrically connected to the conductive layers m1 and m3. That is, the electrode layer 51 also functions as a connection electrode that electrically connects the multiple conductive layers m1 and m3 that make up the capacitance section 30. The electrode layer 52 is electrically connected to the conductive layer m2. By connecting in this manner, the first capacitance Ca1 and the second capacitance Ca2 can be connected in parallel, as shown in FIG. 3 .

[0029] 2 , the electrode layer 51 extends from the first surface s1 side to the lower surface 11 side of the semiconductor substrate 10. The electrode layer 52 extends from the first surface s1 side to the upper surface 12 side of the semiconductor substrate 10. The electrode layers 51 and 52 may extend in a generally L-shape from above the first surface s1 to above the lower surface 11 or above the upper surface 12 in a side view seen from the Y direction.

[0030] The electrode layers 51 and 52 may include portions that are exposed on the surface of the semiconductor device 100 and function as external terminals. In this example, the portion of the electrode layer 51 that forms the lower surface of the semiconductor device 100 and the portion of the electrode layer 52 that forms the upper surface of the semiconductor device 100 can each function as an external terminal.

[0031] The insulating layer 41 is made of an insulating material and is disposed so as to cover at least a portion of the capacitance section 30. In this embodiment, the insulating layer 41 is disposed between the low-resistance section 14 of the semiconductor substrate 10 and the capacitance section 30 and the electrode layers 51 and 52.

[0032] The insulating layer 41 includes, for example, a side portion on the first surface s1 side of the semiconductor substrate 10 that is arranged to cover the capacitive portion 30, a lower portion on the lower surface 11 side that is arranged to cover the low-resistance portion 14, and an upper portion on the upper surface 12 side that is arranged to cover the low-resistance portion 14. The insulating layer 41 (here, the side portion of the insulating layer 41) has a first opening 411 that exposes a portion of the low-resistance portion 14, which is the conductive layer m1, a second opening 412 that exposes a portion of the conductive layer m3, and a third opening 413 that exposes a portion of the conductive layer m2. The electrode layer 51 is formed on the insulating layer 41, in the first opening 411, and in the second opening 412. The electrode layer 51 is electrically connected to the conductive layer m1 in the first opening 411 (first connection portion 511) and electrically connected to the conductive layer m3 in the second opening 412 (second connection portion 512). The electrode layer 52 is formed on the insulating layer 41 and in the third opening 413, and is electrically connected to the conductive layer m2 in the third opening 413 (third connection portion 521).

[0033] <Method for manufacturing semiconductor device> Next, an example of a method for manufacturing the semiconductor device 100 will be described. Figures 4A to 4G are schematic cross-sectional views illustrating the steps of the method for manufacturing the semiconductor device. Figure 4H is a schematic cross-sectional view illustrating the steps of the method for manufacturing the semiconductor device in Figure 1 after mounting.

[0034] 4A, a conductive semiconductor substrate (here, a conductive Si substrate) configured with a low resistance portion 14 is prepared as the semiconductor substrate 1. The conductive Si substrate is, for example, a Si substrate doped with an impurity that imparts n-type or p-type conductivity.

[0035] (Formation of Trench Portion) Next, as shown in FIG. 4B , a trench portion 16 is formed in the main surface 1a of the semiconductor substrate 1. The main surface 1a is a surface corresponding to the first surface s1 of the semiconductor base 10 shown in FIG. 1 . Here, a hard mask is formed on the main surface 1a, and the hard mask is patterned. Next, deep silicon etching (Bosch process) is performed using the hard mask as an etching mask. Thereafter, the hard mask is removed from the main surface 1a. The method for forming the trench portion 16 is not particularly limited to the above method.

[0036] 5A to 5C are plan views illustrating the main surface 1a of a semiconductor substrate 1 on which trench portions 16 are formed. As shown in the figures, the openings of the multiple trench portions 16 are spaced apart from one another on the main surface 1a. The trench portions 16 are arranged regularly or randomly on the main surface 1a. The shape of the openings of each trench portion 16 is not particularly limited. The opening shape may be, for example, a circle as illustrated in FIG. 5A, a polygon such as a hexagon as illustrated in FIG. 5B, or a tetrapod shape as illustrated in FIG. 5C. Alternatively, although not illustrated, groove-shaped trench portions extending in one direction may be arranged on the main surface 1a. The total internal surface area of ​​the trench portions 16 can be increased by adjusting the number, planar shape, depth, etc. of the trench portions 16.

[0037] (Formation of Capacitor Portion) Next, as shown in FIG. 4C , a stacked structure is formed by alternately depositing dielectric layers and conductive layers on the main surface 1 a (including the inside of the trench portion 16). Here, a dielectric layer d1, a conductive layer m2, a dielectric layer d2, and a conductive layer m3 are deposited in this order. As an example, the dielectric layers d1 and d2 may be formed by a chemical vapor deposition (CVD) method. The conductive layers m2 and m3 may be formed by a sputtering method. Alternatively, polysilicon films may be formed as the conductive layers m2 and m3. In this case, after the polysilicon film is deposited, the polysilicon film may be doped with impurities that impart conductivity to reduce the resistance of the polysilicon film.

[0038] Next, as shown in FIG. 4D , each conductive layer and each dielectric layer is etched in order from the top layer. Here, the conductive layer m3 is etched using photolithography. After this, the dielectric layer d2, the conductive layer m2, and the dielectric layer d1 are etched using photolithography, respectively. An opening p1 is formed in the dielectric layer d2 to expose a portion of the underlying conductive layer m2. Furthermore, the dielectric layer d1 is removed to expose a portion of the low resistance portion 14. In this manner, the capacitance portion 30 is formed.

[0039] (Dicing of Semiconductor Substrate) Next, as shown in FIG. 4E , the back surface of the semiconductor substrate 1 is ground and diced (divided into pieces). This results in a semiconductor base material 10 of a predetermined size. In this embodiment, the ground surface s2 of the semiconductor substrate 1 becomes the second surface of the semiconductor base material 10. Furthermore, cut surfaces 11 and 12 formed by dicing the semiconductor substrate 1 in the thickness direction become the lower surface 11 and upper surface 12 of the semiconductor base material 10, respectively.

[0040] 4F , an insulating layer 41 is formed by depositing an insulating material on the first surface s1 of the semiconductor substrate 10 on which the capacitance portion 30 is formed and on the surfaces 11 and 12, which are the cut surfaces, using, for example, a spray deposition method. Then, using, for example, photolithography, patterning (e.g., dry etching) is performed on the side portions of the insulating layer 41 located on the first surface s1. This forms a first opening 411 exposing the low-resistance portion 14 of the semiconductor substrate 10, a second opening 412 exposing a portion of the conductive layer m3, and a third opening 413 exposing a portion of the conductive layer m2 in the insulating layer 41.

[0041] (Formation of Electrode Layers) Next, as shown in FIG. 4G , electrode layers 51 and 52 are formed. Here, first, an electrode conductive film is formed on insulating layer 41 and in first to third openings 411 to 413. Next, the electrode conductive film is patterned (etched) using, for example, photolithography. As a result, an electrode layer 51 that contacts low resistance portion 14 in first opening 411 and contacts conductive layer m3 in second opening 412, and an electrode layer 52 that contacts conductive layer m2 in third opening 413 are formed from the electrode conductive film. In this manner, semiconductor device 100 is manufactured.

[0042] The method and order of forming each layer in the semiconductor device 100 are not limited to the above example. For example, when an insulating layer and an electrode layer are formed only on the main surface of the semiconductor substrate, the semiconductor substrate may be diced after the electrode layer is formed.

[0043] When mounting the semiconductor device 100 on a mounting substrate, as shown in FIG. 4H , the semiconductor device 100 is mounted on the mounting substrate 110 so that the bottom surface 11 of the semiconductor substrate 10 faces the mounting surface 110s. The semiconductor device 100 may be disposed between two mounting substrates. In this case, the bottom surface 11 and the top surface 12 of the semiconductor substrate 10 are disposed so as to face the mounting surfaces of the corresponding mounting substrates (see FIG. 21 ).

[0044] <Effects> The semiconductor device 100 of this embodiment includes a semiconductor substrate 10 having a bottom surface 11 disposed opposite a mounting surface, a top surface 12 disposed at a distance from the bottom surface 11 in the height direction, and a side surface connecting the top surface and the bottom surface, and a capacitance section 30 disposed on the side surface of the semiconductor substrate 10. The capacitance section 30 has a layered structure including at least a first dielectric layer d1 disposed along the side surface, and a first conductive layer m1 and a second conductive layer m2 facing each other with the first dielectric layer d1 sandwiched therebetween. At least a portion of the capacitance section 30 is located inside a trench portion 16 formed in the side surface of the semiconductor substrate 10.

[0045] According to the above configuration, the capacitance section 30 is disposed on the side surface of the semiconductor substrate 10, and therefore the area of ​​the capacitance section 30 can be increased by increasing the height from the lower surface 11 to the upper surface 12 of the semiconductor substrate 10 (i.e., the height of the side surface). Therefore, the capacitance of the capacitance section 30 can be increased while suppressing an increase in the area of ​​the lower surface 11, which is the mounting area. In this specification, the "area of ​​the capacitance section" refers to the area of ​​the capacitance section when viewed from the normal direction (here, the X direction) of the surface on which the capacitance section is formed.

[0046] Furthermore, with the above-described configuration, the height of the semiconductor substrate 10 can be set with a high degree of freedom. Therefore, the height (chip thickness) of the semiconductor device 100 from the mounting surface can be set depending on the intended use of the semiconductor device 100. For example, when the semiconductor device 100 is embedded in a circuit board, setting the chip thickness to be approximately the same as the thickness of the core material makes it easier to mount the semiconductor device 100 on the circuit board (see FIG. 20 ). Furthermore, by making the chip thickness larger than conventionally, the semiconductor device 100 can be used as a bridge for interconnecting substrates (see FIG. 21 ).

[0047] In conventional semiconductor devices, a trench portion and a capacitor portion are provided on the upper surface of a semiconductor substrate. Therefore, depending on the area of ​​the capacitor portion (trench formation surface), the maximum width of the semiconductor substrate may be greater than the height of the semiconductor substrate. Furthermore, the height (thickness) from the mounting surface to the upper surface of the semiconductor substrate is often limited by the thickness of the Si substrate used to cut out the semiconductor substrate and the depth of the trench, and is therefore often approximately 0.725 μm or less.

[0048] In contrast, according to this embodiment, the height from the lower surface 11 to the upper surface 12 of the semiconductor substrate 10 (height in the Z direction) can be set with a high degree of freedom, for example, by changing the dicing width of the semiconductor substrate. Therefore, the height of the semiconductor substrate 10 can be set to be greater than 0.725 μm, for example, 1.0 μm or greater. Furthermore, by making the height of the semiconductor substrate 10 greater than the maximum width of the lower surface 11 of the semiconductor substrate 10, it is also possible to provide a pillar-shaped semiconductor device 100 that is long in the Z direction. Therefore, the capacitor capacitance can be further increased while keeping the mounting area small.

[0049] In the semiconductor device 100 of this embodiment, the depth direction from the opening of the trench portion 16 is parallel to the mounting surface. This configuration allows multiple trench portions 13 to be arranged more densely in the Z direction on the side surface of the semiconductor substrate 10. This allows the capacitor capacitance to be further increased while keeping the mounting area small.

[0050] The semiconductor device 100 of this embodiment further includes a pair of external terminals electrically connected to the capacitance section 30. One of the pair of external terminals (e.g., electrode layer 51) is located on the lower surface 11 of the semiconductor substrate 10, and the other of the pair of external terminals (e.g., electrode layer 52) is located on the upper surface 12 of the semiconductor substrate 10. With this configuration, since the external terminals are located on the lower surface 11 of the semiconductor substrate 10, the semiconductor device 100 can be easily mounted on a mounting substrate with the lower surface 11 of the semiconductor substrate 10 facing the mounting surface. Furthermore, since the external terminals are located on both the lower surface 11 and the upper surface 12 of the semiconductor substrate 10, it is easy to embed the semiconductor device 100 in a circuit board or to mount the semiconductor device 100 on two mounting substrates arranged above and below the semiconductor device 100.

[0051] 2, the portions of the electrode layers 51 and 52 exposed on the bottom and top surfaces of the semiconductor device 100 function as external terminals. The external terminals may be external electrodes separately provided on the electrode layers. Alternatively, portions of the low-resistance portions of the semiconductor substrate may be exposed on the surface of the semiconductor device 100 and used as external terminals.

[0052] In the semiconductor device 100 of this embodiment, one or both of the pair of electrode layers 51, 52 electrically connected to the capacitance section 30 extend from the side surface (first surface s1 side) of the semiconductor substrate 10 to the bottom surface 11 or top surface 12. By extending the electrode layers 51, 52 from above the first surface s1 to the bottom surface 11 and / or top surface 12, the semiconductor device 100 can be easily mounted on a mounting substrate. In particular, the semiconductor device 100 can be easily mounted inside (embedded in) a circuit board or between two mounting substrates.

[0053] The semiconductor device 100 of this embodiment includes an electrode layer 51 electrically connected to the plurality of conductive layers m1, m3 in the capacitance section 30. With this configuration, the plurality of capacitances Ca1, Ca2 included in the capacitance section 30 can be connected in parallel, thereby further increasing the capacitor capacitance.

[0054] In the semiconductor device 100 of this embodiment, the thickness of the conductive layers m1 to m3, which serve as capacitance electrodes, is, for example, at least twice the thickness of the dielectric layers d1 and d2. With this configuration, the capacitance of the capacitor can be increased by thinning the dielectric layers d1 and d2. Furthermore, by thickening the conductive layers m1 to m3, power loss (e.g., copper loss) due to the resistance component of the conductor can be suppressed, thereby achieving a capacitance section 30 with a high Q value.

[0055] In conventional semiconductor devices, increasing the thickness of each conductive layer of the capacitance section increases the area required to form the capacitance section, which can result in increased chip area and mounting area. For this reason, the thickness of the conductive layer is kept at the same level as the thickness of the dielectric layer, for example. In contrast, in this embodiment, the semiconductor substrate 10 is made taller, thereby increasing the area available for forming the capacitance section 30. Therefore, the conductive layers m1 to m3 that make up the capacitance section 30 can be formed to the desired thickness.

[0056] In the semiconductor device 100 of this embodiment, a substrate having a conductive low-resistance portion 14 made of a low-resistance semiconductor is used as the semiconductor substrate 10. With this configuration, the low-resistance portion 14 can be used as a capacitive electrode (here, the conductive layer m1) of the capacitive portion 30. Therefore, the layered structure of the capacitive portion 30 can be made thinner, and the semiconductor device 100 can be made smaller. In addition, the number of film formation steps required to form the capacitive portion 30 can be reduced.

[0057] Furthermore, the low-resistance portion 14 can be exposed on the surface of the semiconductor device 100 and used as an external terminal for electrically connecting the semiconductor device 100 to the outside (see FIG. 20 ). The low-resistance portion 14 can also be used for electrical connection between the conductive layers m1 and m3 that make up the capacitance portion 30, electrical connection between two capacitance portions formed on different surfaces (see FIG. 9 ), or electrical connection between multiple capacitor portions spaced apart (see FIG. 19 ). The use of the low-resistance portion 14 makes it possible to omit the electrode layer (or external electrode) for the above-described connections, thereby enabling the semiconductor device 100 to be made smaller and less expensive.

[0058] The configuration of the semiconductor device of this embodiment is not limited to the configuration shown in FIGS. 1 to 3 . The semiconductor substrate is not limited to a low-resistance substrate, and may be a high-resistance substrate that does not include a low-resistance portion. Alternatively, the semiconductor substrate may have a low-resistance portion and an insulating high-resistance portion that has a higher electrical resistance than the low-resistance portion. The capacitance portion may be disposed on the side surface of the semiconductor substrate. For example, when a rectangular parallelepiped semiconductor substrate is used, the trench portion and capacitance portion may be disposed on one or more of the four surfaces that make up the side surface.

[0059] 3, the two capacitors Ca1 and Ca2 are connected in parallel, but they may also be connected in series. The electrode structure, the structure and position of the connection between the capacitor and the electrode layer, etc. are not particularly limited to the example shown in the figure.

[0060] <Modification> A semiconductor device of a modification differs from the semiconductor device 100 shown in FIGS. 1 to 3 in that it further includes a back electrode layer.

[0061] Fig. 6 is a schematic cross-sectional view showing a semiconductor device according to a modified example, and Fig. 7 is a schematic view illustrating the circuit configuration of the semiconductor device shown in Fig. 6.

[0062] 6 , the semiconductor device 101 of the modified example further includes a back electrode layer 55 on the second surface s2 side of the semiconductor substrate 10. The material of the back electrode layer 55 is not particularly limited, but may be the same material as the electrode layers 51 and 52, for example.

[0063] The back electrode layer 55 is electrically connected to, for example, at least one conductive layer (conductive layer m1 in this example) of the capacitance section 30. In the example shown in Fig. 6 , the back electrode layer 55 is connected on the second surface s2 to the low resistance section 14 that also serves as the conductive layer m1 of the capacitance section 30. With this configuration, the back electrode layer 55, the electrode layer 51, and the conductive layers m1 and m3 of the capacitance section 30 are electrically connected, as shown in Fig. 7 . In Fig. 6 , the back electrode layer 55 is formed over the entire second surface s2, but it may be disposed on only a part of the second surface s2.

[0064] According to the semiconductor device 101 of this modification, for example, by grounding the electrode layer 52 and the back electrode layer 55, noise can be suppressed. Furthermore, ESL (parasitic inductance) can be reduced. Furthermore, the back electrode layer 55 can also be used as an input section for inputting signals from the outside or as an output section for outputting signals to the outside. This increases the degree of design freedom.

[0065] 6 and 7 , the back electrode layer 55 is electrically connected to the capacitance portion 30, but the back electrode layer 55 may be electrically isolated from the capacitance portion 30 and the electrode layers 51 and 52. In this case, the back electrode layer 55 serves as a floating electrode and can be used as a shield. For example, the semiconductor substrate 10 may have an insulating high-resistance portion on the second surface s2 side, and the back electrode layer 55 may be disposed so as to be in contact with the high-resistance portion.

[0066] Second Embodiment A semiconductor device according to a second embodiment differs from the semiconductor device 100 (FIG. 1) according to the first embodiment in that it also has a capacitance portion on the second surface side of the semiconductor substrate. Below, differences from the semiconductor device of the first embodiment will be mainly described, and overlapping descriptions will be omitted as appropriate.

[0067] Fig. 8 is a schematic top view showing a semiconductor device of a second embodiment. Fig. 9 is a schematic cross-sectional view taken along line IX-IX of the semiconductor device of Fig. 8. Fig. 10 is a schematic view showing an example of a circuit configuration of the semiconductor device of Fig. 8.

[0068] The semiconductor device 102 has, for example, a substantially rectangular parallelepiped shape. As an example, the height (thickness) h of the semiconductor device 102 is 1.0 mm, the width wx in the X direction is 1.0 mm, and the width wy in the Y direction is 0.5 mm. The mounting area is, for example, 1.0 mm x 0.5 mm.

[0069] As shown in FIG. 9, the semiconductor device 102 includes a semiconductor substrate 10, a first capacitance section 30A and a second capacitance section 30B, insulating layers 41A and 41B, protective layers 42A and 42B, electrode layers 51 to 54, and external electrodes 61 and 62.

[0070] The semiconductor substrate 10 has conductive low resistance portions 14, 24 and high resistance portions 15, 25 (here, insulating) having higher electrical resistance than the low resistance portions 14, 24. The low resistance portions 14, 24 are, for example, Si layers doped with impurities that impart conductivity. The high resistance portions 15, 25 are, for example, high resistance Si layers or SiO ２ 9, the low resistance portion 14 is exposed on the first surface s1 and the lower surface 11. The low resistance portion 24 is exposed on the second surface s2 and the lower surface 11. The high resistance portions 15 and 25 are exposed on the upper surface 12. At least a portion of the high resistance portions 15 and 25 is arranged so as to electrically separate the low resistance portion 14 and the low resistance portion 24.

[0071] The semiconductor substrate 10 includes, for example, a first substrate 10A including a low-resistance portion 14 and a high-resistance portion 15, and a second substrate 10B including a low-resistance portion 24 and a high-resistance portion 25. The first substrate 10A has a back surface 13a that is spaced apart from the first surface s1 in a first direction (here, the X direction) that intersects with the first surface s1. The high-resistance portion 15 is exposed on the back surface 13a. The second substrate 10B has a back surface 13b that is spaced apart from the second surface s2 in the first direction (X direction). The high-resistance portion 25 is exposed on the back surface 13b. The back surface 13a of the first substrate 10A and the back surface 13b of the second substrate 10B are bonded to each other by, for example, direct bonding, to form a bonding surface 90. The bonding surface 90 may not be visible.

[0072] The semiconductor substrate 10 has at least one trench portion (sometimes referred to as a "first trench portion") 16 having an opening in the first surface s1, and at least one trench portion (sometimes referred to as a "second trench portion") 26 having an opening in the second surface s2. In the example shown in Figure 9, the trench portion 16 is formed in the low resistance portion 14, and the trench portion 26 is formed in the low resistance portion 24. In other words, the low resistance portions 14, 24 are exposed on the inner surfaces of the trench portions 16, 26.

[0073] The first capacitance portion 30A is located on the first surface s1 side of the semiconductor substrate 10. At least a portion of the first capacitance portion 30A is located inside the trench portion 16. The second capacitance portion 30B is located on the second surface s2 side. At least a portion of the second capacitance portion 30B is located inside the trench portion 26. In the example shown in FIG. 9 , the first capacitance portion 30A extends into the trench portion 16 and a portion of the first surface s1 located around the trench portion 16. Similarly, the second capacitance portion 30B extends into the trench portion 26 and a portion of the second surface s2 located around the trench portion 26.

[0074] Each of the first capacitance section 30A and the second capacitance section 30B has a laminated structure including one or more (here, two) capacitance forming structures consisting of a conductive layer-dielectric layer-conductive layer, similar to the capacitance section 30 of the first embodiment (Figure 2).

[0075] 9 , the first capacitance section 30A includes a first capacitance Ca1 composed of a dielectric layer d1 and conductive layers m1 and m2, and a second capacitance Ca2 composed of a dielectric layer d2 and conductive layers m2 and m3. The conductive layer m1 of the first capacitance section 30A is composed of, for example, a low-resistance section 14. The second capacitance section 30B includes a first capacitance Cb1 composed of a dielectric layer d1 and conductive layers m1 and m2, and a second capacitance Cb2 composed of a dielectric layer d2 and conductive layers m2 and m3. The conductive layer m1 of the second capacitance section 30B is composed of, for example, a low-resistance section 24. The first capacitance section 30A and the second capacitance section 30B have, for example, the same stacked structure. The capacitance C1 of the first capacitance section 30A (the combined capacitance of the parallel-connected capacitances Ca1 and Ca2) and the capacitance C2 of the second capacitance section 30B (the combined capacitance of the parallel-connected capacitances Cb1 and Cb2) are configured to be the same.

[0076] The electrode layers 51 and 52 are electrically connected to the first capacitance unit 30A. The electrode layers 51 and 52 have, for example, the same configuration as the electrode layers 51 and 52 ( FIG. 2 ) of the first embodiment. However, the structure of the first connection unit 511 that electrically connects the electrode layer 51 and the conductive layer m1 (low resistance unit 14) is different. In the first connection unit 511 of the semiconductor device 102, the electrode layer 51 extends onto the low resistance unit 14 exposed on the first surface s1 and the lower surface 11.

[0077] The electrode layers 53 and 54 are electrically connected to the second capacitance section 30B. The structure of the connection portions between the electrode layers 53 and 54 and the second capacitance section 30B is similar to the structure of the connection portions 511, 512, and 521 between the electrode layers 51 and 52 and the first capacitance section 30A.

[0078] In this embodiment, the electrode layers 51 and 53 are electrically connected to each other. The electrode layers 52 and 54 are also electrically connected to each other. This allows the four capacitors Ca1, Ca2, Cb1, and Cb2 to be connected in parallel to each other, as shown in FIG.

[0079] In the example shown in FIG. 9 , the electrode layer 51 extends from the first surface s1 side of the semiconductor substrate 10 to the lower surface 11 side. The electrode layer 53 extends from the second surface s2 side of the semiconductor substrate 10 to the lower surface 11 side. The electrode layers 51 and 53 are electrically connected to each other on the lower surface 11 side. The electrode layers 51 and 53 may be in direct contact with each other or may be electrically connected via an external electrode 61. Similarly, the electrode layer 52 extends from the second surface s2 side of the semiconductor substrate 10 to the upper surface 12 side. The electrode layer 54 extends from the second surface s2 side of the semiconductor substrate 10 to the upper surface 12 side. The electrode layers 52 and 54 are electrically connected to each other on the upper surface 12 side. The electrode layers 52 and 54 may be in direct contact with each other or may be electrically connected via an external electrode 62.

[0080] The insulating layer 41A is disposed on the first surface s1 of the first substrate 10A so as to cover the capacitive portion 30A. The insulating layer 41B is disposed on the second surface s2 of the second substrate 10B so as to cover the capacitive portion 30B. In the example shown in Fig. 9, the insulating layer 41A is disposed between the low resistance portion 14 and the capacitive portion 30A and the electrode layers 51 and 52. The insulating layer 41B is disposed between the low resistance portion 24 and the capacitive portion 30B and the electrode layers 53 and 54.

[0081] Similar to the insulating layer 41 ( FIG. 2 ) of the first embodiment, each of the insulating layers 41A and 41B has an opening that exposes the conductive layers m1 to m3 in the corresponding capacitance portions 30A and 30B. However, in this embodiment, the insulating layers 41A and 41B do not extend onto the lower surface 11 and the upper surface 12 of the semiconductor substrate 10. This exposes the low-resistance portions 14 and 24 on the lower surface 11 of the semiconductor substrate 10. By disposing the electrode layers 51 and 53 on the exposed portions of the low-resistance portions 14 and 24, the connection area between the electrode layers 51 and 53 and the low-resistance portions 14 and 24 can be increased. Furthermore, even if the insulating layer 41 does not extend onto the upper surface 12 of the semiconductor substrate 10, the high-resistance portions 15 and 25 can electrically isolate the low-resistance portions 14 and 24 from the electrode layers 52 and 54.

[0082] The protective layers 42A and 42B are made of an insulating material, such as an organic resin layer of polyimide, phenol, or epoxy, or a SiO ２ , TiO ２Alternatively, the protective layers 42A and 42B may be inorganic insulating layers such as SiN, etc. Alternatively, the protective layers 42A and 42B may be made of a composite of an organic material and an inorganic material.

[0083] The protective layer 42A is disposed on the first surface s1 side of the semiconductor substrate 10 so as to cover the first capacitance portion 30A with the insulating layer 41A interposed therebetween. The protective layer 42B is disposed on the second surface s2 side of the semiconductor substrate 10 so as to cover the second capacitance portion 30B with the insulating layer 41B interposed therebetween. On the lower surface 11 side, the electrode layers 51 and 53 are exposed from the protective layers 42A and 42B. On the upper surface 12 side, the electrode layers 52 and 54 are exposed from the protective layers 42A and 42B.

[0084] The external electrodes 61, 62 include a conductor. The external electrodes 61, 62 are, for example, metal electrodes. The external electrodes 61, 62 may be a multilayer conductive film including multiple conductive films. The conductive films constituting the multilayer conductive film may be selected, including the catalyst layer, so as to have desired properties, and may include, for example, at least one metal element selected from Ni, Sn, Au, and Cu. As an example, the external electrodes 61, 62 have a laminated conductive film (Ni / Sn, Ni / Cu) including a Ni film and a Sn film or a Cu film. The external electrodes 61, 62 may be thicker than the electrode layers 51 to 54, for example.

[0085] The external electrodes 61, 62 function as external terminals of the semiconductor device 102. The external electrode 61 is disposed on the lower surface 11 side of the semiconductor substrate 10, outside the electrode layers 51, 53 (on the side of the electrode layers 51, 53 opposite the semiconductor substrate 10). The external electrode 61 is electrically connected to the portions of the electrode layers 51, 53 that are exposed on the lower surface 11 side. In the example shown in Fig. 9, the external electrode 61 is disposed so as to cover the lower end of the protective layer 42A, the exposed portions of the electrode layers 51, 53, and the lower end of the protective layer 42B.

[0086] The external electrode 62 is disposed on the upper surface 12 side of the semiconductor substrate 10, outside the electrode layers 52, 54 (on the side of the electrode layers 52, 54 opposite the semiconductor substrate 10). The external electrode 62 is electrically connected to the portions of the electrode layers 52, 54 that are exposed on the upper surface 12 side. In the example shown in Fig. 9, the external electrode 62 is disposed so as to cover the upper end of the protective layer 42A, the exposed portions of the electrode layers 52, 54, and the upper end of the protective layer 42B.

[0087] <Method for Manufacturing Semiconductor Device> An example of a method for manufacturing the semiconductor device 102 of this embodiment will be described below. Below, differences from the method described in the first embodiment will be mainly described.

[0088] (Preparation of Semiconductor Substrate) First, a semiconductor substrate having a low resistance portion and a high resistance portion is prepared. For example, the low resistance portion may be formed by doping a predetermined region of a high resistance semiconductor substrate (high resistance Si substrate) with an impurity that provides conductivity using a resist mask or the like. The region of the high resistance Si substrate that is not doped with the impurity becomes the high resistance portion.

[0089] (Formation of Trench Portion and Capacitor Portion) Next, a trench portion is formed in the main surface of the semiconductor substrate in the same manner as in the first embodiment. Next, a stacked structure that will become the capacitor portion is formed, and then an insulating layer that covers the capacitor portion is formed.

[0090] (Bonding of Substrates or Base Materials) Next, the back surfaces of the semiconductor substrates on which the capacitance portions are formed are bonded together, and then dicing is performed. Alternatively, the semiconductor substrates on which the capacitance portions are formed may be diced, and then the back surfaces of the diced base materials may be bonded together. It is preferable to polish the back surfaces of the semiconductor substrates or base materials before the bonding process. The bonding method is not particularly limited, but known direct bonding methods such as W2W (Wafer-to-Wafer bonding) and D2D (Die-to-Die bonding) can be used. In this way, a semiconductor base material on which capacitance portions are formed on both sides is obtained.

[0091] (Formation of Electrode Structure) Next, an electrode layer, a protective layer, and external electrodes are formed on the semiconductor substrate on which the capacitance portion has been formed. The method for forming the external electrodes is not particularly limited, but may be, for example, a known dipping method or sputtering method. In this manner, the semiconductor device 102 is manufactured.

[0092] <Effects> In the semiconductor device 101 of this embodiment, the capacitance section includes a first capacitance section 30A located on the first surface s1 side of the semiconductor substrate 10 and a second capacitance section 30B located on the second surface s2 side. At least a portion of the first capacitance section 30A is located inside the trench portion 16, and at least a portion of the second capacitance section 30B is located inside the trench portion 26. With this configuration, by providing the capacitance sections 30A and 30B on the two surfaces s1 and s2, which are side surfaces of the semiconductor substrate 10, the ratio of the area of ​​the capacitance section to the mounting area can be further increased. Therefore, the capacitor capacitance can be further increased while suppressing an increase in the mounting area.

[0093] The semiconductor device 102 of this embodiment further includes external electrodes 61, 62 located outside the electrode layers 51-54 (on the opposite side from the semiconductor substrate 10). This configuration can improve the barrier properties of the semiconductor device 100. Furthermore, by forming the external electrodes 61, 62, which serve as external terminals, separately from the electrode layers 51-54 that extend from the respective capacitance sections 30A, 30B to the bottom surface 11 or top surface 12 of the semiconductor substrate 10, it is possible to select the material and thickness of each electrode according to the application. For example, by using a material with high solder wettability for the external electrodes 61, 62, it is possible to further increase the bonding strength between the external electrodes 61, 62 and the mounting substrate.

[0094] The configuration of the semiconductor device of this embodiment is not limited to the configurations shown in Figures 8 to 10. For example, the arrangement and shape of the low resistance portions 14, 24 and the high resistance portions 15, 25 in the semiconductor substrate 10 are not limited to the examples shown in the figures. Furthermore, the method of joining the substrates 10A and 10B is not limited to direct bonding.

[0095] 9, the semiconductor substrate 10 has a structure in which two substrates are bonded together, but the semiconductor substrate 10 may also be made of a single substrate. Such a semiconductor device can be manufactured, for example, by forming trench portions on the main surface side and the back surface side of a single semiconductor substrate and forming a capacitor portion inside the trench portions.

[0096] <Modification 1> A semiconductor device of Modification 1 differs from semiconductor device 102 shown in FIGS. 8 and 9 in that it further includes a through electrode.

[0097] Fig. 11 is a schematic top view showing a semiconductor device of Modification 1. Fig. 12 is a schematic cross-sectional view taken along line XII-XII in Fig. 11. Fig. 13 is a schematic diagram showing an example of the circuit configuration of the semiconductor device of Fig. 11.

[0098] The semiconductor device 103 includes a semiconductor substrate 10 including a first substrate 10A and a second substrate 10B, a first capacitance section 30A and a second capacitance section 30B, a through electrode 80, insulating layers 41A and 41B, protective layers 42A and 42B, electrode layers 51 to 54, external electrodes 61 to 64, and through-electrode external electrodes 65 and 66. The electrode layers 51 to 54 are electrically connected to the corresponding external electrodes 61 to 64, respectively. Both ends of the through electrode 80 are electrically connected to the through-electrode external electrodes 65 and 66, respectively.

[0099] The first substrate 10A includes a low resistance portion 14 and a high resistance portion 15. The low resistance portion 14 is exposed on the first surface s1. The high resistance portion 15 is exposed on the lower surface 11a, upper surface 12a, and rear surface 13a of the first substrate 10A. Similarly, the second substrate 10B includes a low resistance portion 24 and a high resistance portion 25. The low resistance portion 24 is exposed on the second surface s2. The high resistance portion 25 is exposed on the lower surface 11b, upper surface 12b, and rear surface 13b of the second substrate 10B.

[0100] The through electrode 80 is a metal electrode made of, for example, Cu, Al, or the like. The thickness of the through electrode 80 in the X direction is, for example, 1 μm or less. The through electrode 80 is arranged, for example, between the first surface s1 and the second surface s2 of the semiconductor substrate 10 so as to penetrate the semiconductor substrate 10 from the lower surface to the upper surface. The through electrode 80 has, for example, a quadrangular prism shape extending in the Z direction. In this modification, the through electrode 80 is electrically isolated from the capacitive portions 30A and 30B.

[0101] The through electrode 80 may be located between the back surface 13a of the first substrate 10A and the back surface 13b of the second substrate 10B. In the example shown in FIG. 12 , the back surface 13a of the first substrate 10A and the back surface 13b of the second substrate 10B are spaced apart in the X direction, and the through electrode 80 is located between the back surfaces 13a and 13b. When viewed from the X direction, the through electrode 80 may be located over substantially the entire back surface 13a or 13b. Alternatively, as illustrated in FIG. 11 , the back surface 13a of the first substrate 10A and the back surface 13b of the second substrate 10B may be partially joined to each other, and the through electrode 80 may be located in a recess provided in a portion (e.g., a central portion) of one or both of the back surfaces 13a and 13b (here, both).

[0102] The through electrode 80 can also function as a bonding layer that bonds the first substrate 10A and the second substrate 10B. The through electrode 80 may be formed by bonding (e.g., Cu-Cu bonding) an electrode portion formed on the back surface 13a of the first substrate 10A and an electrode portion formed on the back surface 13b of the second substrate 10B.

[0103] The external electrodes 65, 66 for through electrodes include a conductor and can be formed using the same material (for example, Cu or Al) and by the same method as the other external electrodes 61 to 64.

[0104] The external electrode 65 for the through electrode is disposed on the lower surface side of the semiconductor substrate 10 and is electrically connected to the lower end of the through electrode 80. The external electrode 66 for the through electrode is disposed on the upper surface side of the semiconductor substrate 10 and is electrically connected to the upper end of the through electrode 80. The external electrodes 65, 66 for the through electrode are drawn to the outside of the semiconductor device 103 and can be electrically connected to wiring on a circuit board, etc. Therefore, signals / power can be passed from the outside to the through electrode 80 via the external electrodes 65, 66 for the through electrode.

[0105] The first capacitance section 30A and the second capacitance section 30B have different structures. Here, the capacitance sections 30A and 30B are configured such that the capacitance C1 of the first capacitance section 30A (the combined capacitance of the parallel-connected capacitances Ca1 and Ca2) and the capacitance C2 of the second capacitance section 30B (the combined capacitance of the parallel-connected capacitances Cb1 and Cb2) are different from each other. In the example shown in FIG. 12 , the number of trench sections 26 is made smaller than the number of trench sections 16, thereby making the effective area of ​​the second capacitance section 30B smaller than that of the first capacitance section 30A. Therefore, the capacitance C2 is smaller than the capacitance C1.

[0106] The configuration for differentiating the capacitances of the first capacitance section 30A and the second capacitance section 30B is not particularly limited. For example, the first capacitance section 30A and the second capacitance section 30B may be different in the number of trench sections, the hole diameter (area of ​​the opening), depth, shape, etc. of each trench section. Alternatively, the first capacitance section 30A and the second capacitance section 30B may be different in the number of stacked layers (number of dielectric layers) or the thickness of the dielectric layers.

[0107] 9, the electrode layers 51 to 54 are electrically connected to the corresponding capacitance sections 30A and 30B. The electrode layers 51 and 53 are electrically connected to external electrodes 61 and 63, respectively, on the lower surface 11 side of the semiconductor substrate 10. The electrode layers 52 and 54 are electrically connected to external electrodes 62 and 64, respectively, on the upper surface 12 side of the semiconductor substrate 10.

[0108] 13 , in this modification, the external electrodes 61 and 62 electrically connected to the first capacitance section 30A on the first substrate 10A side are electrically separated from the external electrodes 63 and 64 electrically connected to the second capacitance section 30B on the second substrate 10B side. Furthermore, the through electrode external electrodes 65 and 66 are electrically separated from the external electrodes 61 to 64.

[0109] 11 and 12 , on the underside of the semiconductor device 103, the external electrodes 61, 63 are arranged on both sides of the external electrode for through electrode 65 in the X direction at a distance from the external electrode for through electrode 65. Similarly, on the upper side of the semiconductor device 103, the external electrodes 62, 64 are arranged on both sides of the external electrode for through electrode 66 in the X direction at a distance from the external electrode for through electrode 66. The external electrodes for through electrode 65, 66 are insulated from the external electrodes 61 to 64 on either side thereof by high-resistance portions 15, 25 of the semiconductor substrate 10.

[0110] (Method of Forming Through Electrode) The semiconductor device 103 can be manufactured by the same method as the semiconductor device 102 (FIGS. 8 and 9) described above. The through electrode 80 can be formed, for example, by the following method.

[0111] The back surfaces of the first and second substrates are ground as needed. Next, a conductive film such as an Al film or Cu film is formed on the back surface of each substrate as an electrode portion by, for example, sputtering. Next, the surface of the electrode portion is polished or flattened as needed, and the substrates are then bonded together. This bonds the electrode portions formed on the back surfaces of each substrate (e.g., Cu-Cu bonding), forming a through electrode.

[0112] Instead of the above method, recesses may be formed in the high resistance portions on the rear surface of each substrate by etching or the like, and the recesses may be filled with a conductor such as Cu to form electrode portions. Thereafter, the substrates may be bonded together in the same manner as above, and the electrode portions formed on the rear surfaces of the substrates may be bonded together (e.g., by Cu-Cu bonding).

[0113] According to this modification, the through electrodes 80 that can be electrically connected to external wiring or the like are provided, so that the degree of freedom in designing the semiconductor device 103 can be increased.

[0114] In the semiconductor device 103 of this modification, the through electrode 80 is disposed between at least a part of the back surface (also referred to as the "first back surface") 13a of the first substrate 10A and at least a part of the back surface (also referred to as the "second back surface") 13b of the second substrate 10B. With this configuration, the through electrode 80 can be used as a bonding layer between the first substrate 10A and the second substrate 10B, thereby increasing the bonding strength between the substrates 10A and 10B.

[0115] When viewed along the X direction, the area ratio of the through electrode 80 to the rear surface 13a or the rear surface 13b may be, for example, 50% or more (80% or more in the illustrated example). With such a configuration, it is possible to form a through electrode 80 with lower resistance. Furthermore, when the through electrode 80 is formed by joining an electrode portion on the rear surface 13a side with an electrode portion on the rear surface 13b, the joining of the electrode portions can be utilized to further increase the bonding strength between the base materials 10A and 10B.

[0116] In the semiconductor device 103 of this modification, the first capacitance section 30A and the second capacitance section 30B are configured to have different capacitances. This configuration increases the design freedom of the semiconductor device 103.

[0117] The configuration of the semiconductor device of this modification is not limited to the configuration shown in FIGS. 11 to 13. For example, the upper or lower end of the through electrode may function as an external terminal without providing an external electrode for the through electrode. The circuit configuration of this modification is also not limited to the example shown in FIG. 13. The through electrode may be electrically connected to any of the external electrodes. Furthermore, the capacitors Ca1, Ca2, Cb1, and Cb2 may be connected in parallel with each other.

[0118] <Modification 2> The semiconductor device of Modification 2 differs from semiconductor device 103 of Modification 1 in that a wiring layer including a through electrode is formed at the joint between the first base material and the second base material.

[0119] Fig. 14 is a schematic top view showing a semiconductor device of Modification 2. Fig. 15 is a schematic cross-sectional view taken along line XV-XV of the semiconductor device of Fig. 14. Fig. 16 is a schematic cross-sectional view taken along line XVI-XVI shown in Figs. 14 and 15.

[0120] The semiconductor device 104 includes a wiring layer 91 between the rear surface 13a of the first substrate 10A and the rear surface 13b of the second substrate 10B.

[0121] The wiring layer 91 includes a through electrode 80 and at least one (here, three) dummy electrodes 81 to 83. When viewed along the X direction, the through electrode 80 and the dummy electrodes 81 to 83 are arranged at a distance from each other. The through electrode 80 and the dummy electrodes 81 to 83 are formed so as to form convex portions relative to the rear surfaces 13a and 13b of the respective base materials 10A and 10B.

[0122] The through electrode 80 is patterned to extend from the lower surface 11 to the upper surface 12 of the semiconductor substrate 10. The through electrode 80 may include a bent portion when viewed from the X direction. In the example shown in Fig. 15, the through electrode 80 includes two portions extending in the Z direction and a portion located between these portions and extending in the Y direction.

[0123] The dummy electrodes 81 to 83 are electrodes that are not drawn to the outside of the semiconductor device 104, and in this example, are floating electrodes. In the example shown in Fig. 15, the wiring layer 91 has the dummy electrodes 81 to 83, which are, for example, rectangular, and are arranged so as to fill in the region on the back surface of the base material where the through electrode 80 is not formed.

[0124] As shown in FIGS. 15 and 16, the wiring layer 91 may further include gaps 92 between the dummy electrodes and / or between the dummy electrodes 81 to 83 and the through electrode 80 .

[0125] Portions located on the edges of the wiring layer 91 and in which neither through electrodes nor dummy electrodes are arranged may be filled with resin 93. By filling with resin 93, the external electrodes formed after bonding the base materials are less likely to be recessed due to voids in the wiring layer 91. In this example, the resin 93 is filled along the edges of the wiring layer 91, but the resin 93 may be filled only in part of the edges (for example, only in the portions that form the base of the external electrodes).

[0126] (Method of Forming Wiring Layer) The wiring layer 91 can be formed by, for example, a subtractive method, a SAP (Semi-Additive Process) method, or the like.

[0127] First, the thickness of each substrate is adjusted by grinding or the like as needed. Then, electrode portions (e.g., Al film, Cu film, etc.) that will become through electrodes and dummy electrodes are formed on the rear surface of each substrate. For example, electrolytic plating, sputtering, etc. can be used to form the electrode portions. The thickness of the electrode portions is, for example, 1 μm or less when sputtering is used, and, for example, 20 μm or less when SAP (Semi-Additive Process) is used. The electrode portions on the rear surfaces of the first substrate and the second substrate have patterns that match each other.

[0128] Next, after planarizing the surfaces of the electrode portions as necessary, the electrode portions of each substrate are bonded together. As a result, the electrode portions formed on the back surfaces of each substrate are bonded (e.g., Cu-Cu bonding), and through electrodes and dummy electrodes are formed. Because the electrode portions are convex with respect to the back surfaces of each substrate, bonding the electrode portions forms a gap between the back surfaces of the substrates.

[0129] Next, the gaps in the wiring layer that are exposed on the surfaces of the bonded semiconductor substrates are filled with a resin or the like. After this, if necessary, the surface of the wiring layer is flattened (for example, made flush with the top or bottom surfaces of each substrate). This allows the external electrodes to be formed on the flat surface.

[0130] The through electrodes or dummy electrodes may be disposed up to the edge of the rear surface of the substrate and exposed on the upper or lower surface of the semiconductor substrate. In this case, the exposed portions of the through electrodes or dummy electrodes may be flattened to be flush with the upper or lower surface of each substrate.

[0131] The semiconductor device 104 of this modification includes a wiring layer 91 including a through electrode 80 between the first back surface 13a of the first substrate 10A and the second back surface 13b of the second substrate 10B. With this configuration, the through electrode 80 can be formed in a desired pattern, thereby increasing the design freedom of the semiconductor device 104. Furthermore, by forming the wiring layer 91 by bonding an electrode portion arranged on the first substrate 10A side and an electrode portion arranged on the second substrate 10B side, the bonding strength between the substrates 10A and 10B can be increased.

[0132] In the semiconductor device 104 of this modification, the wiring layer 91 includes dummy electrodes 81-83 in addition to the through electrode 80. With this configuration, the bonding area between the electrode portions can be increased, thereby further increasing the bonding strength between the base materials 10A and 10B. The total area of ​​the through electrode 80 and the dummy electrodes 81-83 relative to the area of ​​the wiring layer 91 may be, for example, 60% or more (80% or more in the example shown in FIG. 15 ).

[0133] According to this modification, the wiring layer 91 includes a void 92. The void 92 serves as a buffer for releasing stress, thereby contributing to stress relaxation. Therefore, problems caused by stress can be suppressed both during the manufacture and use of the semiconductor device 104.

[0134] The layout of the wiring layer 91 is not limited to the example shown in the drawing, and a desired layout can be applied to the wiring layer 91 depending on the application, size, and the like.

[0135] <Modification 3> A semiconductor device of Modification 3 differs from the semiconductor device 104 shown in FIGS. 15 and 16 in that the electrode portion of the wiring layer is disposed in the high resistance portion of the substrate.

[0136] Fig. 17 is a schematic cross-sectional view showing a wiring layer of a semiconductor device according to Modification 3. Fig. 18 is a schematic cross-sectional view taken along line XVIII-XVIII in Fig. 17.

[0137] In the semiconductor device 105, grooves (recesses) 131a, 131b are formed on the back surfaces 13a, 13b of the respective substrates 10A, 10B to form electrode portions that will become through electrodes or dummy electrodes. Portions of the back surfaces 13a, 13b of the respective substrates 10A, 10B where no grooves are formed are joined to each other at a joining surface 90. The through electrodes 80 and dummy electrodes 81-83 are disposed in a space formed by the opposing grooves 131a, 131b of the substrates 10A, 10B. In other words, high resistance portions 15, 25 are located between the electrodes in the wiring layer 91.

[0138] (Method of Forming Wiring Layer) The wiring layer 91 of this modified example can be formed by, for example, a damascene method.

[0139] First, a groove (recess) is formed in the high-resistance portion on the back surface of each substrate by etching or the like. Next, a conductor such as Cu is filled into the groove, for example, by via-filling plating. As an example, a barrier layer or a seed layer can be formed in the groove by sputtering or the like, and then the conductor such as Cu can be filled by electrolytic plating. In this way, an electrode portion can be formed in the groove on the back surface of each substrate. After this, the portion of the electrode portion protruding from the groove can be planarized by CMP (chemical mechanical polishing). This allows the surface of the electrode portion and the surface of the substrate (here, the surface of the high-resistance portion) to be flush with each other on the back surface of each substrate.

[0140] After this, the substrates with electrode portions formed in the grooves are bonded together. The electrode portions formed on the backside of each substrate are bonded (for example, by Cu-Cu bonding) to form through electrodes or dummy electrodes. In addition, the high resistance portions of the substrates (areas where no electrode portions are formed) are also bonded together.

[0141] According to this modification, the bonding surfaces (high resistance portions and electrode portions) on the rear surface side of each base material are flattened, so that not only the electrode portions but also the high resistance portions are bonded to each other at bonding surface 90. This makes it possible to ensure a sufficient contact area between first base material 10A and second base material 10B, further increasing the bonding strength.

[0142] 19 is a schematic perspective view showing a semiconductor device according to a third embodiment. As shown in FIG. 19, a capacitance section of a semiconductor device 106 includes a plurality of capacitor portions (sometimes simply referred to as "portions") 30p arranged side by side at intervals. The semiconductor device 106 is, for example, a capacitor array.

[0143] Each capacitor portion 30p may have the same configuration as the capacitance portion described above. In this embodiment, N (N is an integer of 2 or more; N=3 in FIG. 19 ) capacitor portions 30p are arranged at intervals in the Y direction on the first surface side of the semiconductor substrate 10. Adjacent capacitor portions 30p may be insulated from each other by, for example, a high-resistance portion of the semiconductor substrate 10. Each capacitor portion 30p is electrically connected to a pair of external electrodes 61, 62.

[0144] 19 , N capacitance units and external electrodes may also be arranged at intervals in the Y direction on the second surface side of the semiconductor substrate 10. By arranging capacitance units on the second surface side as well, the number of capacitance units (number of arrays) can be doubled (2×N).

[0145] According to this embodiment, a plurality of capacitor portions 30p can be formed on the side surface (e.g., the first surface) of the semiconductor substrate 10. This allows the mounting area to be further reduced. Alternatively, the capacitor capacitance can be further increased while suppressing an increase in the mounting area.

[0146] 19, three capacitor portions 30p are arranged in the Y direction, but the number of capacitance portions, the arrangement method, and the like are not limited to the illustrated example. Also, in FIG. 19, external electrodes 61, 62 are arranged for each capacitor portion 30p, but a common external electrode may be arranged for multiple capacitor portions 30p. Furthermore, although the semiconductor substrate 10 has a structure in which two substrates 10A, 10B are bonded together at a bonding surface 90, a single substrate (e.g., a Si substrate) may also be used as the semiconductor substrate 10.

[0147] Fourth Embodiment A fourth embodiment is a circuit board including any one of the semiconductor devices described above. The circuit board of this embodiment includes a semiconductor device and a mounting substrate having a mounting surface. The semiconductor device is mounted on the mounting surface such that the underside of the semiconductor substrate faces the mounting surface (see FIG. 4H ).

[0148] FIG. 20 is a schematic cross-sectional view showing a circuit board according to the fourth embodiment.

[0149] The circuit board 201 includes a mounting substrate 110 and semiconductor devices 107 and 108. In this embodiment, the surface of the mounting substrate 110 facing the lower surfaces of the semiconductor devices 107 and 108 is also referred to as a mounting surface 110s.

[0150] The mounting substrate 110 includes a core material 130, an insulating member, and multiple wiring layers. In the example shown in FIG. 20 , the insulating member includes a lower insulating member 112L located below the core material 130 in the Z direction and a wiring layer 112U located above the core material 130. The wiring layers include at least one wiring layer 120L located inside the lower insulating member 112L and at least one wiring layer 120U located inside the upper insulating member 112U. The core material 130 is an insulating layer. The thickness of the core material 130 is, for example, approximately 500 μm to 1200 μm (e.g., 1000 μm).

[0151] The semiconductor devices 107 and 108 are components having trench portions and capacitor portions on their side surfaces. The structure of the semiconductor devices 107 and 108 is not particularly limited to the example shown in the figure, and may be semiconductor devices according to the above-described embodiments or modifications. The height of the semiconductor devices 107 and 108 in the Z direction is slightly smaller than, but roughly the same as, the thickness of the core material 130 in the Z direction. In the Z direction, the semiconductor devices 107 and 108 are disposed between the upper end 130b and the lower end 130a of the core material 130. The lower surfaces of the semiconductor devices 107 and 108 are located near the lower end 130a of the core material 130 in the X direction. The upper surfaces of the semiconductor devices 107 and 108 are located near the upper end 130b of the core material 130 in the X direction. In the example shown in FIG. 20 , the core material 130 has a through-hole extending from the lower end 130a to the upper end 130b, and the semiconductor devices 107 and 108 are disposed within the through-hole. The portions of the through holes where the semiconductor devices 107 and 108 are not disposed may be filled with resin.

[0152] The external terminals on the lower surfaces of the semiconductor devices 107 and 108 are electrically connected to the wiring in the wiring layer 120L, and the external terminals on the upper surfaces are electrically connected to the wiring in the wiring layer 120U. The external terminals of the semiconductor devices 107 and 108 may be external electrodes disposed on the surface of the semiconductor substrate, or may be part of a low-resistance portion of the semiconductor substrate. As an example, an external electrode is provided on the upper surface of the semiconductor device 107 as an external terminal. The external electrode is electrically connected to the wiring in the wiring layer 120U via a connecting conductor 212 in the upper insulating member 112U. Meanwhile, a low-resistance portion of the semiconductor substrate is exposed on the lower surface of the semiconductor device 107. The exposed portion of the low-resistance portion is connected (e.g., directly connected) to a connecting conductor 211 in the lower insulating member 112L.

[0153] The external terminal for the through electrode located on the lower end side of the through electrode 80 of the semiconductor device 107 is electrically connected to the wiring in the wiring layer 120L via a connecting conductor 213. The external terminal for the through electrode located on the upper end side of the through electrode 80 is electrically connected to the wiring in the wiring layer 120U via a connecting conductor 214. In this way, the wiring in the wiring layers 120L and 120U can be electrically connected to each other via the through electrode 80.

[0154] The external terminal for the through electrode may also be an external electrode formed on the surface of the semiconductor substrate, or an end of the through electrode 80 may be used as the external terminal for the through electrode. As an example, an external electrode for the through electrode is arranged on the upper surface side of the semiconductor device 107 as the external terminal for the through electrode. Meanwhile, the lower end of the through electrode 80 is exposed on the lower surface of the semiconductor device 107. The exposed portion of the through electrode 80 is connected to the connecting conductor 213 in the lower insulating member 112L.

[0155] According to this embodiment, the height of the semiconductor device 100 can be set with a high degree of freedom depending on the height of the core material 130. Therefore, for example, the semiconductor device 100 can be easily embedded in a circuit board having a relatively thick core material 130. Furthermore, if the semiconductor device 100 includes a through electrode 80, signals can be passed in the thickness direction (Z direction) of the core material 130 via the through electrode 80. Therefore, for example, when a PMIC (Power Management IC) is provided below the core material 130 and a processor IC such as an XPU is provided above the core material 130, a signal path with little loss can be formed between these ICs via the through electrode 80.

[0156] <Modification> FIG. 21 is a schematic cross-sectional view showing a circuit board according to a modification.

[0157] The circuit board 202 includes a first mounting substrate (e.g., a motherboard) 110A, a second mounting substrate (e.g., a package substrate) 110B, a semiconductor device 109, and a connecting member 140. For example, an integrated circuit component (IC) 150 is disposed on the upper surface of the second mounting substrate 110B.

[0158] The first mounting substrate 110A and the second mounting substrate 110B are disposed opposite each other in the Z direction with the semiconductor device 100 interposed therebetween. The lower surface side of the semiconductor device 109 is mounted on the mounting surface 110s of the first mounting substrate 110A. The upper surface side of the semiconductor device 109 is mounted on the mounting surface of the second mounting substrate 110B.

[0159] The semiconductor device 109 is a component having a trench portion and a capacitance portion on its side surface. The semiconductor device 109 may be any of the semiconductor devices according to the above-described embodiments or modifications. The semiconductor device 109 functions as, for example, a bridge. Therefore, signals can be transmitted between the wiring in the first mounting substrate 110A and the wiring in the second mounting substrate 110B via the semiconductor device 109.

[0160] The connection members 140 are disposed between the mounting substrates 110A and 110B. The connection members 140 are, for example, solder bumps, copper pillars, etc. In the example shown in Fig. 21 , a plurality of connection members 140 and a plurality of semiconductor devices 109 are disposed at intervals in a plan view seen along the Z direction.

[0161] According to this modification, the semiconductor device 109 is provided between the mounting boards 110A and 110B, so that signal transmission and power transmission can be performed between the mounting boards 110A and 110B, and noise can also be removed.

[0162] The height of the semiconductor device 109 in the Z direction can be designed, for example, by dicing the semiconductor substrate to a desired width. Therefore, by setting the height of the semiconductor device 109 according to the thickness of the connecting member 140 (for example, about 400 μm), the semiconductor device 109 can be easily mounted together with the connecting member 140 between the mounting substrates 110A and 110B.

[0163] In FIG. 21, connecting members 140 such as solder bumps are arranged in the space between the mounting substrates 110A and 110B, but only the semiconductor device 109 may be arranged therein.

[0164] The above description can also be expressed as follows.

[0165] According to a first aspect of the present disclosure, there is provided a semiconductor device comprising: a semiconductor substrate having a lower surface, an upper surface arranged at a distance from the lower surface in the height direction, and a side surface connecting the upper surface and the lower surface; and a capacitance portion arranged on the side surface of the semiconductor substrate, wherein the lower surface is a surface facing a mounting surface on which the semiconductor device is mounted; the capacitance portion has a layered structure including at least a first dielectric layer arranged along the side surface, and a first conductive layer and a second conductive layer facing each other with the first dielectric layer sandwiched therebetween; the semiconductor substrate has at least one trench portion having an opening on the side surface; and at least a portion of the capacitance portion is located inside the at least one trench portion.

[0166] According to a second aspect of the present disclosure, there is provided the semiconductor device described in the first aspect, further comprising a pair of external terminals electrically connected to the capacitance portion, one of the pair of external terminals being located on the lower surface side of the semiconductor substrate, and the other of the pair of external terminals being located on the upper surface side of the semiconductor substrate.

[0167] According to a third aspect of the present disclosure, there is provided the semiconductor device according to the first or second aspect, wherein a depth direction of the at least one trench portion from the opening is parallel to the mounting surface.

[0168] According to a fourth aspect of the present disclosure, there is provided a semiconductor device according to any one of the first to third aspects, further comprising an electrode layer electrically connected to the capacitance portion, wherein the laminated structure of the capacitance portion further includes a second dielectric layer located on the opposite side of the second conductive layer from the first dielectric layer, and a third conductive layer facing the second conductive layer across the second dielectric layer, and the first conductive layer and the third conductive layer are electrically connected to the electrode layer.

[0169] According to a fifth aspect of the present disclosure, there is provided a semiconductor device according to any one of the first to third aspects, further comprising an electrode layer electrically connected to the capacitance portion, the electrode layer extending from the side surface side of the semiconductor substrate to the bottom surface side or the top surface side.

[0170] According to a sixth aspect of the present disclosure, there is provided a semiconductor device according to any one of the first to fifth aspects, wherein the side surface of the semiconductor substrate has a first surface and a second surface spaced apart from the first surface in a first direction intersecting the first surface, the opening of the at least one trench portion is located on the first surface, and the semiconductor device further includes a back electrode layer arranged on the second surface side of the semiconductor substrate.

[0171] According to a seventh aspect of the present disclosure, there is provided a semiconductor device according to any one of the first to fifth aspects, wherein the side surface of the semiconductor substrate has a first surface and a second surface spaced apart from the first surface in a first direction intersecting the first surface, the capacitance portion comprises a first capacitance portion located on the first surface side and a second capacitance portion located on the second surface side, the at least one trench portion includes at least one first trench portion having an opening in the first surface and at least one second trench portion having an opening in the second surface, at least a portion of the first capacitance portion is located inside the at least one first trench portion, and at least a portion of the second capacitance portion is located inside the at least one second trench portion.

[0172] According to an eighth aspect of the present disclosure, there is provided the semiconductor device according to the seventh aspect, wherein the first capacitance section and the second capacitance section are configured to have different electrostatic capacitances from each other.

[0173] According to a ninth aspect of the present disclosure, there is provided the semiconductor device according to the seventh or eighth aspect, further comprising a through electrode that penetrates the semiconductor substrate from the lower surface to the upper surface.

[0174] According to a tenth aspect of the present disclosure, there is provided the semiconductor device described in the ninth aspect, wherein the semiconductor substrate comprises: a first substrate in which the at least one first trench portion is formed; and a second substrate in which the at least one second trench portion is formed; the first substrate has a first back surface arranged at a distance from the first surface in the first direction; the second substrate has a first back surface arranged at a distance from the first surface in the first direction; and the through electrode is arranged between at least a portion of the first back surface of the first substrate and at least a portion of the second back surface of the second substrate.

[0175] According to an eleventh aspect of the present disclosure, there is provided the semiconductor device described in the tenth aspect, wherein, when viewed along the first direction, the through electrode occupies an area ratio of 50% or more of the first rear surface or the second rear surface.

[0176] According to a twelfth aspect of the present disclosure, there is provided a semiconductor device according to the tenth or eleventh aspect, comprising a wiring layer located between the first back surface of the first substrate and the second back surface of the second substrate, wherein the wiring layer includes the through electrode and a dummy electrode arranged at a distance from the through electrode when viewed along the first direction.

[0177] According to a thirteenth aspect of the present disclosure, there is provided the semiconductor device according to the twelfth aspect, wherein the wiring layer further includes a void portion.

[0178] According to a fourteenth aspect of the present disclosure, there is provided the semiconductor device according to any one of the first to thirteenth aspects, wherein the capacitance section includes a plurality of portions arranged side by side at intervals from each other on the side surface.

[0179] According to a fifteenth aspect of the present disclosure, there is provided the semiconductor device according to any one of the first to fourteenth aspects, wherein the semiconductor substrate includes a conductive low-resistance portion made of a low-resistance semiconductor, and the first conductive layer or the second conductive layer of the capacitance portion is composed of the low-resistance portion.

[0180] According to a sixteenth aspect of the present disclosure, there is provided the semiconductor device according to any one of the first to fifteenth aspects, wherein the semiconductor substrate includes a conductive low-resistance portion made of a low-resistance semiconductor, and a portion of the low-resistance portion is exposed on a surface of the semiconductor device and functions as an external terminal.

[0181] According to a seventeenth aspect of the present disclosure, there is provided the semiconductor device according to any one of the first to sixteenth aspects, and a circuit board including a mounting substrate having the mounting surface, wherein the semiconductor device is mounted on the mounting surface such that the lower surface of the semiconductor substrate faces the mounting surface of the mounting substrate.

[0182] According to an eighteenth aspect of the present disclosure, there is provided the circuit board according to the seventeenth aspect, wherein the mounting substrate has a core material, and the semiconductor device is disposed between an upper end and a lower end of the core material in the height direction of the semiconductor device.

[0183] According to a 19th aspect of the present disclosure, there is provided the circuit board as set forth in the 17th aspect, further comprising another mounting substrate arranged to face the mounting substrate via the semiconductor device in the height direction of the semiconductor device, wherein the semiconductor device is mounted on the mounting surface of the other mounting substrate such that the top surface of the semiconductor substrate faces the mounting surface of the other mounting substrate.

[0184] According to another aspect of the present disclosure, there is provided a semiconductor device according to any one of the tenth to twelfth aspects, wherein at least a portion of the through electrode is located within a space formed by a groove formed on the first rear surface of the first substrate and a groove formed on the second rear surface of the second substrate facing each other.

[0185] According to another aspect of the present disclosure, there is provided a semiconductor device according to the fourth or fifth aspect, further comprising an external electrode located on the lower surface side or the upper surface side of the semiconductor substrate, on the side of the electrode layer opposite the semiconductor substrate, wherein the external electrode is disposed on a portion of the electrode layer.

[0186] According to another aspect of the present disclosure, there is provided a semiconductor device according to any one of the first to sixteenth aspects, wherein the thickness of the first conductive layer and the second conductive layer is at least twice the thickness of the first dielectric layer.

[0187] According to another aspect of the present disclosure, there is provided the semiconductor device according to any one of the first to sixteenth aspects, wherein a height from the lower surface to the upper surface of the semiconductor substrate is greater than 0.725 μm.

[0188] According to another aspect of the present disclosure, there is provided a semiconductor device according to any one of the first to sixteenth aspects, wherein a height from the lower surface to the upper surface of the semiconductor substrate is greater than a maximum width of the lower surface.

[0189] Any of the various embodiments described above may be combined appropriately to achieve the effects of each of them.

[0190] While the present invention has been fully described in connection with preferred embodiments, with appropriate reference to the drawings, various changes and modifications will become apparent to those skilled in the art, and it is to be understood that such changes and modifications are included within the scope of the present invention as defined by the appended claims unless they depart therefrom.

[0191] 10 Semiconductor substrate 10A First substrate 10B Second substrate 131a, 131b Groove portion (recess) 11, 11a, 11b Lower surface 12, 12a, 12b Upper surface 14, 24 Low resistance portion 15, 25 High resistance portion 16, 26 Trench portion 30 Capacitance portion 30A First capacitance portion 30B Second capacitance portion 41, 41A, 41B Insulation layer 42A, 42B Protective layer 51 to 54 Electrode layer 55 Back electrode layer 61 to 64 External electrode 65, 66 External electrode for through electrode 80 Through electrode 81 to 83 Dummy electrode 90 Bonding surface 91 Wiring layer 92 Void portion 93 Resin 100 to 109 Semiconductor device 110, 110A, 110B Mounting substrate 110s Mounting surface 112L Lower insulating member 112U Upper insulating member 120L, 120U Wiring layer 130 Core material 140 Connection member 150 Integrated circuit component (IC) 201, 202 Circuit board 211 to 214 Connection conductor 411 First opening 412 Second opening 413 Third opening 511 First connection portion 512 Second connection portion 521 Third connection portion Ca1, Ca2, Cb1, Cb2 Capacitance d1, d2 Dielectric layer m1 to m3 Conductive layer s1 First surface s2 Second surface

Claims

1. A semiconductor device comprising: a semiconductor substrate having a bottom surface, an top surface arranged at a distance from the bottom surface in the height direction, and a side surface connecting the top surface and the bottom surface; and a capacitive portion arranged on the side surface of the semiconductor substrate, wherein the bottom surface is a surface facing a mounting surface on which the semiconductor device is mounted, the capacitive portion has a layered structure including at least a first dielectric layer arranged along the side surface, and a first conductive layer and a second conductive layer opposing each other with the first dielectric layer therebetween, the semiconductor substrate has at least one trench portion having an opening on the side surface, and at least a portion of the capacitive portion is located inside the at least one trench portion.

2. The semiconductor device according to claim 1, further comprising a pair of external terminals electrically connected to the capacitance portion, one of the pair of external terminals being located on the lower surface side of the semiconductor substrate, and the other of the pair of external terminals being located on the upper surface side of the semiconductor substrate.

3. The semiconductor device according to claim 1 or 2, wherein a depth direction of said at least one trench portion from said opening is parallel to said mounting surface.

4. A semiconductor device as described in any one of claims 1 to 3, further comprising an electrode layer electrically connected to the capacitance section, wherein the laminated structure of the capacitance section further includes a second dielectric layer located on the opposite side of the second conductive layer to the first dielectric layer, and a third conductive layer facing the second conductive layer with the second dielectric layer in between, and the first conductive layer and the third conductive layer are electrically connected to the electrode layer.

5. A semiconductor device according to any one of claims 1 to 3, further comprising an electrode layer electrically connected to the capacitance portion, the electrode layer extending from the side surface side of the semiconductor substrate to the bottom surface side or the top surface side.

6. A semiconductor device according to any one of claims 1 to 5, wherein the side surface of the semiconductor substrate has a first surface and a second surface spaced apart from the first surface in a first direction intersecting the first surface, the opening of the at least one trench portion is located in the first surface, and the semiconductor device further comprises a back electrode layer arranged on the second surface side of the semiconductor substrate.

7. A semiconductor device as described in any one of claims 1 to 5, wherein the side surface of the semiconductor substrate has a first surface and a second surface spaced apart from the first surface in a first direction intersecting the first surface, the capacitance portion comprises a first capacitance portion located on the first surface side and a second capacitance portion located on the second surface side, the at least one trench portion includes at least one first trench portion having an opening in the first surface and at least one second trench portion having an opening in the second surface, at least a portion of the first capacitance portion is located inside the at least one first trench portion, and at least a portion of the second capacitance portion is located inside the at least one second trench portion.

8. The semiconductor device according to claim 7, wherein the first capacitance section and the second capacitance section are configured to have different electrostatic capacitances.

9. The semiconductor device according to claim 7 or 8, further comprising a through electrode penetrating within said semiconductor substrate from said lower surface to said upper surface.

10. The semiconductor device described in claim 9, wherein the semiconductor substrate comprises: a first substrate in which the at least one first trench portion is formed; and a second substrate in which the at least one second trench portion is formed, the first substrate has a first back surface arranged at a distance from the first surface in the first direction, the second substrate has a first back surface arranged at a distance from the first surface in the first direction, and the through electrode is arranged between at least a portion of the first back surface of the first substrate and at least a portion of the second back surface of the second substrate.

11. The semiconductor device according to claim 10, wherein, when viewed along the first direction, the through electrode occupies 50% or more of the area of ​​the first back surface or the second back surface.

12. A semiconductor device as described in claim 10 or 11, comprising a wiring layer located between the first back surface of the first substrate and the second back surface of the second substrate, the wiring layer including the through electrode and a dummy electrode arranged at a distance from the through electrode when viewed along the first direction.

13. The semiconductor device according to claim 12, wherein the wiring layer further includes a void portion.

14. The semiconductor device according to claim 1, wherein the capacitance section includes a plurality of portions arranged side by side at intervals from each other on the side surface.

15. A semiconductor device according to any one of claims 1 to 14, wherein the semiconductor substrate includes a conductive low resistance portion made of a low resistance semiconductor, and the first conductive layer or the second conductive layer of the capacitance portion is composed of the low resistance portion.

16. A semiconductor device according to any one of claims 1 to 15, wherein the semiconductor substrate includes a conductive low resistance portion made of a low resistance semiconductor, and a portion of the low resistance portion is exposed on a surface of the semiconductor device and functions as an external terminal.

17. A circuit board comprising: a semiconductor device according to any one of claims 1 to 16; and a mounting substrate having the mounting surface, wherein the semiconductor device is mounted on the mounting surface such that the lower surface of the semiconductor substrate faces the mounting surface of the mounting substrate.

18. The circuit board according to claim 17, wherein the mounting substrate has a core material, and the semiconductor device is disposed between an upper end and a lower end of the core material in a height direction of the semiconductor device.

19. The circuit board according to claim 17, further comprising another mounting substrate arranged to face the mounting substrate via the semiconductor device in a height direction of the semiconductor device, the semiconductor device being mounted on the mounting surface of the other mounting substrate such that the top surface of the semiconductor substrate faces the mounting surface of the other mounting substrate.

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