Semiconductor device, module member, and method for manufacturing semiconductor device

Abstract

The present invention provides a semiconductor device in which the electrostatic capacitance of a capacitive part can be increased. The semiconductor device comprises: a semiconductor substrate having one main surface and another main surface which is spaced apart from the one main surface at an interval in a thickness direction and which faces away from the one main surface in the thickness direction, the semiconductor substrate having at least one first trench part in the one main surface and at least one second trench part in the other main surface; a first capacitive part provided at least inside the first trench part and having a dielectric layer and two electrode layers sandwiching the dielectric layer; and a second capacitive part provided at least inside the second trench part and having a dielectric layer and two electrode layers sandwiching the dielectric layer.

Description

Semiconductor device, module member, and method for manufacturing semiconductor device

[0001] The present disclosure relates to a semiconductor device in which a capacitance portion is provided inside a trench portion.

[0002] As an example of a semiconductor device having a capacitance portion provided inside a trench portion, a capacitor is disclosed that includes a substrate having a recess on its surface, and a dielectric film and a conductive film provided inside the recess.

[0003] Patent No. 7052867

[0004] In a semiconductor device in which a capacitor is provided inside a trench, there is still room for improvement in terms of increasing the capacitance of the capacitor.

[0005] Therefore, an object of the present disclosure is to solve the above-mentioned problems and to provide a semiconductor device, a module member, and a method for manufacturing a semiconductor device that can increase the capacitance of a capacitive section.

[0006] In order to achieve the above-mentioned object, the semiconductor device according to the present disclosure comprises: a semiconductor substrate having one main surface and another main surface that is spaced apart in the thickness direction from the one main surface and faces the opposite direction from the one main surface in the thickness direction, the semiconductor substrate having at least one first trench portion in the one main surface and at least one second trench portion in the other main surface; a first capacitance portion that is provided at least inside the first trench portion and has a dielectric layer and two electrode layers that sandwich the dielectric layer; and a second capacitance portion that is provided at least inside the second trench portion and has a dielectric layer and two electrode layers that sandwich the dielectric layer.

[0007] A module member according to the present disclosure includes the semiconductor device; an electronic component; and a mounting substrate having a mounting surface on which the electronic component is mounted and in which the semiconductor device is provided.

[0008] Furthermore, the method for manufacturing a semiconductor device according to the present disclosure includes: a first trench portion forming step of forming at least one first trench portion in a main surface of a first substrate; a first capacitance portion forming step of forming a first capacitance portion having a dielectric layer and two electrode layers sandwiching the dielectric layer, in at least the first trench portion of the first substrate; a second trench portion forming step of forming at least one second trench portion in a main surface of a second substrate; a second capacitance portion forming step of forming a second capacitance portion having a dielectric layer and two electrode layers sandwiching the dielectric layer, in at least the second trench portion of the second substrate; and a bonding step of bonding a back surface of the first substrate relative to the main surface and a back surface of the second substrate relative to the main surface.

[0009] According to the present disclosure, it is possible to provide a semiconductor device, a module member, and a method for manufacturing a semiconductor device that can increase the capacitance of a capacitive section.

[0010] 1 is a plan view of a semiconductor device according to an embodiment of the present disclosure; FIG. 1 is a schematic cross-sectional view illustrating a cross section II-II of FIG. 1; FIG. 2 is an equivalent circuit diagram of a semiconductor device according to an embodiment of the present disclosure; FIG. 3 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure; FIG. 4 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure; FIG. 5 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure; FIG. 6 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0011] An example of the present disclosure will now be described with reference to the accompanying drawings. Note that the following description is merely illustrative in nature and is not intended to limit the present disclosure, its applications, or its uses. The drawings are schematic, and the ratios of dimensions and the like do not necessarily correspond to reality. Furthermore, in the following description, terms indicating specific directions or positions (e.g., terms including "upper," "lower," "right," "left," "front," and "rear") are used as necessary. However, the use of terms indicating specific directions or positions is intended to facilitate understanding of the present disclosure with reference to the drawings, and the meanings of these terms do not limit the technical scope of the present disclosure.

[0012] <Semiconductor Device> Fig. 1 is a plan view of a semiconductor device according to an embodiment of the present disclosure, and Fig. 2 is a schematic cross-sectional view showing a cross section taken along line II-II of Fig. 1.

[0013] As shown in Figures 1 and 2, the semiconductor device 10 includes a semiconductor substrate 20, a first capacitance section 31, a second capacitance section 32, a filling section 40, a first insulating layer 53, a second insulating layer 54, and an external terminal 51.

[0014] The semiconductor substrate 20 is, for example, a silicon (Si) substrate, and is formed from insulating, high-resistivity Si.

[0015] The semiconductor substrate 20 has one main surface 20A, the other main surface 20B, and a side surface 20F. The one main surface 20A and the other main surface 20B are spaced apart from each other in the thickness direction 101 of the semiconductor substrate 20. The one main surface 20A and the other main surface 20B face opposite each other in the thickness direction 101. The side surface 20F connects the outer edge of the one main surface 20A to the outer edge of the other main surface 20B.

[0016] The semiconductor substrate 20 has recesses 20Ea and 20Eb, four first trench portions 20Ca, and four second trench portions 20Cb.

[0017] The recess 20Ea is filled with a first electrode layer 321 of the first capacitance portion 31, which will be described later. The first electrode layer 321 of the first capacitance portion 31 forms part of one major surface 20A of the semiconductor substrate 20. The recess 20Eb is filled with a first electrode layer 321 of the second capacitance portion 32, which will be described later. The first electrode layer 321 of the second capacitance portion 32 forms part of the other major surface 20B of the semiconductor substrate 20. In this embodiment, the first electrode layer 321 of the first capacitance portion 31 is part of both the first capacitance portion 31 and the semiconductor substrate 20. In addition, in this embodiment, the second electrode layer of the second capacitance portion 32 is part of both the second capacitance portion 32 and the semiconductor substrate 20.

[0018] 2, one recess 20Ea is provided on one main surface 20A, and one recess 20Eb is provided on the other main surface 20B. That is, the semiconductor substrate 20 has two recesses. However, the number of recesses provided on the semiconductor substrate 20 is not limited to two. For example, multiple recesses 20Ea may be provided on the one main surface 20A. Also, for example, multiple recesses 20Eb may be provided on the other main surface 20B.

[0019] The four first trench portions 20Ca are provided in a portion of the first electrode layer 321 that constitutes a part of the one main surface 20A, and are recessed in the thickness direction 101. That is, each of the four first trench portions 20Ca is a recess provided in the one main surface 20A. The four second trench portions 20Cb are provided in a portion of the first electrode layer 321 that constitutes a part of the other main surface 20B, and are recessed in the thickness direction 101. That is, each of the four second trench portions 20Cb is a recess provided in the other main surface 20B.

[0020] The first trench portion 20Ca and the second trench portion 20Cb may have any shape. For example, the first trench portion 20Ca and the second trench portion 20Cb may be circular or rectangular when viewed along the thickness direction 101, or may be narrow grooves that extend in a curved or straight line. This groove may branch into multiple parts. The four first trench portions 20Ca may have the same shape or different shapes. The four second trench portions 20Cb may have the same shape or different shapes. The first trench portion 20Ca and the second trench portion 20Cb may have the same shape or different shapes.

[0021] 2 shows four first trench portions 20Ca and four second trench portions 20Cb, the number of first trench portions 20Ca included in the semiconductor substrate 20 is not limited to four, and the number of second trench portions 20Cb included in the semiconductor substrate 20 is not limited to four. The semiconductor substrate 20 only needs to have at least one first trench portion 20Ca and at least one second trench portion 20Cb.

[0022] The semiconductor substrate 20 has a hole 20D. The hole 20D penetrates the semiconductor substrate 20 in the thickness direction 101. The hole 20D extends in the thickness direction 101 and opens to both the one main surface 20A and the other main surface 20B. The hole 20D has a side surface 20Da. In this embodiment, the hole 20D is circular when viewed along the thickness direction 101. In other words, the hole 20D is cylindrical.

[0023] The hole 20D does not have to penetrate the semiconductor substrate 20 in the thickness direction 101. That is, the hole 20D may be open to only one of the one main surface 20A and the other main surface 20B. For example, as in a modified example shown in FIG. 19 , which will be described later, the hole 20D may be open to the one main surface 20A but not to the other main surface 20B. Furthermore, for example, the hole 20D may be open to the other main surface 20B but not to the one main surface 20A.

[0024] The shape of the hole 20D is arbitrary, similar to the shapes of the first trench 20Ca and the second trench 20Cb. For example, the hole 20D may be circular or rectangular when viewed along the thickness direction 101, or may be a narrow groove that extends in a curved or straight line. This groove may branch into multiple parts.

[0025] When viewed along the thickness direction 101, the hole 20D has a larger area than each of the first trench portions 20Ca and each of the second trench portions 20Cb. In other words, when viewed along the thickness direction 101, the hole 20D has a larger area than each of one of the first trench portions 20Ca and one of the second trench portions 20Cb.

[0026] The width of the hole 20D is greater than the width of each of the first trench portions 20Ca and the second trench portions 20Cb. Here, the width of the hole 20D is defined, for example, as follows: When the hole 20D is circular as viewed along the thickness direction 101, the width of the hole 20D is the diameter of the circle. When the hole 20D is rectangular as viewed along the thickness direction 101, the width of the hole 20D is the length of the short side of the rectangle. When the hole 20D is a narrow groove as viewed along the thickness direction 101, the width of the hole 20D is in a direction perpendicular to the extension direction of the groove. The above definitions also apply to the widths of the first trench portions 20Ca and the second trench portions 20Cb.

[0027] The width of the hole 20D is at least twice the width of each of the first trenches 20Ca and the second trenches 20Cb. Preferably, the width of the hole 20D is at least five times the width of each of the first trenches 20Ca and the second trenches 20Cb. More preferably, the width of the hole 20D is at least ten times the width of each of the first trenches 20Ca and the second trenches 20Cb.

[0028] 2 shows one hole 20D, the number of holes 20D in the semiconductor substrate 20 is not limited to one. The semiconductor substrate 20 may have multiple holes 20D. The semiconductor substrate 20 may not have any holes 20D.

[0029] The first capacitance portion 31 is provided inside the recess 20Ea, inside the first trench portion 20Ca, and on the one main surface 20A. That is, the first capacitance portion 31 is provided at least inside the first trench portion 20Ca. The second capacitance portion 32 is provided inside the recess 20Eb, inside the second trench portion 20Cb, and on the other main surface 20B. That is, the second capacitance portion 32 is provided at least inside the second trench portion 20Cb.

[0030] When viewed along the thickness direction 101, at least a part of the first capacitance portion 31 and at least a part of the second capacitance portion 32 are positioned to overlap each other. In this embodiment, when viewed along the thickness direction 101, at least the entire first capacitance portion 31 and at least the entire second capacitance portion 32 are positioned to overlap each other.

[0031] The following describes the configuration of the first capacitance section 31. The configuration of the second capacitance section 32 is the same as the configuration of the first capacitance section 31. Therefore, the description of the second capacitance section 32 will be omitted in principle and will be described only when necessary.

[0032] The first capacitance portion 31 has a dielectric layer and an electrode layer. In this embodiment, the first capacitance portion 31 includes two dielectric layers (a first dielectric layer 311 and a second dielectric layer 312) and three electrode layers (a first electrode layer 321, a second electrode layer 322, and a third electrode layer 323).

[0033] The dielectric layer includes a dielectric. In this embodiment, the dielectric layer includes silicon dioxide (SiO ２ ) and silicon nitride (Si ３ N ４ ) and hafnium oxide (HfO ２ The first dielectric layer 311 and the second dielectric layer 312 may be made of the same material or different materials.

[0034] The electrode layers include a conductor. In this embodiment, the electrode layers are made of a conductor such as a metal such as copper, low-resistivity silicon (Si) such as conductive n-type Si or p-type Si, or polysilicon (Poly-Si). The first electrode layer 321, the second electrode layer 322, and the third electrode layer 323 may be made of the same material or different materials.

[0035] The first electrode layer 321 is provided inside the recess 20Ea. In this embodiment, the first electrode layer 321 is made of low-resistivity silicon (Si). As described above, the first electrode layer 321 has four first trench portions 20Ca in a portion that constitutes a part of the one main surface 20A.

[0036] The first dielectric layer 311 is stacked on the first electrode layer 321 and the semiconductor substrate 20, both inside and outside the four first trench portions 20Ca. The first dielectric layer 311 is stacked on the first electrode layer 321 along the first trench portions 20Ca, inside the four first trench portions 20Ca. The first dielectric layer 311 is stacked on the first electrode layer 321 and one main surface 20A of the semiconductor substrate 20, outside the four first trench portions 20Ca.

[0037] The second electrode layer 322 is stacked on the first dielectric layer 311 across the inside and outside of the four first trench portions 20Ca. The second electrode layer 322 is stacked on the first dielectric layer 311 inside the four first trench portions 20Ca and along the first trench portions 20Ca.

[0038] The second dielectric layer 312 is stacked on the second electrode layer 322 across the inside and outside of the four first trench portions 20Ca. The second dielectric layer 312 is stacked on the second electrode layer 322 inside the four first trench portions 20Ca and along the first trench portions 20Ca.

[0039] The third electrode layer 323 is stacked on the second dielectric layer 312 across the inside and outside of the four first trench portions 20Ca. The third electrode layer 323 is stacked on the second dielectric layer 312 so as to fill spaces not shown in the first dielectric layer 311, the second electrode layer 322, and the second dielectric layer 312 inside the four first trench portions 20Ca.

[0040] As a result of the dielectric layers and electrode layers being stacked as described above, the first dielectric layer 311 is sandwiched between the first electrode layer 321 and the second electrode layer 322, and the second dielectric layer 312 is sandwiched between the second electrode layer 322 and the third electrode layer 323. That is, the first capacitance unit 31 has at least a dielectric layer and two electrode layers sandwiching the dielectric layer. In this embodiment, the first capacitance unit 31 has two pairs of a dielectric layer and two electrode layers sandwiching the dielectric layer. One of the two pairs is composed of the first dielectric layer 311 and the first electrode layer 321 and the second electrode layer 322 sandwiching the first dielectric layer 311. The other of the two pairs is composed of the second dielectric layer 312 and the second electrode layer 322 and the third electrode layer 323 sandwiching the second dielectric layer 312.

[0041] Similar to the first capacitance section 31, the second capacitance section 32 has two dielectric layers (a first dielectric layer 311 and a second dielectric layer 312) and three electrode layers (a first electrode layer 321, a second electrode layer 322, and a third electrode layer 323).

[0042] The first electrode layer 321 of the second capacitance portion 32 is provided inside the recess 20Eb. As described above, the first electrode layer 321 of the second capacitance portion 32 has four second trench portions 20Cb in a portion that forms part of the other main surface 20B.

[0043] The first dielectric layer 311, the second electrode layer 322, the second dielectric layer 312, and the third electrode layer 323 of the second capacitance portion 32 (in other words, the layers of the second capacitance portion 32) are stacked in the same manner as the first dielectric layer 311, the second electrode layer 322, the second dielectric layer 312, and the third electrode layer 323 of the first capacitance portion 31. The layers of the second capacitance portion 32 are stacked throughout the interior and exterior of the four second trench portions 20Cb.

[0044] Each of the first capacitance section 31 and the second capacitance section 32 may have only one set of a dielectric layer and two electrode layers sandwiching the dielectric layer, or may have three or more sets. The number of dielectric layers and the number of electrode layers in the first capacitance section 31 may be the same as or different from the number of dielectric layers and the number of electrode layers in the second capacitance section 32.

[0045] The filling portion 40 is provided inside the hole 20D. The filling portion 40 extends from one end to the other end in the thickness direction 101 of the hole 20D. The upper surface 40A of the filling portion 40 is a portion of the filling portion 40 located at one end of the hole 20D in the thickness direction 101. The upper surface 40A of the filling portion 40 constitutes a part of one main surface 20A of the semiconductor substrate 20. The lower surface 40B of the filling portion 40 is a portion of the filling portion 40 located at the other end of the hole 20D in the thickness direction 101. The lower surface 40B of the filling portion 40 constitutes a part of the other main surface 20B of the semiconductor substrate 20.

[0046] The filling portion 40 contains a conductive material. In this embodiment, the filling portion 40 is configured with a conductive layer 42 made of copper as the conductive material. Note that in this embodiment, the filling portion 40 is configured only with the conductive material, but the filling portion 40 may also contain a material other than the conductive material. An example in which the filling portion 40 contains a material other than the conductive material will be described later.

[0047] The semiconductor device 10 may not have the filling portion 40. In this case, the semiconductor substrate 20 may not have the hole portion 20D.

[0048] The first insulating layer 53 and the second insulating layer 54 are made of an insulator. The first insulating layer 53 and the second insulating layer 54 may be made of an inorganic or organic material as long as the material has high insulating properties. In this embodiment, the first insulating layer 53 and the second insulating layer 54 are provided on the one main surface 20A and the other main surface 20B, respectively.

[0049] The first insulating layer 53 provided on the one principal surface 20A is laminated so as to cover a part of the exposed part on the one principal surface 20A side of each layer (first electrode layer 321, second electrode layer 322, third electrode layer 323, first dielectric layer 311, and second dielectric layer 312) of the first capacitance section 31. The first insulating layer 53 provided on the other principal surface 20B is laminated so as to cover a part of the exposed part on the other principal surface 20B side of each layer (first electrode layer 321, second electrode layer 322, third electrode layer 323, first dielectric layer 311, and second dielectric layer 312) of the second capacitance section 32.

[0050] The second insulating layer 54 provided on the one principal surface 20A is laminated so as to cover a part of the one principal surface 20A, the first insulating layer 53, and parts of the second dielectric layer 312, the second electrode layer 322, and the third electrode layer 323 of the first capacitance portion 31 that are exposed on the one principal surface 20A side. The second insulating layer 54 provided on the other principal surface 20B is laminated so as to cover a part of the other principal surface 20B, the first insulating layer 53, and parts of the second dielectric layer 312, the second electrode layer 322, and the third electrode layer 323 of the second capacitance portion 32 that are exposed on the other principal surface 20B side.

[0051] The external terminals 51 are provided on at least one of the first principal surface 20A and the second principal surface 20B. The external terminals 51 may also be provided on the side surfaces 20F. In this embodiment, the external terminals 51 are provided on the first principal surface 20A and the second principal surface 20B. The external terminals 51 are made of a conductive material such as nickel (Ni) or gold (Au). In this embodiment, the external terminals 51 have a multilayer structure of copper (Cu), nickel, and gold.

[0052] In the present embodiment, the external terminals 51 include a first external terminal 511, a second external terminal 512, a third external terminal 513, a fourth external terminal 514, a fifth external terminal 515, and a sixth external terminal 516. In the present embodiment, the first external terminal 511, the second external terminal 512, and the third external terminal 513 are provided on one main surface 20A of the semiconductor substrate 20. In the present embodiment, the fourth external terminal 514, the fifth external terminal 515, and the sixth external terminal 516 are provided on the other main surface 20B of the semiconductor substrate 20. In the present embodiment, the first external terminal 511, the second external terminal 512, the third external terminal 513, the fourth external terminal 514, the fifth external terminal 515, and the sixth external terminal 516 are made of the same material, but may be made of different materials.

[0053] The first external terminal 511, the second external terminal 512, and the third external terminal 513 are insulated from one another by the second insulating layer 54 on the one main surface 20A side. The fourth external terminal 514, the fifth external terminal 515, and the sixth external terminal 516 are insulated from one another by the second insulating layer 54 on the other main surface 20B side.

[0054] The first external terminal 511 is laminated on the first electrode layer 321, the third electrode layer 323, and the first insulating layer 53 of the first capacitance section 31. As a result, the first external terminal 511 is in contact with the first electrode layer 321 and the third electrode layer 323 of the first capacitance section 31. In other words, the first electrode layer 321 and the third electrode layer 323 of the first capacitance section 31 are electrically connected to each other via the first external terminal 511.

[0055] On the other hand, a first insulating layer 53 is provided between the first external terminal 511 and the first dielectric layer 311, the second electrode layer 322, and the second dielectric layer 312 of the first capacitance section 31. As a result, the first external terminal 511 and the first dielectric layer 311, the second electrode layer 322, and the second dielectric layer 312 of the first capacitance section 31 are insulated from each other by the first insulating layer 53.

[0056] The second external terminal 512 is laminated on the second electrode layer 322 of the first capacitance section 31. As a result, the second external terminal 512 and the second electrode layer 322 of the first capacitance section 31 are in contact with each other and electrically connected.

[0057] The third external terminal 513 is laminated on the upper surface 40A of the filling portion 40. As a result, the third external terminal 513 and the filling portion 40 are in contact with each other and electrically connected.

[0058] The fourth external terminal 514 is laminated on the first electrode layer 321, the third electrode layer 323, and the first insulating layer 53 of the second capacitance section 32. As a result, the fourth external terminal 514 is in contact with the first electrode layer 321 and the third electrode layer 323 of the second capacitance section 32. In other words, the first electrode layer 321 and the third electrode layer 323 of the second capacitance section 32 are electrically connected to each other via the fourth external terminal 514.

[0059] On the other hand, a first insulating layer 53 is provided between the fourth external terminal 514 and the first dielectric layer 311, the second electrode layer 322, and the second dielectric layer 312 of the second capacitance section 32. As a result, the fourth external terminal 514 and the first dielectric layer 311, the second electrode layer 322, and the second dielectric layer 312 of the second capacitance section 32 are insulated from each other by the first insulating layer 53.

[0060] The fifth external terminal 515 is laminated on the second electrode layer 322 of the second capacitance section 32. As a result, the fifth external terminal 515 and the second electrode layer 322 of the second capacitance section 32 are in contact with each other and electrically connected.

[0061] The sixth external terminal 516 is laminated on the lower surface 40B of the filling portion 40. As a result, the sixth external terminal 516 and the filling portion 40 are in contact with each other and electrically connected.

[0062] In this embodiment, the semiconductor device 10 is mounted on a printed circuit board (not shown) or the like via external terminals 51 provided on the one main surface 20A and the other main surface 20B. That is, in this embodiment, the one main surface 20A and the other main surface 20B are the mounting surfaces of the semiconductor device 10. However, the side surface 20F may also be the mounting surface of the semiconductor device 10. In this case, the external terminals 51 are provided on the side surface 20F of the semiconductor substrate 20, and the semiconductor device 10 is mounted on a printed circuit board or the like via the external terminals 51 provided on the side surface 20F.

[0063] 3 is an equivalent circuit diagram of the semiconductor device according to the embodiment of the present disclosure. The semiconductor device 10 is configured as described above, and thereby forms a circuit as shown in FIG.

[0064] 3, a capacitor C1 is formed by the first dielectric layer 311 of the first capacitance section 31 and the first electrode layer 321 and second electrode layer 322 that sandwich the first dielectric layer 311. A capacitor C2 is formed by the second dielectric layer 312 of the first capacitance section 31 and the second electrode layer 322 and third electrode layer 323 that sandwich the second dielectric layer 312.

[0065] One electrode of the capacitor C1 (the first electrode layer 321 of the first capacitance section 31) and one electrode of the capacitor C2 (the third electrode layer 323 of the first capacitance section 31) are connected to a first external terminal 511 (terminal T3 in FIGS. 2 and 3). The other electrodes of the capacitors C1 and C2 (the second electrode layer 322 of the first capacitance section 31) are connected to a second external terminal 512 (terminal T4 in FIGS. 2 and 3).

[0066] One electrode of the capacitor C3 (the first electrode layer 321 of the second capacitance section 32) and one electrode of the capacitor C4 (the third electrode layer 323 of the second capacitance section 32) are connected to a fourth external terminal 514 (terminal T5 in FIGS. 2 and 3). The other electrodes (the second electrode layer 322) of the capacitors C3 and C4 are connected to a fifth external terminal 515 (T6 in FIGS. 2 and 3).

[0067] The filling portion 40 constitutes a resistor R. One end of the resistor R (the upper surface 40A of the filling portion 40) is connected to a third external terminal 513 (terminal T1 in FIGS. 2 and 3 ). The other end of the resistor R (the lower surface 40B of the filling portion 40) is connected to a sixth external terminal 516 (terminal T2 in FIGS. 2 and 3 ).

[0068] The semiconductor device 10 described above has the following dimensions, for example. Specifically, the length in the thickness direction 101 is 0.15 mm, the length in the width direction 102 is 0.6 mm, and the length in the depth direction, which is a direction perpendicular to the thickness direction 101 and the width direction 102, is 0.3 mm. The depth (length in the thickness direction 101) of each of the first trench portion 20Ca and the second trench portion 20Cb is 30 μm. The thickness of the electrode layers (first electrode layer 321, second electrode layer 322, and third electrode layer 323) is 1000 nm. Note that when the electrode layers are made of titanium nitride (TiN), the thickness of the electrode layers is 20 nm. The thickness of the dielectric layers (first dielectric layer 311 and second dielectric layer 312) is 10 nm.

[0069] <Method for manufacturing semiconductor device> A method for manufacturing the semiconductor device 10 according to an embodiment of the present disclosure will be described below with reference to Figures 4 to 11 and Figure 2. Figures 4 to 11 are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to an embodiment of the present disclosure.

[0070] The semiconductor device 10 is manufactured by dividing a laminate into a plurality of pieces. The laminate is formed by integrating a plurality of semiconductor devices 10 in an arranged state. For ease of explanation, only a portion of the laminate corresponding to one semiconductor device 10 is shown in FIGS. 4 to 11 . The manufacturing method for the semiconductor device 10 according to this embodiment includes a hole forming step, a filling portion forming step, a recess forming step, a capacitance portion forming step (an electrode layer forming step, a dielectric layer forming step, and a trench portion forming step), a first insulating layer forming step, a second insulating layer forming step, an external terminal forming step, a bonding step, and a dividing step.

[0071] The first substrate 21 and the second substrate 22 are manufactured in the hole forming process, the filling portion forming process, the recess forming process, the capacitance portion forming process, the first insulating layer forming process, the second insulating layer forming process, and the external terminal forming process. In the bonding process, two substrates (the first substrate 21 and the second substrate 22) are bonded to form a single semiconductor substrate 20. In this example of the manufacturing method, the first substrate 21 and the second substrate 22 have the same configuration. Therefore, the following descriptions of the hole forming process, the filling portion forming process, the capacitance portion forming process, the first insulating layer forming process, the second insulating layer forming process, and the external terminal forming process will focus on the manufacturing method of the first substrate 21. Meanwhile, the description of the manufacturing method of the second substrate 22 will be omitted in principle and will be explained only as needed.

[0072] (Hole Forming Process) First, the hole forming process is performed. In the hole forming process, as shown in Fig. 4, holes 20D penetrating the first substrate 21 in the thickness direction 101 are formed in the first substrate 21. For example, a hard mask is formed on the first substrate 21, patterning is performed on the hard mask corresponding to the holes 20D, and deep silicon etching is performed, thereby forming the holes 20D in the first substrate 21. After deep silicon etching is performed, the hard mask is removed.

[0073] (Filling Portion Forming Process) Next, the filling portion forming process is performed. In the filling portion forming process, as shown in FIG. 5, a conductive paste is filled into the hole 20D. This paste corresponds to the conductive layer 42 of the filling portion 40. For example, the filling portion 40 is formed by forming a seed, performing via-filling plating, removing the seed, and planarizing. Note that the filling portion 40 may be filled by a method other than the above-described formation method. For example, a conductive material such as copper (Cu) or aluminum (Al) may be filled as the filling portion 40 by a method such as sputtering, wet plating, or paste.

[0074] (Capacitor portion forming process) Next, the capacitor portion forming process is performed. The capacitor portion forming process is divided into an electrode layer forming process, a dielectric layer forming process, and a trench portion forming process. The capacitor portion forming process in the manufacture of the first substrate 21 is an example of a first capacitor portion forming process. The capacitor portion forming process in the manufacture of the second substrate 22 is an example of a second capacitor portion forming process. The trench portion forming process in the manufacture of the first substrate 21 is an example of a first trench portion forming process. The trench portion forming process in the manufacture of the second substrate 22 is an example of a second trench portion forming process.

[0075] In the capacitance portion forming step, an electrode layer forming step and a dielectric layer forming step are alternately performed, and the trench portion forming step is performed after the first electrode layer forming step and before the first dielectric layer forming step.

[0076] In the first electrode layer formation step, as shown in FIG. 6 , impurities are doped into the semiconductor substrate 20 as a high-resistance portion formed of high-resistance Si. As a result, a recess 20Ea is formed in the semiconductor substrate 20 as a high-resistance portion, and a first electrode layer 321 as a low-resistance portion is formed in the recess 20Ea. The first electrode layer 321 is formed, for example, by forming a patterned resist at the position of the recess 20Ea, etching the impurity-doped silicon, and removing the resist. The first electrode layer 321 constitutes a part of one main surface 21A of the first substrate 21.

[0077] In the trench portion forming step, four first trench portions 20Ca are formed in parts of one main surface 21A of the first electrode layer 321. The first trench portions 20Ca are formed, for example, by hard mask patterning and deep silicon etching, similar to the hole portions 20D. Note that in the trench portion forming step in manufacturing the second substrate 22, four second trench portions 20Cb are formed in the first electrode layer 321.

[0078] Next, a dielectric layer forming process and an electrode layer forming process are alternately performed. As a result, dielectric layers and electrode layers are alternately stacked (deposited) on one main surface 20A of the first substrate 21 and on the surface constituting the first trench portion 20Ca. In detail, as shown in FIG. 7 , a first dielectric layer 311 is formed on the first substrate 21, the filling portion 40, and the first electrode layer 321. A second electrode layer 322 is formed on the first dielectric layer 311. A second dielectric layer 312 is formed on the second electrode layer 322. A third electrode layer 323 is formed on the second dielectric layer 312.

[0079] As described above, in the capacitive portion forming step in the manufacture of the first substrate 21, a first capacitive portion 31 having a dielectric layer and two electrode layers sandwiching the dielectric layer is formed in at least the first trench portion 20Ca of the first substrate 21. Similarly, in the capacitive portion forming step in the manufacture of the second substrate 22, a second capacitive portion 32 having a dielectric layer and two electrode layers sandwiching the dielectric layer is formed in at least the second trench portion 20Cb of the second substrate 22.

[0080] In the dielectric layer forming process and the electrode layer forming process, after the dielectric layers 311, 312 and the electrode layers 322, 323 are formed, photolithography and etching are performed on the dielectric layers 311, 312 and the electrode layers 322, 323. As a result, parts of the dielectric layers 311, 312 and the electrode layers 322, 323 are removed, as shown in FIG.

[0081] In this embodiment, the trench portion forming process is defined as part of the capacitance portion forming process. However, the trench portion forming process may be defined separately from the capacitance portion forming process. In this case, the capacitance portion forming process is divided into an electrode layer forming process and a dielectric layer forming process. Then, after the electrode layer forming process of the first capacitance portion forming process is performed, the trench portion forming process is performed, and then the remaining steps of the capacitance portion forming process are performed.

[0082] (First Insulating Layer Forming Process) Next, the first insulating layer forming process is performed. In the first insulating layer forming process, a first insulating layer 53 is laminated as shown in Fig. 9. Specifically, the first insulating layer 53 is deposited on the upper surface of Fig. 8 (the surface on the one main surface 21A side of the first base material 21), and is patterned by photolithography and dry etching at a position corresponding to the first insulating layer 53 in Fig. 9.

[0083] (Second Insulating Layer Forming Step) Next, the second insulating layer forming step is performed. In the second insulating layer forming step, a second insulating layer 54 is laminated as shown in Fig. 10 . Specifically, the second insulating layer 54 is deposited on the upper surface of Fig. 9 (the surface on the one main surface 21A side of the first base material 21) and patterned by photolithography and dry etching into a position corresponding to the second insulating layer 54 in Fig. 10 . Note that the second insulating layer forming step may be performed before the first insulating layer forming step or may be performed in parallel with the first insulating layer forming step.

[0084] The first insulating layer 53 and the second insulating layer 54 may be formed by known means other than deposition, such as CVD (Chemical Vapor Deposition), for example, spin coating or film lamination. If necessary, a protective layer, which is an insulating layer, may be provided on the second insulating layer 54. For example, the protective layer is made of an organic resin such as epoxy, polyimide, or acrylic.

[0085] (External Terminal Forming Process) Next, the external terminal forming process is carried out. In the external terminal forming process, as shown in Fig. 11 , a first external terminal 511, a second external terminal 512, and a third external terminal 513 among the external terminals 51 are formed. In detail, a conductive layer as the external terminals 51 is formed at a predetermined position (position shown in Fig. 2 ) on the upper surface (surface on the one main surface 21A side of the first base material 21) in Fig. 10 by a known means such as metal sputtering, electroless plating, or paste. In the external terminal forming process in the manufacturing method of the second base material 22, a fourth external terminal 514, a fifth external terminal 515, and a sixth external terminal 516 among the external terminals 51 are formed.

[0086] The external terminals 51 may be composed of a plurality of conductive layers. By forming the external terminals 51 with a plurality of conductive layers, the external terminals 51 have electromigration resistance and the barrier properties and solder wettability of the external terminals 51 are improved.

[0087] (Bonding Process) Next, the bonding process is performed. In the bonding process, as shown in FIG. 2 , the other main surface 21B of the first substrate 21 and the other main surface 22B of the second substrate 22 are bonded to produce one semiconductor substrate 20. The other main surface 21B is the surface opposite to the one main surface 21A in the thickness direction 101 and faces away from the one main surface 21A. The other main surface 22B is the surface opposite to the one main surface 22A in the thickness direction 101 and faces away from the one main surface 22A. The other main surface 21B is an example of a back surface relative to the main surface of the first substrate. The other main surface 22B is an example of a back surface relative to the main surface of the second substrate. Note that in the semiconductor substrate 20 after bonding the first substrate 21 and the second substrate 22, the interface between the first substrate 21 and the second substrate 22 may disappear. Therefore, in the figure, the interface between the first substrate 21 and the second substrate 22 is indicated by a dashed line.

[0088] Before the first substrate 21 and the second substrate 22 are bonded, the first substrate 21 and the second substrate 22 are ground or polished to adjust the lengths of the first substrate 21 and the second substrate 22 in the thickness direction 101. At this time, the other main surface 21B of the first substrate 21 and the other main surface 22B of the second substrate 22 are made sufficiently flat, which facilitates bonding of the first substrate 21 and the second substrate 22 in the bonding step. Furthermore, as an activation treatment, functional groups or partial sputtered films may be formed to increase bonding strength.

[0089] After grinding or polishing the first base material 21 and the second base material 22, the other main surface 21B of the first base material 21 and the other main surface 22B of the second base material 22 are bonded together. The bonding is performed by a known method such as thermocompression bonding or adhesion.

[0090] In this manufacturing method, since no chip components or the like are mounted on either of the other main surfaces 21B, 22B, the first substrate 21 and the second substrate 22 are bonded together. However, if chip components or the like are mounted on at least one of the other main surfaces 21B, 22B, the first substrate 21 and the second substrate 22 may be bonded together via the chip components or the like. For example, if chip components or the like are mounted on one of the other main surfaces 21B, 22B, the chip components or the like may be bonded to the other of the other main surfaces 21B, 22B. Furthermore, for example, if chip components or the like are mounted on both the other main surfaces 21B, 22B, the chip components or the like mounted on the other main surface 21B may be bonded to the chip components or the like mounted on the other main surface 22B.

[0091] (Singulation Step) Next, the singulation step is performed. In the singulation step, the stack in which the plurality of semiconductor devices 10 are arranged is cut into the plurality of semiconductor devices 10 .

[0092] In the above-described exemplary manufacturing method, the semiconductor substrate 20 is manufactured through a bonding process in which two substrates (the first substrate 21 and the second substrate 22) each having a trench portion and a capacitance portion formed therein are bonded together. However, the bonding process may not be performed. In this case, instead of manufacturing two substrates, a single substrate is manufactured. Specifically, in the recess forming process, a recess 20Ea is formed on one main surface 20A of the semiconductor substrate 20, and a recess 20Eb is formed on the other main surface 20B of the semiconductor substrate 20. In addition, in the capacitance portion forming process, a first capacitance portion 31 is formed on one main surface 20A of the semiconductor substrate 20, and a second capacitance portion 32 is formed on the other main surface 20B of the semiconductor substrate 20. In addition, in the trench portion forming process, a first trench portion 20Ca is formed on the one main surface 20A side of the semiconductor substrate 20, and a second trench portion 20Cb is formed on the other main surface 20B side of the semiconductor substrate 20.

[0093] According to this embodiment, trench portions (first trench portion 20Ca and second trench portion 20Cb) are provided on both the one main surface 20A and the other main surface 20B of the semiconductor substrate 20. Furthermore, a first capacitance portion 31 is provided in the first trench portion 20Ca, and a second capacitance portion 32 is provided in the second trench portion 20Cb. Therefore, the capacitance of the capacitance portions (first capacitance portion 31 and second capacitance portion 32) can be increased compared to a configuration in which trench portions are provided on only one side of the substrate and capacitance portions are provided in the trench portions.

[0094] According to this embodiment, the filling portion 40 containing a conductive material can function as a shield against noise. This allows the filling portion 40 to reduce noise traveling from the outside of the first capacitance portion 31 and the second capacitance portion 32 through the filling portion 40 to the first capacitance portion 31 and the second capacitance portion 32.

[0095] By using the fill portion 40 as wiring in the semiconductor device 10, it is possible to reduce the amount of wiring routed to the semiconductor device 10. This makes it possible to reduce the parasitic capacitance generated in the semiconductor device 10. Furthermore, by using the fill portion 40 as wiring in the semiconductor device 10, the fill portion 40 can be used to extract signals from the semiconductor device 10, thereby improving the design freedom of the semiconductor device 10.

[0096] According to this embodiment, the area of ​​the hole 20D as viewed along the thickness direction 101 is larger than the area of ​​each of the first trenches 20Ca and the second trenches 20Cb. This reduces manufacturing variations in the hole 20D. As a result, it is easy to fill the hole 20D with the filling portion 40. Furthermore, because the area of ​​the hole 20D as viewed along the thickness direction 101 is large, it is easy to form a deep hole 20D.

[0097] In the capacitor disclosed in Patent Document 1, a dielectric film and a conductive film are provided on the front surface side of the substrate, which makes it difficult to handle signals from the back surface of the substrate. In contrast, according to this embodiment, the hole 20D is open to both the one main surface 20A and the other main surface 20B; in other words, the hole 20D penetrates the semiconductor substrate 20 in the thickness direction 101. In this case, it is possible to easily handle signals from the other main surface 20B to the first capacitance section 31 provided on the one main surface 20A side. It is also possible to easily handle signals from the one main surface 20A to the second capacitance section 32 provided on the other main surface 20B side.

[0098] According to this embodiment, when the semiconductor device 10 is mounted on a substrate via a paste such as solder, the mounting can be easily performed by applying the paste to the external terminals 51 .

[0099] According to this embodiment, the area of ​​the semiconductor device 10 can be reduced when viewed along the thickness direction 101 compared to a configuration in which the first capacitance section 31 and the second capacitance section 32 are in positions where they do not overlap when viewed along the thickness direction 101.

[0100] According to this manufacturing method, the semiconductor device 10 is manufactured by bonding two base materials (the first base material 21 and the second base material 22). Therefore, the semiconductor device 10 can be manufactured easily.

[0101] The following describes modified examples of this embodiment and the configuration of the module member 70. In the following description, the same reference numerals are used to designate components that have been previously described, and descriptions of those components will be omitted in principle and will be provided only when necessary.

[0102] <First Modification of Semiconductor Device> FIG. 12 is a schematic cross-sectional view of a first modification of the semiconductor device according to the embodiment of the present disclosure.

[0103] The semiconductor device 10A in Modification 1 may include external terminals 51 that protrude more than other portions. For example, as shown in FIG. 12 , the semiconductor device 10A includes a first columnar external terminal 521 and a second columnar external terminal 522 as the external terminals 51 that protrude more than other portions. The semiconductor device 10A may also include an insulating protective layer that covers at least one of the first main surface 20A and the second main surface 20B. For example, as shown in FIG. 12 , the semiconductor device 10A includes an insulating protective film 55 that is provided on the first main surface 20A and the second main surface 20B and covers both the first main surface 20A and the second main surface 20B.

[0104] The first columnar external terminal 521 is provided on the first external terminal 511. That is, the first columnar external terminal 521 is provided on the one main surface 20A via the first external terminal 511. The second columnar external terminal 522 is provided on the second external terminal 512. That is, the second columnar external terminal 522 is provided on the one main surface 20A via the second external terminal 512. The first columnar external terminal 521 and the second columnar external terminal 522 are examples of specific external terminals. The one main surface 20A is an example of a specific main surface.

[0105] The first columnar external terminal 521 and the second columnar external terminal 522 protrude in the thickness direction 101 from the one main surface 20A.

[0106] The protrusion lengths of the first columnar external terminal 521 and the second columnar external terminal 522 from the one main surface 20A in the thickness direction 101 are greater than the protrusion lengths of other portions provided on the one main surface 20A from the one main surface 20A in the thickness direction 101. Here, the other portions refer to portions provided on the one main surface 20A excluding the first columnar external terminal 521 and the second columnar external terminal 522. In the configuration shown in FIG. 12 , the other portions are the first capacitive portion 31, the first external terminal 511, the second external terminal 512, the first insulating layer 53, the second insulating layer 54, and the protective film 55.

[0107] 12 , of the external terminals 51, the first columnar external terminal 521 and the second columnar external terminal 522 correspond to the specific external terminals. However, the other external terminals 51 (the first external terminal 511, the second external terminal 512, the third external terminal 513, the fourth external terminal 514, the fifth external terminal 515, and the sixth external terminal 516) may also correspond to the specific external terminals. In other words, at least one of the external terminals 51 may also correspond to the specific external terminal. The specific external terminal protrudes in the thickness direction 101 from the specific main surface, and the protruding length is greater than that of the other portions.

[0108] 12 , a first columnar external terminal 521 and a second columnar external terminal 522 serving as specific external terminals are provided on the one main surface 20A. However, the specific external terminals may be provided on the other main surface 20B. The specific external terminals may be provided on both the one main surface 20A and the other main surface 20B.

[0109] The protective film 55 provided on the one main surface 20A covers the first capacitance portion 31, the first external terminal 511, the second external terminal 512, the first insulating layer 53, and the second insulating layer 54. The protective film 55 provided on the one main surface 20A covers only the first columnar external terminal 521 and the second columnar external terminal 522 except for their tip portions. As a result, the tip portions of the first columnar external terminal 521 and the second columnar external terminal 522 protrude in the thickness direction 101 from the protective film 55 and are exposed to the outside of the semiconductor device 10A. As described above, the protective film 55 provided on the one main surface 20A does not completely cover the one main surface 20A.

[0110] The protective film 55 provided on the other principal surface 20B covers the first capacitance portion 31, the first external terminal 511, the second external terminal 512, the first insulating layer 53, and the second insulating layer 54. In other words, the protective film 55 provided on the other principal surface 20B completely covers the other principal surface 20B.

[0111] As described above, the protective film 55 covers the other main surface 20B of the one main surface 20A and the other main surface 20B, but does not cover the one main surface 20A. Note that the protective film 55 may cover the one main surface 20A of the one main surface 20A and the other main surface 20B, but not cover the other main surface 20B. Furthermore, the protective film 55 may completely cover both the one main surface 20A and the other main surface 20B.

[0112] The semiconductor device 10A has two holes 20D and two filling sections 40. The two filling sections 40 are a first filling section 401 and a second filling section 402. The first filling section 401 fills one of the two holes 20D. The second filling section 402 fills the other of the two holes 20D.

[0113] The semiconductor device 10A has a first external terminal 511, a second external terminal 512, a fourth external terminal 514, and a fifth external terminal 515, but does not have a third external terminal 513 or a sixth external terminal 516.

[0114] The first external terminal 511 is in contact with the first filling portion 401 and the first columnar external terminal 521 in addition to the first electrode layer 321 and the third electrode layer 323 of the first capacitance portion 31. The fourth external terminal 514 is in contact with the first filling portion 401 in addition to the first electrode layer 321 and the third electrode layer 323 of the second capacitance portion 32. As a result, the first electrode layer 321 and the third electrode layer 323 of the first capacitance portion 31, the first electrode layer 321 and the third electrode layer 323 of the second capacitance portion 32, and the first columnar external terminal 521 are electrically connected to one another via the first external terminal 511, the fourth external terminal 514, and the first filling portion 401.

[0115] The second external terminal 512 is in contact with the second filling portion 402 and the second columnar external terminal 522 in addition to the second electrode layer 322 of the first capacitance portion 31. The fifth external terminal 515 is in contact with the second filling portion 402 in addition to the second electrode layer 322 of the second capacitance portion 32. As a result, the second electrode layer 322 of the first capacitance portion 31, the second electrode layer 322 of the second capacitance portion 32, and the second columnar external terminal 522 are electrically connected to one another via the second external terminal 512, the fifth external terminal 515, and the second filling portion 402.

[0116] As described above, the filling section 40 is electrically connected to both the first capacitance section 31 and the second capacitance section 32 .

[0117] In the semiconductor device 10A, the material of the first external terminal 511 and the second external terminal 512 located on one main surface 20A is different from the material of the fourth external terminal 514 and the fifth external terminal 515 located on the other main surface 20B. The first external terminal 511 and the second external terminal 512 located on one main surface 20A are an example of a first wiring layer. The fourth external terminal 514 and the fifth external terminal 515 located on the other main surface 20B are an example of a second wiring layer.

[0118] The material of the first columnar external terminal 521 and the second columnar external terminal 522 may be the same as the material of the first external terminal 511 and the second external terminal 512. The material of the first columnar external terminal 521 and the second columnar external terminal 522 may be the same as the material of the fourth external terminal 514 and the fifth external terminal 515. The material of the first columnar external terminal 521 and the second columnar external terminal 522 may be different from the material of any of the first external terminal 511, the second external terminal 512, the fourth external terminal 514, and the fifth external terminal 515.

[0119] In the semiconductor device 10 of the embodiment described above, the external terminals 51 have a multilayer structure of copper (Cu), nickel, and gold, but in the semiconductor device 10A of Modification 1, a lower-resistance, less expensive material, such as aluminum (Al), is used. Of course, the material of the external terminals 51 is not limited to aluminum, and a metal that can adhere to the seed layer, such as titanium (Ti), can be selected as needed. For example, aluminum is used as the material for the first external terminal 511 and the second external terminal 512, and titanium is used as the material for the fourth external terminal 514 and the fifth external terminal 515.

[0120] In the semiconductor device 10A, the first electrode layer 321 of the first capacitance portion 31 and the first electrode layer 321 of the second capacitance portion 32 are integral. Here, "integral" refers to the fact that the boundary between the first electrode layer 321 of the first capacitance portion 31 and the first electrode layer 321 of the second capacitance portion 32 is not clearly defined, and the two are electrically connected. The first electrode layer 321 of the first capacitance portion 31 is one of the two electrode layers (the first electrode layer 321 and the second electrode layer 322) of the first capacitance portion 31 that is provided outside the first trench portion 20Ca and constitutes at least a portion of the semiconductor substrate 20. The first electrode layer 321 of the second capacitance portion 32 is one of the two electrode layers (the first electrode layer 321 and the second electrode layer 322) of the second capacitance portion 32 that is provided outside the second trench portion 20Cb and constitutes at least a portion of the semiconductor substrate 20.

[0121] The semiconductor device 10A includes four first trench portions 20Ca and three second trench portions 20Cb. That is, in the semiconductor device 10A, the number of first trench portions 20Ca is greater than the number of second trench portions 20Cb. Note that the number of first trench portions 20Ca is not limited to four, and the number of second trench portions 20Cb is not limited to three. The number of second trench portions 20Cb may be greater than the number of first trench portions 20Ca. As described above, in the semiconductor device 10A, the number of first trench portions 20Ca is different from the number of second trench portions 20Cb.

[0122] In the semiconductor device 10 of the above-described embodiment, the size of each first trench portion 20Ca is the same as the size of each second trench portion 20Cb. However, the size of each first trench portion 20Ca and the size of each second trench portion 20Cb may be different. The size of each first trench portion 20Ca and each second trench portion 20Cb (hereinafter referred to as each trench portion) is determined, for example, by the area and shape of each trench portion when viewed along the thickness direction 101, the length of each trench portion in the thickness direction 101 (the depth of each trench portion), etc. In other words, the area and shape of each trench portion when viewed along the thickness direction 101, the depth of each trench portion, etc. may be different from each other.

[0123] For example, in the semiconductor device 10A, the area of ​​each of the three second trench portions 20Cb is smaller than the area of ​​each of the four first trench portions 20Ca when viewed along the thickness direction 101. In other words, in the semiconductor device 10A, the size of the first trench portion 20Ca is different from the size of the second trench portion 20Cb.

[0124] In the semiconductor device 10A, the capacitance of the first capacitance portion 31 is larger than the capacitance of the second capacitance portion 32. That is, in the semiconductor device 10A, the capacitance of the first capacitance portion 31 is different from the capacitance of the second capacitance portion 32. In the semiconductor device 10A shown in FIG. 12 , the first trench portion 20Ca and the second trench portion 20Cb have different sizes and numbers, so that the capacitance of the first capacitance portion 31 is larger than the capacitance of the second capacitance portion 32.

[0125] Fig. 13 is an equivalent circuit diagram of the semiconductor device shown in Fig. 12. The semiconductor device 10A is configured as described above, thereby forming a circuit as shown in Fig. 13. Capacitors C1 and C2 are connected in parallel, and capacitors C3 and C4 are connected in parallel. One electrode of each of the capacitors C1, C2, C3, and C4 is connected to a first columnar external terminal 521. The other electrode of each of the capacitors C1, C2, C3, and C4 is connected to a second columnar external terminal 522.

[0126] According to the first modification, the filling portion 40 is electrically connected to both the first capacitance portion 31 and the second capacitance portion 32, which improves the degree of freedom in designing the semiconductor device 10A.

[0127] According to the first modification, the first columnar external terminal 521 and the second columnar external terminal 522 protrude from other portions. This makes it easy to bring a measurement needle into contact with the first columnar external terminal 521 and the second columnar external terminal 522. This facilitates measurement.

[0128] According to the first modification, the electrode layer 321 of the first trench portion 20Ca and the electrode layer 321 of the second trench portion 20Cb are shared, which allows the semiconductor device 10A to be made smaller than in a configuration in which the electrode layer 321 of the first trench portion 20Ca and the electrode layer 321 of the second trench portion 20Cb are provided separately.

[0129] According to the first modification, the conductive portions (e.g., the first capacitance portion 31, the second capacitance portion 32, and the external terminals 51) provided on each of the one main surface 20A and the other main surface 20B can be protected by the protective film 55. This makes it possible to prevent, for example, foreign matter from adhering to the conductive portions.

[0130] According to Modification 1, the first wiring layer (first external terminal 511 and second external terminal 512) and the second wiring layer (fourth external terminal 514 and fifth external terminal 515) are wired, thereby improving the design freedom of the semiconductor device 10A. By configuring the first wiring layer and the second wiring layer from different materials, the material of the first wiring layer can be selected according to the process in which the first wiring layer is stacked, and the material of the second wiring layer can be selected according to the process in which the second wiring layer is stacked.

[0131] According to the first modification, the capacitance of the first capacitance section 31 is different from the capacitance of the second capacitance section 32. Therefore, two different amounts of capacitance can be obtained in one semiconductor device 10A.

[0132] <Second Modification of Semiconductor Device> FIG. 14 is a schematic cross-sectional view of a second modification of the semiconductor device according to the embodiment of the present disclosure.

[0133] 14, the filling portion 40 may include a material other than a conductive material. The filling portion 40 shown in FIG. 14 includes a buried layer 41, a barrier layer 43, and an isolation layer 44 in addition to a conductive layer 42.

[0134] The buried layer 41 is made of a resin such as epoxy. The barrier layer 43 includes a conductive material such as titanium nitride (TiN) or nickel (Ni). The isolation layer 44 is made of silicon dioxide (SiO ２ ) and silicon nitride (Si ３ N ４ 14 , the filling portion 40 of the semiconductor device 10B contains a conductive material in the conductive layer 42 and the barrier layer 43, which are part of the filling portion 40, but does not contain a conductive material in the buried layer 41 and the isolation layer 44, which are other parts of the filling portion 40.

[0135] The buried layer 41, the conductive layer 42, the barrier layer 43, and the isolation layer 44 each penetrate the hole 20D in the thickness direction 101. In other words, the buried layer 41, the conductive layer 42, the barrier layer 43, and the isolation layer 44 each extend from one end to the other end of the hole 20D in the thickness direction 101.

[0136] When viewed along the thickness direction 101, the conductive layer 42 surrounds the buried layer 41. When viewed along the thickness direction 101, the barrier layer 43 surrounds the conductive layer 42. When viewed along the thickness direction 101, the isolation layer 44 surrounds the barrier layer 43. The outer peripheral surface of the isolation layer 44 is in contact with the side surface 20Da of the hole 20D.

[0137] The filling portion 40 may not include at least one of the buried layer 41 and the barrier layer 43. Furthermore, a magnetic layer 45 (described later) may be provided between any two adjacent layers among the buried layer 41, the conductive layer 42, the barrier layer 43, and the isolation layer 44.

[0138] The semiconductor substrate 20 of the semiconductor device 10B includes a first substrate 21, a second substrate 22, and an adhesive layer 23. Similar to the semiconductor substrate 20 shown in FIG. 2 , the first substrate 21 and the second substrate 22 are formed of insulating, high-resistance Si. The first substrate 21 includes a first trench portion 20Ca. The second substrate 22 includes a second trench portion 20Cb. The adhesive layer 23 is located between the first substrate 21 and the second substrate 22. The first substrate 21 and the second substrate 22 are bonded together by the adhesive layer 23. The adhesive layer 23 may be an organic resin such as polyimide, an inorganic oxide film, or a conductive conductor layer. When the adhesive layer 23 is a conductor layer, the adhesive layer 23 can be used as a ground or wiring between electronic components.

[0139] The semiconductor device 10B is generally manufactured by the manufacturing method described above. However, in the bonding step, the first substrate 21 and the second substrate 22 are bonded by adhesion. At this time, an adhesive layer 23 is formed. In addition, the hole forming step, the filling portion forming step, and the external terminal forming step are performed after the bonding step. Note that the recess forming step, the capacitance portion forming step, the first insulating layer forming step, and the second insulating layer forming step may also be performed after the bonding step.

[0140] In the hole forming process, a hole 20D is formed by using, for example, a microdrill or a laser, penetrating the semiconductor substrate 20 in the thickness direction 101, where the first substrate 21 and the second substrate 22 are bonded together by the adhesive layer 23.

[0141] In the next filling portion formation process, the layers constituting the filling portion 40 are filled in order from the outermost layer. More specifically, the isolation layer 44 is first filled into the hole 20D. Next, a hole penetrating the isolation layer 44 in the thickness direction 101 is formed using a microdrill or a laser, and the hole is filled with the barrier layer 43. Thereafter, the conductive layer 42 and the buried layer 41 are filled in the same manner.

[0142] In the next external terminal forming step, a third external terminal 513 is layered on the upper surface 40A of the filled portion 40, and a sixth external terminal 516 is layered on the lower surface 40B of the filled portion 40.

[0143] According to the second modification, the isolation layer 44 is made of an insulating material, and therefore, the isolation layer 44 can block signals from propagating from the conductive layer 42 to other portions, such as the first capacitance portion 31 and the second capacitance portion 32, via the semiconductor substrate 20.

[0144] For example, there is a risk that the electrical resistance of the conductive layer 42 may change due to diffusion of the conductive material (e.g., copper) contained in the conductive layer 42. According to the second modification, the barrier layer 43 can suppress the diffusion of the conductive layer 42. Therefore, the change in the electrical resistance of the conductive layer 42 can be reduced.

[0145] According to the second modification, the barrier layer 43 contains a conductive material, and therefore, the barrier layer 43 can function as a seed layer. In addition, an electrical signal can be transmitted through the barrier layer 43.

[0146] According to the second modification, the filling portion 40 includes the buried layer 41, which can suppress unwanted voids, foreign matter contamination, and the occurrence of unevenness in the exposed portions of the filling portion 40 on the one main surface 20A and the other main surface 20B. In other words, the filling portion 40 includes the buried layer 41, which eliminates the need to fill the entire hole 20D with the conductive layer 42. This reduces the manufacturing cost of the semiconductor device 10.

[0147] According to the second modification, the semiconductor substrate 20 having the first main surface 20A and the other main surface 20B can be formed by bonding the first substrate 21 and the second substrate 22 with the adhesive layer 23. This makes it possible to realize a highly accurate semiconductor device 10B at low cost.

[0148] <Third Modification of Semiconductor Device> FIG. 15 is a schematic cross-sectional view of a third modification of the semiconductor device according to the embodiment of the present disclosure.

[0149] 15 differs from the semiconductor device 10B of Modification 2 only in the configuration of the filling portion 40. Hereinafter, the configuration of the filling portion 40, which is the difference from the semiconductor device 10B, will be described, and descriptions of the configurations of other parts will be omitted.

[0150] 15, the filling portion 40 may contain a magnetic material. The filling portion 40 shown in FIG.

[0151] 15 , the filling portion 40 of the semiconductor device 10 of the third modification example shown in FIG. 15 includes a magnetic layer 45 that is a part of the filling portion 40 and does not include a conductive material in the conductive layer 42 other than the part.

[0152] The magnetic material is, for example, spherical metal magnetic powder. The metal magnetic powder has a maximum composition element of iron (Fe) and a median diameter D50 of 5 μm or less. The metal magnetic powder is a composite material with organic resins such as epoxy, phenol, acrylic, and polyimide. Because the metal powder is a composite material, insulation between the powder particles can be achieved, allowing the semiconductor device 10 to be provided as an inductor component with low loss.

[0153] The conductive layer 42 and the magnetic layer 45 each penetrate the hole 20D in the thickness direction 101. In other words, the conductive layer 42 and the magnetic layer 45 each extend from one end to the other end of the hole 20D in the thickness direction 101.

[0154] When viewed along the thickness direction 101, the magnetic layer 45 surrounds the conductive layer 42. In other words, the conductive layer 42 penetrates the magnetic layer 45 in the thickness direction 101. The outer peripheral surface of the magnetic layer 45 is in contact with the side surface 20Da of the hole 20D.

[0155] The conductive layer 42 does not have to penetrate the magnetic layer 45 in the thickness direction 101. For example, the conductive layer 42 may be provided on the first capacitance portion 31 side of the hole 20D in the width direction 102, and the magnetic layer 45 may be provided on the opposite side of the hole 20D from the first capacitance portion 31 in the width direction 102, so that the conductive layer 42 and the magnetic layer 45 are arranged side by side in the width direction 102 when viewed along the thickness direction 101.

[0156] The semiconductor device 10C is manufactured by the same manufacturing method as the semiconductor device 10B. However, what is filled in the filling portion formation process differs from that of the semiconductor device 10B. Specifically, first, the magnetic layer 45 is filled into the hole 20D. Next, a hole penetrating the magnetic layer 45 in the thickness direction 101 is formed using a microdrill or a laser, and the conductive layer 42 is filled into the hole.

[0157] Fig. 16 is an equivalent circuit diagram of the semiconductor device shown in Fig. 15. The semiconductor device 10C is configured as described above, and thus forms a circuit as shown in Fig. 16. The circuit shown in Fig. 16 is generally the same as the circuit shown in Fig. 3, but the filling portion 40 includes a magnetic layer 45, and therefore the resistor R shown in Fig. 3 becomes an inductor L.

[0158] According to the third modification, the magnetic layer 45 can function as a magnetic shield, and the filling portion 40 can function as an inductor.

[0159] <Variation 4 of Semiconductor Device> FIG. 17 is a schematic cross-sectional view of a variation of the semiconductor device according to the embodiment of the present disclosure.

[0160] 17 differs from the semiconductor device 10 shown in Fig. 2 only in the configurations of the hole 20D and the filling portion 40. Below, the configurations of the hole 20D and the filling portion 40, which are the differences from the semiconductor device 10, will be described, and a description of the configurations of other parts will be omitted.

[0161] 17, the hole 20D includes a first hole 201D and a second hole 202D. The first hole 201D opens to one main surface 20A. The second hole 202D opens to the other main surface 20B. The second hole 202D communicates with the first hole 201D.

[0162] The filling section 40 includes a first filling section 401 and a second filling section 402. The first filling section 401 is filled in the first hole 201D. The second filling section 402 is filled in the second hole 202D. When viewed along the thickness direction 101, the center of gravity position Ax1 of the first filling section 401 is different from the center of gravity position Ax2 of the second filling section 402. In the present disclosure, the "center of gravity" refers to a geometric center of gravity that does not take into account the specific gravity of the substances in the first filling section 401 and the second filling section 402.

[0163] 17, hole 20D has two portions (first hole 201D and second hole 202D), but may have three or more portions with different center of gravity positions. Also, in FIG. 17, when viewed along thickness direction 101, the area of ​​second hole 202D may be larger than the area of ​​first hole 201D, but the area of ​​second hole 202D may be equal to or smaller than the area of ​​first hole 201D.

[0164] According to the fourth modification, the position of the filling portion 40 on the one main surface 20A and the position on the other main surface 20B can be set to different positions, thereby improving the degree of freedom in designing the semiconductor device 10D.

[0165] <Variation 5 of Semiconductor Device> FIG. 18 is a schematic cross-sectional view of a variation of the semiconductor device according to the embodiment of the present disclosure.

[0166] The semiconductor device 10E of the fifth modification shown in Fig. 18 differs from the semiconductor device 10D shown in Fig. 17 only in the configurations of the hole 20D and the filling portion 40. Below, the configurations of the hole 20D and the filling portion 40, which are the differences from the semiconductor device 10D, will be described, and a description of the configurations of other parts will be omitted.

[0167] As shown in FIG. 18, the hole 20D of the semiconductor device 10E includes a first hole 201D and a second hole 202D, similar to the hole 20D of the semiconductor device 10D.

[0168] Similar to the filling portion 40 of the semiconductor device 10D, the filling portion 40 of the semiconductor device 10E includes a first filling portion 401 and a second filling portion 402. In the semiconductor device 10E, the area of ​​the second hole 202D is larger than the area of ​​the first hole 201D when viewed along the thickness direction 101. Furthermore, in the semiconductor device 10E, the center of gravity Ax of the first filling portion 401 is the same as the center of gravity Ax of the second filling portion 402 when viewed along the thickness direction 101.

[0169] 18, hole 20D has two portions (first hole 201D and second hole 202D), but may have three or more portions that have the same center of gravity and different areas when viewed along thickness direction 101. Also, in FIG. 18, the area of ​​second hole 202D may be larger than the area of ​​first hole 201D when viewed along thickness direction 101, but the area of ​​second hole 202D may be smaller than the area of ​​first hole 201D.

[0170] According to the fifth modification, the size of the filling portion 40 on the one main surface 20A is different from the size on the other main surface 20B, which improves the degree of freedom in designing the semiconductor device 10E.

[0171] <Sixth Modification of Semiconductor Device> FIG. 19 is a schematic cross-sectional view of a sixth modification of the semiconductor device according to the embodiment of the present disclosure.

[0172] 19, the semiconductor substrate 20 of the semiconductor device 10F includes a first substrate 21 and a second substrate 22. The first substrate 21 is formed of insulating, high-resistance Si, similar to the semiconductor substrate 20 shown in FIG. 2. The second substrate 22 is formed of a first electrode layer 321. The first substrate 21 and the second substrate 22 are joined by known means such as thermocompression bonding.

[0173] In the semiconductor device 10F, the hole 20D penetrates the first base material 21 in the thickness direction 101. On the other hand, the second base material 22 (first electrode layer 321) does not have the hole 20D. That is, in the semiconductor device 10F, the hole 20D does not penetrate the semiconductor base material 20 and has a bottom. The hole 20D opens to one main surface 20A and has a bottom on the other main surface 20B side.

[0174] The filling portion 40 is filled in the hole 20D. The bottom surface of the hole 20D is formed by the second substrate 22. That is, the bottom surface of the hole 20D is formed by the first electrode layer 321 of the second capacitance portion 32. As a result, the portion of the first electrode layer 321 that forms the bottom surface of the hole 20D is in contact with the filling portion 40. That is, the first electrode layer 321 and the filling portion 40 are electrically connected.

[0175] According to the sixth modification, it is not necessary to form the hole 20D so as to penetrate the semiconductor substrate 20 in the thickness direction 101. This allows the depth of the hole 20D to be shallow. Furthermore, this allows, when manufacturing the semiconductor device 10F by bonding two substrates (a first substrate 21 and a second substrate 22), to provide the hole 20D penetrating the substrate in one of the two substrates, while not providing the hole 20D in the other of the two substrates. As a result, a configuration that electrically connects the one main surface 20A and the other main surface 20B can be realized at a lower cost than a configuration in which the hole 20D penetrates the semiconductor substrate 20 in the thickness direction 101.

[0176] <Module Component> FIG. 20 is a schematic cross-sectional view of a module component according to an embodiment of the present disclosure.

[0177] 20 , the module member 70 includes the semiconductor device 10 described in the above-described embodiment and each of the modified examples, an electronic component 71, and a mounting substrate 72 that is an interposer layer on which the semiconductor device 10 and the electronic component 71 are provided. When viewed along the thickness direction 101, the area of ​​each of the electronic component 71 and the mounting substrate 72 in FIG. 20 is larger than the area of ​​the semiconductor device 10, but may be equal to or smaller than the area of ​​the semiconductor device 10.

[0178] The electronic component 71 is mounted on at least one of the front mounting surface 72A and the back mounting surface 72B of the mounting board 72. In the configuration shown in Fig. 20, the electronic component 71 is mounted on the front mounting surface 72A. In the configuration shown in Fig. 20, the front mounting surface 72A corresponds to the mounting surface. The electronic component 71 is an integrated circuit (IC), but is not limited to an IC. For example, the electronic component 71 may be a resistor, an inductor, or the like.

[0179] The mounting substrate 72 shown in FIG. 20 includes a core material 721 which is a resin molding material containing an inorganic filler, and insulating base materials 722 and 723 which are provided so as to sandwich the core material 721 in the thickness direction 101 .

[0180] The semiconductor device 10 is provided inside a mounting substrate 72. In the configuration shown in Fig. 20, the semiconductor device 10 is provided inside a core material 721. Although the semiconductor device 10 shown in Fig. 20 has four filled portions 40, the number of filled portions 40 is not limited to four. The semiconductor device 10 may be mounted on at least one of the front mounting surface 72A and the back mounting surface 72B of the mounting substrate 72. The semiconductor device 10 is not limited to the configuration shown in Fig. 20, and may have any of the various configurations described above.

[0181] Internal electrodes 724 are provided inside the insulating base materials 722 and 723. External electrodes 725 are provided on the front mounting surface 72A and the back mounting surface 72B. In other words, the insulating base materials 722 and 723, the internal electrodes 724, and the external electrodes 725 form a redistribution layer (RDL).

[0182] The through electrode 726 may penetrate at least one of the core material 721, the insulating substrate 722, and the insulating substrate 723. The through electrode 726 may be electrically connected to the internal electrode 724 and the external electrode 725.

[0183] In the mounting substrate 72 shown in FIG. 20, at least a part of the semiconductor device 10 and at least a part of the electronic component 71 overlap with each other when viewed along the thickness direction 101 .

[0184] The core material 721 is made of, for example, epoxy or silica, and the insulating base materials 722 and 723 are made of, for example, silicon.

[0185] The mounting substrate 72 is not limited to the configuration including the core material 721 and insulating base materials 722 and 723 as shown in Fig. 20. For example, the mounting substrate 72 may be made of a glass core. In this case, the mounting substrate 72 contains glass fiber. The inclusion of glass fiber increases the strength of the mounting substrate 72, making it possible to suppress warping of the substrate.

[0186] According to this embodiment, the semiconductor device 10 can be provided near the electronic component 71. As a result, the signal integrity (SI) of the semiconductor device 10 can be improved.

[0187] The semiconductor device and module member described above can also be expressed as follows.

[0188] According to a first aspect of the present disclosure, there is provided a semiconductor device comprising: a semiconductor substrate having one main surface and another main surface that is spaced apart in the thickness direction from the one main surface and faces the opposite direction from the one main surface in the thickness direction, the semiconductor substrate having at least one first trench portion in the one main surface and at least one second trench portion in the other main surface; a first capacitance portion that is provided at least inside the first trench portion and has a dielectric layer and two electrode layers that sandwich the dielectric layer; and a second capacitance portion that is provided at least inside the second trench portion and has a dielectric layer and two electrode layers that sandwich the dielectric layer.

[0189] According to a second aspect of the present disclosure, there is provided the semiconductor device described in the first aspect, wherein the semiconductor substrate further has a hole portion extending along the thickness direction, opening to at least one of the one main surface and the other main surface, and having an area larger than each of the one first trench portion and the one second trench portion when viewed along the thickness direction, and further comprising a filling portion provided inside the hole portion and containing a conductive material.

[0190] According to a third aspect of the present disclosure, there is provided the semiconductor device according to the second aspect, wherein the hole opens to both the one main surface and the other main surface.

[0191] According to a fourth aspect of the present disclosure, there is provided the semiconductor device according to the second or third aspect, wherein the filling portion comprises: a buried layer made of resin; a conductive layer containing a conductive material and surrounding the buried layer when viewed along the thickness direction; a barrier layer containing a conductive material and surrounding the conductive layer when viewed along the thickness direction; and an isolation layer made of an insulating material and surrounding the barrier layer when viewed along the thickness direction.

[0192] According to a fifth aspect of the present disclosure, there is provided a semiconductor device according to any one of the second to fourth aspects, wherein the filling portion is electrically connected to both the first capacitance portion and the second capacitance portion.

[0193] According to a sixth aspect of the present disclosure, there is provided a semiconductor device according to any one of the second to fifth aspects, wherein the filling portion comprises: a conductive layer extending from one end to the other end in the thickness direction of the hole portion and including a conductive material; and a magnetic layer extending from one end to the other end in the thickness direction of the hole portion and including a magnetic material.

[0194] According to a seventh aspect of the present disclosure, there is provided the semiconductor device according to the sixth aspect, wherein the conductive layer penetrates the magnetic layer in the thickness direction.

[0195] According to an eighth aspect of the present disclosure, there is provided a semiconductor device according to any one of the second to seventh aspects, wherein the hole portion comprises a first hole portion opening to the one main surface and a second hole portion opening to the other main surface and communicating with the first hole portion, the filling portion comprises a first filling portion filled in the first hole portion and a second filling portion filled in the second hole portion, and when viewed along the thickness direction, the position of the center of gravity of the first filling portion is different from the position of the center of gravity of the second filling portion.

[0196] According to a ninth aspect of the present disclosure, there is provided a semiconductor device described in any one of the second to eighth aspects, wherein the hole portion comprises a first hole portion that opens to the one main surface, and a second hole portion that opens to the other main surface and communicates with the first hole portion, and when viewed along the thickness direction, an area of ​​the first hole portion is different from an area of ​​the second hole portion.

[0197] According to a tenth aspect of the present disclosure, there is provided a semiconductor device according to any one of the second to ninth aspects, wherein the hole opens to the one main surface and has a bottom on the other main surface side, the bottom surface of the hole is formed by an electrode layer of the second capacitance section, and the filling section filled in the hole is in contact with a portion of the electrode layer of the second capacitance section that forms the bottom surface.

[0198] According to an eleventh aspect of the present disclosure, there is provided the semiconductor device according to any one of the first to tenth aspects, further comprising conductive external terminals provided on both the one main surface and the other main surface.

[0199] According to a twelfth aspect of the present disclosure, there is provided the semiconductor device as set forth in the eleventh aspect, wherein a specific external terminal that is at least one of the external terminals protrudes in the thickness direction relative to a specific main surface that is the one main surface or the other main surface on which the specific external terminal is provided, and the protrusion length of the specific external terminal in the thickness direction relative to the specific main surface is greater than the protrusion length of other portions excluding the specific external terminal provided on the specific main surface relative to the specific main surface in the thickness direction.

[0200] According to a thirteenth aspect of the present disclosure, there is provided a semiconductor device according to any one of the first to twelfth aspects, wherein, when viewed along the thickness direction, at least a portion of the first capacitance section and at least a portion of the second capacitance section are positioned to overlap.

[0201] According to a fourteenth aspect of the present disclosure, there is provided a semiconductor device according to any one of the first to thirteenth aspects, wherein one of the two electrode layers of the first capacitance section that is provided outside the first trench section and constitutes at least a part of the semiconductor substrate is integral with one of the two electrode layers of the second capacitance section that is provided outside the second trench section and constitutes at least a part of the semiconductor substrate.

[0202] According to a fifteenth aspect of the present disclosure, there is provided the semiconductor device according to any one of the first to fourteenth aspects, further comprising an insulating protective film covering at least one of the one main surface and the other main surface.

[0203] According to a sixteenth aspect of the present disclosure, there is provided a semiconductor device according to any one of the first to fifteenth aspects, further comprising: a conductive first wiring layer located on the one main surface; and a conductive second wiring layer located on the other main surface and made of a material different from that of the first wiring layer.

[0204] According to a seventeenth aspect of the present disclosure, there is provided a semiconductor device according to any one of the first to sixteenth aspects, wherein at least one of the number and size of the first trench portions is different from at least one of the number and size of the second trench portions, and the capacitance of the first capacitance portion is different from the capacitance of the second capacitance portion.

[0205] According to an eighteenth aspect of the present disclosure, there is provided a semiconductor device according to any one of the first to seventeenth aspects, wherein the semiconductor substrate comprises: a first substrate comprising the first trench portion; a second substrate comprising the second trench portion; and an adhesive layer located between the first substrate and the second substrate and adhering the first substrate and the second substrate.

[0206] According to a 19th aspect of the present disclosure, there is provided a module member comprising: a semiconductor device according to any one of the first to 18th aspects; an electronic component; and a mounting substrate having a mounting surface on which the electronic component is mounted and having the semiconductor device provided therein.

[0207] According to a twentieth aspect of the present disclosure, there is provided a method for manufacturing a semiconductor device, including: a first trench portion forming step of forming at least one first trench portion in a main surface of a first substrate; a first capacitance portion forming step of forming a first capacitance portion having a dielectric layer and two electrode layers sandwiching the dielectric layer, in at least the first trench portion in the first substrate; a second trench portion forming step of forming at least one second trench portion in a main surface of a second substrate; a second capacitance portion forming step of forming a second capacitance portion having a dielectric layer and two electrode layers sandwiching the dielectric layer, in at least the second trench portion in the second substrate; and a bonding step of bonding a back surface of the first substrate relative to the main surface and a back surface of the second substrate relative to the main surface.

[0208] In addition, by appropriately combining any of the various embodiments described above, the effects of each embodiment can be achieved. For example, although the trench portions have different sizes in the semiconductor device 10A shown in FIG. 12, a configuration in which the trench portions have different sizes may be applied to the semiconductor device 10 of other embodiments and modifications.

[0209] While the present invention has been fully described in connection with preferred embodiments, with appropriate reference to the drawings, various changes and modifications will become apparent to those skilled in the art, and it is to be understood that such changes and modifications are included within the scope of the present invention as defined by the appended claims unless they depart therefrom.

[0210] 10 Semiconductor device 20 Semiconductor substrate 20A One main surface (specific main surface) 20B Other main surface 20Ca First trench portion 20Cb Second trench portion 20D Hole portion 201D First hole portion 202D Second hole portion 21 First substrate 22 Second substrate 23 Adhesion layer 31 First capacitance portion 32 Second capacitance portion 40 Filling portion 401 First filling portion 402 Second filling portion 41 Buried layer 42 Conductive layer 43 Barrier layer 44 Isolation layer 45 Magnetic layer 51 External terminal 511 First external terminal (first wiring layer) 512 Second external terminal (first wiring layer) 514 Fourth external terminal (second wiring layer) 515 Fifth external terminal (second wiring layer) 521 First pillar-shaped external terminal (external terminal, specific external terminal) 522 Second columnar external terminal (external terminal, specific external terminal) 55 Protective film 70 Module member 71 Electronic component 72 Mounting substrate 72A Front mounting surface (mounting surface) 101 Thickness direction

Claims

1. A semiconductor device comprising: a semiconductor substrate having one main surface and another main surface that is spaced apart in the thickness direction from the one main surface and faces the opposite direction from the one main surface in the thickness direction, the semiconductor substrate having at least one first trench portion in the one main surface and at least one second trench portion in the other main surface; a first capacitive portion provided at least inside the first trench portion and having a dielectric layer and two electrode layers that sandwich the dielectric layer; and a second capacitive portion provided at least inside the second trench portion and having a dielectric layer and two electrode layers that sandwich the dielectric layer.

2. The semiconductor device according to claim 1, wherein the semiconductor substrate further has a hole portion extending along the thickness direction, opening to at least one of the one main surface and the other main surface, and having an area larger than each of the one first trench portion and the one second trench portion when viewed along the thickness direction, and further comprising a filling portion provided inside the hole portion and containing a conductive material.

3. The semiconductor device according to claim 2, wherein the hole opens to both the one main surface and the other main surface.

4. The semiconductor device of claim 2 or 3, wherein the filling portion comprises: an embedded layer made of resin; a conductive layer containing a conductive material and surrounding the embedded layer when viewed along the thickness direction; a barrier layer containing a conductive material and surrounding the conductive layer when viewed along the thickness direction; and an isolation layer made of an insulating material and surrounding the barrier layer when viewed along the thickness direction.

5. The semiconductor device according to claim 2, wherein the filling section is electrically connected to both the first capacitance section and the second capacitance section.

6. A semiconductor device according to any one of claims 2 to 5, wherein the filling portion comprises: a conductive layer extending from one end to the other end of the hole in the thickness direction and including a conductive material; and a magnetic layer extending from one end to the other end of the hole in the thickness direction and including a magnetic material.

7. The semiconductor device according to claim 6, wherein said conductive layer penetrates said magnetic layer in said thickness direction.

8. A semiconductor device as described in any one of claims 2 to 7, wherein the hole portion comprises a first hole portion opening to the one main surface and a second hole portion opening to the other main surface and communicating with the first hole portion, the filling portion comprises a first filling portion filled in the first hole portion and a second filling portion filled in the second hole portion, and when viewed along the thickness direction, the center of gravity of the first filling portion is different from the center of gravity of the second filling portion.

9. A semiconductor device as described in any one of claims 2 to 8, wherein the hole portion comprises a first hole portion opening into the one main surface and a second hole portion opening into the other main surface and communicating with the first hole portion, and when viewed along the thickness direction, an area of ​​the first hole portion is different from an area of ​​the second hole portion.

10. A semiconductor device as described in any one of claims 2 to 9, wherein the hole opens to the one main surface and has a bottom on the other main surface side, the bottom surface of the hole is formed by an electrode layer of the second capacitance section, and the filling section filled in the hole is in contact with a portion of the electrode layer of the second capacitance section that forms the bottom surface.

11. The semiconductor device according to claim 1, further comprising conductive external terminals provided on both the one main surface and the other main surface.

12. The semiconductor device described in claim 11, wherein a specific external terminal which is at least one of the external terminals protrudes in the thickness direction relative to a specific main surface which is the one main surface or the other main surface on which the specific external terminal is provided, and the protrusion length of the specific external terminal in the thickness direction relative to the specific main surface is greater than the protrusion length of other portions excluding the specific external terminal provided on the specific main surface relative to the specific main surface in the thickness direction.

13. The semiconductor device according to claim 1, wherein at least a portion of the first capacitance section and at least a portion of the second capacitance section are positioned to overlap each other when viewed along the thickness direction.

14. A semiconductor device described in any one of claims 1 to 13, wherein one of the two electrode layers of the first capacitance section, which is provided outside the first trench section and constitutes at least a part of the semiconductor substrate, is integral with one of the two electrode layers of the second capacitance section, which is provided outside the second trench section and constitutes at least a part of the semiconductor substrate.

15. The semiconductor device according to claim 1, further comprising an insulating protective film covering at least one of the one main surface and the other main surface.

16. A semiconductor device according to any one of claims 1 to 15, further comprising: a conductive first wiring layer located on said one main surface; and a conductive second wiring layer located on said other main surface and made of a material different from that of the first wiring layer.

17. A semiconductor device according to any one of claims 1 to 16, wherein at least one of the number and size of the first trench portions is different from at least one of the number and size of the second trench portions, and the capacitance of the first capacitance portion is different from the capacitance of the second capacitance portion.

18. A semiconductor device according to any one of claims 1 to 17, wherein the semiconductor substrate comprises: a first substrate having the first trench portion; a second substrate having the second trench portion; and an adhesive layer located between the first substrate and the second substrate and adhering the first substrate and the second substrate.

19. A module member comprising: a semiconductor device according to any one of claims 1 to 18; an electronic component; and a mounting substrate having a mounting surface on which the electronic component is mounted and in which the semiconductor device is provided.

20. A method for manufacturing a semiconductor device, comprising: a first trench portion forming step of forming at least one first trench portion on a main surface of a first substrate; a first capacitance portion forming step of forming a first capacitance portion having a dielectric layer and two electrode layers sandwiching the dielectric layer, in at least the first trench portion of the first substrate; a second trench portion forming step of forming at least one second trench portion on a main surface of a second substrate; a second capacitance portion forming step of forming a second capacitance portion having a dielectric layer and two electrode layers sandwiching the dielectric layer, in at least the second trench portion of the second substrate; and a bonding step of bonding a back surface of the first substrate relative to the main surface and a back surface of the second substrate relative to the main surface.

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