Semiconductor device, semiconductor module, and electronic apparatus

Abstract

A semiconductor device including a protection element including: a first conductive region disposed on a surface of a substrate and having conductivity; a second conductive region disposed on the surface so as to be separated from the first conductive region and having conductivity; and a resistance region disposed between the first conductive region and the second conductive region and having a specific resistance greater than the specific resistance of each of the first conductive region and the second conductive region.

Description

Semiconductor device, semiconductor module and electronic device

[0001] The present disclosure relates to a semiconductor device, a semiconductor module, and an electronic device.

[0002] Patent Document 1 discloses a power converter and a GaN-based semiconductor device used therein. This power converter and GaN-based semiconductor device use a power FET (Field Effect Transistor) as a switching element. A protective element is connected between the source and drain electrodes of the power FET. The protective element prevents element breakdown due to input of a surge voltage. A GaN-based Schottky barrier diode is used as the protective element. The GaN-based Schottky barrier diode is formed including an undoped AlGaN layer and an anode electrode laminated on the undoped AlGaN layer in Schottky contact. The power converter and GaN-based semiconductor device configured in this manner can achieve high reliability that ensures stable operation and high power conversion efficiency.

[0003] Japanese Patent Application Laid-Open No. 2003-229566

[0004] In the above-mentioned protection element, multi-stage construction is required to reduce leakage current during device operation and increase operating voltage to enhance protection function. Multi-stage construction refers to a structure in which multiple GaN-based Schottky barrier diodes, which are protection elements, are electrically connected in series. This increases the area occupied by the protection element, and therefore there has been a demand for the development of semiconductor devices, semiconductor modules, and electronic devices that can effectively reduce the area occupied.

[0005] A semiconductor device according to a first embodiment of the present disclosure includes a protection element including a first conductive region having conductivity arranged on the surface of a substrate, a second conductive region having conductivity arranged on the surface at a distance from the first conductive region, and a resistive region arranged between the first conductive region and the second conductive region and having a resistive property greater than the resistive properties of the first conductive region and the second conductive region.

[0006] A semiconductor device according to a second embodiment of the present disclosure is a semiconductor device according to the first embodiment, further comprising a high electron mobility transistor having a first channel layer disposed on the surface in a region different from the protective element, in which a two-dimensional electron gas is generated, a first barrier layer disposed in the first channel layer, a gate electrode disposed on the first channel layer with the first barrier layer interposed therebetween, and a pair of main electrode regions disposed on both sides of the gate electrode in the gate length direction and electrically connected to the first channel layer, respectively.

[0007] A semiconductor device according to a third embodiment of the present disclosure is a semiconductor device according to the second embodiment, in which the first conductive region is electrically connected to the gate electrode and the second conductive region is electrically connected to one of a pair of main electrode regions.

[0008] A semiconductor module according to a fourth embodiment of the present disclosure includes a semiconductor device, the semiconductor device including a protection element including a first conductive region having conductivity and disposed on a surface of a substrate, a second conductive region having conductivity and disposed on the surface at a distance from the first conductive region, and a resistive region disposed between the first and second conductive regions and having a resistive property greater than the resistive properties of the first and second conductive regions.

[0009] An electronic device according to a fifth embodiment of the present disclosure includes a semiconductor device, the semiconductor device including a protection element including a first conductive region having conductivity and disposed on a surface of a substrate, a second conductive region having conductivity and disposed on the surface at a distance from the first conductive region, and a resistive region disposed between the first and second conductive regions and having a resistive property greater than the resistive properties of the first and second conductive regions.

[0010] FIG. 1 is a circuit diagram including a protection element and a semiconductor element that constitutes an internal circuit mounted on a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a plan configuration diagram of the protection element and the semiconductor element shown in FIG. 1. FIG. 3 is a vertical cross-sectional configuration diagram of the protection element and the semiconductor element shown in FIG. 2 (a cross-sectional diagram cut along the A-A cutting line shown in FIG. 2). FIG. 4 is a current-voltage characteristic diagram of the protection element shown in FIGS. 1 and 2. FIG. 5 is a cross-sectional diagram corresponding to FIG. 3 at a first step, illustrating each step of a manufacturing method of a semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional diagram corresponding to FIG. 3 at a second step. FIG. 7 is a cross-sectional diagram corresponding to FIG. 3 at a third step. FIG. 8 is a cross-sectional diagram corresponding to FIG. 3 at a fourth step. FIG. 9 is a vertical cross-sectional diagram corresponding to FIG. 3 of a protection element and a semiconductor element mounted on a semiconductor device according to a second embodiment of the present disclosure. FIG. 10 is a vertical cross-sectional diagram corresponding to FIG. 3 of a protection element and a semiconductor element mounted on a semiconductor device according to a third embodiment of the present disclosure. FIG. 11 is a vertical cross-sectional diagram corresponding to FIG. 3 of a protection element and a semiconductor element mounted on a semiconductor device according to a fourth embodiment of the present disclosure. Fig. 12 is a longitudinal cross-sectional configuration diagram corresponding to Fig. 3 of a protection element and a semiconductor element mounted on a semiconductor device according to a fifth embodiment of the present disclosure. Fig. 13 is a longitudinal cross-sectional configuration diagram corresponding to Fig. 3 of a protection element and a semiconductor element mounted on a semiconductor device according to a sixth embodiment of the present disclosure. Fig. 14 is a perspective view of a semiconductor module according to a seventh embodiment of the present disclosure. Fig. 15 is a block configuration diagram of an electronic device according to an eighth embodiment of the present disclosure.

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order. 1. First Embodiment The first embodiment is a first example in which the present technology is applied to a semiconductor device mounted with a semiconductor element that constitutes a protective element and an internal circuit. Here, the circuit configuration, planar configuration, cross-sectional configuration, and manufacturing method of the protective element and internal circuit will be described. 2. Second Embodiment The second embodiment is a second example in which the configuration of the protective element of the semiconductor device according to the first embodiment is changed. 3. Third Embodiment The third embodiment is a third example in which the configuration of the protective element and semiconductor element of the semiconductor device according to the first embodiment is changed. 4. Fourth Embodiment The fourth embodiment is a fourth example in which the configuration of the protective element of the semiconductor device according to the third embodiment is changed. 5. Fifth Embodiment The fifth embodiment is a fifth example in which the configuration of the protective element of the semiconductor device according to the first embodiment is changed. 6. Sixth Embodiment The sixth embodiment is a sixth example in which the configuration of the protective element of the semiconductor device according to the fifth embodiment is changed. 7. Seventh Embodiment The seventh embodiment is a seventh example in which a semiconductor module is mounted with a semiconductor device according to any one of the first to sixth embodiments. 8. Eighth Embodiment The eighth embodiment is an eighth example illustrating an electronic device in which any one of the semiconductor devices according to the first to sixth embodiments is mounted. 9. Other Embodiments

[0012] 1 to 8, a semiconductor device 1 according to a first embodiment of the present disclosure will be described. Here, the arrow X direction shown as appropriate in the figures conveniently represents one planar direction of the semiconductor device 1 placed on a flat surface. The arrow Y direction represents another planar direction perpendicular to the arrow X direction. Furthermore, the arrow Z direction represents an upward direction perpendicular to the arrow X and arrow Y directions. In other words, the arrow X direction, arrow Y direction, and arrow Z direction exactly correspond to the X-axis direction, Y-axis direction, and Z-axis direction, respectively, of a three-dimensional coordinate system. Note that these directions are illustrated to facilitate understanding of the description and do not limit the directions of the present technology.

[0013] 1 shows an example of a circuit configuration including a protection element 2 and an internal circuit 3 mounted on a semiconductor device 1 according to a first embodiment. As shown in FIG. 1, the semiconductor device 1 includes a protection element 2 and an internal circuit 3.

[0014] The internal circuit 3 includes one semiconductor element 4, or a plurality of semiconductor elements 4 (not shown). In the first embodiment, the semiconductor element 4 is configured by a field effect transistor Tr that constitutes, for example, a power device, a high frequency device, or the like. More specifically, the field effect transistor Tr is configured as, for example, a high electron mobility transistor (HEMT) based on a GaN-based compound semiconductor. Here, the field effect transistor Tr is formed as an n-channel conductivity type.

[0015] The field effect transistor Tr includes a gate electrode and a pair of main electrode regions. The detailed vertical cross-sectional structure of the field effect transistor Tr will be described later.

[0016] An input terminal Pin is electrically connected to the gate electrode of the field effect transistor Tr which serves as the input stage of the internal circuit 3. A signal is input to the input terminal Pin from outside the semiconductor device 1.

[0017] One of the main electrode regions of the field effect transistor Tr is used, for example, as a source region (or source electrode). One of the main electrode regions is electrically connected to a power supply terminal Vss. The power supply terminal Vss supplies, for example, a fixed potential, specifically, the circuit ground voltage of 0 V. The other main electrode region is used, for example, as a drain region (or drain electrode). The other main electrode region is electrically connected to an output terminal Pout. The output terminal Pout is electrically connected to a next-stage circuit or a next-stage element. An output signal from the field effect transistor Tr is output to the next-stage circuit or a next-stage element through the output terminal Pout.

[0018] A detailed cross-sectional configuration will be described later, but the protection element 2 has an equivalent circuit configuration including a diode D1 and a diode D2. The anode region of the diode D1 is electrically connected to the input terminal Pin. The cathode region of the diode D1 is electrically connected to and shared with the cathode region of the diode D2. The anode region of the diode D2 is electrically connected to the power supply terminal Vss. In other words, the protection element 2 has the diode D1 connected in the forward direction and the diode D2 connected in the reverse direction electrically inserted in parallel between the gate electrode and one of the main electrode regions (here, the source region) of the field-effect transistor Tr.

[0019] (2) Specific Device Configuration of Semiconductor Element 4 (Field-Effect Transistor Tr) Fig. 2 shows an example of a planar configuration of the semiconductor element 4 and the protective element 2 that constitute the internal circuit 3. Fig. 3 shows an example of a longitudinal cross-sectional configuration of the semiconductor element 4 and the protective element 2 shown in Fig. 2.

[0020] 2 and 3, the semiconductor device 1 is configured with a substrate 10 as a base. In the first embodiment, the substrate 10 is formed of gallium nitride (GaN), which is a III-V group compound semiconductor material. This compound semiconductor is formed as i-GaN, a so-called intrinsic semiconductor. The compound semiconductor has a density of, for example, 1×10 １７ [atoms / cm ３ The compound semiconductor according to the present technology is generally represented by the following composition formula: Al １－ｘ－ｙ Ga ｘ In ｙ N (0≦x<1, 0≦y<1) In the above composition formula, Al is aluminum, and In is indium.

[0021] The substrate 10 may be formed by laminating or bonding a GaN layer as a compound semiconductor onto a silicon (Si) substrate, a silicon carbide (SiC) substrate, or a diamond substrate.

[0022] The field effect transistor Tr includes a channel layer 41, a barrier layer 43, a gate electrode 47, and a pair of main electrode regions 44 as main components.

[0023] The channel layer 41 is formed on at least the main surface of the substrate 10. That is, the channel layer 41 is formed of GaN in this example. In the channel layer 41, carriers accumulate near the barrier layer 43, and a two-dimensional electron gas (2DEG) 42 that functions as a channel region for the carriers is generated.

[0024] The barrier layer 43 is disposed on the channel layer 41. The barrier layer 43 is made of a compound semiconductor material that accumulates carriers in the channel layer 41 due to polarization with the channel layer 41. The barrier layer 43 is made of a compound semiconductor. Compound semiconductors are generally represented by the following composition formula: Al １－ｘ－ｙ Ga ｘ In ｙ N (0≦x<1, 0≦y<1) In the first embodiment, the barrier layer 43 is made of, for example, AlInN or AlGaN.

[0025] The gate electrode 47 is disposed in contact with the barrier layer 43 through an opening 46H formed in an insulating layer 46 laminated on the barrier layer 43. A portion of the gate electrode 47 on the side opposite the barrier layer 43 is drawn around the opening 46H in the insulating layer 46 and formed as wiring 47L. The gate electrode 47 is formed of at least one metal material selected from titanium (Ti), molybdenum (Mo), Al, nickel (Ni), and gold (Au), or by sequentially laminating these metal materials. In other words, in the first embodiment, the field effect transistor Tr has the gate electrode 47 formed on the channel layer 41 with the barrier layer 43 interposed therebetween, and therefore the field effect transistor Tr is constructed as a Schottky junction field effect transistor.

[0026] 2, the field-effect transistor Tr has a multi-gate electrode structure. Here, the field-effect transistor Tr includes two gate electrodes 47, two main electrode regions 44, and one shared main electrode region 44. The two gate electrodes 47 are electrically connected in parallel. The two main electrode regions 44 are electrically connected in parallel by layer wiring indicated by dashed lines. In the first embodiment, one protective element 2 is connected to the field-effect transistor Tr having the multi-gate electrode structure, and the field-effect transistor Tr can be protected by this one protective element 2.

[0027] A pair of main electrode regions 44 are disposed in the channel layer 41 at both ends in the gate length direction of the gate electrode 47. One of the main electrode regions 44 is used as, for example, a source electrode (S), and the other main electrode region 44 is used as, for example, a drain electrode (D).

[0028] A detailed description will be given. The pair of main electrode regions 44 are each disposed in a recess 44R dug down from the main surface of the substrate 10 in the thickness direction of the substrate 10. The main electrode region 44 is formed of GaN as a compound semiconductor. The main electrode region 44 is formed to have a higher impurity density than the substrate 10. In other words, the impurity density of the compound semiconductor forming the main electrode region 44 is set to be higher than the impurity density of the compound semiconductor forming the substrate 10. The main electrode region 44 is formed by regrowing GaN in the recess 44R formed in the substrate 10. The epitaxial growth method is used to grow the GaN. The main electrode region 44 has a density of, for example, 1×10 １９ [atoms / cm ３ ] or more.

[0029] An electrode 45 is disposed on each of the pair of main electrode regions 44. The electrode 45 is formed of an electrode material that is in ohmic contact or near-ohmic contact with the main electrode region 44. For example, the electrode 45 is made of a composite film in which Ti, Mo, Al, Ni, and Au are sequentially stacked. Basically, the electrode 45 is made of the same metal material as the gate electrode 47. Here, the electrode 45 corresponds to a "first electrode" according to the present technology.

[0030] (3) Specific Device Configuration of the Protection Element 2 As shown in FIGS. 2 and 3, the protection element 2 includes at least a first conductive region 21, a second conductive region 22, and a resistance region 20 as main components.

[0031] The first conductive region 21 is basically conductive and is formed by two-dimensional electron gas 42 generated in a channel layer 41 of the substrate 10. To explain in more detail, the first conductive region 21 is a conductive region generated in the same layer as the two-dimensional electron gas 42 of the field-effect transistor Tr. For this reason, the channel layer 41 that becomes the first conductive region 21 is provided with a barrier layer 43 that is in the same layer as the barrier layer 43 of the field-effect transistor Tr.

[0032] The second conductive region 22 is disposed at a distance from the first conductive region 21. Like the first conductive region 21, the second conductive region 22 has conductivity and is formed by two-dimensional electron gas 42 generated in a channel layer 41 of the substrate 10. Furthermore, a barrier layer 43 is disposed in the channel layer 41 that becomes the second conductive region 22.

[0033] Here, in the formation region of the field-effect transistor Tr, the channel layer 41 corresponds to the "first channel layer" according to the present technology, and in the formation region of the protection element 2, the channel layer 41 corresponds to the "second channel layer" according to the present technology. Also, in the formation region of the field-effect transistor Tr, the barrier layer 43 corresponds to the "first barrier layer" according to the present technology, and in the formation region of the protection element 2, the barrier layer 43 corresponds to the "second barrier layer" according to the present technology.

[0034] The resistance region 20 is disposed in the channel layer 41 between the first conductive region 21 and the second conductive region 22. The resistance region 20 has a resistivity greater than the resistivity of each of the first conductive region 21 and the second conductive region 22. Specifically, the resistance region 20 is formed by the channel layer 41 in which no two-dimensional electron gas 42 is generated between the first conductive region 21 and the second conductive region 22. In the resistance region 20, no barrier layer 43 is disposed in the channel layer 41.

[0035] 1 is generated near the boundary between the resistance region 20 and the first conductive region 21. Similarly, the diode D2 is generated near the boundary between the resistance region 20 and the second conductive region 22.

[0036] The resistance value R of the resistance region 20 is calculated by multiplying the distance L1 between the first conductive region 21 and the second conductive region 22 by the resistivity and dividing the result by the cross-sectional area obtained by multiplying the opposing length L2 between the first conductive region 21 and the second conductive region 22 by the depth L3 of the channel layer 41 through which current effectively flows (R = resistivity × L1 / (L2 × L3)). In the first embodiment, the resistance value R is set to, for example, 100 kΩ or more and 100 MΩ or less. That is, the operating voltage required for the protection element 2 can be easily adjusted by changing one or more factors selected mainly from the distance L1 and the opposing length L2. Furthermore, for example, since the operating voltage changes significantly with respect to a change in the distance L1, the change in the area occupied by the protection element 2 is small.

[0037] The first conductive region 21 is electrically connected to the electrode region 24 on the side opposite the resistance region 20, and is further electrically connected to the electrode 45 through the electrode region 24. The electrode region 24 is a compound semiconductor region formed in the same layer as the main electrode region 44 of the field-effect transistor Tr. That is, the electrode region 24 is disposed in a recess 24R dug down from the main surface of the substrate 10 in the thickness direction of the substrate 10. The electrode region 24 is formed of GaN as a compound semiconductor. The electrode 45 is disposed on the electrode region 24. The electrode 45 is formed from the same electrode material as the electrode 45 formed on the main electrode region 44.

[0038] On the other hand, the second conductive region 22 is electrically connected to the electrode region 24 on the opposite side to the resistance region 20. The electrode region 24 is a compound semiconductor region formed in the same layer as the main electrode region 44 of the field effect transistor Tr, and is disposed within the recess 24R. The electrode region 24 electrically connected to the second conductive region 22 is electrically connected to the main electrode region 44 of the field effect transistor Tr and is formed integrally therewith.

[0039] Here, in the formation region of the field-effect transistor Tr, the recess 44R corresponds to the "first recess" according to the present technology, and the main electrode region 44 corresponds to the "first compound semiconductor region" according to the present technology. Also, in the formation region of the protection element 2, the recess 24R corresponds to the "second recess" according to the present technology, and the electrode region 24 corresponds to the "second compound semiconductor region" according to the present technology.

[0040] The first conductive region 21 of the protection element 2 electrically connects the electrode region 24 and the electrode 45 to the wiring 47L. That is, the first conductive region 21 is electrically connected to the gate electrode 47 of the field-effect transistor Tr. In other words, when the gate electrode 47 is formed in the manufacturing process of the semiconductor device 1, the field-effect transistor Tr is essentially completed, and simultaneously with this completion, the gate electrode 47 is electrically connected to the protection element 2. That is, in the process of forming the gate electrode 47 and in subsequent processes, it is possible to effectively suppress or prevent plasma induced damage (PID) or electrostatic discharge (ESD) breakdown occurring in the field-effect transistor Tr.

[0041] (4) Current-Voltage Characteristics of Protection Element 2 Figure 4 shows an example of the current-voltage characteristics of the protection element 2. In Figure 4, the horizontal axis represents the operating voltage [V] of the protection element 2. The vertical axis represents the operating current [mA] of the protection element 2.

[0042] As is clear from FIG. 4 , in the protection element 2, increasing the separation distance L1 between the resistive regions 20 increases the operating voltage, as indicated by data d1, d2, and d3. That is, increasing the separation distance L1 shifts the threshold voltage at which a positive current begins to flow toward the positive side, and the breakdown voltage at which a negative current begins to flow toward the negative side, thereby adjusting the operating voltage. For example, when the separation distance L1 is set within a range of 0.1 μm to 0.9 μm, the operating voltage of the protection element 2 can be adjusted to approximately 100 V or less. When the separation distance L1 exceeds 1.0 μm, the operating voltage of the protection element 2 exceeds approximately 100 V. As an example, when the separation distance L1 is set to 0.6 μm, the operating voltage of the protection element 2 can be adjusted to approximately 36 V. When the semiconductor device 1 is used for a mobile terminal, the operating voltage of the protection element 2 is required to be 100 V or less.

[0043] 5 to 8 show an example of cross sections illustrating each step in the manufacturing method of the semiconductor device 1. The manufacturing method of the semiconductor device 1 according to the first embodiment is as follows.

[0044] First, a substrate 10 is prepared (see FIG. 5). A GaN substrate as a compound semiconductor is used for the substrate 10. The substrate 10 is formed as a channel layer 41 in a region where the field-effect transistor Tr is formed and a region where the protection element 2 is formed.

[0045] 5, a barrier layer 43 is formed in a channel layer 41. The barrier layer 43 is formed by, for example, epitaxial growth. When the barrier layer 43 is formed, a two-dimensional electron gas 42 is generated in the channel layer 41 in a region where the field-effect transistor Tr is to be formed. Similarly, a two-dimensional electron gas 42 is generated in the channel layer 41 in a region where the protection element 2 is to be formed.

[0046] 6 , a pair of main electrode regions 44 are formed in the region where the field-effect transistor Tr is formed. The main electrode regions 44 are embedded in recesses (first recesses) 44R dug in the depth direction from the main surface of the channel layer 41. The main electrode regions 44 are compound semiconductor regions (first compound semiconductor regions) grown using, for example, selective epitaxial growth, and are made of, for example, GaN. The recesses 44R are formed using, for example, photolithography and etching techniques.

[0047] Meanwhile, in the region where the protective element 2 is formed, the electrode region 24 is formed in the same process as the process of forming the main electrode region 44. The electrode region 24 is embedded in a recess (second recess) 24R that is dug down in the depth direction from the main surface of the channel layer 41. The recess 24R is formed in the same process as the process of forming the recess 44R. The electrode region 24 is a compound semiconductor region (second compound semiconductor region) grown using, for example, selective epitaxial growth, and is made of, for example, GaN.

[0048] As shown in FIG. 7 , a portion of the barrier layer 43 is removed in the region where the protection element 2 is to be formed. This removal is performed using, for example, photolithography and etching. When the portion of the barrier layer 43 is removed, the two-dimensional electron gas 42 in this region disappears, and the resistance region 20 is formed. Furthermore, when the resistance region 20 is formed, the two-dimensional electron gas 42 is divided, and a first conductive region 21 is formed from one of the divided portions of the two-dimensional electron gas 42, and a second conductive region 22 is formed from the other. In other words, the protection element 2 is formed, including the first conductive region 21, the resistance region 20, and the second conductive region 22. The operating voltage of the protection element 2 can be adjusted using, for example, the length of the resistance region 20 that coincides with the direction of current flow, i.e., the distance L1 between the first conductive region 21 and the second conductive region 22, as a factor.

[0049] 8, in the region where the field-effect transistor Tr is formed, an electrode 45 is formed in the main electrode region 44. In the same process, in the region where the protection element 2 is formed, an electrode 45 is formed in the electrode region 24. Note that the process of forming the resistance region 20 of the protection element 2 (the process of removing a part of the barrier layer 43) can be performed after the process of forming the electrode 45.

[0050] Subsequently, an insulating layer 46 is formed to cover the electrode 45 (see FIG. 3). Next, an opening 46H is formed in the insulating layer 46 in the region where the field-effect transistor Tr is to be formed (see FIG. 3). The opening 46H is a through-hole that exposes the surface of the barrier layer 43. In the same process as the process for forming the opening 46H, an opening 46H is formed in the insulating layer 46 in the region where the protection element 2 is to be formed. This opening 46H is a through-hole that exposes the surface of the electrode 45. For example, photolithography and etching techniques are used to form the opening 46H.

[0051] 2 and 3 , in the region where the field-effect transistor Tr is formed, a gate electrode 47 is formed in contact with the barrier layer 43 through the opening 46H. In the same process as the process for forming the gate electrode 47, a wiring 47L is formed in the region where the protection element 2 is formed, the wiring 47L being integral with and electrically connected to the gate electrode 47. The wiring 47L is electrically connected to the electrode 45 drawn out from the protection element 2 through the opening 46H.

[0052] Thereafter, an insulating layer and upper layer wiring (not shown) are sequentially formed, thereby completing the semiconductor device 1 according to the first embodiment and completing the manufacturing method.

[0053] [Operation and Effect] As shown in FIGS. 1 to 3, the semiconductor device 1 according to the first embodiment includes a protection element 2. The protection element 2 includes a first conductive region 21, a second conductive region 22, and a resistance region 20. The first conductive region is disposed on the surface of the substrate 10 and is conductive. The second conductive region 22 is disposed on the surface of the substrate 10, spaced apart from the first conductive region 21, and is conductive. The resistance region 20 is disposed between the first conductive region 21 and the second conductive region 22. The resistance region 20 has a higher resistivity than the first conductive region 21 and the second conductive region 22. In the protection element 2 configured in this manner, the operating voltage can be adjusted by changing the separation distance L1 between the first conductive region 21 and the second conductive region 22, as shown in FIG. 4. For example, in the comparative example, the operating voltage is increased by staging GaN-based Schottky barrier diodes, but in the protection element 2 according to the first embodiment, the operating voltage can be increased by increasing the separation distance L1, thereby reducing the area occupied by the protection element 2. Therefore, the integration degree of the semiconductor device 1 can be improved, and the semiconductor device 1 can be made smaller.

[0054] 2 and 3, the substrate 10 of the semiconductor device 1 is formed to include a compound semiconductor. It is difficult to fabricate a highly doped p-type semiconductor region for forming, for example, a diode as a protective element in a compound semiconductor. Therefore, the protective element 2 is an effective element for effectively suppressing or preventing PID or ESD breakdown of the semiconductor device 1.

[0055] As shown in FIGS. 2 and 3 , the semiconductor device 1 also includes a field-effect transistor Tr in a region different from the protection element 2. The field-effect transistor Tr is a HEMT. The field-effect transistor Tr includes a channel layer (first channel layer) 41, a barrier layer (first barrier layer) 43, a gate electrode 47, and a pair of main electrode regions 44. The channel layer 41 is disposed on the surface of the substrate 10, and a two-dimensional electron gas 42 is generated therein. The barrier layer 43 is disposed in the channel layer 41. The gate electrode 47 is disposed on the channel layer 41 with the barrier layer 43 interposed therebetween. The pair of main electrode regions 44 are disposed on both sides of the gate electrode 47 in the gate length direction and are electrically connected to the channel layer 41, respectively. As described above, the field-effect transistor Tr is formed including a compound semiconductor. It is difficult to fabricate a highly doped p-type semiconductor region in a compound semiconductor to form, for example, a diode as a protection element. Therefore, the protective element 2 is an effective element in terms of effectively suppressing or preventing PID or ESD damage to the semiconductor device 1 .

[0056] 1 to 3, in the semiconductor device 1, the first conductive region 21 of the protection element 2 is electrically connected to the gate electrode 47 of the field-effect transistor Tr, and the second conductive region 22 is electrically connected to one main electrode region 44(S) of the pair of main electrode regions 44. Therefore, when a surge is input to the gate electrode 47 of the field-effect transistor Tr, the protection element 2 can mitigate or absorb the surge, thereby effectively suppressing or preventing PID or ESD damage to the semiconductor device 1.

[0057] As shown in FIGS. 2 and 3 , the semiconductor device 1 further includes an electrode (first electrode) 45 disposed in and electrically connected to one of a pair of main electrode regions 44 of the field-effect transistor Tr. Meanwhile, the semiconductor device 1 further includes an electrode (second electrode) 45 electrically connected to at least the first conductive region 21 of the protection element 2 and in the same layer as the electrode (first electrode) 45. The gate electrode 47 of the field-effect transistor Tr is electrically connected to the electrode (second electrode) 45 of the protection element 2 through a wiring 47L in the same layer as the gate electrode 47. As shown in FIGS. 2 , 3 , 7 , and 8 , according to the manufacturing method of the semiconductor device 1, the wiring 47L is formed in the same process as the process of forming the gate electrode 47 of the field-effect transistor Tr. The wiring 47L electrically connects the gate electrode 47 to the first conductive region 21 of the protection element 2. This makes it possible to effectively suppress or prevent PID or ESD damage occurring in the field effect transistor Tr in the process of forming the gate electrode 47 and in subsequent processes in the manufacturing process of the semiconductor device 1. Furthermore, it is possible to effectively suppress or prevent ESD damage after the semiconductor device 1 is completed.

[0058] 2 and 3 , in the semiconductor device 1, the first conductive region 21 and the second conductive region 22 of the protection element 2 are each formed to include two-dimensional electron gas 42 generated in a channel layer (second channel layer) 41 that is the same layer as the channel layer (first channel layer) 41 of the field-effect transistor Tr. The resistance region 20 of the protection element 2 is formed to include a channel layer (second channel layer) 41 in which two-dimensional electron gas 42 is not generated. Therefore, the components of the first conductive region 21, the second conductive region 22, and the resistance region 20 of the protection element 2 can be easily constructed using the components of the two-dimensional electron gas 42 and the barrier layer 43 of the field-effect transistor Tr. In the manufacturing method of the semiconductor device 1, the protection element 2 is formed using the process of forming the field-effect transistor Tr, so the number of manufacturing steps can be reduced compared to when a new process of forming the protection element 2 is added.

[0059] 2 and 3 , in the semiconductor device 1, a barrier layer 43 is disposed in the channel layer 41 in regions corresponding to the first conductive region 21 and the second conductive region 22 of the protection element 2, and the barrier layer 43 is not disposed in the channel layer 41 in a region corresponding to the resistance region 20. Therefore, in the protection element 2, the first conductive region 21, the second conductive region 22, and the resistance region 20 can be easily formed depending on the presence or absence of the barrier layer 43.

[0060] 2. Second Embodiment A semiconductor device 1 according to a second embodiment of the present disclosure will be described with reference to Fig. 9. In the second embodiment and the embodiments described thereafter, components that are the same as or substantially the same as components in the first embodiment are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0061] [Configuration of Semiconductor Device 1] FIG. 9 shows an example of a vertical cross-sectional configuration of the semiconductor element 4 and the protective element 2 that constitute the internal circuit 3 of the semiconductor device 1. As shown in FIG.

[0062] The semiconductor device 1 according to the second embodiment has a different configuration of the resistance region 20 of the protection element 2 from the semiconductor device 1 according to the first embodiment. This will be explained in detail. That is, the resistance region 20 of the protection element 2 has crystal defects formed in the corresponding region of the channel layer 41. The number of crystal defects in the resistance region 20 is greater than the number of crystal defects in the channel layer 41 other than the resistance region 20.

[0063] The resistance region 20 is formed by introducing impurities into the channel layer 41. For example, ion implantation is used for the introduction. The impurity ion species may be one or more substances selected from the group consisting of boron (B), carbon (C), iron (Fe), magnesium (Mg), and zinc (Zn). In other words, the concentration of a substance that generates crystal defects in the resistance region 20 is higher than the concentration of the same substance in the channel layer 41 other than the resistance region 20. In particular, the concentration of a substance that generates crystal defects in the resistance region 20 is higher than the concentrations of the same substance in each of the first conductive region 21 and the second conductive region 22.

[0064] In the second embodiment, a barrier layer 43 is disposed in the channel layer 41 in a region corresponding to the resistor region 20. In other words, the barrier layer 43 is not removed. Of course, the barrier layer 43 does not have to be disposed in the region corresponding to the resistor region 20. The resistor region 20 can be formed regardless of whether or not the barrier layer 43 is present.

[0065] The other components are the same or substantially the same as the components of the semiconductor device 1 according to the first embodiment described above.

[0066] [Operational Effects] According to the semiconductor device 1 of the second embodiment, it is possible to obtain the same operational effects as those obtained by the semiconductor device 1 of the first embodiment.

[0067] Furthermore, in the semiconductor device 1, as shown in FIG. 9, the resistive region 20 of the protective element 2 can be formed by crystal defects, so that the protective element 2 can be easily configured.

[0068] 9 , the resistive region 20 of the protective element 2 is formed by introducing impurities to generate crystal defects. The resistivity of the resistive region 20 can be changed by appropriately changing either or both of the ion species and the introduction amount (dose) of the impurity that generates the crystal defects. Therefore, in the protective element 2, the operating voltage can be adjusted not only by dimensional factors such as the separation distance L1 but also by using physical factors that determine the electrical characteristics of the channel layer 41 itself.

[0069] 3. Third Embodiment A semiconductor device 1 according to a third embodiment of the present disclosure will be described with reference to FIG.

[0070] [Configuration of Semiconductor Device 1] FIG. 10 shows an example of a vertical cross-sectional configuration of the semiconductor element 4 and the protective element 2 that constitute the internal circuit 3 of the semiconductor device 1. As shown in FIG.

[0071] 10, the semiconductor device 1 according to the third embodiment has different configurations of the protection element 2 and the field effect transistor Tr from the semiconductor device 1 according to the first embodiment.

[0072] First, in the field-effect transistor Tr, the main electrode region 44 of the field-effect transistor Tr of the semiconductor device 1 according to the first embodiment is omitted, and the two-dimensional electron gas 42 is directly and electrically connected to the electrode 45. Similarly, in the protection element 2, the first conductive region 21 and the second conductive region 22 formed by the two-dimensional electron gas 42 are each directly and electrically connected to the electrode 45.

[0073] The other components are the same or substantially the same as the components of the semiconductor device 1 according to the first embodiment described above.

[0074] [Operational Effects] According to the semiconductor device 1 of the third embodiment, it is possible to obtain the same operational effects as those obtained by the semiconductor device 1 of the first embodiment.

[0075] 4. Fourth Embodiment A semiconductor device 1 according to a fourth embodiment of the present disclosure will be described with reference to FIG.

[0076] [Configuration of Semiconductor Device 1] FIG. 11 shows an example of a vertical cross-sectional configuration of the semiconductor element 4 and the protective element 2 that constitute the internal circuit 3 of the semiconductor device 1. As shown in FIG.

[0077] 11, the semiconductor device 1 according to the fourth embodiment is an application example in which the semiconductor device 1 according to the third embodiment is combined with the semiconductor device 1 according to the second embodiment.

[0078] That is, crystal defects are formed in the resistance region 20 of the protection element 2 in the corresponding region of the channel layer 41. The number of crystal defects in the resistance region 20 is greater than the number of crystal defects in the channel layer 41 other than the resistance region 20. The method for generating crystal defects, the ion species of the impurities, etc. are the same as the method for generating crystal defects, the ion species of the impurities, etc. of the semiconductor device 1 according to the second embodiment.

[0079] The other components are the same or substantially the same as the components of the semiconductor device 1 according to the second and third embodiments described above.

[0080] [Effects] According to the semiconductor device 1 of the fourth embodiment, it is possible to obtain an effect that combines the effects obtained by the semiconductor device 1 of the second embodiment and the effects obtained by the semiconductor device 1 of the third embodiment.

[0081] 5. Fifth Embodiment A semiconductor device 1 according to a fifth embodiment of the present disclosure will be described with reference to FIG.

[0082] [Configuration of Semiconductor Device 1] FIG. 12 shows an example of a vertical cross-sectional configuration of the semiconductor element 4 and the protective element 2 that constitute the internal circuit 3 of the semiconductor device 1. As shown in FIG.

[0083] 12, the semiconductor device 1 according to the fifth embodiment is different from the semiconductor device 1 according to the first embodiment in that the configurations of the first conductive region 21 and the second conductive region 22 of the protective element 2 are changed.

[0084] That is, in the protection element 2, the first conductive region 21 is formed by the electrode region 24, and the second conductive region 22 is similarly formed by the electrode region 24. As described above, the electrode region 24 is embedded in the recess 24R formed in the channel layer 41. In addition, the electrode region 24 is a compound semiconductor region (second compound semiconductor region) embedded in the recess 24R.

[0085] The resistance region 20 is disposed between the first conductive region 21 and the second conductive region 22, and between the electrode regions 24. The resistance region 20 is formed by a channel layer 41 in which a two-dimensional electron gas 42 is not generated.

[0086] The other components are the same or substantially the same as the components of the semiconductor device 1 according to the first embodiment described above.

[0087] [Operational Effects] According to the semiconductor device 1 of the fifth embodiment, it is possible to obtain the same operational effects as those obtained by the semiconductor device 1 of the first embodiment.

[0088] 6. Sixth Embodiment A semiconductor device 1 according to a sixth embodiment of the present disclosure will be described with reference to FIG.

[0089] [Configuration of Semiconductor Device 1] FIG. 13 shows an example of a vertical cross-sectional configuration of the semiconductor element 4 and the protective element 2 that constitute the internal circuit 3 of the semiconductor device 1. As shown in FIG.

[0090] 13, the semiconductor device 1 according to the sixth embodiment is different from the semiconductor device 1 according to the fifth embodiment in the configuration of the resistance region 20 of the protection element 2. This will be described in detail.

[0091] That is, in the resistive region 20 of the protective element 2, similar to the resistive region 20 of the semiconductor device 1 according to the second embodiment, crystal defects are formed in the corresponding region of the channel layer 41. The number of crystal defects in the resistive region 20 is greater than the number of crystal defects in the channel layer 41 other than the resistive region 20. In this case, the number of crystal defects is greater than the number of crystal defects in the electrode regions 24, which are the first conductive region 21 and the second conductive region 22.

[0092] The other components are the same or substantially the same as the components of the semiconductor device 1 according to the fifth embodiment described above.

[0093] [Effects] According to the semiconductor device 1 of the sixth embodiment, it is possible to obtain an effect that combines the effects obtained by the semiconductor device 1 of the second embodiment and the effects obtained by the semiconductor device 1 of the fifth embodiment.

[0094] 7. Seventh Embodiment A semiconductor module 100 according to a seventh embodiment of the present disclosure will be described with reference to Fig. 14. Fig. 14 shows a schematic structure of the semiconductor module 100 according to the seventh embodiment.

[0095] [Configuration of Semiconductor Module 100] The semiconductor module 100 according to the fifth embodiment is an antenna-integrated module in which, for example, edge antennas 101 arranged in an array and front-end components are mounted as a single module on a substrate 110. The front-end components include a switch 102, a low-noise amplifier 103, a band-pass filter 104, and a power amplifier 105. The semiconductor module 100 can be used, for example, as a transceiver for communications.

[0096] The semiconductor module 100 includes, for example, a semiconductor device 1 according to any one of the first to fourth embodiments as a transistor constituting a switch 102, a low-noise amplifier 103, a power amplifier 105, or the like.

[0097] [Effects] The semiconductor module 100 according to the seventh embodiment includes the semiconductor device 1, which makes it possible to achieve even faster wireless communication, higher efficiency, and lower power consumption. The protection element 2 according to any one of the first to sixth embodiments is mounted on the semiconductor device 1. Therefore, in the semiconductor module 100, the structure of the protection element 2 can be simplified, and the area occupied by the protection element 2 can be reduced while improving protection tolerance against PID or ESD damage.

[0098] 8. Eighth Embodiment A wireless communication device 300 according to an eighth embodiment of the present disclosure will be described with reference to Fig. 15. Fig. 15 shows a schematic block configuration of the wireless communication device 300 according to the eighth embodiment.

[0099] [Configuration of Wireless Communication Device 300] The wireless communication device 300 according to the eighth embodiment includes an antenna ANT, an antenna switch circuit 301, a high-power amplifier HPA, a radio frequency integrated circuit RFIC (Radio Frequency Integrated Circuit), a baseband unit BB, an audio output unit MIC, a data output unit DT, and an interface unit I / F. The interface unit I / F includes, for example, a wireless local area network (W-LAN) and Bluetooth (registered trademark). The wireless communication device 300 is, for example, a mobile phone system having multiple functions such as voice and data communication and LAN connection.

[0100] The wireless communication device 300 includes a semiconductor device 1 according to any one of the first to fourth embodiments as transistors constituting an antenna switch circuit 301, a high power amplifier HPA, a radio frequency integrated circuit RFIC, or a baseband unit BB.

[0101] [Effects] The wireless communication device 300 according to the eighth embodiment includes the semiconductor device 1, which enables wireless communication to be performed at a higher speed, with higher efficiency, and with lower power consumption. Therefore, when the wireless communication device 300 is a mobile communication terminal, the wireless communication device 300 can further extend the operating time, thereby further improving portability. Furthermore, the protection element 2 according to any one of the first to sixth embodiments is mounted on the semiconductor device 1. Therefore, the wireless communication device 300 can simplify the structure of the protection element 2, improve protection tolerance against PID or ESD damage, and reduce the area occupied by the protection element 2.

[0102] 9. Other Embodiments The present technology is not limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the technology.

[0103] For example, the semiconductor device according to the present technology can use a compound semiconductor other than GaN that can achieve the same effect. The present technology can also be applied to a semiconductor device including a field-effect transistor having an insulated gate structure. Furthermore, the present technology may combine the protection element with another protection element. For example, the other protection element may be one or more elements selected from a diode, a resistor, and a capacitor.

[0104] As described above, the semiconductor device according to the first embodiment of the present disclosure includes a protection element including a first conductive region, a second conductive region, and a resistance region. The first conductive region is disposed on the surface of a substrate and is conductive. The second conductive region is disposed on the surface of the substrate at a distance from the first conductive region and is conductive. The resistance region is disposed between the first conductive region and the second conductive region and has a resistivity greater than the resistivity of each of the first conductive region and the second conductive region. In a semiconductor device configured in this manner, the operating voltage of the protection element can be adjusted by changing the separation distance between the first conductive region and the second conductive region. This reduces the area occupied by the protection element, thereby enabling the miniaturization of the semiconductor device.

[0105] A semiconductor device according to a second embodiment of the present disclosure is the semiconductor device according to the first embodiment, further comprising a high electron mobility transistor in a region different from the protection element. The high electron mobility transistor has a first channel layer, a first barrier layer, a gate electrode, and a pair of main electrode regions. The first channel layer is disposed on a surface of a substrate, and two-dimensional electron gas is generated in the first channel layer. The first barrier layer is disposed in the first channel layer. The gate electrode is disposed on the first channel layer with the first barrier layer interposed therebetween. The pair of main electrode regions are disposed on both sides of the gate electrode in the gate length direction and are electrically connected to the first channel layer, respectively. In a semiconductor device configured in this manner, the protection element is an effective element in terms of effectively suppressing or preventing PID or ESD breakdown.

[0106] A semiconductor device according to a third embodiment of the present disclosure is the semiconductor device according to the second embodiment, wherein the first conductive region is electrically connected to the gate electrode, and the second conductive region is electrically connected to one of the pair of main electrode regions. With this semiconductor device configured in this manner, when a surge is input to the gate electrode of the high electron mobility transistor, the surge can be mitigated or absorbed by the protection element. Therefore, PID or ESD damage of the semiconductor device can be effectively suppressed or prevented.

[0107] A semiconductor module according to a fourth embodiment of the present disclosure includes a semiconductor device. The semiconductor device includes a protection element including a first conductive region, a second conductive region, and a resistance region. The first conductive region is disposed on a surface of a substrate and is conductive. The second conductive region is disposed on the surface of the substrate, spaced apart from the first conductive region, and is conductive. The resistance region is disposed between the first conductive region and the second conductive region and has a resistivity greater than the resistivity of each of the first conductive region and the second conductive region. According to a semiconductor module configured in this manner, the operating voltage of the protection element of the semiconductor device can be adjusted by changing the separation distance between the first conductive region and the second conductive region. This reduces the area occupied by the protection element, thereby achieving a miniaturized semiconductor module including the semiconductor device.

[0108] An electronic device according to a fifth embodiment of the present disclosure includes a semiconductor device. The semiconductor device includes a protective element including a first conductive region, a second conductive region, and a resistive region. The first conductive region is disposed on a surface of a substrate and is conductive. The second conductive region is disposed on the surface of the substrate, spaced apart from the first conductive region, and is conductive. The resistive region is disposed between the first conductive region and the second conductive region and has a resistivity greater than the resistivity of each of the first conductive region and the second conductive region. According to a semiconductor device configured in this manner, the protective element of the semiconductor device can adjust its operating voltage by changing the separation distance between the first conductive region and the second conductive region. This reduces the area occupied by the protective element, thereby enabling the miniaturization of the electronic device, including the semiconductor device.

[0109] <Configuration of the Present Technology> The present technology has the following configuration: According to the present technology having the following configuration, it is possible to reduce the area occupied by a protection element of a semiconductor device in a semiconductor device, a semiconductor module, and an electronic device, thereby realizing miniaturization.

[0110] (1) A semiconductor device including a protection element including: a first conductive region having conductivity disposed on a surface of a substrate; a second conductive region having conductivity disposed on the surface and spaced apart from the first conductive region; and a resistive region disposed between the first conductive region and the second conductive region and having a resistive property higher than the resistive property of each of the first conductive region and the second conductive region. (2) The semiconductor device according to (1), wherein the substrate is formed to contain a compound semiconductor. (3) The semiconductor device according to (2), further including: a high electron mobility transistor disposed on the surface in a region different from the protection element, the high electron mobility transistor having: a first channel layer in which two-dimensional electron gas is generated, a first barrier layer disposed in the first channel layer, a gate electrode disposed on the first channel layer with the first barrier layer interposed therebetween; and a pair of main electrode regions disposed on both sides of the gate electrode in a gate length direction and electrically connected to the first channel layer, respectively. (4) The semiconductor device according to (3), wherein the first conductive region is electrically connected to the gate electrode, and the second conductive region is electrically connected to one of the pair of main electrode regions. (5) The semiconductor device according to (3) or (4), wherein the first conductive region and the second conductive region are each formed to include two-dimensional electron gas generated in a second channel layer in the same layer as the first channel layer, and the resistance region is formed to include the second channel layer in which the two-dimensional electron gas is not generated. (6) The semiconductor device according to (5), wherein a second barrier layer in the same layer as the first barrier layer is disposed in the second channel layer in regions corresponding to the first conductive region and the second conductive region, and the second barrier layer is not disposed in the second channel layer in a region corresponding to the resistance region. (7) The semiconductor device according to (5), wherein a second barrier layer in the same layer as the first barrier layer is disposed in the second channel layer in regions corresponding to the first conductive region and the second conductive region, and the second channel layer has more crystal defects than the first channel layer in a region corresponding to the resistance region.(8) The semiconductor device according to (5) or (6), wherein in the high electron mobility transistor, one or the other of the pair of main electrode regions is formed to include a first compound semiconductor region buried in a first recess dug down from the surface of the first channel layer in the depth direction and electrically connected to the two-dimensional electron gas, and in the protection element, at least the first conductive region is electrically connected to a second compound semiconductor region buried in a second recess dug down from the surface of the second channel layer in the depth direction. (9) The semiconductor device according to (7), wherein in the high electron mobility transistor, one or the other of the pair of main electrode regions is formed to include a first compound semiconductor region buried in a first recess dug down from the surface of the first channel layer in the depth direction and electrically connected to the two-dimensional electron gas, and in the protection element, at least the first conductive region is electrically connected to a second compound semiconductor region buried in a second recess dug down from the surface of the second channel layer in the depth direction. (10) The semiconductor device according to (5) or (6), wherein in the high electron mobility transistor, one or the other of the pair of main electrode regions is formed to include a first compound semiconductor region buried in a first recess dug down from the surface of the first channel layer in the depth direction and electrically connected to the two-dimensional electron gas, and in the protection element, at least the first conductive region is a second compound semiconductor region buried in a second recess dug down from the surface of the second channel layer in the depth direction. (11) The semiconductor device according to (7), wherein in the high electron mobility transistor, one or the other of the pair of main electrode regions is formed to include a first compound semiconductor region buried in a first recess dug down from the surface of the first channel layer in the depth direction and electrically connected to the two-dimensional electron gas, and in the protection element, at least the first conductive region is a second compound semiconductor region buried in a second recess dug down from the surface of the second channel layer in the depth direction.(12) The semiconductor device according to (7), (9) or (11), wherein the resistance region contains one or more substances selected from B, C, Fe, Mg and Zn, and a concentration of the substance contained in the resistance region is higher than a concentration of the same type of substance contained in each of the first conductive region and the second conductive region. (13) The semiconductor device according to any one of (3) to (12), wherein each of the first channel layer and the first barrier layer is a compound semiconductor represented by the following composition formula: Al. １－ｘ－ｙ Ga ｘ In ｙ N (0≦x<1, 0≦y<1) (14) The semiconductor device according to any one of (8) to (13), wherein each of the first compound semiconductor region and the second compound semiconductor region is a compound semiconductor represented by the following composition formula: Al １－ｘ－ｙ Ga ｘ In ｙN (0≦x<1, 0≦y<1) (15) The semiconductor device according to any one of (3) to (14), wherein the high electron mobility transistor further comprises a first electrode disposed on and electrically connected to one of the pair of main electrode regions, and the protection element further comprises a second electrode electrically connected to at least the first conductive region and in the same layer as the first electrode, and the gate electrode is electrically connected to the second electrode through wiring in the same layer as the gate electrode. (16) A semiconductor module comprising a semiconductor device, the semiconductor device including a protection element including: a first conductive region disposed on a surface of a substrate and having conductivity; a second conductive region disposed on the surface and spaced apart from the first conductive region; and a resistive region disposed between the first conductive region and the second conductive region and having a resistive property higher than that of the first conductive region and the second conductive region. (17) An electronic device comprising a semiconductor device, the semiconductor device comprising a protection element including: a first conductive region disposed on a surface of a substrate and having conductivity; a second conductive region disposed on the surface and spaced apart from the first conductive region; and a resistive region disposed between the first conductive region and the second conductive region and having a resistive property greater than the resistive properties of the first conductive region and the second conductive region.

[0111] This application claims priority based on Japanese Patent Application No. 2023-200328, filed on November 28, 2023, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0112] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. A semiconductor device equipped with a protection element including: a first conductive region having conductivity arranged on a surface of a substrate; a second conductive region having conductivity arranged on the surface and spaced apart from the first conductive region; and a resistive region arranged between the first conductive region and the second conductive region and having a resistive property greater than the resistive properties of the first conductive region and the second conductive region.

2. The semiconductor device according to claim 1, wherein the substrate is formed to include a compound semiconductor.

3. The semiconductor device according to claim 2, further comprising a high electron mobility transistor having: a first channel layer disposed on the surface in a region different from said protective element, in which a two-dimensional electron gas is generated; a first barrier layer disposed on said first channel layer; a gate electrode disposed on said first channel layer with said first barrier layer interposed therebetween; and a pair of main electrode regions disposed on both sides of said gate electrode in the gate length direction and each electrically connected to said first channel layer.

4. The semiconductor device according to claim 3, wherein the first conductive region is electrically connected to the gate electrode, and the second conductive region is electrically connected to one of the pair of main electrode regions.

5. The semiconductor device according to claim 3, wherein each of the first conductive region and the second conductive region is formed to include two-dimensional electron gas generated in a second channel layer which is the same layer as the first channel layer, and the resistance region is formed to include the second channel layer in which the two-dimensional electron gas is not generated.

6. The semiconductor device according to claim 5, wherein a second barrier layer, which is the same layer as the first barrier layer, is disposed in the second channel layer in regions corresponding to the first conductive region and the second conductive region, respectively, and wherein the second barrier layer is not disposed in the second channel layer in a region corresponding to the resistance region.

7. The semiconductor device according to claim 5, wherein a second barrier layer identical to the first barrier layer is disposed in the second channel layer in regions corresponding to the first conductive region and the second conductive region, and wherein more crystal defects are formed in the second channel layer than in the first channel layer in a region corresponding to the resistance region.

8. The semiconductor device according to claim 5, wherein in the high electron mobility transistor, each of the pair of main electrode regions is formed to include a first compound semiconductor region buried in a first recess dug down in the depth direction from the surface of the first channel layer and electrically connected to the two-dimensional electron gas, and in the protection element, at least the first conductive region is electrically connected to a second compound semiconductor region buried in a second recess dug down in the depth direction from the surface of the second channel layer.

9. The semiconductor device according to claim 7, wherein in the high electron mobility transistor, each of the pair of main electrode regions is formed to include a first compound semiconductor region buried in a first recess dug down in the depth direction from the surface of the first channel layer and electrically connected to the two-dimensional electron gas, and in the protection element, at least the first conductive region is electrically connected to a second compound semiconductor region buried in a second recess dug down in the depth direction from the surface of the second channel layer.

10. The semiconductor device according to claim 5, wherein in the high electron mobility transistor, each of the pair of main electrode regions is formed to include a first compound semiconductor region buried in a first recess dug down in the depth direction from the surface of the first channel layer and electrically connected to the two-dimensional electron gas, and in the protection element, at least the first conductive region is a second compound semiconductor region buried in a second recess dug down in the depth direction from the surface of the second channel layer.

11. The semiconductor device according to claim 7, wherein in the high electron mobility transistor, each of the pair of main electrode regions is formed to include a first compound semiconductor region buried in a first recess dug down in the depth direction from the surface of the first channel layer and electrically connected to the two-dimensional electron gas, and in the protection element, at least the first conductive region is a second compound semiconductor region buried in a second recess dug down in the depth direction from the surface of the second channel layer.

12. The semiconductor device described in claim 7, wherein the resistance region contains one or more substances selected from B, C, Fe, Mg and Zn, and the concentration of the substance contained in the resistance region is higher than the concentration of the same type of substance contained in each of the first conductive region and the second conductive region.

13. The semiconductor device according to claim 3, wherein the first channel layer and the first barrier layer are each a compound semiconductor represented by the following composition formula: Al １－ｘ－ｙ G ｘ In ｙ N (0≦x<1, 0≦y<1) 14. The semiconductor device according to claim 8, wherein the first compound semiconductor region and the second compound semiconductor region are each a compound semiconductor represented by the following composition formula: Al １－ｘ－ｙ G ｘ In ｙ N (0≦x<1, 0≦y<1) 15. The semiconductor device described in claim 3, wherein the high electron mobility transistor further comprises a first electrode disposed in and electrically connected to one of the pair of main electrode regions, and the protection element further comprises a second electrode electrically connected to at least the first conductive region and in the same layer as the first electrode, and the gate electrode is electrically connected to the second electrode through a wiring in the same layer as the gate electrode.

16. A semiconductor module comprising a semiconductor device, the semiconductor device comprising a protection element including: a first conductive region having conductivity arranged on a surface of a substrate; a second conductive region having conductivity arranged on the surface and spaced apart from the first conductive region; and a resistive region arranged between the first conductive region and the second conductive region and having a resistive property greater than the resistive properties of the first conductive region and the second conductive region.

17. An electronic device comprising a semiconductor device, the semiconductor device comprising a protection element including: a first conductive region having conductivity arranged on a surface of a substrate; a second conductive region having conductivity arranged on the surface and spaced apart from the first conductive region; and a resistive region arranged between the first conductive region and the second conductive region and having a resistive property greater than the resistive properties of the first conductive region and the second conductive region.

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