Semiconductor device and semiconductor device manufacturing method

Abstract

A semiconductor device according to an embodiment of the present disclosure is configured so that a gate electrode of each of a p-type FET and a n-type FET which are included in a second inverter is constituted by a first shared electrode. A first electrode of each of a first ferroelectric capacitor and a second ferroelectric capacitor is constituted by a second shared electrode. The first shared electrode and the second shared electrode are connected to each other. A second electrode of the first ferroelectric capacitor and a second electrode of the second ferroelectric capacitor are disposed so as to be mutually separated.

Description

Semiconductor device and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] A CMOS (Complementary MOS) circuit composed of an nMOSFET (n-type Metal-Oxide-Semiconductor Field-Effect Transistor) and a pMOSFET (p-type MOSFET) provided on the same substrate is known as a circuit that consumes little power, is capable of high-speed operation, and is easy to miniaturize and highly integrate. For this reason, CMOS circuits are used in many LSI (Large Scale Integration) devices. In recent years, such LSI devices have been commercialized as SoCs (Systems on a Chip), which combine analog circuits, memory, logic circuits, and the like on a single chip.

[0003] For example, static random access memory (SRAM) is used as memory mounted on an LSI device. SRAM is capable of high-speed operation, but is a volatile memory in which stored information is lost when the power supply is stopped. Therefore, for example, Patent Documents 1 to 4 propose a structure in which a ferroelectric capacitor is connected to the storage node of a CMOS SRAM. With this structure, the SRAM operates as a normal SRAM during operation, and data is saved to the ferroelectric capacitor during standby, so that data is not lost even when the power is turned off during standby. Therefore, by stopping the power supply after storing data when not in use and then restoring it, the SRAM can be made nonvolatile and consume less power.

[0004] JP 2019-194931 A JP 2019-215941 A JP 2012-065042 A JP 2019-201034 A

[0005] However, when a ferroelectric capacitor is provided in a CMOS SRAM, the area increases by the amount of the ferroelectric capacitor and the wiring required for providing the ferroelectric capacitor, which hinders high integration of the memory. It is desirable to provide a semiconductor device and a method for manufacturing the semiconductor device that can achieve both non-volatility and high integration when a ferroelectric capacitor is provided in a CMOS SRAM.

[0006] A semiconductor device according to an embodiment of the present disclosure includes a first inverter including a p-type FET and an n-type FET, and a second inverter including a p-type FET and an n-type FET. The input of the first inverter is connected to the output of the second inverter, and the input of the second inverter is connected to the output of the first inverter. The semiconductor device further includes a first ferroelectric capacitor and a second ferroelectric capacitor, each having a first electrode and a second electrode, and a third ferroelectric capacitor and a fourth ferroelectric capacitor, each having a third electrode and a fourth electrode. The first electrodes of the first ferroelectric capacitor and the second ferroelectric capacitor are connected in parallel to the output of the first inverter. The third electrodes of the third ferroelectric capacitor and the fourth ferroelectric capacitor are connected in parallel to the output of the second inverter. The semiconductor device further includes a first plate line and a second plate line. The first plate line connects the second electrodes of the first ferroelectric capacitor and the third ferroelectric capacitor. The second plate line connects the fourth electrodes of the second ferroelectric capacitor and the fourth ferroelectric capacitor.

[0007] In a semiconductor device according to an embodiment of the present disclosure, the gate electrodes of the p-type FET and the n-type FET included in the second inverter are formed by a first shared electrode. The first electrodes of the first ferroelectric capacitor and the second ferroelectric capacitor are formed by a second shared electrode. The first shared electrode and the second shared electrode are connected to each other. The gate electrodes of the p-type FET and the n-type FET included in the first inverter are formed by a third shared electrode. The third electrodes of the third ferroelectric capacitor and the fourth ferroelectric capacitor are formed by a fourth shared electrode. The third shared electrode and the fourth shared electrode are connected to each other. The second electrode of the first ferroelectric capacitor and the second electrode of the second ferroelectric capacitor are provided separately from each other. The fourth electrode of the third ferroelectric capacitor and the fourth electrode of the fourth ferroelectric capacitor are provided separately from each other.

[0008] A method for manufacturing a semiconductor device according to an embodiment of the present disclosure is a method for manufacturing a semiconductor device having the following configuration. Here, the semiconductor device includes a first inverter including a p-type FET and an n-type FET, and a second inverter including a p-type FET and an n-type FET. The output of the second inverter is connected to the input of the first inverter, and the input of the second inverter is connected to the output of the first inverter. The semiconductor device further includes a first ferroelectric capacitor and a second ferroelectric capacitor, each having a first electrode and a second electrode, and a third ferroelectric capacitor and a fourth ferroelectric capacitor, each having a third electrode and a fourth electrode. The first electrodes of the first ferroelectric capacitor and the second ferroelectric capacitor are connected in parallel to the output of the first inverter. The third electrodes of the third ferroelectric capacitor and the fourth ferroelectric capacitor are connected in parallel to the output of the second inverter. The semiconductor device further includes a first plate line and a second plate line. The first plate line connects the second electrodes of the first ferroelectric capacitor and the third ferroelectric capacitor. The second plate line connects the fourth electrodes of the second ferroelectric capacitor and the fourth ferroelectric capacitor.

[0009] A method for manufacturing a semiconductor device according to an embodiment of the present disclosure includes: forming the gate electrodes of the p-type FET and the n-type FET included in the second inverter as first shared electrodes; forming the gate electrodes of the p-type FET and the n-type FET included in the first inverter as third shared electrodes; forming, in this order, a first metal film in contact with the first shared electrode and the third shared electrode, a high-dielectric film in contact with the first metal film, and a second metal film in contact with the high-dielectric film; annealing the high-dielectric film to change its phase to a ferroelectric film; and selectively etching the second metal film to form second electrodes of the first ferroelectric capacitor and the second ferroelectric capacitor separated from each other, and also forming fourth electrodes of the third ferroelectric capacitor and the fourth ferroelectric capacitor separated from each other; sidewalls are formed on side surfaces of the second electrode of the first ferroelectric capacitor, the second electrode of the second ferroelectric capacitor, the fourth electrode of the third ferroelectric capacitor, and the fourth electrode of the fourth ferroelectric capacitor so as to cover a gap between the second electrode of the first ferroelectric capacitor and the second electrode of the second ferroelectric capacitor, and to cover a gap between the fourth electrode of the third ferroelectric capacitor and the fourth electrode of the fourth ferroelectric capacitor; and the high dielectric film and the first metal film are etched using the second electrode of the first ferroelectric capacitor, the second electrode of the second ferroelectric capacitor, the fourth electrode of the third ferroelectric capacitor, and the fourth electrode of the fourth ferroelectric capacitor, and the sidewalls as a mask, thereby forming the first electrodes of the first ferroelectric capacitor and the second ferroelectric capacitor as second shared electrodes, and forming the third electrodes of the third ferroelectric capacitor and the fourth ferroelectric capacitor as fourth shared electrodes.

[0010] FIG. 1 is a diagram illustrating an example of a circuit configuration of a semiconductor device 1 according to a first embodiment of the present disclosure. FIG. 2 is a diagram illustrating the correspondence between symbols in FIG. 4 . FIG. 3 is a diagram illustrating an example of a planar configuration and a cross-sectional configuration of the semiconductor device of FIG. 1 . FIG. 4 is a diagram in which the planar configuration of the semiconductor device of FIG. 3 is omitted from the illustration of some components. FIG. 5 is a diagram for explaining an example of a manufacturing process of the semiconductor device of FIG. 3 . FIG. 6 is a diagram for explaining an example of a manufacturing process subsequent to FIG. 4 . FIG. 7 is a diagram for explaining an example of a manufacturing process subsequent to FIG. 5 . FIG. 8 is a diagram for explaining an example of a manufacturing process subsequent to FIG. 6 . FIG. 9 is a diagram for explaining an example of a manufacturing process subsequent to FIG. 7 . FIG. 10 is a diagram for explaining an example of a manufacturing process subsequent to FIG. 8 . FIG. 11 is a diagram for explaining an example of a manufacturing process subsequent to FIG. 9 . FIG. 12 is a diagram for explaining an example of a manufacturing process subsequent to FIG. 10 . FIG. 13 is a diagram for explaining various operations in the semiconductor device of FIG. 1 . FIG. 14 is a diagram for explaining an example of a state transition of the semiconductor device of FIG. 1 . FIG. 15 is a diagram for explaining a modified example of the manufacturing process of the semiconductor device of FIG. 3 . FIG. 16 is a diagram for explaining an example of a manufacturing process subsequent to FIG. 14 . FIG. 17 is a diagram for explaining an example of a manufacturing process subsequent to FIG. 15 . FIG. 18 is a diagram for explaining an example of a manufacturing process subsequent to FIG. 16 . FIG. 19 is a diagram illustrating an example of a planar configuration of a semiconductor device 2 according to a second embodiment of the present disclosure. FIG. 20 is a diagram illustrating an example of a cross-sectional configuration taken along line D-D of FIG. 19 . FIG. 21 is a diagram for explaining an example of a manufacturing process of the semiconductor device of FIG. 19 . FIG. 22 is a diagram for explaining an example of a manufacturing process subsequent to FIG. 21 . FIG. 23 is a diagram for explaining an example of a manufacturing process subsequent to FIG. 22 . FIG. 24 is a diagram for explaining an example of a manufacturing process subsequent to FIG. 23 . FIG. 25 is a diagram for explaining an example of a manufacturing process subsequent to FIG. 24 . FIG. 26 is a diagram for explaining an example of a manufacturing process subsequent to FIG. 25 . FIG. 27 is a diagram illustrating a modification of the circuit configurations of FIGS. 1 and 19 . FIG. 28 is a diagram illustrating an example of a planar configuration of the semiconductor device of FIG. 27 . FIG. 29 is a diagram illustrating an example of a cross-sectional configuration taken along line E-E of FIG. 28 . FIG. 30 is a plan view of the semiconductor device of FIG. 28, with some of the components omitted.

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings.

[0012] <1. Background> CMOS circuits, consisting of nMOSFETs and pMOSFETs mounted on the same substrate, are known for their low power consumption, high-speed operation, and ease of miniaturization and high integration. For this reason, CMOS circuits are used in many LSI devices. In recent years, such LSI devices have been commercialized as SoCs, which combine analog circuits, memory, logic circuits, and other components on a single chip.

[0013] Static RAMs, for example, are used as memories mounted on LSI devices. SRAMs are capable of high-speed operation, but are volatile memories in which stored information is lost when power supply is stopped. Therefore, for example, Patent Documents 1 to 4 propose a structure in which a ferroelectric capacitor is connected to the storage node of a CMOS SRAM. With this structure, the SRAM operates as a normal SRAM during operation, and data is saved to the ferroelectric capacitor during standby, so that data is not lost even when the power is turned off during standby. Therefore, by stopping the power supply after storing data when not in use and then restoring it, the SRAM can be made nonvolatile and consume less power.

[0014] For example, Patent Document 1 describes providing two or four ferroelectric capacitors. For example, Patent Document 2 describes providing four ferroelectric capacitors by providing two ferroelectric capacitors for each of two storage nodes. Here, by adjusting the area ratio of the two ferroelectric capacitors provided in one storage node, it is possible to increase the probability (recall rate) that information stored at the time of evacuation can be correctly reproduced at the time of restoration.

[0015] Incidentally, for example, Patent Document 3 describes providing a ferroelectric capacitor on a MOSFET or on a wiring. However, in such a configuration, the area increases by the amount of the ferroelectric capacitor and the wiring required for providing the ferroelectric capacitor, hindering high integration of the memory. For example, Patent Document 4 describes reducing the area by forming a ferroelectric capacitor on a contact (shared contact) connecting memory nodes. However, this method is applicable only when two ferroelectric capacitors are provided, and cannot be applied when four ferroelectric capacitors are provided.

[0016] In view of the above problems, the present applicant has conceived of providing a semiconductor device and a method for manufacturing the semiconductor device that can achieve both non-volatility and high integration when four ferroelectric capacitors are provided in a CMOS SRAM. Below, a method for compactly forming four ferroelectric capacitors will be described in detail.

[0017] 2. First Embodiment [Configuration] A semiconductor device 1 according to a first embodiment of the present disclosure will be described. Figures 1 and 2 show an example of a circuit configuration of the semiconductor device 1 according to the first embodiment of the present disclosure. Figure 2 shows the correspondence with the reference symbols shown in Figure 4, which will be described later.

[0018] The semiconductor device 1 includes two inverters 10 and 20. The inverter 10 includes a p-type transistor T11 and an n-type transistor T12. The inverter 20 includes a p-type transistor T21 and an n-type transistor T22. The p-type transistor T11, the n-type transistor T12, the p-type transistor T21, and the n-type transistor T22 are configured by voltage-controllable field effect transistors (FETs). The semiconductor device 1 further includes two ferroelectric capacitors C11 and C12 connected to the output (storage node N1) of the inverter 10 and two ferroelectric capacitors C21 and C22 connected to the output (storage node N2) of the inverter 20. The semiconductor device 1 is, for example, a flip-flop circuit capable of holding one bit of information in a "0" or "1" state.

[0019] The inverter 10 is an inverter (NOT) circuit including a p-type transistor T11 and an n-type transistor T12. Specifically, in the inverter 10, one of the source and drain (impurity diffusion region 36a) of the p-type transistor T11 is electrically connected to the power supply line PWR, the other of the source and drain (impurity diffusion region 37a) of the p-type transistor T11 is electrically connected to one of the source and drain (impurity diffusion region 36b) of the n-type transistor T12, and the other of the source and drain (impurity diffusion region 37b) of the n-type transistor T12 is electrically connected to the ground line GND. The gate electrodes of the p-type transistor T11 and the n-type transistor T12 are electrically connected to each other. The gate electrodes of the p-type transistor T11 and the n-type transistor T12 are formed by a common gate electrode 35a (first shared electrode).

[0020] In the inverter 10, the connection point (gate electrode 35a) of the gate of the p-type transistor T11 and the gate of the n-type transistor T12 serves as an input, and the connection point (storage node N1) of the impurity diffusion region 37a of the p-type transistor T11 and the impurity diffusion region 36b of the n-type transistor T12 serves as an output. The input of the inverter 10 is electrically connected to the output of the inverter 20, and the output of the inverter 10 is electrically connected to the input of the inverter 20. Two ferroelectric capacitors C11 and C12 are connected in parallel to the output of the inverter 10 (storage node N1).

[0021] The inverter 20 is an inverter (NOT) circuit including a p-type transistor T21 and an n-type transistor T22. Specifically, in the inverter 20, one of the source and drain (impurity diffusion region 36c) of the p-type transistor T21 is electrically connected to the power supply line PWR, the other of the source and drain (impurity diffusion region 37c) of the p-type transistor T21 is electrically connected to one of the source and drain (impurity diffusion region 36d) of the n-type transistor T22, and the other of the source and drain (impurity diffusion region 37d) of the n-type transistor T22 is electrically connected to the ground line GND. The gate electrodes of the p-type transistor T21 and the n-type transistor T22 are electrically connected to each other. The gate electrodes of the p-type transistor T21 and the n-type transistor T22 are formed by a common gate electrode 35b (third shared electrode).

[0022] In the inverter 20, the connection point (gate electrode 35b) of the gate of the p-type transistor T21 and the gate of the n-type transistor T22 serves as an input, and the connection point (storage node N2) of the impurity diffusion region 37c of the p-type transistor T21 and the impurity diffusion region 36d of the n-type transistor T22 serves as an output. The input of the inverter 20 is electrically connected to the output of the inverter 10, and the output of the inverter 20 is electrically connected to the input of the inverter 10. Two ferroelectric capacitors C21 and C22 are connected in parallel to the output of the inverter 20 (storage node N2).

[0023] Each of the ferroelectric capacitors C11, C12, C21, and C22 is a capacitor formed by sandwiching a ferroelectric film between a pair of electrodes. Each of the ferroelectric capacitors C11, C12, C21, and C22 can store information based on the direction of remanent polarization of the ferroelectric film. One electrode of the ferroelectric capacitor C11 is electrically connected to the output (storage node N1) of the inverter 10, and the other electrode of the ferroelectric capacitor C11 is electrically connected to a plate line PL1 to which an arbitrary potential can be applied. One electrode of the ferroelectric capacitor C12 is electrically connected to the output (storage node N1) of the inverter 10, and the other electrode of the ferroelectric capacitor C11 is electrically connected to a plate line PL2 to which an arbitrary potential can be applied. The electrode of the ferroelectric capacitor C11 electrically connected to the storage node N1 and the electrode of the ferroelectric capacitor C12 electrically connected to the storage node N1 are formed by a common lower electrode 44a (second shared electrode).

[0024] One electrode of the ferroelectric capacitor C21 is electrically connected to the output (storage node N2) of the inverter 20, and the other electrode of the ferroelectric capacitor C21 is electrically connected to a plate line PL1 to which an arbitrary potential can be applied. One electrode of the ferroelectric capacitor C22 is electrically connected to the output (storage node N2) of the inverter 20, and the other electrode of the ferroelectric capacitor C22 is electrically connected to a plate line PL2 to which an arbitrary potential can be applied. The electrode of the ferroelectric capacitor C21 electrically connected to the storage node N2 and the electrode of the ferroelectric capacitor C22 electrically connected to the storage node N2 are formed by a common lower electrode 44b (fourth shared electrode).

[0025] When power is supplied, the semiconductor device 1 can maintain a state of "0" or "1" by feeding back the outputs of the inverters 10 and 20 to each other's inputs. Specifically, if the output of the inverter 10 is a storage node N1 and the output of the inverter 20 is a storage node N2, the semiconductor device 1 can store information depending on the level of the potential of the storage node N1 and the potential of the storage node N2.

[0026] When power is not supplied to the semiconductor device 1, the states of the storage nodes N1 and N2 can be stored in the four ferroelectric capacitors C11, C12, C21, and C22. Specifically, the semiconductor device 1 can control the polarization states of the ferroelectric films of the four ferroelectric capacitors C11, C12, C21, and C22 based on the potentials of the storage nodes N1 and N2 by performing a predetermined operation.

[0027] Therefore, when power is supplied to the semiconductor device 1, the semiconductor device 1 can operate as a flip-flop circuit, and can therefore write or read information at high speed. When power is not supplied to the semiconductor device 1, the semiconductor device 1 can store the information held by the flip-flop circuit in the four non-volatile ferroelectric capacitors C11, C12, C21, and C22.

[0028] The semiconductor device 1 further includes, for example, two selection transistors T13 and T23, as shown in FIG. 1 . The selection transistors T13 and T23 are FETs that control the selection and non-selection of a memory cell 1A including inverters 10 and 20 and ferroelectric capacitors C11, C12, C21, and C22. The selection transistors T13 and T23 are formed as n-type FETs. A memory cell array is obtained by providing multiple sets of cells including the memory cell 1A and the selection transistors T13 and T23.

[0029] One of the source and drain of the select transistor T13 (impurity diffusion region 13a) is electrically connected to the storage node N1 and the lower electrodes 44a of the two ferroelectric capacitors C11 and C12, and the other of the source and drain of the select transistor T13 (impurity diffusion region 13b) is electrically connected to the bit line BL1. The gate of the select transistor T13 is electrically connected to a word line WL, and the on / off state of the channel of the select transistor T13 is controlled by the voltage applied from the word line WL.

[0030] One of the source and drain of the select transistor T23 (impurity diffusion region 23a) is electrically connected to the storage node N2 and the lower electrodes 44b of the two ferroelectric capacitors C21 and C22, and the other of the source and drain of the select transistor T23 (impurity diffusion region 23b) is electrically connected to the bit line BL2. The gate of the select transistor T23 is electrically connected to the word line WL, and the on / off state of the channel of the select transistor T23 is controlled by the voltage applied from the word line WL.

[0031] When writing information to the memory cell 1A, first, the potential of the word line WL is set to a high potential, thereby transitioning the channels of the select transistors T13 and T23 to an ON state. Next, complementary potentials are applied to the bit lines BL1 and BL2, thereby controlling the state of the flip-flop of the semiconductor device 1. Here, "complementary potentials" refers to, for example, when the bit line BL1 is at a high potential, the bit line BL2 is at a low potential, or when the bit line BL1 is at a low potential, the bit line BL2 is at a high potential. Then, the potential of the word line WL is set to a low potential, thereby transitioning the channels of the select transistors T13 and T23 to an OFF state. This allows the memory cell 1A to write information to the flip-flop circuit of the semiconductor device 1.

[0032] On the other hand, when reading information from memory cell 1A, first, the potential of word line WL is turned off, and then the same potential is applied to bit line BL1 and bit line BL2. Next, the potential of word line WL is set to high. At this time, based on the state of the flip-flop of semiconductor device 1, bit lines BL1 and BL2 whose memory nodes have high potentials will be at high potentials, and bit lines whose memory nodes have low potentials will be at low potentials. Therefore, memory cell 1A can read information from the flip-flop circuit of semiconductor device 1 by amplifying the potentials of bit line BL1 and bit line BL2 using an amplifier or the like.

[0033] Therefore, the semiconductor device 1 can operate as a memory device that operates in the same manner as an SRAM. Note that, in the semiconductor device 1, the operation of storing information written in the flip-flop circuit of the semiconductor device 1 in the four ferroelectric capacitors C11, C12, C21, and C22, and the operation of restoring the information stored in the four ferroelectric capacitors C11, C12, C21, and C22 to the flip-flop circuit of the semiconductor device 1 will be described later.

[0034] From the above, the semiconductor device 1 is capable of writing or reading information at high speeds similar to SRAM, and is also capable of retaining information using the four ferroelectric capacitors C11, C12, C21, and C22 even when the power supply is lost.

[0035] Next, a specific structure of the semiconductor device 1 will be described with reference to Figures 2 to 4. Figure 3 shows an example of the planar configuration and cross-sectional configuration of the semiconductor device 1 of Figures 1 and 2. Figure 4 is a diagram in which the illustration of some components in the planar configuration of the semiconductor device 1 of Figure 3 is omitted, and corresponds to the planar configuration during the manufacturing process shown in Figure 9, which will be described later.

[0036] As shown in FIG. 3 , the semiconductor device 1 includes a memory layer 30 and a wiring layer 40. The memory layer 30 includes a semiconductor substrate 31, inverters 10 and 20, and select transistors T13 and 23 formed on the surface of the semiconductor substrate 31. The wiring layer 40 is stacked on the memory layer 30 and includes an interlayer film 41 in contact with the surface of the memory layer 30 (including the surface of the semiconductor substrate 31) and an interlayer film 42 stacked on the interlayer film 41. Four ferroelectric capacitors C11, C12, C21, and C22 are formed in the wiring layer 40. A plug 43 is formed in the same layer as the interlayer film 41. A word line WL, bit lines BL1 and BL2, a power supply line PWR, and a ground line GND are formed in the same layer as the interlayer film 42. Plate lines PL1 and PL2 are formed in the same layer as the interlayer film stacked on the interlayer film 42.

[0037] The semiconductor substrate 31 is, for example, a silicon substrate. The semiconductor substrate 31 is, for example, a silicon substrate having SiO ２The semiconductor substrate 31 may be an SOI (Silicon On Insulator) substrate sandwiching an insulating film such as silicon dioxide (SiOx), silicon nitride (SiNx), or silicon carbide (SiC). The semiconductor substrate 31 may be a substrate formed of another elemental semiconductor such as germanium, or a substrate formed of a compound semiconductor such as gallium arsenide (GaAs), gallium nitride (GaN), or silicon carbide (SiC). The interlayer films 41 and 42 are formed of an insulating oxynitride such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON).

[0038] An impurity diffusion region 31a is formed on the surface of the semiconductor substrate 31 by ion implantation. For example, a p-type impurity diffusion region is formed by implanting B+ into the Si layer, and an n-type impurity diffusion region is formed by implanting As+ into the Si layer. Furthermore, increasing the impurity concentration enables ohmic contact with a plug or the like. For example, a p-type contact region capable of making ohmic contact with a plug or the like is formed in the p-type impurity diffusion region, and an n-type contact region capable of making ohmic contact with a plug or the like is formed in the n-type impurity diffusion region.

[0039] The p-type transistor T11 is an FET formed by providing a gate electrode 35a via a gate insulating film on an n-type impurity diffusion region of a semiconductor substrate 31. In the p-type transistor T11, the source and drain are formed of p-type impurity diffusion regions formed by, for example, implanting B+ into a portion of the n-type impurity diffusion region. In the p-type transistor T11, one of the source and drain is formed of a p-type impurity diffusion region 36a, and the other is formed of a p-type impurity diffusion region 37a.

[0040] The n-type transistor T12 is an FET formed by providing a gate electrode 35a via a gate insulating film on a p-type impurity diffusion region of the semiconductor substrate 31. In the n-type transistor T12, the source and drain are formed by n-type impurity diffusion regions formed, for example, by implanting As+ into a portion of the p-type impurity diffusion region. In the n-type transistor T12, one of the source and drain is formed by an n-type impurity diffusion region 36b, and the other is formed by an n-type impurity diffusion region 37b.

[0041] The p-type transistor T21 is an FET formed by providing a gate electrode 35b via a gate insulating film on an n-type impurity diffusion region of the semiconductor substrate 31. In the p-type transistor T21, the source and drain are formed by p-type impurity diffusion regions formed by, for example, implanting B+ into a portion of the n-type impurity diffusion region. In the p-type transistor T21, one of the source and drain is formed by a p-type impurity diffusion region 36c, and the other is formed by a p-type impurity diffusion region 37c.

[0042] The n-type transistor T22 is an FET formed by providing a gate electrode 35b via a gate insulating film on a p-type impurity diffusion region of the semiconductor substrate 31. In the n-type transistor T22, the source and drain are formed by n-type impurity diffusion regions formed, for example, by implanting As+ into a portion of the p-type impurity diffusion region. In the n-type transistor T22, one of the source and drain is formed by an n-type impurity diffusion region 36d, and the other is formed by an n-type impurity diffusion region 37d.

[0043] The select transistor T13 is an FET formed by providing a gate electrode 35c via a gate insulating film on a p-type impurity diffusion region of the semiconductor substrate 31. In the select transistor T13, the source and drain are formed of n-type impurity diffusion regions formed by, for example, implanting As+ into a portion of the p-type impurity diffusion region. In the select transistor T13, one of the source and drain is formed of an n-type impurity diffusion region 13a, and the other is formed of an n-type impurity diffusion region 13b.

[0044] The select transistor T23 is an FET formed by providing a gate electrode 35d via a gate insulating film on a p-type impurity diffusion region of the semiconductor substrate 31. In the select transistor T23, the source and drain are formed of n-type impurity diffusion regions formed by, for example, implanting As+ into a portion of the p-type impurity diffusion region. In the select transistor T23, one of the source and drain is formed of an n-type impurity diffusion region 23a, and the other is formed of an n-type impurity diffusion region 23b.

[0045] The gate insulating film is made of an insulating material and is provided on the surface of the impurity diffusion region 31 a of the semiconductor substrate 31. The gate insulating film may be made of an insulating material known as a gate insulating film for an FET. The gate insulating film may be made of an insulating oxynitride such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON).

[0046] A plurality of grooves 32 extending in a first direction are formed on the surface of the semiconductor substrate 31. A convex portion extending in the first direction is formed between two adjacent grooves 32 on the surface of the semiconductor substrate 31. Hereinafter, the portion of the semiconductor substrate 31 corresponding to the convex portion will be referred to as a semiconductor layer 33. FIG. 3 illustrates an example of six semiconductor layers 33 formed on the surface of the semiconductor substrate 31, and the six semiconductor layers 33 are assigned the reference numerals 33A, 33B, 33C, 33D, 33E, and 33F in order from the top of the page in FIG. 3 .

[0047] The memory layer 30 has a plurality of element isolation layers 34 that sandwich the plurality of semiconductor layers 33 from a second direction perpendicular to the extension direction (first direction) of the semiconductor layers 33. The element isolation layers 34 are formed in the trenches 32. The element isolation layers 34 are formed so as to fill the trenches 32. The element isolation layers 34 may be formed of an insulating oxynitride such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON). Specifically, the element isolation layers 34 may be formed by, for example, removing a portion of the semiconductor substrate 31 by etching or the like using an STI (Shallow Trench Isolation) method, and then filling the formed trenches 32 with silicon oxide (SiOx). The element isolation layers 34 may be formed by, for example, thermally oxidizing a portion of the semiconductor substrate 31 using a LOCOS (Local Oxidation of Silicon) method.

[0048] An impurity diffusion region 31a is formed on the surface of each semiconductor layer 33. A p-type impurity diffusion region is formed as the impurity diffusion region 31a on the surface of the semiconductor layer 33B, and the n-type transistor T12 is formed in the p-type impurity diffusion region of the semiconductor layer 33B. An n-type impurity diffusion region is formed as the impurity diffusion region 31a on the surface of the semiconductor layer 33C, and the p-type transistor T11 is formed in the n-type impurity diffusion region of the semiconductor layer 33C. An n-type impurity diffusion region is formed as the impurity diffusion region 31a on the surface of the semiconductor layer 33D, and the p-type transistor T21 is formed in the n-type impurity diffusion region of the semiconductor layer 33D. A p-type impurity diffusion region is formed as the impurity diffusion region 31a on the surface of the semiconductor layer 33E, and the n-type transistor T22 is formed in the p-type impurity diffusion region of the semiconductor layer 33E.

[0049] Gate electrodes 35a, 35b, 35c, and 35d are provided extending in a second direction perpendicular to the semiconductor layers 33. Gate electrode 35a is provided across semiconductor layers 33B and 33C. P-type impurity diffusion regions 36a and 37a are formed in the n-type impurity diffusion region of semiconductor layer 33C, and gate electrode 35a, p-type impurity diffusion regions 36a and 37a form p-type FET 11. N-type impurity diffusion regions 36b and 37b are formed in the p-type impurity diffusion region of semiconductor layer 33B, and gate electrode 35a, n-type impurity diffusion regions 36b and 37b form n-type FET 12.

[0050] Gate electrode 35b is provided across semiconductor layers 33D and 33E. P-type impurity diffusion regions 36c and 37c are formed in the n-type impurity diffusion region of semiconductor layer 33D, and gate electrode 35b, p-type impurity diffusion regions 36c and 37c together form p-type FET 21. N-type impurity diffusion regions 36d and 37d are formed in the p-type impurity diffusion region of semiconductor layer 33E, and gate electrode 35b, n-type impurity diffusion regions 36d and 37d together form n-type FET 22.

[0051] The gate electrodes 35a, 35b, 35c, and 35d may be formed of, for example, polysilicon or the like, or may be formed of a metal, alloy, metal compound, or alloy of a metal (such as Ni) and polysilicon (so-called silicide). The gate electrodes 35a, 35b, 35c, and 35d may be formed of, for example, a stacked structure of a metal layer and a polysilicon layer. Sidewalls may be provided on the side surfaces of each of the gate electrodes 35a, 35b, 35c, and 35d. The sidewalls may be made of an insulating material, such as an insulating oxynitride, such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON).

[0052] The ferroelectric capacitor C11 has a lower electrode 44a, an upper electrode 45a, and a ferroelectric film 47a sandwiched between the lower electrode 44a and the upper electrode 45a. The ferroelectric capacitor C12 has a lower electrode 44a, an upper electrode 46a, and a ferroelectric film 47a sandwiched between the lower electrode 44a and the upper electrode 46a. The lower electrode 44a of the ferroelectric capacitor C11 and the lower electrode 44a of the ferroelectric capacitor C12 are formed by a common lower electrode (second shared electrode). The ferroelectric film 47a of the ferroelectric capacitor C11 and the ferroelectric film 47a of the ferroelectric capacitor C12 are formed by a common ferroelectric film. The upper electrode 45a and the upper electrode 46a are arranged with a predetermined gap between them and are separated from each other.

[0053] The ferroelectric capacitor C21 has a lower electrode 44b, an upper electrode 45b, and a ferroelectric film 47b sandwiched between the lower electrode 44b and the upper electrode 45b. The ferroelectric capacitor C22 has a lower electrode 44b, an upper electrode 46b, and a ferroelectric film 47b sandwiched between the lower electrode 44b and the upper electrode 46b. The lower electrode 44b of the ferroelectric capacitor C21 and the lower electrode 44b of the ferroelectric capacitor C212 are formed by a common lower electrode (fourth shared electrode). The ferroelectric film 47b of the ferroelectric capacitor C21 and the ferroelectric film 47b of the ferroelectric capacitor C22 are formed by a common ferroelectric film. The upper electrode 45b and the upper electrode 46b are arranged with a predetermined gap between them and are separated from each other.

[0054] The wiring layer 40 has two openings H1 and two openings H2 that penetrate the interlayer films 41 and 42. A ferroelectric capacitor C11 is embedded in one of the openings H1. That is, the ferroelectric capacitor C11 is formed in the opening H1. The ferroelectric capacitor C11 is a stacked cylindrical capacitor configured by stacking a lower electrode 44a, a ferroelectric film 47a, and an upper electrode 45a within the opening H1. The surface of the gate electrode 35b is exposed at the bottom of the opening H1. In the opening H1, the lower electrode 44a of the ferroelectric capacitor C11 contacts the gate electrode 35b. The upper electrode 45a of the ferroelectric capacitor C11 is exposed from the opening H1 and contacts the plate line PL1. The plate line PL1 extends in a second direction perpendicular to the extension direction (first direction) of the semiconductor layer 33.

[0055] The ferroelectric capacitor C21 is buried in the other opening H1. That is, the ferroelectric capacitor C21 is formed in the opening H1. The ferroelectric capacitor C21 is a stacked cylindrical capacitor configured by laminating a lower electrode 44b, a ferroelectric film 47b, and an upper electrode 45b in the opening H1. The surface of the gate electrode 35a is exposed at the bottom of the opening H1. In the opening H1, the lower electrode 44b of the ferroelectric capacitor C21 contacts the gate electrode 35a. The upper electrode 45a of the ferroelectric capacitor C21 is exposed from the opening H1 and contacts the plate line PL1.

[0056] A ferroelectric capacitor C12 is embedded in one of the openings H2. That is, the ferroelectric capacitor C12 is formed in the opening H2. The ferroelectric capacitor C12 is a stacked cylindrical capacitor configured by stacking a lower electrode 44a, a ferroelectric film 47a, and an upper electrode 46a in the opening H2. The impurity diffusion region 37a of the p-type transistor T11 (semiconductor layer 33C) and the impurity diffusion region 36b of the n-type transistor T12 (semiconductor layer 33B) are exposed at the bottom of the opening H2. In the opening H2, the lower electrode 44a of the ferroelectric capacitor C12 contacts the impurity diffusion region 37a of the p-type transistor T11 (semiconductor layer 33C) and the impurity diffusion region 36b of the n-type transistor T12 (semiconductor layer 33B). The upper electrode 46a of the ferroelectric capacitor C12 is exposed from the opening H2 and contacts the plate line PL2. The plate line PL2 extends in a second direction perpendicular to the extending direction (first direction) of the semiconductor layer 33.

[0057] A ferroelectric capacitor C22 is buried in the other opening H2. That is, the ferroelectric capacitor C22 is formed in the opening H2. The ferroelectric capacitor C22 is a stacked cylindrical capacitor configured by stacking a lower electrode 44b, a ferroelectric film 47b, and an upper electrode 46b in the opening H2. The impurity diffusion region 37c of the p-type transistor T21 (semiconductor layer 33D) and the impurity diffusion region 36d of the n-type transistor T22 (semiconductor layer 33E) are exposed at the bottom of the opening H2. In the opening H2, the lower electrode 44b of the ferroelectric capacitor C22 contacts the impurity diffusion region 37c of the p-type transistor T21 (semiconductor layer 33D) and the impurity diffusion region 36d of the n-type transistor T22 (semiconductor layer 33E). The upper electrode 46b of the ferroelectric capacitor C22 is exposed from the opening H2 and contacts the plate line PL2.

[0058] The lower electrode 44a has an L-shape including a portion extending in a second direction perpendicular to the semiconductor layers 33 and a portion extending in a first direction parallel to the semiconductor layers 33. The lower electrode 44a is provided across the semiconductor layers 33B and 33C and is positioned opposite the semiconductor layer 33C. The lower electrode 44a extends from the inner surface of the opening H1 to the inner surface of the opening H2, forming a shared contact with the gate electrode 35b in the opening H1, the impurity diffusion region 37a of the p-type transistor T11 (semiconductor layer 33C), and the impurity diffusion region 36b of the n-type transistor T12 (semiconductor layer 33B). The gate electrode 35b, the plate line PL2, and the gate electrode 35a are arranged in this order in the extension direction (first direction) of the semiconductor layers 33.

[0059] The lower electrode 44b has an L-shape including a portion extending in a second direction perpendicular to the semiconductor layers 33 and a portion extending in a first direction parallel to the semiconductor layers 33. The lower electrode 44b is provided across the semiconductor layers 33D and 33E and is located opposite the semiconductor layer 33D. The lower electrode 44b extends from the inner surface of the opening H1 to the inner surface of the opening H2. The lower electrode 44b forms a shared contact with the gate electrode 35a in the opening H1, the impurity diffusion region 37c of the p-type transistor T21 (semiconductor layer 33D), and the impurity diffusion region 36d of the n-type transistor T22 (semiconductor layer 33E).

[0060] The lower electrodes 44a and 44b are formed of, for example, TiN or TaN. The upper electrodes 45a, 45b, 46a, and 46b are formed of, for example, TiN. The ferroelectric films 47a and 47b are formed of, for example, HfZrOx or ZrOx. The ferroelectric films 47a and 47b may be formed of, for example, HfZrOx or ZrOx doped with atoms such as La, Si, or Gd.

[0061] Here, the area of ​​each of the ferroelectric capacitors C11 and C21 in a planar view is A1, and the area of ​​each of the ferroelectric capacitors C12 and C22 in a planar view is A2. In this case, the area ratio (A1 / (A1+A2)) has a predetermined correlation with the recall rate. When A2=3×A1, the area ratio (A1 / (A1+A2)) is 1 / 4, and the recall rate at this time is higher than the recall rate when A1=0 (a memory cell in which the ferroelectric capacitors C11 and C21 are omitted). Therefore, it is preferable that the area ratio (A1 / (A1+A2)) is greater than 0.

[0062] The plug 43 is formed of, for example, a metal film formed by depositing Ti or TiN and W in this order. The plug 43 electrically connects the word line WL, the bit lines BL1 and BL2, the plate lines PL1 and PL2, the power supply line PWR, or the ground line GND to a p-type contact region or an n-type contact region formed in the semiconductor layer 33. The word line WL, the bit lines BL1 and BL2, the plate lines PL1 and PL2, the power supply line PWR, and the ground line GND are formed of, for example, a wiring material such as Cu or Al.

[0063] [Manufacturing Method] Next, a description will be given of a manufacturing method of the semiconductor device 1. Figures 5 to 12 are diagrams for explaining an example of a manufacturing process of the semiconductor device 1.

[0064] First, a layer of, for example, SiO ２ and Si ３ N ４ After forming the first insulating film by depositing these in this order, a resist pattern is formed in the areas where the plurality of semiconductor layers 33 are to be formed. ３ N ４ , SiO ２ ) and the semiconductor substrate 31 are sequentially etched to form a plurality of grooves 32 in the semiconductor substrate 31. Then, each groove 32 is covered with a second insulating film (e.g., SiO ２ For example, each of the grooves 32 is filled by high density plasma CVD. This makes it possible to form a dense second insulating film with good step coverage.

[0065] Next, the surface is polished and planarized by CMP (Chemical Mechanical Polish). At this time, polishing is performed to the extent that the second insulating film can be removed. As a result, an element isolation layer 34 is formed in each groove 32 (FIG. 5). Next, for example, Si contained in the first insulating film is polished. ３ N ４ is removed, for example, with hot phosphoric acid.

[0066] Next, the surface of each semiconductor layer 33 is oxidized to a depth of, for example, 10 nm. This forms a sacrificial oxide film on the surface of each semiconductor layer 33. Subsequently, for example, ion implantation is performed on regions of each semiconductor layer 33 where the n-type transistors T12, T22 and the select transistors T13, T23 are to be formed. This forms a pwell region.

[0067] Next, the sacrificial oxide film is removed with an HF solution, and the surface of each semiconductor layer 33 is oxidized. This forms a gate oxide film. Subsequently, polysilicon is deposited by low-pressure CVD, and a resist pattern is then formed in the areas where gate electrodes 35a, 35b, 35c, and 35d will be formed. Using this resist pattern as a mask, anisotropic etching is performed on the polysilicon. This results in the formation of gate electrodes 35a, 35b, 35c, and 35d (FIG. 6). For example, in 40-nm node technology, gate electrodes 35a, 35b, 35c, and 35d are formed with gate lengths of approximately 40 nm to 50 nm.

[0068] Next, As+ ions, for example, are implanted into the areas where the drain ends of the n-type transistors T12 and T22 and the select transistors T13 and T23 will be formed. This forms an NLDD (Lightly Doped Drain). Phos may be used as the dopant at this time. B+ ions, for example, are implanted into the areas where the drain ends of the p-type transistors T11 and T21 will be formed. This forms a PLDD.

[0069] Next, the entire surface including the gate electrodes 35a, 35b, 35c, and 35d is coated with SiO by plasma CVD. ２ , Si ３ N ４After forming a third insulating film by depositing these in this order, the third insulating film is anisotropically etched. This forms sidewalls on the sides of the gate electrodes 35a, 35b, 35c, and 35d. Subsequently, As+ ions, for example, are implanted into the locations where the sources and drains of the n-type transistors T12 and T22 and the select transistors T13 and T23 will be formed. This results in the formation of impurity diffusion regions 36b and 37b as the source and drain of the n-type transistor T12, and impurity diffusion regions 36d and 37d as the source and drain of the n-type transistor T22 (FIG. 7). Impurity diffusion regions 13a and 13b as the source and drain of the select transistor T13, and impurity diffusion regions 23a and 23b as the source and drain of the select transistor T23 (FIG. 7).

[0070] Furthermore, B+ ions, for example, are implanted into the regions where the sources and drains of the p-type transistors T11 and T21 will be formed. As a result, impurity diffusion regions 36a and 37a are formed as the source and drain of the p-type transistor T11, and impurity diffusion regions 36c and 37c are formed as the source and drain of the p-type transistor T21 (FIG. 7). For example, impurities are activated by RTA to activate the impurities in the impurity diffusion regions 36a, 36b, 36c, 36d, 37a, 37b, 37c, and 37d. Annealing by spike RTA may be performed to promote dopant activation and suppress dopant diffusion.

[0071] For example, Ni is deposited by sputtering, and then RTA is performed. As a result, the portions of the Ni deposition film facing the impurity diffusion regions 13a, 13b, 23a, 23b, 36a, 36b, 36c, 36d, 37a, 37b, 37c, and 37d are silicided. As a result, the portions of the Ni deposition film facing the impurity diffusion regions 13a, 13b, 23a, 23b, 36a, 36b, 36c, 36d, 37a, 37b, 37c, and 37d become low-resistance contact regions that can make ohmic contact with the plug 43, etc. Thereafter, H ２ SO４ and H ２ O ２ The unreacted Ni deposition film is removed by the above method. By depositing Co or NiPt instead of Ni, CoSi ２ In either case, the RTA temperature can be set appropriately.

[0072] Next, silicon nitride may be deposited by plasma CVD, low pressure CVD, ALD, or the like. In this case, the deposited silicon nitride can function as a stopper liner film. It is also possible to deposit silicon nitride so that it has compressive stress or tensile stress. Next, a fourth insulating film (e.g., SiO ２ After depositing the fourth insulating film to a thickness of about 100 nm to 500 nm, the surface of the fourth insulating film is polished by CMP to flatten the surface of the fourth insulating film, thereby forming an interlayer film 41 (FIG. 8).

[0073] Next, a resist pattern having openings where the openings H1 and H2 are to be formed is formed. Using this resist pattern as a mask, anisotropic etching is performed on the interlayer film 41. As a result, the openings H1 and H2 are formed in the interlayer film 41 (FIG. 8). At this time, two openings H1 and two openings H2 are formed, and the opening area of ​​each opening H1 and the opening area of ​​each opening H2 are set to a predetermined size. From the viewpoint of ease of forming the ferroelectric capacitors C11, C12, C21, and C22, it is preferable that the aspect ratio of the openings H1 and H2 is approximately 20 or less. If a stopper liner film is provided, the stopper liner film can also be used as an etch stop.

[0074] Next, a first metal film (e.g., TiN or TaN) is deposited to a thickness of approximately 3 to 20 nm by CVD, ALD, or the like. Subsequently, a resist pattern is formed in predetermined regions including the openings H1 and H2, where the lower electrodes 44a and 44b will be formed. Using this resist pattern as a mask, the first metal film is anisotropically etched. This results in the formation of the lower electrode 44a, which is electrically connected to the gate electrode 35b and the impurity diffusion regions 36b and 37a. Furthermore, the formation of the lower electrode 44b, which is electrically connected to the gate electrode 35a and the impurity diffusion regions 36d and 37c, is also performed (FIG. 9). Next, a high-dielectric film (e.g., HfZrOx or ZrOx) is deposited to a thickness of approximately 3 to 10 nm by CVD, ALD, or the like.

[0075] Next, a second metal film (e.g., TiN) is deposited to a thickness of approximately 3 to 20 nm by CVD, ALD, or the like, to fill the openings H1 and H2 with the second metal film. Subsequently, a resist pattern is formed in predetermined regions including the openings H1 and H2, where the upper electrodes 45a, 45b, 46a, and 46b will be formed. Using this resist pattern as a mask, the second metal film is anisotropically etched. As a result, the upper electrodes 45a and 46a are formed on the high-dielectric film with a predetermined gap therebetween. In other words, the upper electrodes 45a and 46a are provided separately from each other. Furthermore, the upper electrodes 45b and 46b are formed on the high-dielectric film with a predetermined gap therebetween (FIG. 10). In other words, the upper electrodes 45b and 46b are provided separately from each other.

[0076] Next, crystallization annealing is performed to phase-change the high-dielectric film (e.g., HfZrOx or ZrOx) into a ferroelectric film. This annealing can be performed either before or after the formation of the upper electrodes 45a, 45b, 46a, and 46b. The crystallization annealing temperature is set to a range of 400°C to 700°C, within the heat resistance range of MOSFETs, NiSi, and the like. Next, a resist pattern is formed in predetermined regions including the openings H1 and H2, where the ferroelectric films 47a and 47b will be formed. Using this resist pattern as a mask, the ferroelectric film is anisotropically etched, thereby forming the ferroelectric films 47a and 47b (FIG. 10). In this manner, stacked cylindrical ferroelectric capacitors C11, C12, C21, and C22 are formed.

[0077] Next, a resist pattern having openings where the plugs 43 will be formed is formed. Using this resist pattern as a mask, anisotropic etching is performed on the interlayer film 41, thereby forming multiple openings H3 in the interlayer film 41 (FIG. 11). Subsequently, a third metal film is formed by depositing, for example, Ti or TiN and W in this order by CVD, thereby filling each opening H3 with the third metal film. After that, the portions of the third metal film other than those filled in each opening H3 are etched. Thus, plugs 43 are formed in each opening H3 (FIG. 12). In addition to CVD, sputtering using IMP can also be used as a method for forming the third metal film. It is also possible to form the plugs 43 by etching back the entire surface.

[0078] In the above manufacturing process, the ferroelectric capacitors C11, C12, C21, and C22 may be formed after the plug 43 is formed.

[0079] Next, a fifth insulating film (e.g., SiO ２), the fifth insulating film is then deposited, and the surface is polished by CMP to flatten the fifth insulating film. As a result, an interlayer film 42 is formed on the interlayer film 41. Next, openings are formed in the interlayer film 42 by the damascene method, and wiring material such as Cu is embedded in the openings formed in the fifth insulating film. As a result, bit lines BL1, BL2, word lines WL, power supply lines PWR, and ground lines GND are formed in the same layer as the interlayer film 42 (FIG. 3). Next, a sixth insulating film (e.g., SiO ２ After depositing the sixth insulating film 42, openings are formed in the sixth insulating film by the damascene method, and wiring material such as Cu is embedded in the openings formed in the sixth insulating film 42. As a result, plate lines PL1 and PL2 are formed on the interlayer film 42. Al can also be used as the material for the bit lines BL1 and BL2, word lines WL, plate lines PL1 and PL2, power supply line PWR, ground line GND, and plate lines PL1 and PL2. In this manner, the semiconductor device 1 is manufactured.

[0080] [Operation] Next, the operation of the semiconductor device 1 will be described.

[0081] Fig. 13 is a diagram for explaining various operations in the semiconductor device 1. Fig. 14 is a diagram for explaining an example of state transitions of the semiconductor device 1. Fig. 13 shows standby (operating), save, pause, and return (recall) as states of the semiconductor device 1.

[0082] In standby mode, data in the SRAM is held with Vdd applied to the power supply line PWR, similar to a volatile SRAM that does not have ferroelectric capacitors C11, C12, C21, and C22. At this time, the potential of storage node N1 is 0 V, and the potential of storage node N2 is Vdd (FIG. 14A). Vdd can be set to a high or low voltage as long as it is within a range that allows data to be held in the SRAM.

[0083] By transitioning from standby to save, the data in the storage nodes N1 and N2 is saved to the ferroelectric capacitors C11, C12, C21, and C22. For example, after Vw is applied to the plate lines PL1 and PL2 and the power supply line PWR, 0V is applied to the plate lines PL1 and PL2, and 0V is applied to the potentials of the storage nodes N1 and N2. As a result, the storage nodes N1 and N2 transition as shown in FIGS. 14(A), 14(B), and 14(C). At this time, Vw is set to a voltage that polarizes the ferroelectric capacitors C11, C12, C21, and C22.

[0084] Next, by shifting from the save state to the pause state, all power supplies become 0V. At this time, the potentials of the storage nodes N1 and N2 also become 0V (FIG. 14(D)). However, since the data of the storage nodes N1 and N2 are held in the ferroelectric capacitors C11, C12, C21, and C22, the data held in the ferroelectric capacitors C11, C12, C21, and C22 is not lost even if the potentials of the storage nodes N1 and N2 become 0V.

[0085] Next, by transitioning from pause to resume, the data held in the ferroelectric capacitors C11, C12, C21, and C22 is restored to the storage nodes N1 and N2. For example, after Vpl is applied to the plate line PL1, Vdd is applied to the plate line PL1 and the power supply line PWR. When Vpl is applied to the plate line PL1, a potential difference occurs between the storage nodes N1 and N2 due to the capacitance difference (a magnitude corresponding to the slope in the figure). In other words, the storage node N2, which has a smaller capacitance, has a higher potential than the storage node N1, which has a larger capacitance (FIG. 14(E)). With the power supply line PWR at Vdd, the gate voltages of the two loads (p-type transistors T11 and T21) become 0V, so the two loads (p-type transistors T11 and T21) are turned on. As a result, charge is supplied to the storage nodes N1 and N2 from the power supply line PWR. At this time, the voltage of storage node N1 is smaller than the voltage of storage node N2, so the on-current of p-type transistor T21 and the on-current of n-type transistor T12 increase. As a result, storage node N1 transitions to 0 V and stabilizes, and storage node N2 transitions to Vdd and stabilizes (FIG. 14(F)).

[0086] [Effects] Next, the effects of the semiconductor device 1 will be described.

[0087] In this embodiment, the gate electrodes 35b of the p-type transistor 21 and the n-type transistor 22 included in the inverter 20 are configured by a first shared electrode, the lower electrodes 44a of the ferroelectric capacitors C11 and C12 are configured by a second shared electrode, and the first shared electrode and the second shared electrode are connected to each other. The upper electrode 45a of the ferroelectric capacitor C11 and the upper electrode 46a of the ferroelectric capacitor C12 are provided separately from each other. This allows the two ferroelectric capacitors C11 and C12 to be connected to the storage node N1 while utilizing the lower electrode 44a as a shared contact. As a result, it is possible to prevent an increase in the SRAM area and reduce the chip area.

[0088] Furthermore, in this embodiment, the gate electrodes 35a of the p-type transistor T11 and the n-type transistor T12 included in the inverter 10 are configured by the third shared electrode 35a, and the lower electrodes 44b of the ferroelectric capacitors C21 and C22 are configured by the fourth shared electrode, and the third shared electrode and the fourth shared electrode are connected to each other. The upper electrode 45b of the ferroelectric capacitor C21 and the upper electrode 46b of the ferroelectric capacitor C22 are provided separately from each other. This allows the two ferroelectric capacitors C21 and C22 to be connected to the storage node N2 while utilizing the lower electrode 44b as a shared contact. As a result, an increase in the SRAM area can be suppressed, and the chip area can be reduced. Therefore, in this embodiment, when four ferroelectric capacitors C11, C12, C21, and C22 are provided in a CMOS SRAM, non-volatility and high integration can both be achieved.

[0089] In this embodiment, the ferroelectric capacitor C11 is formed in one opening H1, the ferroelectric capacitor C21 is formed in the other opening H1, the ferroelectric capacitor C12 is formed in one opening H2, and the ferroelectric capacitor C22 is formed in the other opening H2. By adjusting the area ratio (A1 / (A1+A2)) of the openings H1 and H2, a higher recall rate can be obtained compared to the recall rate of a memory cell in which the ferroelectric capacitors C11 and C21 are omitted.

[0090] In this embodiment, the lower electrodes 44a and 44b of the four ferroelectric capacitors C11, C12, C21, and C22 are utilized as shared contacts, which makes it possible to suppress an increase in the SRAM area and reduce the chip area.

[0091] In this embodiment, the sources and drains of p-type transistor T11 and n-type transistor T12 included in inverter 10, and the sources and drains of p-type transistor 21 and n-type transistor 22 included in inverter 20 are formed in a plurality of semiconductor layers 33. Furthermore, gate electrodes 35a, 35b, and plate line PL2 extend in a second direction perpendicular to the extending direction (first direction) of semiconductor layer 33. This allows inverters 10, 20 and plate line PL2 to be laid out efficiently, thereby preventing an increase in the SRAM area and reducing the chip area.

[0092] In this embodiment, the gate electrode 35b, the plate line PL2, and the gate electrode 35a are arranged in this order in the extending direction (first direction) of the semiconductor layer 33, and the lower electrodes 44a and 44b of the four ferroelectric capacitors C11, C12, C21, and C22 are L-shaped. This allows the four ferroelectric capacitors C11, C12, C21, and C22 to be laid out efficiently, thereby preventing an increase in the SRAM area and reducing the chip area.

[0093] 3. Modifications of the First Embodiment Next, modifications of the display device 1 according to the first embodiment will be described.

[0094] 15 to 18 are diagrams illustrating a modified example of the manufacturing process of the semiconductor device 1 of FIG. In the manufacturing process of the semiconductor device 1 according to the above embodiment, for example, as shown in FIG. 15 , a metal film 44x (e.g., TiN or TaN) having a thickness of about 3 to 20 nm, a high-dielectric film 47x (e.g., HfZrOx or ZrOx) having a thickness of about 3 to 10 nm, and a metal film 48 (e.g., TiN) may be sequentially deposited over the entire surface including the openings H1 and H2 by CVD, ALD, or the like. At this time, the metal film 44x and the high-dielectric film 47x are formed along the inner surfaces of the openings H1 and H2 and the surface of the interlayer film 41, and the metal film 48 covers the metal film 44x and the high-dielectric film 47x and fills the openings H1 and H2.

[0095] Thereafter, a resist pattern is formed in predetermined regions including the openings H1 and H2 where the upper electrodes 45a, 45b, 46a, and 46b are to be formed, and the metal film 48 is anisotropically etched using the resist pattern as a mask. As a result, the upper electrodes 45a, 45b, 46a, and 46b are formed ( FIG. 16 ). The upper electrodes 45a and 46a are not shown in FIG. 16 . At this time, the etching may be stopped midway through etching the high-dielectric film 47x to avoid dividing the metal film 44x or the high-dielectric film 47x.

[0096] Next, the entire surface including the upper electrodes 45a, 45b, 46a, and 46b is coated with SiO by plasma CVD. ２ and Si ３ N ４ After forming the seventh insulating film by depositing the above-mentioned material, the seventh insulating film is subjected to anisotropic etching. As a result, sidewalls 49 are formed on the side surfaces of the upper electrodes 45a, 45b, 46a, and 46b (FIG. 17). The upper electrodes 45a and 46a are not shown in FIG. 17. At this time, the thickness of the seventh insulating film is set so that the gap between the upper electrodes 45a and 46a and the gap between the upper electrodes 45b and 46b are covered with the seventh insulating film. In other words, the sidewalls 49 are formed so as to cover the gap between the upper electrodes 45a and 46a and the gap between the upper electrodes 45b and 46b.

[0097] Next, the high-dielectric film 47x and the metal film 44x are anisotropically etched using the upper electrodes 45a, 45b, 46a, and 46b and the sidewalls 49 as masks, thereby forming the lower electrodes 44a and 44b and the ferroelectric films 47a and 47b (FIG. 18). The lower electrode 44a and the ferroelectric film 47a are not shown in FIG.

[0098] In this modification, the metal film 44x may be etched to form the lower electrodes 44a and 44b, and then the high-dielectric film 47x may be formed, and the high-dielectric film 47x may be etched to form the ferroelectric films 47a and 47b.

[0099] In this modification, sidewalls 49 are formed to cover the gap between the upper electrodes 45 a and 46 a and the gap between the upper electrodes 45 b and 46 b. This makes it possible to eliminate the risk of removing the metal film 44 x present in the gap between the upper electrodes 45 a and 46 a and the gap between the upper electrodes 45 b and 46 b by using the sidewalls 49 as a mask in the process of forming the lower electrodes 44 a and 44 b.

[0100] 4. Second Embodiment [Configuration] A semiconductor device 2 according to a second embodiment of the present disclosure will be described. Fig. 19 shows an example of a planar configuration and a cross-sectional configuration of the semiconductor device 2 according to the second embodiment of the present disclosure. Fig. 20 shows an example of a cross-sectional configuration of the semiconductor device 2 of Fig. 19 taken along line DD.

[0101] 19, the semiconductor device 2 includes an SRAM region 2A and an FeRAM (Ferroelectric Random Access Memory) region 2B. The SRAM region 2A and the FeRAM region 2B are formed on a common semiconductor substrate 31. The FeRAM region 2B is formed around the SRAM region 2A.

[0102] The SRAM region 2A has the semiconductor device 1 according to the first embodiment and its modifications. The FeRAM region 2B has a ferroelectric capacitor C31 that stores information and a selection transistor T31 that controls selection and non-selection of the ferroelectric capacitor C31. The FeRAM region 2B is provided with a plurality of sets of memory cells, each including a ferroelectric capacitor C31 and a selection transistor T31. The memory layer 30 has the ferroelectric capacitor C31 in the FeRAM region 2B. The wiring layer 40 has the selection transistor T31 in the FeRAM region 2B.

[0103] As shown in FIG. 20 , the ferroelectric capacitor C31 includes a lower electrode 44c, an upper electrode 46c, and a ferroelectric film 47c sandwiched between the lower electrode 44c and the upper electrode 46c. Openings H4 and H5 penetrating the interlayer films 41 and 42 are provided in the wiring layer 40. The ferroelectric capacitor C31 is embedded in the opening H4. The ferroelectric capacitor C31 is a stacked cylindrical capacitor configured by stacking the lower electrode 44c, the ferroelectric film 47c, and the upper electrode 46c in the opening H4. In the opening H4, the lower electrode 44c of the ferroelectric capacitor C31 contacts the impurity diffusion region 63 of the select transistor T31. The upper electrode 46c of the ferroelectric capacitor C31 is exposed from the opening H4 and contacts the signal line SL. A plug 61 is embedded in the opening H5. The plug 61 electrically connects the impurity diffusion region 62 of the select transistor T31 and the bit line BL3.

[0104] The lower electrode 44c is formed of, for example, TiN or TaN. The upper electrode 46c is formed of, for example, TiN. The ferroelectric film 47c is formed of, for example, HfZrOx or ZrOx. The ferroelectric film 47c may be formed of, for example, HfZrOx or ZrOx doped with atoms such as La, Si, or Gd.

[0105] The select transistor T31 is configured as a voltage-controllable FET. The select transistor T31 is an FET formed by providing a gate electrode 35e on a p-type impurity diffusion region of the semiconductor substrate 31 via a gate insulating film. A plug 61 is electrically connected to one of the source and drain of the select transistor T31 (impurity diffusion region 62), and a lower electrode 44c is electrically connected to the other of the source and drain of the select transistor T31 (impurity diffusion region 63). The gate electrode 35e of the select transistor T31 is electrically connected to a word line (not shown).

[0106] In the select transistor T31, the source and drain are formed of, for example, n-type impurity diffusion regions formed by implanting As+ into a part of a p-type impurity diffusion region. In the select transistor T31, one of the source and drain is formed of an n-type impurity diffusion region 62, and the other is formed of an n-type impurity diffusion region 63.

[0107] The gate electrode 35e may be formed of, for example, polysilicon, or may be formed of a metal, alloy, metal compound, or alloy of a metal (such as Ni) and polysilicon (so-called silicide). The gate electrode 35e may be formed of, for example, a stacked structure of a metal layer and a polysilicon layer. Sidewalls may be provided on the side surfaces of the gate electrode 35e. The sidewalls may be made of an insulating material, and may be formed of, for example, an insulating oxynitride such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON).

[0108] When writing information to the ferroelectric capacitor C31, in the FeRAM region 2B, a voltage is first applied to the word line, causing the channel of the selection transistor T31 to transition to the ON state. Then, a potential is applied to each of the bit line BL3 and the signal line SL, causing an electric field corresponding to the information to be written to be applied to the ferroelectric film 47c of the ferroelectric capacitor C31. This allows the FeRAM region 2B to write information to the ferroelectric capacitor C31 by controlling the direction of the remanent polarization of the ferroelectric film 47c of the ferroelectric capacitor C31 using an external electric field.

[0109] On the other hand, when reading information from the ferroelectric capacitor C31, in the FeRAM region 2B, a voltage is first applied to the word line, causing the channel of the selection transistor T31 to transition to an ON state. Then, a predetermined potential is applied to each of the bit line BL3 and the signal line SL, causing the polarization direction of the ferroelectric film 47c of the ferroelectric capacitor C31 to transition to a predetermined direction. At this time, the magnitude of the current flowing into the ferroelectric film 47c before the transition changes depending on the polarization direction of the ferroelectric film 47c before the transition. Therefore, the FeRAM region 2B can read the information stored in the ferroelectric capacitor C31 by measuring the magnitude of the current flowing into the ferroelectric capacitor C31.

[0110] Therefore, the FeRAM region 2B can operate as an FeRAM that stores information in the ferroelectric capacitor C31 including the ferroelectric film 47c.

[0111] [Manufacturing Method] Next, a description will be given of a manufacturing method of the semiconductor device 2. Figures 21 to 26 are diagrams for explaining an example of a manufacturing process of the semiconductor device 2.

[0112] First, a layer of, for example, SiO ２ and Si ３ N ４After forming a first insulating film by depositing these in this order, a resist pattern is formed in the locations where a plurality of semiconductor layers 33 are to be formed. Using this resist pattern as a mask, the first insulating film and the semiconductor substrate 31 are sequentially etched to form a plurality of grooves 32 in the semiconductor substrate 31. Next, each groove 32 is filled with a second insulating film (e.g., SiO ２ For example, each of the grooves 32 is filled by high density plasma CVD. This makes it possible to form a dense second insulating film with good step coverage.

[0113] Next, the surface is polished by CMP to be flattened. At this time, the polishing is performed to a degree that the second insulating film can be removed. As a result, an element isolation layer 34 is formed in each groove 32 (FIG. 21). Next, for example, Si contained in the first insulating film is removed. ３ N ４ is removed, for example, with hot phosphoric acid.

[0114] Next, the surface of each semiconductor layer 33 is oxidized to a depth of, for example, 10 nm. This forms a sacrificial oxide film on the surface of each semiconductor layer 33. Subsequently, for example, ion implantation is performed on regions of each semiconductor layer 33 where the n-type transistors T12, T22 and the select transistors T13, T23, and T31 are to be formed. This forms a pwell region.

[0115] Next, the sacrificial oxide film is removed with an HF solution, and the surface of each semiconductor layer 33 is oxidized. This forms a gate oxide film. Subsequently, polysilicon is deposited by low-pressure CVD, and a resist pattern is then formed in the areas where gate electrodes 35a, 35b, 35c, 35d, and 35e will be formed. Using this resist pattern as a mask, anisotropic etching is performed on the polysilicon. This results in the formation of gate electrodes 35a, 35b, 35c, 35d, and 35e (FIG. 21). For example, in 40-nm node technology, gate electrodes 35a, 35b, 35c, 35d, and 35e are formed with gate lengths of approximately 40 to 50 nm.

[0116] Next, As+ ions, for example, are implanted into the areas where the drain ends of the n-type transistors T12 and T22 and the select transistors T13, T23, and T31 will be formed. This forms an NLDD. At this time, Phos may be used as the dopant. B+ ions, for example, are implanted into the areas where the drain ends of the p-type transistors T11 and T21 will be formed. This forms a PLDD.

[0117] Next, the entire surface including the gate electrodes 35a, 35b, 35c, 35d, and 35e is coated with SiO by plasma CVD. ２ , Si ３ N ４ After forming a third insulating film by depositing these in this order, anisotropic etching is performed on the third insulating film. This forms sidewalls on the sides of the gate electrodes 35a, 35b, 35c, 35d, and 35e. Next, As+ ions, for example, are implanted into the locations where the sources and drains of the n-type transistors T12 and T22 and the select transistors T13, T23, and T31 will be formed. This forms impurity diffusion regions 36b and 37b as the source and drain of the n-type transistor T12. Impurity diffusion regions 36d and 37d as the source and drain of the n-type transistor T22. Furthermore, impurity diffusion regions 13a and 13b are formed as the source and drain of the select transistor T13, and impurity diffusion regions 23a and 23b are formed as the source and drain of the select transistor T23. Impurity diffusion regions 62 and 63 are formed as the source and drain of the select transistor T31 ( FIG. 21 ).

[0118] Furthermore, for example, B+ ions are implanted into the locations where the sources and drains of the p-type transistors T11 and T21 will be formed. As a result, impurity diffusion regions 36a and 37a are formed as the source and drain of the p-type transistor T11. Impurity diffusion regions 36c and 37c are formed as the source and drain of the p-type transistor T21 (FIG. 21). For example, impurities in the impurity diffusion regions 36a, 36b, 36c, 36d, 37a, 37b, 37c, 37d, 62, and 63 are activated by RTA. Annealing by spike RTA may be performed to promote dopant activation and suppress dopant diffusion.

[0119] For example, Ni is deposited by sputtering, and then RTA is performed. As a result, the portions of the Ni deposition film that face the impurity diffusion regions 36a, 36b, 36c, 36d, 37a, 37b, 37c, 37d, 62, and 63 are silicided. As a result, the portions of the Ni deposition film that face the impurity diffusion regions 36a, 36b, 36c, 36d, 37a, 37b, 37c, 37d, 62, and 63 become low-resistance contact regions that can make ohmic contact with the plug 43, etc. Thereafter, H ２ SO ４ and H ２ O ２ The unreacted Ni deposition film is removed by the above method. By depositing Co or NiPt instead of Ni, CoSi ２ In either case, the RTA temperature can be set appropriately.

[0120] Next, silicon nitride may be deposited by plasma CVD, low pressure CVD, ALD, or the like. In this case, the deposited silicon nitride can function as a stopper liner film. It is also possible to deposit silicon nitride so that it has compressive stress or tensile stress. Next, a fourth insulating film (e.g., SiO ２After depositing a ferroelectric film (C11, C12, C21, C22, C31) of about 100 nm to 500 nm, the fourth insulating film is subjected to surface polishing by CMP to flatten the surface of the fourth insulating film. This forms the interlayer film 41 (FIG. 22). Next, a resist pattern having openings is formed where the openings H1, H2, and H4 will be formed. Using this resist pattern as a mask, the interlayer film 41 is anisotropically etched. This forms the openings H1, H2, and H4 in the interlayer film 41 (FIG. 22). At this time, two openings H1 and two openings H2 are formed, and the opening areas of each opening H1 and each opening H2 are set to predetermined sizes. From the viewpoint of ease of forming the ferroelectric capacitors C11, C12, C21, C22, and C31, it is preferable that the aspect ratios of the openings H1, H2, and H4 be about 20 or less. If a stopper liner film is provided, the stopper liner film can also be used as an etch stop.

[0121] Next, a first metal film (e.g., TiN or TaN) is deposited to a thickness of approximately 3 to 20 nm by CVD, ALD, or the like. Subsequently, a resist pattern is formed in predetermined regions including the openings H1, H2, and H4, where the lower electrodes 44a, 44b, and 44c will be formed. Using this resist pattern as a mask, the first metal film is anisotropically etched. This results in the formation of a lower electrode 44a electrically connected to the gate electrode 35b and the impurity diffusion regions 36b and 37a. Furthermore, a lower electrode 44b electrically connected to the gate electrode 35a and the impurity diffusion regions 36d and 37c is formed (FIG. 23). Furthermore, a lower electrode 44c is formed in contact with the impurity diffusion region 63 (FIG. 23).

[0122] Next, a high-dielectric film (e.g., HfZrOx or ZrOx) is deposited to a thickness of approximately 3 to 10 nm by CVD, ALD, or the like. Subsequently, a second metal film (e.g., TiN) is deposited to a thickness of approximately 3 to 20 nm by CVD, ALD, or the like, thereby filling the openings H1, H2, and H4 with the second metal film. Subsequently, a resist pattern is formed in predetermined regions including the openings H1, H2, and H4, where the upper electrodes 45a, 45b, 46a, 46b, and 46c will be formed. Using this resist pattern as a mask, the second metal film is anisotropically etched. As a result, the upper electrodes 45a and 46a are formed on the high-dielectric film with a predetermined gap therebetween. Furthermore, the upper electrodes 45b and 46b are formed on the high-dielectric film with a predetermined gap therebetween (FIG. 24). Furthermore, the upper electrode 46c is formed on the high-dielectric film (FIG. 24).

[0123] Next, crystallization annealing is performed to change the phase of the high-dielectric film (e.g., HfZrOx or ZrOx) into a ferroelectric film. This annealing can be performed either before or after the formation of the upper electrodes 45a, 45b, 46a, and 46b. The temperature of the crystallization annealing is in the range of 400°C to 700°C, which is set within the heat resistance range of the MOSFET, NiSi, and the like. Next, a resist pattern is formed in predetermined regions including the openings H1, H2, and H4, where the ferroelectric films 47a, 47b, and 47c will be formed. Using this resist pattern as a mask, the high-dielectric film is anisotropically etched. As a result, the ferroelectric film 47a is formed on the lower electrode 44a. Furthermore, the ferroelectric film 47b is formed on the lower electrode 44b (FIG. 24). Furthermore, the ferroelectric film 47c is formed on the lower electrode 44c (FIG. 24). In this manner, stacked cylindrical ferroelectric capacitors C11, C12, C21, and C22 are formed.

[0124] Next, a resist pattern having openings where plugs 43 and 61 will be formed is formed. Using this resist pattern as a mask, anisotropic etching is performed on the interlayer film 41. This forms an opening H3 in the interlayer film 41. Furthermore, an opening H5 is formed in the interlayer film 41 (FIG. 25). Subsequently, a third metal film is formed by depositing, for example, Ti or TiN and W in this order by CVD, thereby filling the openings H3 and H5 with the third metal film. After that, the portions of the third metal film other than those filled in the openings H3 and H5 are etched. This forms plug 43 (FIG. 26). Furthermore, plug 61 is formed (FIG. 26). In addition to CVD, sputtering using IMP can also be used as a method for forming the third metal film. It is also possible to form plug 43 by full-surface etch-back.

[0125] In the above manufacturing process, the ferroelectric capacitors C11, C12, C21, C22, and C31 may be formed after the plugs 43 and 61 are formed.

[0126] Next, a fifth insulating film (e.g., SiO ２ ), and then the fifth insulating film is planarized by surface polishing using CMP. In this way, the interlayer film 42 is formed. Next, openings are formed in the interlayer film 42 by the damascene method, and wiring material such as Cu is embedded in the openings formed in the fifth insulating film. As a result, bit lines BL1, BL2, BL3, word lines WL, signal lines SL, power supply lines PWR, and ground lines GND are formed in the same layer as the interlayer film 42. Next, a sixth insulating film (e.g., SiO ２ After depositing the sixth insulating film 42, openings are formed in the sixth insulating film by the damascene method, and wiring material such as Cu is embedded in the openings formed in the sixth insulating film 42. As a result, plate lines PL1 and PL2 are formed on the interlayer film 42. Al can also be used as the material for the bit lines BL1, BL2, and BL3, word lines WL, signal lines SL, power supply lines PWR, ground lines GND, and plate lines PL1 and PL2. In this manner, the semiconductor device 2 is manufactured.

[0127] [Effects] Next, the effects of the semiconductor device 2 will be described.

[0128] In this embodiment, a ReRAM including a ferroelectric capacitor C31 and a select transistor T31 is formed on a common semiconductor substrate 31, and the ferroelectric capacitor C31 is formed in an opening H4 provided in the wiring layer 40. This makes it possible to simultaneously form the ferroelectric capacitors C11, C12, C21, and C22 in the SRAM region 2A and the ferroelectric capacitor C31 in the FeRAM region 2B. As a result, it is possible to form a nonvolatile SRAM and an FeRAM on the same chip without increasing the number of processes.

[0129] 5. Modifications common to all embodiments Next, modifications common to all embodiments will be described.

[0130] Fig. 27 shows a modified example of the circuit configuration of the semiconductor device 1 shown in Fig. 1 and Fig. 19. Fig. 28 shows an example of the planar configuration of the semiconductor device 1 shown in Fig. 27. Fig. 29 shows an example of the cross-sectional configuration of the semiconductor device 1 shown in Fig. 28 taken along line E-E. Fig. 30 is a diagram in which the planar configuration of the semiconductor device 1 shown in Fig. 28 is omitted from the illustration of some of the configuration.

[0131] In each of the above embodiments and their modifications, the semiconductor device 1 may further include a read transistor 41 and a select transistor T42, for example, as shown in Fig. 27. In this case, the memory layer 30 further includes, on the semiconductor substrate 31, a read transistor T41 whose gate is connected to the output (storage node N1) of the inverter 10, and a select transistor T42 that controls signal reading from the read transistor T41.

[0132] The read transistor T41 and the select transistor T42 are formed as n-type FETs. In the read transistor T41, one of the source and drain (impurity diffusion region 41b) is electrically connected to one of the source and drain (impurity diffusion region 42b) of the select transistor T42, and the other of the source and drain (impurity diffusion region 41a) is electrically connected to, for example, the ground line GND. In the read transistor T41, the gate is electrically connected to the output (storage node N1) of the inverter 10, and the on / off state of the channel of the read transistor T41 is controlled by the voltage applied from the storage node N1. In other words, the gate electrode of the read transistor T41 is shared with the gate electrodes of the p-type transistor T21 and the n-type transistor T22, and is constituted by the common gate electrode 35b.

[0133] In the select transistor T42, one of the source and drain (impurity diffusion region 42a) is electrically connected to the bit line RBL, and the other of the source and drain (impurity diffusion region 42b) is electrically connected to one of the source and drain (impurity diffusion region 41b) of the read transistor 41. In the select transistor T42, the gate is electrically connected to the word line RWL, and the on / off state of the channel of the select transistor T42 is controlled by the voltage applied from the word line RWL.

[0134] The read transistor T41 is an FET formed by providing a gate electrode 35b via a gate insulating film on a p-type impurity diffusion region of the semiconductor substrate 31. In the read transistor T41, the source and drain are formed of n-type impurity diffusion regions formed by, for example, implanting As+ into a part of the p-type impurity diffusion region. In the read transistor T41, one of the source and drain is formed of an n-type impurity diffusion region 41a, and the other is formed of an n-type impurity diffusion region 41b.

[0135] The select transistor T42 is an FET formed by providing a gate electrode 35f via a gate insulating film on a p-type impurity diffusion region of the semiconductor substrate 31. In the select transistor T42, the source and drain are formed of n-type impurity diffusion regions formed by, for example, implanting As+ into a portion of the p-type impurity diffusion region. In the select transistor T42, one of the source and drain is formed of an n-type impurity diffusion region 42a, and the other is formed of an n-type impurity diffusion region 42b.

[0136] The gate insulating film described above is made of an insulating material and is provided on the surface of the impurity diffusion region 31a of the semiconductor substrate 31. The gate insulating film may be formed of an insulating material known as a gate insulating film for an FET. The gate insulating film may be formed of an insulating oxynitride such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON). A p-type impurity diffusion region is formed on the surface of the semiconductor layer 33F as the impurity diffusion region 31a, and the read transistor T41 and the select transistor T42 are formed in the p-type impurity diffusion region of the semiconductor layer 33F.

[0137] The gate electrode 35b is provided at a position facing the semiconductor layer 33F. N-type impurity diffusion regions 41a and 41b are formed in the p-type impurity diffusion region of the semiconductor layer 33F, and the gate electrode 35b, the n-type impurity diffusion regions 41a and 41b, and the read transistor T41 are formed by the gate electrode 35b, the n-type impurity diffusion regions 41a and 41b. The gate electrode 35f is provided at a position facing the semiconductor layer 33F. N-type impurity diffusion regions 42a and 42b are formed in the p-type impurity diffusion region of the semiconductor layer 33F, and the select transistor T42 is formed by the gate electrode 35f, the n-type impurity diffusion regions 42a and 42b, and the select transistor T42.

[0138] The gate electrode 35f may be formed of, for example, polysilicon, or may be formed of a metal, alloy, metal compound, or alloy of a metal (such as Ni) and polysilicon (so-called silicide). The gate electrode 35f may be formed of, for example, a stacked structure of a metal layer and a polysilicon layer. Sidewalls may be provided on the side surfaces of the gate electrode 35f. The sidewalls may be made of an insulating material, for example, an insulating oxynitride such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON).

[0139] [Effects] Next, the effects of the semiconductor device 1 according to this modification will be described.

[0140] In this modification, a read transistor T41 and a select transistor T42 are further provided in the semiconductor device 1, and the gate electrode of the read transistor T41 is shared with the gate electrode 35b of the p-type transistor T21 and the n-type transistor T22. Even in this case, the lower electrode 44a can be used as a shared contact to connect the two ferroelectric capacitors C11 and C12 and the read transistor T41 to the storage node N1. As a result, it is possible to prevent an increase in the SRAM area and reduce the chip area.

[0141] The present disclosure has been described above by way of embodiments and their modified examples, but the present disclosure is not limited to the above embodiments, and various modifications are possible. Note that the effects described in this specification are merely examples. The effects of the present disclosure are not limited to the effects described in this specification. The present disclosure may have effects other than those described in this specification.

[0142] Furthermore, for example, the present disclosure may have the following configuration: <1> A first inverter (10) including a p-type FET (T11) and an n-type FET (T12), a second inverter (20) including a p-type FET (T21) and an n-type FET (T22), an output of which is connected to the input of the first inverter (10) and an input of which is connected to the output of the first inverter (10), a first ferroelectric capacitor (C11) and a second ferroelectric capacitor (C12) each having a first electrode (44a) and a second electrode (45a, 46a), each of which is connected in parallel to the output of the first inverter (10), a third ferroelectric capacitor (C21) and a fourth ferroelectric capacitor (C22) each having a third electrode (44b) and a fourth electrode (45b, 46b), each of which is connected in parallel to the output of the second inverter (20), a first plate line (PL1) connecting the second electrodes (45a, 46a) of the first ferroelectric capacitor (C11) and the third ferroelectric capacitor (C21), and a second plate line (PL2) connecting the fourth electrodes (45b, 46b) of the second ferroelectric capacitor (C12) and the fourth ferroelectric capacitor (C22), respectively; wherein gate electrodes (35b) of the p-type FET (T21) and the n-type FET (T22) included in the second inverter (20) are configured with a first shared electrode (35b), and the first electrodes (44a) of the first ferroelectric capacitor (C11) and the second ferroelectric capacitor (C12) are configured with a second shared electrode (44a), and the first shared electrode (35b) and the second shared electrode (44a) are connected to each other; the gate electrodes (35 a) of the p-type FET (T11) and the n-type FET (T12) included in the first inverter (10) are configured with a third shared electrode (35 a), the third electrodes (44 b) of the third ferroelectric capacitor (C21) and the fourth ferroelectric capacitor (C22) are configured with a fourth shared electrode (44 b), and the third shared electrode (35 a) and the fourth shared electrode (44 b) are connected to each other;a semiconductor device in which the second electrode (45a) of the first ferroelectric capacitor (C11) and the second electrode (46a) of the second ferroelectric capacitor (C12) are provided separately from each other, and the fourth electrode (45b) of the third ferroelectric capacitor (C21) and the fourth electrode (46b) of the fourth ferroelectric capacitor (C22) are provided separately from each other. <2> A semiconductor device further comprising: a memory layer (30) in which the first inverter (10) and the second inverter (20) are formed on a semiconductor substrate (31); and a wiring layer (40) in which the first ferroelectric capacitor (C11), the second ferroelectric capacitor (C12), the third ferroelectric capacitor (C21), the fourth ferroelectric capacitor (C22), the first plate line (PL1), and the second plate line (PL2), The wiring layer (40) is formed with a first opening (H1) exposing the surface of the first common electrode (35b) at its bottom surface, a second opening (H2) exposing the sources or drains (36b, 37a) of the p-type FET (T11) and the n-type FET (T12) included in the first inverter (10) at its bottom surface, a third opening (H1) exposing the surface of the third common electrode (35a) at its bottom surface, and a fourth opening (H2) exposing the sources or drains (36d, 37c) of the p-type FET (T21) and the n-type FET (T22) included in the second inverter (20) at its bottom surface, the first ferroelectric capacitor (C11) is formed in the first opening (H1), the second ferroelectric capacitor (C12) is formed in the second opening (H2), and the third ferroelectric capacitor (C21) is formed in the third opening (H1), the fourth ferroelectric capacitor (C22) is formed in the fourth opening (H2). <3> The second shared electrode (44a) extends from the inner surface of the first opening (H1) to the inner surface of the second opening (H2) and forms a shared contact that contacts the first shared electrode (35b) and each of the sources or drains (36b, 37a) of the p-type FET (T11) and the n-type FET (T12) included in the first inverter (10),The semiconductor device according to <2>, wherein the fourth shared electrode (44b) extends from the inner surface of the third opening (H1) to the inner surface of the fourth opening (H2) and forms a shared contact that contacts the third shared electrode (35a) and the sources or drains (36d, 37c) of the p-type FET (T21) and the n-type FET (T22) included in the second inverter (20). <4> The semiconductor device according to <2> or <3>, wherein the semiconductor substrate (31) has a plurality of semiconductor layers extending in a first direction and a plurality of element isolation layers sandwiching each of the semiconductor layers from a second direction perpendicular to the first direction, wherein sources and drains (36b, 37a) of the p-type FET (T11) and the n-type FET (T12) included in the first inverter (10) and sources and drains (36d, 37c) of the p-type FET (T21) and the n-type FET (T22) included in the second inverter (20) are formed in the plurality of semiconductor layers, and the first shared electrode (35b), the third shared electrode (35a), and the second plate line (PL2) extend in the second direction. <5> The semiconductor device according to <4>, wherein the first shared electrode (35b), the second plate line (PL2), and the third shared electrode (35a) are arranged in this order in the first direction, and the second shared electrode (44a) and the fourth shared electrode (44b) are L-shaped and include a portion extending in the first direction and a portion extending in the second direction. <6> The semiconductor device according to <2>, wherein the memory layer (30) has, on the semiconductor substrate (31), a ReRAM including a fifth ferroelectric capacitor (C31) and a selection transistor (T31) that controls selection and non-selection of the fifth ferroelectric capacitor (C31), and the wiring layer (40) has a fifth opening (H4) formed in it, exposing a source or drain (63) of the selection transistor (T31) at a bottom surface thereof, and the fifth ferroelectric capacitor (C31) is formed in the fifth opening (H4). <7> A first inverter (10) including a p-type FET (T11) and an n-type FET (T12);a second inverter (20) including a p-type FET (T21) and an n-type FET (T22), the output of which is connected to the input of the first inverter (10) and the input of which is connected to the output of the first inverter (10); a first ferroelectric capacitor (C11) and a second ferroelectric capacitor (C12), each having a first electrode (44a) and a second electrode (45a, 46a), each of which is connected in parallel to the output of the first inverter (10); a third ferroelectric capacitor (C21) and a fourth ferroelectric capacitor (C22), each having a third electrode (44b) and a fourth electrode (45b, 46b), each of which is connected in parallel to the output of the second inverter (20); a first plate line (PL1) connecting the second electrodes (45a, 46a) of the first ferroelectric capacitor (C11) and the third ferroelectric capacitor (C21), and a second plate line (PL2) connecting the fourth electrodes (45b, 46b) of the second ferroelectric capacitor (C12) and the fourth ferroelectric capacitor (C22), wherein the gate electrodes (35b) of the p-type FET (T21) and the n-type FET (T22) included in the second inverter (20) are formed as first shared electrodes (35b), and the gate electrodes (35a) of the p-type FET (T11) and the n-type FET (T12) included in the first inverter (10) are formed as third shared electrodes (35a), a first metal film (44x) in contact with the first shared electrode (35b) and the third shared electrode (35a), a high dielectric film (47x) in contact with the first metal film (44x), and a second metal film (48) in contact with the high dielectric film (47x) are formed in this order, and then annealing is performed to change the phase of the high dielectric film (47x) into a ferroelectric film (47b), and the second metal film (48) is selectively etched, thereby forming the second electrode (45a) of the first ferroelectric capacitor (C11) and the second electrode (46a) of the second ferroelectric capacitor (C12) separately from each other, and forming the fourth electrode (45b) of the third ferroelectric capacitor (C21) and the fourth electrode (46b) of the fourth ferroelectric capacitor (C22) separately from each other;sidewalls (49) are formed on side surfaces of the second electrode (45a) of the first ferroelectric capacitor (C11), the second electrode (46a) of the second ferroelectric capacitor (C12), the fourth electrode (45b) of the third ferroelectric capacitor (C21), and the fourth electrode (46b) of the fourth ferroelectric capacitor (C22), so as to fill a gap between the second electrode (45a) of the first ferroelectric capacitor (C11) and the second electrode (46a) of the second ferroelectric capacitor (C12) and to fill a gap between the fourth electrode (45b) of the third ferroelectric capacitor (C21) and the fourth electrode (46b) of the fourth ferroelectric capacitor (C22); a high dielectric constant film (47x) and a first metal film (44x) are etched using the second electrode (45a) of the first ferroelectric capacitor (C11), the second electrode (46a) of the second ferroelectric capacitor (C12), the fourth electrode (45b) of the third ferroelectric capacitor (C21), the fourth electrode (46b) of the fourth ferroelectric capacitor (C22), and the sidewalls (49) as a mask, thereby forming the first electrode (44a) of each of the first ferroelectric capacitor (C11) and the second ferroelectric capacitor (C12) as a second shared electrode (44a), and forming the third electrode (44b) of each of the third ferroelectric capacitor (C21) and the fourth ferroelectric capacitor (C22) as a fourth shared electrode (44b).

[0143] This application claims priority based on Japanese Patent Application No. 2023-203116, filed on November 30, 2023, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0144] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. A first inverter including a p-type FET and an n-type FET; a second inverter including a p-type FET and an n-type FET, an output of which is connected to the input of the first inverter and an input of which is connected to the output of the first inverter; a first ferroelectric capacitor and a second ferroelectric capacitor, each having a first electrode and a second electrode, each of which is connected in parallel to the output of the first inverter; a third ferroelectric capacitor and a fourth ferroelectric capacitor, each of which is connected in parallel to the output of the second inverter, each of which is connected in parallel to the output of the second inverter; a first plate line connecting the second electrodes of the first ferroelectric capacitor and the third ferroelectric capacitor; and a second plate line connecting the fourth electrodes of the second ferroelectric capacitor and the fourth ferroelectric capacitor, wherein the gate electrodes of the p-type FET and the n-type FET included in the second inverter are formed by a first shared electrode, the first electrodes of the first ferroelectric capacitor and the second ferroelectric capacitor are formed by a second shared electrode, and the first shared electrode and the second shared electrode are connected to each other, a gate electrode of each of the p-type FET and the n-type FET included in the first inverter is configured by a third shared electrode, the third electrodes of each of the third ferroelectric capacitor and the fourth ferroelectric capacitor are configured by a fourth shared electrode, and the third shared electrode and the fourth shared electrode are connected to each other, the second electrode of the first ferroelectric capacitor and the second electrode of the second ferroelectric capacitor are provided separately from each other, and the fourth electrode of the third ferroelectric capacitor and the fourth electrode of the fourth ferroelectric capacitor are provided separately from each other.

2. The semiconductor device according to claim 1, further comprising: a memory layer in which the first inverter and the second inverter are formed on a semiconductor substrate; and a wiring layer in which the first ferroelectric capacitor, the second ferroelectric capacitor, the third ferroelectric capacitor, the fourth ferroelectric capacitor, the first plate line and the second plate line are formed, wherein the wiring layer is formed with a first opening, the surface of the first shared electrode being exposed at its bottom surface, a second opening, the sources or drains of the p-type FET and the n-type FET included in the first inverter being exposed at their bottom surface, a third opening, the surface of the third shared electrode being exposed at its bottom surface, and a fourth opening, the sources or drains of the p-type FET and the n-type FET included in the second inverter being exposed at their bottom surface, wherein the first ferroelectric capacitor is formed in the first opening, the second ferroelectric capacitor is formed in the second opening, the third ferroelectric capacitor is formed in the third opening, and the fourth ferroelectric capacitor is formed in the fourth opening.

3. The semiconductor device according to claim 2, wherein the second shared electrode extends from the inner surface of the first opening to the inner surface of the second opening, and forms a shared contact between the first shared electrode and the sources or drains of the p-type FET and the n-type FET included in the first inverter, and the fourth shared electrode extends from the inner surface of the third opening to the inner surface of the fourth opening, and forms a shared contact between the third shared electrode and the sources or drains of the p-type FET and the n-type FET included in the second inverter.

4. The semiconductor device according to claim 2, wherein the semiconductor substrate has a plurality of semiconductor layers extending in a first direction and a plurality of element isolation layers sandwiching each of the semiconductor layers from a second direction perpendicular to the first direction, the sources and drains of the p-type FET and the n-type FET included in the first inverter and the sources and drains of the p-type FET and the n-type FET included in the second inverter are formed in the plurality of semiconductor layers, and the first shared electrode, the third shared electrode, and the second plate line extend in the second direction.

5. The semiconductor device described in claim 4, wherein the first shared electrode, the second plate line, and the third shared electrode are arranged in this order in the first direction, and the second shared electrode and the fourth shared electrode are L-shaped including a portion extending in the first direction and a portion extending in the second direction.

6. The semiconductor device according to claim 2, wherein the memory layer further includes a ReRAM on the semiconductor substrate, the ReRAM including a fifth ferroelectric capacitor and a selection transistor that controls selection and non-selection of the fifth ferroelectric capacitor, the wiring layer is formed with a fifth opening in which the source or drain of the selection transistor is exposed at a bottom surface, and the fifth ferroelectric capacitor is formed in the fifth opening.

7. A method for manufacturing a semiconductor device comprising: a first inverter including a p-type FET and an n-type FET; a second inverter including a p-type FET and an n-type FET, an output of which is connected to the input of the first inverter and an input of which is connected to the output of the first inverter; a first ferroelectric capacitor and a second ferroelectric capacitor, each having a first electrode and a second electrode, each of which is connected in parallel to the output of the first inverter; a third ferroelectric capacitor and a fourth ferroelectric capacitor, each of which is connected in parallel to the output of the second inverter, a first plate line connecting the second electrodes of the first ferroelectric capacitor and the third ferroelectric capacitor; and a second plate line connecting the fourth electrodes of the second ferroelectric capacitor and the fourth ferroelectric capacitor, the method comprising forming the gate electrodes of the p-type FET and the n-type FET included in the second inverter as a first shared electrode, forming the gate electrodes of the p-type FET and the n-type FET included in the first inverter as a third shared electrode, forming a first metal film in contact with the first shared electrode and the third shared electrode, a high dielectric film in contact with the first metal film, and a second metal film in contact with the high dielectric film in this order, and then performing annealing to change the phase of the high dielectric film into a ferroelectric film, and selectively etching the second metal film to form the second electrode of the first ferroelectric capacitor and the second electrode of the second ferroelectric capacitor separately from each other, and form the fourth electrode of the third ferroelectric capacitor and the fourth electrode of the fourth ferroelectric capacitor separately from each other; forming sidewalls on side surfaces of the second electrode of the first ferroelectric capacitor, the second electrode of the second ferroelectric capacitor, the fourth electrode of the third ferroelectric capacitor, and the fourth electrode of the fourth ferroelectric capacitor so as to fill a gap between the second electrode of the first ferroelectric capacitor and the second electrode of the second ferroelectric capacitor, and to fill a gap between the fourth electrode of the third ferroelectric capacitor and the fourth electrode of the fourth ferroelectric capacitor;a high dielectric film and a first metal film are etched using the second electrode of the first ferroelectric capacitor, the second electrode of the second ferroelectric capacitor, the fourth electrode of the third ferroelectric capacitor, the fourth electrode of the fourth ferroelectric capacitor, and the sidewall as a mask, thereby forming the first electrodes of the first ferroelectric capacitor and the second ferroelectric capacitor as second shared electrodes, and forming the third electrodes of the third ferroelectric capacitor and the fourth ferroelectric capacitor as fourth shared electrodes.

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