Light detection device and electronic apparatus

Abstract

The present invention achieves improvement in resolution. This light detection device comprises: a semiconductor layer which has a light incidence surface part and in which photoelectric conversion regions that performs photoelectric conversion of light, into a signal charge, incident from the light incidence surface part side are arranged in a matrix; a shutter layer which is provided on the light incidence surface part side of the semiconductor layer and in which shutter parts that controls the incidence of light on the photoelectric conversion regions by transmitting and blocking are arranged in a matrix at the same arrangement pitch as the photoelectric conversion regions; and a shutter block which includes the plurality of shutter parts and in which a part of each of the plurality of shutter parts overlaps one of the photoelectric conversion regions in plan view.

Description

Photodetector and electronic equipment

[0001] The present technology (technology related to the present disclosure) relates to a photodetector and an electronic device, and in particular to a technology that is effective when applied to a photodetector having a shutter portion and an electronic device including the same.

[0002] In photodetection devices (image sensors) such as distance measuring devices and solid-state imaging devices, a technique for controlling the incidence of light on a photoelectric conversion region provided in a semiconductor layer using a shutter unit is known. Patent Document 1 discloses an imaging device in which two liquid crystal shutter units are provided in one photoelectric conversion region. Patent Document 1 achieves high resolution by combining an image captured with only one of the two liquid crystal shutter units in an open state (the other in a closed state) and an image captured with only the other in an open state (the other in a closed state) in accordance with the opening positions of the liquid crystal shutter units.

[0003] Japanese Patent Application Laid-Open No. 2004-14802

[0004] However, even in ferroelectric liquid crystals, which can suppress crosstalk between adjacent pixels, the pixels are arranged at a minimum pitch of 1 μm at the research level, which is wider than the pixel pitch of, for example, the 0.6 μm of the most advanced image sensors. Therefore, with conventional technology, the size at which pixels can be pseudo-miniaturized is limited to the size of the liquid crystal shutter section.

[0005] An object of the present technology is to provide a technology that can achieve higher resolution.

[0006] (1) A photodetector according to one aspect of the present technology includes: a semiconductor layer having a light incident surface portion, and having photoelectric conversion regions arranged in a matrix, which photoelectrically convert light incident from the light incident surface portion side into signal charges; a shutter layer provided on the light incident surface portion side of the semiconductor layer, and having shutter portions arranged in a matrix at the same arrangement pitch as the photoelectric conversion regions, which control the incidence of light on the photoelectric conversion regions by transmitting and blocking light; and shutter blocks including a plurality of the shutter portions, each of which has a portion overlapping one of the photoelectric conversion regions in a planar view.

[0007] (2) An electronic device according to another aspect of the present technology includes the above-mentioned photodetector; an optical lens that focuses image light from a subject on an imaging surface of the photodetector; and a signal processing circuit that performs signal processing on a signal output from the photodetector.

[0008] 1 is a chip layout diagram showing a configuration example of a solid-state imaging device according to a first embodiment of the present technology. FIG. 2 is a block diagram showing a configuration example of a solid-state imaging device according to a first embodiment of the present technology. FIG. 3 is an equivalent circuit diagram showing a configuration example of a pixel according to a first embodiment of the present technology. FIG. 4 is a plan view schematically showing a positional relationship between shutter portions and photoelectric conversion regions of a shutter layer in a solid-state imaging device according to a first embodiment of the present technology. FIG. 5 is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a4-a4 cutting line of FIG. 4. FIG. 6 is a plan view schematically showing a state in which portions of four shutter portions included in one shutter block overlap with one photoelectric conversion region in a solid-state imaging device according to a first embodiment of the present technology. FIG. 7 is a plan view schematically showing a state in which portions of four photoelectric conversion regions overlap with one shutter portion in a solid-state imaging device according to a first embodiment of the present technology. FIG. 8 is a perspective view schematically showing an arrangement of upper electrodes and lower electrodes included in a shutter layer in a solid-state imaging device according to a first embodiment of the present technology. FIG. 9 is a plan view schematically showing an arrangement of upper electrodes and lower electrodes included in a shutter layer in a solid-state imaging device according to a first embodiment of the present technology. 11A is a plan view schematically showing a first opening and closing pattern of a shutter block in a solid-state imaging device according to a first embodiment of the present technology. FIG. 9A is a plan view schematically showing a first opening and closing pattern of a shutter block in a solid-state imaging device according to a first embodiment of the present technology. FIG. 10A is a plan view schematically showing a second opening and closing pattern of a shutter block in a solid-state imaging device according to a first embodiment of the present technology. FIG. 11A is a plan view schematically showing a third opening and closing pattern of a shutter block in a solid-state imaging device according to a first embodiment of the present technology. FIG. 11A is a plan view schematically showing a fourth opening and closing pattern of a shutter block in a solid-state imaging device according to a first embodiment of the present technology. FIG. 12A is a plan view schematically showing a longitudinal cross-sectional structure of a solid-state imaging device according to a second embodiment of the present technology. FIG. 12B is a longitudinal cross-sectional view schematically showing a modified example 1-1 of the second embodiment of the present technology. FIG. 12C is a longitudinal cross-sectional view schematically showing a modified example 1-2 of the second embodiment of the present technology. FIG. 12D is a longitudinal cross-sectional view schematically showing a modified example 1-3 of the second embodiment of the present technology. FIG. 12E is a longitudinal cross-sectional view schematically showing a modified example 1-4 of the second embodiment of the present technology. FIG. 10 is a longitudinal cross-sectional view schematically showing a modified example 1-5 of the second embodiment of the present technology.20A is a plan view schematically showing a state in which a portion of each of two shutter portions included in one shutter block overlaps one photoelectric conversion region in a solid-state imaging device according to a third embodiment of the present technology. FIG. 19A is an enlarged plan view of a portion of FIG. 19A. FIG. 20A is an enlarged plan view of a portion of FIG. 20 ...4A. FIG. 24A is an enlarged plan view of a portion of FIG. 24A. FIG. 24A is an enlarged plan view of a portion of FIG. 24A. FIG. 24A is an enlarged plan view of a portion of FIG. 24A. 10 is a perspective view schematically showing an arrangement state of upper electrodes and lower electrodes included in a shutter layer in a solid-state imaging device according to a fourth embodiment of the present technology. FIG. 11 is a plan view schematically showing an arrangement state of upper electrodes and lower electrodes included in a shutter layer in a solid-state imaging device according to a fourth embodiment of the present technology. FIG. 12 is a plan view schematically showing a plane pattern of relay electrodes included in an inter-pixel isolation region in a solid-state imaging device according to a fourth embodiment of the present technology. FIG. 13 is a plan view schematically showing a modified example 4-1 of the fourth embodiment of the present technology. FIG. 14 is a plan view schematically showing a modified example 4-2 of the fourth embodiment of the present technology. FIG. 15 is a longitudinal sectional view schematically showing a modified example 4-3 of the fourth embodiment of the present technology. FIG. 16 is a plan view schematically showing a modified example 4-3 of the fourth embodiment of the present technology. FIG. 17 is a plan view schematically showing a modified example 4-4 of the fourth embodiment of the present technology. FIG. 18 is a longitudinal sectional view schematically showing a longitudinal sectional structure of a solid-state imaging device according to a fifth embodiment of the present technology. FIG. 19 is a diagram showing an example of a configuration of an electronic device according to a sixth embodiment of the present technology.

[0009] Hereinafter, embodiments of the present technology will be described in detail with reference to the drawings. Note that in the drawings referred to in the following description, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description.

[0010] Furthermore, it goes without saying that the dimensional relationships and ratios may differ between the drawings. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be present.

[0011] Furthermore, the following embodiments exemplify devices and methods for embodying the technical idea of ​​the present technology, and do not limit the configuration to the following. In other words, the technical idea of ​​the present technology can be modified in various ways within the technical scope described in the claims.

[0012] Furthermore, the definitions of directions such as up and down in the following description are merely for the sake of convenience and do not limit the technical concept of the present technology. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if an object is rotated 180 degrees and observed, up and down are obviously read as reversed.

[0013] In the following embodiments, among the three mutually orthogonal directions in space, a first direction and a second direction that are mutually orthogonal in the same plane are defined as the X direction and the Y direction, respectively, and a third direction that is orthogonal to each of the first and second directions is defined as the Z direction. In the following embodiments, the thickness direction of a semiconductor layer 21, which will be described later, will be described as the Z direction.

[0014] In the following embodiments, the Z direction will be described as "one direction" of the present technology.

[0015] In addition, in the following embodiments, the thickness of the semiconductor layer 21 is the distance between the first surface portion S1 and the second surface portion S2, which are located on opposite sides in the Z direction, and the thickness direction of the semiconductor layer 21 is the direction representing the thickness of the semiconductor layer 21.

[0016] In the following embodiments, a plan view refers to a case where the semiconductor layer 21 is viewed from the Z direction (one direction), and a cross-sectional view refers to a case where a cross section along the Z direction (one direction) is viewed from a direction perpendicular to the Z direction.

[0017] First Embodiment In this first embodiment, an example in which the present technology is applied to a solid-state imaging device that is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor as a photodetector will be described. Also, in this first embodiment, an example in which a liquid crystal layer 58 is used as a material layer that can be electrically switched between transmitting and blocking light, and four pseudo pixels are configured in one photoelectric conversion region 22 will be described.

[0018] <Overall Configuration of Solid-State Imaging Device> First, the overall configuration of the solid-state imaging device 1A will be described. As shown in Fig. 1 , the solid-state imaging device 1A according to the first embodiment of the present technology is mainly composed of a semiconductor chip 2 having a rectangular two-dimensional planar shape when viewed in a plan view. That is, the solid-state imaging device 1A is mounted on the semiconductor chip 2, and the semiconductor chip 2 can be considered as the solid-state imaging device 1A. As shown in Fig. 35 , this solid-state imaging device 1A (101) captures image light (incident light 106) from a subject via an optical lens 102, converts the amount of incident light 106 formed on the imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs the electrical signal as a pixel signal.

[0019] As shown in FIG. 1, a semiconductor chip 2 on which a solid-state imaging device 1A is mounted includes, in a two-dimensional plane including an X direction and a Y direction which are orthogonal to each other, a rectangular pixel array section 2A provided in the center, and a peripheral section 2B provided outside the pixel array section 2A so as to surround the pixel array section 2A.

[0020] Here, the semiconductor chips 2 are formed in the manufacturing process by dicing a semiconductor wafer including a semiconductor layer 21 (described later) into chip formation regions. Therefore, the configuration of the solid-state imaging device 1A described below is generally the same in the wafer state before the semiconductor wafer is diced. Therefore, the present technology can be applied to both the semiconductor chip state and the semiconductor wafer state.

[0021] The pixel array unit 2A shown in Fig. 1 is, for example, a light receiving surface that receives light collected by an optical lens (optical system) 102 shown in Fig. 35. The pixel array unit 2A has a plurality of pixels 3 (sensor pixels) arranged in a matrix (rows and columns) on a two-dimensional plane including the X direction and the Y direction. In other words, the pixels 3 are repeatedly arranged in each of the X direction and the Y direction that are orthogonal to each other within the two-dimensional plane.

[0022] 1, a plurality of bonding pads 14 are arranged in the peripheral portion 2B. Each of the plurality of bonding pads 14 is arranged, for example, along each of the four sides in a two-dimensional plane of the semiconductor chip 2. Each of the plurality of bonding pads 14 functions as an input / output terminal that electrically connects the semiconductor chip 2 to an external device.

[0023] <Logic Circuit> The semiconductor chip 2 includes a logic circuit 13 shown in Fig. 2. As shown in Fig. 2, the logic circuit 13 includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The logic circuit 13 is configured of a CMOS (Complementary MOS) circuit having, as field effect transistors, for example, n-channel conductivity type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and p-channel conductivity type MOSFETs.

[0024] The vertical drive circuit 4 shown in Fig. 2 is configured with, for example, a shift register. The vertical drive circuit 4 sequentially selects desired pixel drive lines 10, supplies pulses to the selected pixel drive lines 10 for driving the pixels 3, and drives each pixel 3 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 3 in the pixel array section 2A row by row in the vertical direction, and supplies pixel signals from the pixels 3 based on signal charges generated by the photoelectric conversion section 25 (see Fig. 3) of each pixel 3 in accordance with the amount of received light to the column signal processing circuit 5 via the vertical signal line 11.

[0025] 2 is arranged for each column of pixels 3, and performs signal processing such as noise removal for each pixel column on signals output from one row of pixels 3. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) and AD (Analog-Digital) conversion to remove fixed pattern noise specific to each pixel.

[0026] 2 is configured by, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to the column signal processing circuits 5, thereby selecting each of the column signal processing circuits 5 in turn and causing each column signal processing circuit 5 to output a pixel signal that has undergone signal processing to a horizontal signal line 12.

[0027] 2 performs signal processing on pixel signals sequentially supplied from each of the column signal processing circuits 5 via the horizontal signal line 12, and outputs the processed signals. The signal processing may include, for example, buffering, black level adjustment, column variation correction, various types of digital signal processing, etc.

[0028] 2 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc., based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal. Then, the control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

[0029] <Pixels> Each of the plurality of pixels 3 includes a photoelectric conversion region 22 shown in FIG.

[0030] <Photoelectric Conversion Region> As shown in FIG. 3, the photoelectric conversion region 22 includes a photoelectric conversion section 25, a transfer transistor TR, and a floating diffusion region FD as the photoelectric conversion section.

[0031] 3 is configured, for example, by a pn junction photodiode (PD) and generates a signal charge according to the amount of light received. The photoelectric conversion unit 25 also temporarily holds (accumulates) the generated signal charge. The cathode side of the photoelectric conversion unit 25 is electrically connected to the source region of the transfer transistor TR, and the anode side is electrically connected to a reference potential line (for example, ground).

[0032] 3 transfers the signal charges photoelectrically converted by the photoelectric conversion unit 25 to the floating diffusion region FD. The source region of the transfer transistor TR is electrically connected to the cathode side of the photoelectric conversion unit 25, and the drain region is electrically connected to the floating diffusion region FD. The gate electrode of the transfer transistor TR is electrically connected to a transfer transistor drive line of the pixel drive lines 10 shown in FIG.

[0033] (Floating Diffusion Region) The floating diffusion region FD shown in FIG. 3 temporarily accumulates and holds the signal charge transferred from the photoelectric conversion unit 25 via the transfer transistor TR.

[0034] <Pixel Circuit> The solid-state imaging device 1A of the first embodiment further includes a pixel circuit (readout circuit) 15 shown in FIG. 3. As shown in FIG. 3, the input stage of the pixel circuit 15 is electrically connected to the floating diffusion region FD of the photoelectric conversion region 22. In the first embodiment, as an example, a circuit configuration is used in which one pixel circuit 15 is assigned to one pixel 3. However, this is not limited to this, and one pixel circuit 15 may be shared by multiple pixels 3. For example, a circuit configuration may be used in which one pixel circuit 15 is shared by a pixel block, each of which includes four pixels 3 arranged in a 2×2 array, two pixels 3 in each of the X and Y directions. Alternatively, a circuit configuration may be used in which one pixel circuit 15 is assigned to a pixel block, each of which includes two or more pixels 3, or in which one pixel circuit 15 is assigned to multiple pixel blocks, each of which includes multiple pixels 3.

[0035] 3 reads out the signal charge held in the floating diffusion region FD of one pixel 3 and outputs a pixel signal based on the read signal charge. In other words, the pixel circuit 15 converts the signal charge photoelectrically converted by the photoelectric conversion unit 25 (photodiode PD) into a pixel signal based on this signal charge and outputs it.

[0036] 3, the pixel circuit 15 includes a plurality of pixel transistors Q. The pixel circuit 15 of the first embodiment includes, but is not limited to, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and a switching transistor FDG as the pixel transistors Q. These pixel transistors Q (AMP, SEL, RST, FDG) and the transfer transistor TR are insulated gate field effect transistors, and the gate insulating film is made of, for example, silicon oxide (SiO ２ These transistors are configured with MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) made of a silicon nitride (Si) film. ３ N ４ Alternatively, a metal insulator semiconductor field effect transistor (MISFET) made of a laminated film of a silicon nitride film, a silicon oxide film, or the like may be used.

[0037] Of the pixel transistors Q (AMP, SEL, RST, FDG) included in the pixel circuit 15, the selection transistor SEL, the reset transistor RST, and the switching transistor FDG mainly function as switching elements, and the remaining amplification transistor AMP mainly functions as an amplification element.

[0038] 3, the source region of the amplifier transistor AMP is electrically connected to the drain region of the select transistor SEL, and the drain region is electrically connected to the power supply line Vdd and the drain region of the reset transistor RST. The gate electrode of the amplifier transistor AMP is electrically connected to the floating diffusion region FD and the source region of the switching transistor FDG.

[0039] 3, the source region of the selection transistor SEL is electrically connected to the vertical signal line 11 (VSL), the drain region is electrically connected to the source region of the amplification transistor AMP, and the gate electrode of the selection transistor SEL is electrically connected to the selection transistor drive line of the pixel drive lines 10 shown in FIG.

[0040] 3, the source region of the reset transistor RST is electrically connected to the drain of the switching transistor FDG, and the drain region of the reset transistor RST is electrically connected to the power supply line Vdd and the drain region of the amplification transistor AMP. The gate electrode of the reset transistor RST is electrically connected to the reset transistor drive line of the pixel drive line 10 shown in FIG.

[0041] 3, the source region of the switching transistor FDG is electrically connected to the gate electrode of the amplification transistor AMP and the floating diffusion region FD, and the drain region is electrically connected to the source region of the reset transistor RST. The gate electrode of the switching transistor FDG is electrically connected to the switching transistor drive line of the pixel drive line 10 shown in FIG.

[0042] The selection transistor SEL and the switching transistor FDG may be omitted as necessary. When the selection transistor SEL is omitted, the source region of the amplification transistor AMP is electrically connected to the vertical signal line 11 (VSL). When the switching transistor FDG is omitted, the source region of the reset transistor RST is electrically connected to the gate electrode and floating diffusion region FD of the amplification transistor AMP.

[0043] (Function of Transfer Transistor) When the transfer transistor TR shown in FIG. 3 is turned on, it transfers the signal charge generated in the photoelectric conversion unit 25 (photodiode PD) to the floating diffusion region FD.

[0044] (Function of Reset Transistor) When the reset transistor RST shown in FIG. 3 is turned on, it resets the potential (signal charge) of the floating diffusion region FD to the potential of the power supply line Vdd.

[0045] (Function of Selection Transistor) The selection transistor SEL shown in FIG. 3 controls the output timing of the pixel signal from the pixel circuit 15 .

[0046] (Function of Amplification Transistor) The amplification transistor AMP shown in Figure 3 generates a pixel signal with a voltage corresponding to the level of the signal charge held in the floating diffusion region FD. The amplification transistor AMP constitutes a source follower amplifier and outputs a pixel signal with a voltage corresponding to the level of the signal charge generated in the photoelectric conversion unit 25 (photodiode PD). When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion region FD and outputs a voltage corresponding to the potential to the column signal processing circuit 5 via the vertical signal line 11 (VSL).

[0047] (Function of Switching Transistor) The switching transistor FDG shown in FIG. 3 controls charge retention by the floating diffusion region FD, and adjusts the multiplication factor of the voltage according to the potential amplified by the amplifier transistor AMP.

[0048] The switching transistor FDG is used to switch the conversion efficiency. Generally, pixel signals are small when shooting in dark locations. Based on Q = CV, when performing charge-to-voltage conversion, if the FD capacitance C (floating diffusion capacitance C) of the floating diffusion region FD is large, the voltage V converted to a voltage by the amplifier transistor AMP will be small. On the other hand, in bright locations, pixel signals are large, so if the FD capacitance C of the floating diffusion region FD is not large, the floating diffusion region FD cannot fully absorb the charge of the photoelectric conversion unit 25 (photodiode PD). Furthermore, the FD capacitance C of the floating diffusion region FD must be large so that the voltage V converted to a voltage by the amplifier transistor AMP does not become too large (in other words, to reduce it). Based on these considerations, when the switching transistor FDG is turned on, the gate capacitance of the switching transistor FDG increases, thereby increasing the overall FD capacitance C. On the other hand, when the switching transistor FDG is turned off, the overall FD capacitance C decreases. In this way, by switching the switching transistor FDG on and off, the FD capacitance C can be made variable, and the conversion efficiency can be changed.

[0049] (Function of Pixel Circuit) During operation of the solid-state imaging device 1A according to the first embodiment, signal charges generated in the photoelectric conversion unit 25 of the pixel 3 are held (accumulated) in the floating diffusion region FD via the transfer transistor TR of the pixel 3. The signal charges held in the floating diffusion region FD are then read out by the pixel circuit 15 and applied to the gate electrode of the amplifier transistor AMP of the pixel circuit 15. A horizontal line selection control signal is applied to the gate electrode of the select transistor SEL of the pixel circuit 15 from the vertical shift register. By setting the selection control signal to a high (H) level, the select transistor SEL becomes conductive, and a current corresponding to the potential of the floating diffusion region FD, amplified by the amplifier transistor AMP, flows through the vertical signal line 11. Furthermore, by setting the reset control signal applied to the gate electrode of the reset transistor RST of the pixel circuit 15 to a high (H) level, the reset transistor RST becomes conductive, resetting the signal charges accumulated in the floating diffusion region FD.

[0050] <<Specific Configuration of Solid-State Imaging Device>> Next, a specific configuration of the semiconductor chip 2 (solid-state imaging device 1A) will be described with reference to FIGS. 4 to 8. FIG. 4 is a plan view schematically showing a portion of the pixel array section 2A of FIG. 1. FIG. 5 is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a4-a4 cutting line of FIG. 4. FIG. 6A is a plan view schematically showing a state in which a portion of each of the four shutter sections 52 overlaps with one photoelectric conversion region 22. FIG. 6B is a plan view schematically showing a state in which a portion of each of the four photoelectric conversion regions 22 overlaps with one shutter section 52. FIG. 7 is a perspective view schematically showing the arrangement of the upper electrode 60 and the lower electrode 56 included in the shutter layer 51. FIG. 8 is a plan view schematically showing the arrangement of the upper electrode 60 and the lower electrode 56 included in the shutter layer 51.

[0051] As shown in Figures 4 and 5, the semiconductor chip 2 (solid-state imaging device 1A) comprises a semiconductor layer 21 having a first surface portion S1 and a second surface portion S2 located opposite each other in the thickness direction (Z direction) as one direction, a shutter layer 51 provided on the second surface portion S2 side of the semiconductor layer 21, and a lens layer 71 provided on the opposite side of the shutter layer 51 from the semiconductor layer 21 side.

[0052] Although not shown in detail, the semiconductor chip 2 further includes a multi-layer wiring layer provided on the first surface S1 side of the semiconductor layer 21. This multi-layer wiring layer includes an interlayer insulating film 46 and a wiring layer 48 provided in this order from the semiconductor layer 21 side (see FIG. 5).

[0053] Here, the first surface S1 of the semiconductor layer 21 may also be referred to as a main surface or element formation surface, and the second surface S2 as a back surface. As will be described in detail later, the solid-state imaging device 1A according to the first embodiment photoelectrically converts incident light incident from the second surface S2 side of the semiconductor layer 21 by a photoelectric conversion unit 25 (photodiode PD) provided in the photoelectric conversion region 22 of the semiconductor layer 21. Therefore, in the first embodiment, the second surface S2 of the semiconductor layer 21 may also be referred to as a light incident surface.

[0054] 5 , the semiconductor layer 21 includes an inter-pixel isolation region 31 extending in the thickness direction (Z direction) of the semiconductor layer 21, and a photoelectric conversion region 22 partitioned by the inter-pixel isolation region 31. The photoelectric conversion region 22 is provided for each pixel 3. The semiconductor layer 21 may be a Si substrate, a SiGe substrate, an InGaAs substrate, or the like. In the first embodiment, a p-type semiconductor substrate made of single crystal silicon, for example, is used as the semiconductor layer 21, although the present invention is not limited thereto.

[0055] 6A and 6B , the inter-pixel isolation regions 31 extend in the X direction and are repeatedly arranged at predetermined intervals in the Y direction. The inter-pixel isolation regions 31 also extend in the Y direction and are repeatedly arranged at predetermined intervals in the X direction. That is, the inter-pixel isolation regions 31 have a grid-like planar pattern in plan view.

[0056] As shown in Fig. 6A , the inter-pixel isolation region 31 corresponding to one photoelectric conversion region 22 has a rectangular annular planar pattern (ring-shaped planar pattern) in a plan view, and surrounds the periphery of one photoelectric conversion region 22. As shown in Fig. 6B , the inter-pixel isolation regions 31 corresponding to four photoelectric conversion regions 22 arranged two by two in a 2 × 2 arrangement adjacent to each other in each of the X and Y directions in the same plane form a composite planar pattern having a cross-shaped planar pattern within the rectangular annular planar pattern.

[0057] As shown in Figure 5, the inter-pixel isolation region 31 extends in the thickness direction (Z direction) in which the first surface portion S1 and the second surface portion S2 of the semiconductor layer 21 are separated from each other, and electrically and optically isolates two adjacent photoelectric conversion regions 22 in a planar view of the semiconductor layer 21 from the thickness direction (Z direction) of the semiconductor layer 21.

[0058] Although not limited to this, the inter-pixel isolation region 31 is configured as, for example, a trench isolation type including a recessed portion 32 extending in the thickness direction (Z direction) of the semiconductor layer 21 and an isolation insulating film 34 provided in this recessed portion 32. The inter-pixel isolation region 31 reaches both the first surface S1 and the second surface S2 of the semiconductor layer 21.

[0059] 6A and 6B , the photoelectric conversion region 22 is surrounded by inter-pixel isolation regions 31 in a plan view and has a rectangular planar shape. The photoelectric conversion region 22 is partitioned by the inter-pixel isolation regions 31 and is separated from other photoelectric conversion regions 22.

[0060] 4, the photoelectric conversion regions 22 are repeatedly arranged in the X direction and the Y direction, which are orthogonal to each other, in a two-dimensional plane, with inter-pixel isolation regions 31 interposed therebetween, and are provided for each pixel 3. That is, the photoelectric conversion regions 22 are arranged in a matrix (row and column) in the pixel array section 2A shown in FIG.

[0061] As shown in Figure 5, the photoelectric conversion region 22 has a p-type well region 23 consisting of a p-type semiconductor region provided in the semiconductor layer 21 across the first surface portion S1 and the second surface portion S2 of the semiconductor layer 21, an n-type semiconductor region 24 provided in the p-type well region 23 at a distance from the first surface portion S1 of the semiconductor layer 21, and a photoelectric conversion unit 25 including the p-type well region 23 and the n-type semiconductor region 24 and provided in the semiconductor layer 21 at a distance from the first surface portion S1 of the semiconductor layer 21.

[0062] The photoelectric conversion region 22 further includes an n-type floating diffusion region FD that is provided on the first surface S1 side of the semiconductor layer 21 and overlaps with the n-type semiconductor region 24 in a planar view, and serves as a charge holding section that holds signal charges photoelectrically converted by the photoelectric conversion section 25, and a transfer transistor TR that is provided on the first surface S1 side of the semiconductor layer 21 and overlaps with the n-type semiconductor region 24 in a planar view, and transfers the signal charges photoelectrically converted by the photoelectric conversion section 25 to the n-type floating diffusion region FD.

[0063] Although not shown, the photoelectric conversion region 22 further includes, for example, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and a switching transistor FDG as pixel transistors Q included in the pixel circuit 15 of Fig. 3. These pixel transistors Q (AMP, SEL, RST, FDG) are provided in the photoelectric conversion region 22 on the first surface S1 side of the semiconductor layer 21.

[0064] 5, the p-type well region 23 is provided over a wide area across the first surface portion S1 side and the second surface portion S2 side of the semiconductor layer 21 in each photoelectric conversion region 22. The p-type well region 23 is in contact with the inter-pixel isolation region 31 along the thickness direction (Z direction) of the semiconductor layer 21.

[0065] 5 , the n-type semiconductor region 24 is provided in the p-type well region 23 in each photoelectric conversion region 22. That is, six sides of the n-type semiconductor region 24, including the top surface, bottom surface, and four side surfaces, are surrounded by the p-type well region 23. The n-type semiconductor region 24 is separated from the first surface S1 and second surface S2 of the semiconductor layer 21 and the inter-pixel isolation region 31.

[0066] 5 includes a p-type well region 23 and an n-type semiconductor region 24 in each photoelectric conversion region 22. The photoelectric conversion unit 25 is configured as a p-n junction photodiode (PD) including a p-n junction between the p-type well region 23 and the n-type semiconductor region 24.

[0067] The photoelectric conversion unit 25 photoelectrically converts light incident on the n-type semiconductor region 24 from the second surface S2 side of the semiconductor layer 21 into signal charges in the n-type semiconductor region 24, and temporarily holds (accumulates) the photoelectrically converted signal charges at the pn junction between the p-type well region 23 and the n-type semiconductor region 24. That is, the semiconductor layer 21 has the second surface S2 as a light incident surface, and photoelectric conversion regions 22 that photoelectrically convert light incident from the second surface S2 into signal charges in the photoelectric conversion unit 25 are arranged in a matrix.

[0068] 5 , the n-type floating diffusion region FD is provided in the p-type well region 23 on the first surface portion S1 side of the semiconductor layer 21. The n-type floating diffusion region FD overlaps with the n-type semiconductor region 24 of the photoelectric conversion unit 25 in a plan view, and is spaced apart from the n-type semiconductor region 24 of the photoelectric conversion unit 25 in the thickness direction (Z direction) of the semiconductor layer 21. That is, the p-type well region 23 is provided between the n-type floating diffusion region FD and the n-type semiconductor region 24. The n-type floating diffusion region FD is composed of an n-type semiconductor region having a higher impurity concentration than the n-type semiconductor region 24.

[0069] The n-type floating diffusion region FD is covered with an interlayer insulating film 46 provided on the first surface S1 side of the semiconductor layer 21. The n-type floating diffusion region FD is electrically connected to a wiring 48f provided in the wiring layer 48 via a contact electrode 47f provided in the interlayer insulating film 46.

[0070] 5 , the transfer transistor TR is provided on the first surface S1 side of the semiconductor layer 21 (the first surface S1 side of the photoelectric conversion region 22). The transfer transistor TR has a gate electrode 43 provided across the inside and outside of the semiconductor layer 21 on the first surface S1 side of the photoelectric conversion region 22 (semiconductor layer 21), and a gate insulating film 42 provided between the gate electrode 43 and the semiconductor layer 21.

[0071] The transfer transistor TR further includes an n-type semiconductor region 24 that functions as a source region, an n-type floating diffusion region FD that functions as a drain region, and a p-type well region 23 that functions as a channel formation portion. The transfer transistor RT is configured as a vertical type.

[0072] The gate electrode 43 of the transfer transistor TR is covered with an interlayer insulating film 46 provided on the first surface S1 side of the semiconductor layer 21. The gate electrode 43 is electrically connected to a wiring 48t provided in the wiring layer 48 via a contact electrode 47t provided in the interlayer insulating film 46.

[0073] <Shutter Layer> As shown in FIG. 5 , the shutter layer 51 includes a polarizer 54, an insulating film 55, a lower electrode 56, an alignment film 57, a liquid crystal layer 58, an alignment film 59, an upper electrode 60, an insulating film 61, a polarizer 62, and an insulating film 63, which are arranged in this order from the second surface S2 side of the semiconductor layer 21. In this first embodiment, the liquid crystal layer 58 is used as a material layer that can be electrically switched between transmitting and blocking light. The shutter layer 51 also includes a shutter portion 52 shown in FIGS. 4 to 6B , which is arranged on the light incident surface side (second surface S2) of the semiconductor layer 21 and controls the incidence of light on the photoelectric conversion region 22 by transmitting (open state) or blocking (closed state). The shutter layer 51 also includes a shutter block 53 shown in FIG. 6A .

[0074] 7 and 8, the upper electrodes 60 extend in the X direction and are repeatedly arranged at predetermined intervals in the Y direction at an arrangement pitch identical to the arrangement pitch 52Py of the shutter sections 52 in the Y direction. The lower electrodes 56 extend in the Y direction and are repeatedly arranged at predetermined intervals in the Y direction at an arrangement pitch identical to the arrangement pitch 52Px of the shutter sections 52 in the X direction. The intersections of the upper electrodes 60 and the lower electrodes 56 are located at positions overlapping the shutter sections 52 in a plan view. Each of the upper electrodes 60 and the lower electrodes 56 is made of a transparent conductive film such as ITO (Indium Tin Oxide).

[0075] 4, the shutter sections 52 are repeatedly arranged in a two-dimensional plane in the X direction and the Y direction, which are orthogonal to each other. The shutter sections 52 are repeatedly arranged in the X direction at an arrangement pitch 52Px, and repeatedly arranged in the Y direction at an arrangement pitch 52Py.

[0076] As shown in FIGS. 5 and 8 , the shutter section 52 is disposed at the intersection of the upper electrode 60 and the lower electrode 56. The shutter section 52 includes the intersection of the upper electrode 60 and the lower electrode 56. The shutter section 52 controls the incidence of light into the photoelectric conversion region 22 by applying a voltage to the upper electrode 60 and the lower electrode 56, generating an electric field at the intersection of the upper electrode 60 and the lower electrode 56, and driving the liquid crystal molecules of the liquid crystal layer 58 to an open state (transmitting state) or a closed state (blocking state). That is, the shutter layer 51 is configured, for example, using a simple matrix system, although this is not limited thereto. The shutter section 52 is provided at each intersection of the upper electrode 60 and the lower electrode 56, and is arranged in a matrix with these intersections. In the simple matrix system, the desired shutter section 52 is selected using the potential difference between the upper electrode 60 and the lower electrode 56.

[0077] The shutter unit 52 of this first embodiment controls the transmission and blocking of light by generating an electric field to drive the liquid crystal molecules of the liquid crystal layer 58. In other words, the shutter unit 52 controls the incidence of light on the photoelectric conversion region 22 by generating an electric field to drive the liquid crystal molecules of the liquid crystal layer 58. In other words, the shutter unit 52 of this first embodiment is a liquid crystal shutter that controls the transmission and blocking of light by generating an electric field to drive the liquid crystal molecules of the liquid crystal layer 58.

[0078] (Shutter Block) As shown in FIG. 6A , the shutter block 53 includes, as a unit, a plurality of shutter sections 52, each of which partially overlaps with one photoelectric conversion region 22 in a planar view. In this first embodiment, the plurality of shutter sections 52 included in the shutter block 53 may be, but are not limited to, four shutter sections 52 (52a, 52b, 52c, 52d) arranged adjacent to each other in the X direction and the Y direction, which are orthogonal to each other, within the same plane. The shutter blocks 53 are repeatedly arranged in the X direction and the Y direction, forming a shutter block array in the shutter layer 51. That is, the shutter layer 51 has a shutter block array in which a plurality of shutter blocks 53, each of which includes four shutter sections 52 arranged in a 2×2 configuration, are arranged in a matrix.

[0079] As shown in FIG. 4 , each of the four shutter portions 52 included as one unit in one shutter block 53 is shifted in position in the X direction relative to the photoelectric conversion region 22 by an amount equivalent to half the arrangement pitch 22Px of the photoelectric conversion region 22 in the X direction. Furthermore, each of the four shutter portions 52 included as one unit in one shutter block 53 is shifted in position in the Y direction relative to the photoelectric conversion region 22 by an amount equivalent to half the arrangement pitch 22Py of the photoelectric conversion region 22 in the Y direction. That is, each of the four shutter portions 52 included in the shutter block 53 overlaps one photoelectric conversion region 22 evenly in a plan view. Furthermore, as shown in FIGS. 4 and 6A , one photoelectric conversion region 22 includes four overlapping regions 27 (27a, 27b, 27c, 27d) in which portions of the four shutter portions 52 individually overlap one another. Each of the four overlapping regions 27 (27a, 27b, 27c, 27d) functions as a pseudo pixel, and one photoelectric conversion region 22 constitutes four pseudo pixels.

[0080] 6A, four shutter portions 52 (52a, 52b, 52c, 52d) adjacent to each other in a plan view partially overlap with one photoelectric conversion region 22. In other words, as shown in FIG. 6B, four photoelectric conversion regions 22 adjacent to each other partially overlap with one shutter portion 52.

[0081] (Lens Layer) As shown in Fig. 5 , the lens layer 71 is provided with microlenses 72 that collect light (irradiated light) and allow the collected light to efficiently enter the photoelectric conversion region 22. As shown in Figs. 4 to 6B , the microlenses 72 are provided for each of four overlapping regions 27 (27a, 27b, 27c, 27d) in one photoelectric conversion region 22, where portions of the four shutter sections 52 individually overlap. That is, one pixel 3 includes four microlenses 72 that individually overlap with each of the four overlapping regions 27 of the photoelectric conversion region 22 in a planar view.

[0082] <Image Composition> Next, image composition will be described with reference to FIGS. 9A to 12B. FIG. 9A is a plan view schematically showing a first opening pattern of a shutter block. FIG. 9B is a plan view enlarged from a portion of FIG. 9A. FIG. 10A is a plan view schematically showing a second opening pattern of a shutter block. FIG. 10B is a plan view enlarged from a portion of FIG. 10A. FIG. 11A is a plan view schematically showing a third opening pattern of a shutter block. FIG. 11B is a plan view enlarged from a portion of FIG. 11A. FIG. 12A is a plan view schematically showing a fourth opening pattern of a shutter block. FIG. 12B is a plan view enlarged from a portion of FIG. 12A. Note that in FIGS. 9A to 12B, in order to clarify the open / closed state of the shutter unit 52, a dot pattern is applied to the shutter unit 52 in the closed state, and a dot pattern is not applied to the shutter unit 52 in the open state.

[0083] As shown in Figures 9A and 9B, the shutter block 53 of this first embodiment includes four shutter sections 52 (52a, 52b, 52c, 52d) as a unit, each of which partially overlaps with one photoelectric conversion region 22 in a planar view.

[0084] Therefore, in one shutter block 53, as shown in Figures 9A and 9B, a first opening pattern is used in which, of the four shutter sections 52 (52a, 52b, 52c, 52d), shutter section 52a is in an open state and the remaining three shutter sections 52b, 52c, 52d are in a closed state, thereby allowing light to selectively enter the overlapping region 27a (first pseudo pixel) of the photoelectric conversion region 22.

[0085] Furthermore, as shown in Figures 10A and 10B, a second opening pattern in which, of the four shutter sections 52 (52a, 52b, 52c, 52d), shutter section 52b is in an open state and the remaining three shutter sections 52a, 52c, 52d are in a closed state allows light to selectively enter the overlap region 7b (second pseudo pixel) of the photoelectric conversion region 22.

[0086] Furthermore, as shown in Figures 11A and 11B, a third opening pattern in which, of the four shutter sections 52 (52a, 52b, 52c, 52d), shutter section 52c is in an open state and the remaining three shutter sections 52a, 52b, 52d are in a closed state allows light to selectively enter the overlap region 7c (third pseudo pixel) of the photoelectric conversion region 22.

[0087] Furthermore, as shown in Figures 12A and 12B, a fourth opening pattern in which, of the four shutter sections 52 (52a, 52b, 52c, 52d), shutter section 52d is in an open state and the remaining three shutter sections 52a, 52b, 52c are each in a closed state enables selective incidence of light into the overlap region 27d (fourth pseudo pixel) of the photoelectric conversion region 22.

[0088] In other words, this single shutter block 53 can partially open one photoelectric conversion region 22 in four separate steps using four shutter sections 52 (52a, 52b, 52c, 52d), allowing light to be incident on one photoelectric conversion region 22 in four separate steps.

[0089] Then, a first image is taken with the first aperture pattern shown in Figures 9A and 9B, a second image is taken with the second aperture pattern shown in Figures 10A and 10B, a third image is taken with the third aperture pattern shown in Figures 11A and 11B, and a fourth image is taken with the fourth aperture pattern shown in Figures 12A and 12B. In other words, by obtaining images four times by changing the aperture position, an image with four times the resolution as if it were taken with pixels having half the pitch of the actual pixel 3 can be synthesized.

[0090] This makes it possible to achieve high resolution even if the planar size of the shutter portion 52 is the same as the planar size of the pixel 3 (photoelectric conversion region 22). For example, even if the shutter portion 52 has a pitch of 1 μm, it is possible to obtain a resolution similar to that of a pixel 3 with a pitch of 0.5 μm.

[0091] <<Major Effects of First Embodiment>> As described above, the solid-state imaging device 1A according to the first embodiment can achieve high resolution.

[0092] Furthermore, the four shutter sections 52 included as one unit in one shutter block 53 are shifted in position relative to the photoelectric conversion area 22 in each of the X and Y directions by an amount equivalent to half the pitch (1 / 2 pitch) of the arrangement pitch (22Px, 22Py) of the photoelectric conversion area 22, so that the accuracy of each of the four images taken can be made uniform, thereby improving the image quality performance of the composite image.

[0093] It is preferable to use a ferroelectric liquid crystal for the liquid crystal layer 58, which is resistant to the crosstalk phenomenon between adjacent pixels 3.

[0094] Second Embodiment This second embodiment is an example in which the present technology is applied to a solid-state imaging device including a color filter layer 65. Fig. 13 is a longitudinal sectional view schematically showing a longitudinal sectional structure of a solid-state imaging device according to the second embodiment of the present technology.

[0095] As shown in FIG. 13 , the solid-state imaging device 1B according to the second embodiment of the present technology has basically the same configuration as the solid-state imaging device 1A according to the first embodiment described above, but differs in the following configuration.

[0096] That is, the solid-state imaging device 1B according to the second embodiment further includes a color filter layer 65 that transmits light of a specific wavelength. The present technology can also be applied to the solid-state imaging device 1B that includes the color filter layer 65.

[0097] As shown in FIG. 13 , the color filter layer 65 is provided on the side of the shutter layer 51 opposite the semiconductor layer 21. The color filter layer 65 is provided between the shutter layer 51 and the lens layer 71. The color filter layer 65 includes a plurality of filter portions (color filter portions) 66. The color filter layer 65 of the second embodiment includes a filter portion 66 for each shutter portion 52 that transmits light of a specific wavelength, such as, but not limited to, red (R), green (G), or blue (B). The color filter layer 65 also includes separation walls (filter separation walls) 67 between adjacent filter portions 66 to suppress color mixing. The separation walls 67 are preferably made of a low-refractive material having a lower refractive index than the filter portions 66.

[0098] The solid-state imaging device 1B according to the second embodiment also provides the same effects as the solid-state imaging device 1A according to the first embodiment.

[0099] <<Modification of Second Embodiment>> Next, a modification of the second embodiment will be described.

[0100] <Modification 2-1> Fig. 14 is a longitudinal cross-sectional view schematically illustrating Modification 2-1 of the second embodiment of the present technology. As shown in Fig. 14, Modification 2-1 includes separation walls (shutter separation walls) 64 between adjacent shutter sections 52 to suppress uneven transmission. The separation walls 64 are provided in the liquid crystal layer 58 for each shutter section 52 and are configured in an annular planar pattern corresponding to the planar shape of the shutter sections 52. In other words, the separation walls 64 are provided in the liquid crystal layer 58 in a lattice-like planar pattern corresponding to the matrix arrangement of the shutter sections 52. In other words, the liquid crystal layer 58 is divided into each shutter section 52 by the separation walls 64. That is, the shutter sections 52 are divided into a plurality of sub-regions by the separation walls 64. It is preferable to use an insulating material as the material for the separation walls 64.

[0101] In addition, in order to allow the liquid crystal to flow between adjacent shutter sections 52, it is preferable to provide a notch in part of the separation wall 64 or to form a shape that separates the separation wall 64 from either the lower alignment film 57 or the upper alignment film 59.

[0102] In this modification 2-1, the same effects as those of the solid-state imaging device 1B according to the second embodiment described above can be obtained.

[0103] Furthermore, the separation wall 64 can suppress unevenness in transmission between the shutter portions 52 adjacent to each other in a plan view, thereby achieving even higher image quality.

[0104] The separation wall 64 can also be applied to the solid-state imaging device 1A according to the first embodiment described above, which does not include the color filter layer 65 shown in FIG.

[0105] <Modification 2-2> Fig. 15 is a longitudinal cross-sectional view schematically illustrating Modification 2-2 of the second embodiment of the present technology. As shown in Fig. 15, Modification 2-2 includes a separation wall 64 provided within each shutter section 52 to prevent incident light from penetrating into adjacent pixels. The separation wall 64 of Modification 2-2 is provided in the liquid crystal layer 58 in a planar pattern that individually surrounds each of the four overlapping regions 27 included in one photoelectric conversion region 22 in a planar view. In other words, the liquid crystal layer 58 that overlaps with one shutter section 52 in a planar view is divided into each overlapping region 27 by the separation wall 64.

[0106] In this modification 2-2, the same effects as those of the solid-state imaging device 1B according to the second embodiment described above can be obtained.

[0107] Furthermore, in pixels that overlap one shutter section 52 in a planar view and are adjacent to each other, the separation wall 64 can suppress the intrusion of incident light into adjacent pixels (color mixing), thereby further improving the image quality performance of the composite image.

[0108] The configuration in which the separation wall 64 is also disposed inside the shutter section 52 can also be applied to the solid-state imaging device 1A according to the first embodiment described above.

[0109] 16 is a longitudinal cross-sectional view schematically illustrating a modification 2-3 of the second embodiment of the present technology. As shown in FIG. 16, the modification 2-3 is obtained by changing the arrangement of the filter portion 66 of the color filter layer 65 in the modification 2-2.

[0110] That is, in the modified example 2-2 shown in FIG. 15, the filter portion 66 of the color filter layer 65 overlaps with each shutter portion 52 in a plan view.

[0111] 16, in this modified example 2-3, the filter portions 66 of the color filter layer 65 overlap the photoelectric conversion regions 22 for each photoelectric conversion region 22 in a planar view. That is, the filter portions 66 of this modified example 2-3 overlap with a portion of each of the four shutter portions 52 included in one shutter block 53 in a planar view.

[0112] In the case of this modified example 2-3, even when all pixels are in a transmitting state, only light of one color enters each pixel, just like when each pixel is in a quarter transmitting state.

[0113] In this modification 2-3, the same effects as those of the solid-state imaging device 1B according to the second embodiment described above can be obtained.

[0114] The arrangement of the filter section 66 in this modified example 2-3 can also be applied to the second embodiment and modified example 2-1.

[0115] <Modification 2-4> Fig. 17 is a longitudinal cross-sectional view schematically showing Modification 2-4 of the second embodiment of the present technology. As shown in Fig. 17, Modification 2-4 is similar to Modification 2-2 described above, except that the filter portions 66 of the color filter layer 65 are arranged so as to overlap with the overlapping regions 27 of the photoelectric conversion regions 22 in a plan view. Separation walls 67 are provided between the filter portions 66 adjacent to each other.

[0116] In the case of this variant example 2-4, by making the planar size of the overlapping region 27 in the photoelectric conversion region 22 1 / 4 of the planar size of the photoelectric conversion region 22, it is possible to arrange a filter section 66 that is approximately the same size as a micro-pixel (pseudo pixel) that is actually 1 / 4 of the planar size of pixel 3.

[0117] This modification 2-4 also provides the same effects as the solid-state imaging device 1B according to the second embodiment described above.

[0118] The arrangement of the filter section 66 in this modified example 2-4 can also be applied to the second embodiment and modified example 2-1 described above.

[0119] <Modification 2-5> FIG. 18 is a longitudinal sectional view schematically showing Modification 2-5 of the second embodiment of the present technology.

[0120] As shown in FIG. 18, this modification 2-5 is the same as the modification 2-4 except that the position of the color filter layer 65 is changed.

[0121] That is, in the modified example 2-4 shown in FIG. 17, a color filter layer 65 is provided between the shutter layer 51 and the lens layer 71 on the side of the shutter layer 51 opposite to the semiconductor layer 21 side.

[0122] 18, in this modified example 2-5, the color filter layer 65 is provided on the semiconductor layer 21 side of the shutter layer 51. The color filter layer 65 in this modified example 2-3 is provided between the shutter layer 51 and the semiconductor layer 21.

[0123] In this modification 2-5, the same effects as those of the solid-state imaging device 1B according to the second embodiment described above can be obtained.

[0124] The arrangement of the color filter layer 65 in this modified example 2-5 can be applied to the second embodiment described above, and can also be applied to any of the modified examples 2-1 to 2-3 described above.

[0125] Third Embodiment In this third embodiment, a shutter block 53C including two shutter sections 52 will be described. Fig. 19A is a plan view schematically showing a state in which a portion of each of the two shutter sections 52 included in one shutter block 53C overlaps one photoelectric conversion region 22 in a solid-state imaging device 1C according to a third embodiment of the present technology. Fig. 19B is an enlarged plan view of a portion of Fig. 19A .

[0126] A solid-state imaging device 1C according to the third embodiment of the present technology basically has the same configuration as the solid-state imaging device 1A according to the first embodiment described above, but differs in the following configuration.

[0127] 19A and 19B , a solid-state imaging device 1C according to the third embodiment of the present technology includes a shutter block 53C instead of the shutter block 53 shown in FIGS. 4 and 6A of the first embodiment. The shape and arrangement of the microlenses 72 included in the lens layer 71 are different. The other configurations are generally similar to those of the first embodiment.

[0128] 19A and 19B , the shutter block 53C includes, as a unit, a plurality of shutter sections 52, each of which partially overlaps with one photoelectric conversion region 22 in a plan view. In the second embodiment, the plurality of shutter sections 52 included in the shutter block 53C may be, but are not limited to, two shutter sections 52 (52a, 52b) arranged adjacent to each other in the X direction, among the X direction and the Y direction which are orthogonal to each other in the same plane. The shutter blocks 53C are repeatedly arranged in both the X direction and the Y direction, forming a shutter block array in the shutter layer 51. That is, the shutter layer 51 of the third embodiment has a shutter block array in which a plurality of shutter blocks 53C, each of which includes two shutter sections 52 arranged in a 1×2 configuration in the X direction, are arranged in a matrix.

[0129] 19A , each of the two shutter portions 52 included as one unit in one shutter block 53C is shifted in position in the X direction relative to the photoelectric conversion region 22 by an amount equivalent to half the arrangement pitch 22Px of the photoelectric conversion regions 22 in the X direction. That is, each of the two shutter portions 52 included in the shutter block 53C overlaps one photoelectric conversion region 22 evenly in a plan view. One photoelectric conversion region 22 includes two overlapping regions 27 (27a, 27b) in which portions of the two shutter portions 52 individually overlap. Each of the two overlapping regions 27 (27a, 27b) functions as a pseudo pixel, and two pseudo pixels are configured in one photoelectric conversion region 22.

[0130] 19B, two shutter portions 52 (52a, 52b) adjacent to each other in a plan view partially overlap with one photoelectric conversion region 22. In other words, referring to Fig. 19A, two photoelectric conversion regions 22 adjacent to each other in the X direction partially overlap with one shutter portion 52.

[0131] 19B , a microlens 72 in the third embodiment is provided for each of two overlapping regions 27 (27a, 27b) in which portions of two shutter sections 52 individually overlap in one photoelectric conversion region 22. That is, one pixel 3 in the third embodiment includes two microlenses 72 that individually overlap with each of the two overlapping regions 27 of the photoelectric conversion region 22 in a plan view.

[0132] <Image Composition> Next, image composition will be described with reference to Figs. 20A to 21B. Fig. 20A is a plan view schematically showing a first opening pattern of a shutter block. Fig. 20B is a plan view enlarged from a portion of Fig. 20A. Fig. 21A is a plan view schematically showing a second opening pattern of a shutter block. Fig. 21B is a plan view enlarged from a portion of Fig. 21A. Note that in Figs. 20A to 21B, in order to clarify the open / closed state of the shutter section 52, a dot pattern is applied to the shutter section 52 in the closed state, and a dot pattern is not applied to the shutter section 52 in the open state.

[0133] As shown in Figures 20A and 20B, the shutter block 53C of this third embodiment includes two shutter sections 52 (52a, 52b) as a unit, each of which partially overlaps with one photoelectric conversion region 22 in a planar view.

[0134] Therefore, in one shutter block 53C, as shown in Figures 20A and 20B, a first opening pattern is used in which one of the two shutter sections 52 (52a, 52b), 52a, is in an open state and the other shutter section 52b is in a closed state, thereby allowing light to selectively enter the overlapping region 27a (first pseudo pixel) of the photoelectric conversion region 22.

[0135] Furthermore, as shown in Figures 21A and 21B, a second opening pattern in which the other shutter section 52b of the two shutter sections 52 (52a, 52b) is in an open state and the remaining shutter section 52a is in a closed state allows light to selectively enter the overlapping region 7b (second pseudo pixel) of the photoelectric conversion region 22.

[0136] In other words, this single shutter block 53C can partially open one photoelectric conversion region 22 in two separate times using two shutter sections 52 (52a, 52b), allowing light to enter one photoelectric conversion region 22 partially in two separate times.

[0137] Then, a first image is taken with the first aperture pattern shown in Figures 20A and 20B, and a second image is taken with the second aperture pattern shown in Figures 21A and 21B. In other words, by obtaining two images by changing the aperture position, an image with twice the resolution, as if it were taken with pixels having half the pitch of the actual pixel 3, can be synthesized.

[0138] This makes it possible to achieve high resolution even if the planar size of the shutter portion 52 is the same as the planar size of the pixel 3 (photoelectric conversion region 22). For example, even if the shutter portion 52 has a pitch of 1 μm, it is possible to obtain a resolution similar to that of a pixel 3 with a pitch of 0.5 μm.

[0139] The shutter units 52 are opened or closed, for example, for each shutter row in which a plurality of shutter units 52 are lined up in the Y direction.

[0140] <<Major Effects of Third Embodiment>> As described above, the solid-state imaging device 1C according to the third embodiment can achieve higher resolution.

[0141] In addition, the two shutter sections 52 included as one unit in one shutter block 53C are shifted in position relative to the photoelectric conversion area 22 in the X direction by an amount equivalent to half the pitch (1 / 2 pitch) of the arrangement pitch (22Px) of the photoelectric conversion area 22, so that the accuracy of each image taken twice can be made uniform, thereby improving the image quality performance of the composite image.

[0142] In addition, in the third embodiment, it is preferable to use a ferroelectric liquid crystal as the liquid crystal layer 58, which is resistant to the crosstalk phenomenon between adjacent pixels 3.

[0143] The shutter block 53 of the third embodiment can also be applied to the second embodiment described above, and can also be applied to any of the above-described modified examples 2-1 to 2-5.

[0144] <Modification of Third Embodiment> <Modification 3-1> Fig. 22 is a plan view schematically showing a first opening pattern of a shutter block 53C in Modification 3-1 of the third embodiment of the present technology. Fig. 23 is a plan view schematically showing a second opening pattern of a shutter block 53C in Modification 3-1 of the second embodiment of the present technology. Note that in Figs. 22 and 23 , in order to clarify the open / closed state of the shutter section 52, a dot pattern is applied to the shutter section 52 in the closed state, and a dot pattern is not applied to the shutter section 52 in the open state.

[0145] 22 and 23, in this modification 3-1, the open and closed states of the shutters 52 are set in a checkered pattern. That is, in the first opening pattern shown in Fig. 20A and 20B, as shown in Fig. 22, a first checkered pattern is set in which the open shutters 52 and the closed shutters 52 are alternately arranged in the X and Y directions, and in the second opening pattern shown in Fig. 21A and 21B, a second checkered pattern is set in which the open and closed states of the shutters 52 in the first checkered pattern are reversed (the open shutters 52 are set in the closed state, and the closed shutters 52 are set in the open state).

[0146] In this modification 3-1, light can be partially incident on one photoelectric conversion region 22 in two separate incidents, so that high resolution can be achieved, similar to the solid-state imaging device 1C according to the third embodiment described above.

[0147] In this modification 3-2, instead of the shutter block 53C of the third embodiment, ２ It is equipped with the following.

[0148] FIG. 24A is a plan view schematically showing the positional relationship between the shutter portions 52 of the shutter layer 51 and the photoelectric conversion regions 22 in Modification 3-2 of the second embodiment of the present technology.

[0149] FIG. 24B is an enlarged plan view of a portion of FIG. 24A.

[0150] 19A and 19B , the shutter block 53C of the third embodiment described above includes, as a unit, two shutter portions 52 (52a, 52b) arranged adjacent to each other in the X direction as a plurality of shutter portions 52, each of which partially overlaps with one photoelectric conversion region 22 in plan view. The shutter blocks 53C are repeatedly arranged in both the X and Y directions to form a shutter block array in the shutter layer 51.

[0151] In contrast, as shown in FIGS. 24A and 24B, the shutter block 53C of this modified example 3-2 ２ Each shutter block 53C includes two shutter sections 52 (52a, 52b) arranged adjacent to each other in the Y direction as a unit, each of which is a plurality of shutter sections 52 that partially overlap one photoelectric conversion region 22 in a plan view. ２ are repeatedly arranged in both the X and Y directions to form a shutter block array in the shutter layer 51. That is, the shutter layer 51 of this modified example 3-2 has a shutter block array in which a plurality of shutter blocks 53C2 are arranged in a matrix, each unit including two shutter sections 52 arranged in a 1 x 2 configuration in the Y direction.

[0152] As shown in FIG. 24A, one shutter block 53C ２ Each of the two shutter portions 52 included as one unit in shutter block 53C2 is shifted in position in the Y direction relative to the photoelectric conversion region 22 by an amount equivalent to half the Y-direction arrangement pitch 22Py of the photoelectric conversion regions 22. That is, each of the two shutter portions 52 included in shutter block 53C2 overlaps one photoelectric conversion region 22 evenly in a plan view. One photoelectric conversion region 22 includes two overlapping regions 27 (27a, 27b) in which portions of the two shutter portions 52 individually overlap. Each of these two overlapping regions 27 (27a, 27b) functions as a pseudo pixel, and one photoelectric conversion region 22 constitutes two pseudo pixels.

[0153] 24B, two shutter portions 52 (52a, 52b) adjacent to each other in a plan view partially overlap with one photoelectric conversion region 22. In other words, referring to FIG. 24A, two photoelectric conversion regions 22 adjacent to each other in the X direction partially overlap with one shutter portion 52.

[0154] 24B , the microlenses 72 of this modified example 3-2 are provided for each of two overlapping regions 27 (27a, 27b) where portions of two shutter sections 52 individually overlap in one photoelectric conversion region 22. That is, one pixel 3 of this modified example 3-2 includes two microlenses 72 that individually overlap with each of the two overlapping regions 27 of the photoelectric conversion region 22 in a planar view, similar to the third embodiment described above.

[0155] As shown in FIGS. 24A and 24B, the shutter block 53C of this modified example 3-2 ２ includes, as one unit, two shutter portions 52 (52a, 52b) each of which partially overlaps one photoelectric conversion region 22 in a plan view.

[0156] For this reason, although not shown in detail, one shutter block 53C ２ In this case, a first opening pattern in which one of the two shutter sections 52 (52a, 52b) is in an open state, and the other shutter section 52b is in a closed state, allows light to selectively enter the overlapping region 27a (first pseudo pixel) of the photoelectric conversion region 22.

[0157] In addition, a second opening pattern, which sets the other shutter section 52b of the two shutter sections 52 (52a, 52b) in an open state and the remaining shutter section 52a in a closed state, allows light to selectively enter the overlapping region 7b (second pseudo pixel) of the photoelectric conversion region 22.

[0158] That is, this one shutter block 53C ２ Even in this case, two shutter sections 52 (52a, 52b) can be used to partially open one photoelectric conversion region 22 in two separate steps, allowing light to be incident on one photoelectric conversion region 22 in two separate steps.

[0159] Then, a first image taken with the first aperture pattern and a second image taken with the second aperture pattern are obtained, i.e., by obtaining two images by changing the aperture position, an image with double the resolution, as if it were taken with pixels having half the pitch of the actual pixel 3, can be synthesized.

[0160] This makes it possible to achieve high resolution even if the planar size of the shutter portion 52 is the same as the planar size of the pixel 3 (photoelectric conversion region 22). For example, even if the shutter portion 52 has a pitch of 1 μm, it is possible to obtain a resolution similar to that of a pixel 3 with a pitch of 0.5 μm.

[0161] The opening and closing of the shutter units 52 is performed, for example, for each shutter row in which a plurality of shutter units 52 are lined up in the Y direction. As described above, in this modified example 3-2, high resolution can be achieved in the same way as in the third embodiment.

[0162] Also, one shutter block 53C ２ The two shutter sections 52 included as one unit are shifted in position relative to the photoelectric conversion region 22 in the Y direction by an amount equivalent to half the pitch (1 / 2 pitch) of the arrangement pitch (22Py) of the photoelectric conversion region 22, so that, as in the third embodiment described above, the accuracy of each image taken twice can be made uniform, and the image quality performance of the composite image can be improved.

[0163] In this modified example 3-2, the shutter units 52 can be opened or closed for each row of shutters arranged in the Y direction, as in the third embodiment. Also, the shutter units 52 can be opened or closed in a checkerboard pattern, as in the modified example 3-1.

[0164] [Fourth Embodiment] In this fourth embodiment, an active matrix shutter layer 51D will be described. Fig. 25 is a longitudinal sectional view schematically showing a longitudinal sectional structure of a solid-state imaging device according to a fourth embodiment of the present technology. Fig. 26 is a perspective view schematically showing an arrangement of upper electrodes and lower electrodes included in a shutter layer in a solid-state imaging device according to a fourth embodiment of the present technology. Fig. 27 is a plan view schematically showing an arrangement of upper electrodes and lower electrodes included in a shutter layer in a solid-state imaging device according to a fourth embodiment of the present technology. Fig. 28 is a plan view schematically showing a planar pattern of relay electrodes included in an inter-pixel isolation region in a solid-state imaging device according to a fourth embodiment of the present technology.

[0165] A solid-state imaging device 1D according to the fourth embodiment of the present technology has basically the same configuration as the solid-state imaging device 1A according to the first embodiment described above, but differs in the following configuration.

[0166] That is, as shown in Fig. 25 , a solid-state imaging device 1D according to the fourth embodiment of the present technology includes an active matrix shutter layer 51D instead of the simple matrix shutter layer 51 of the first embodiment shown in Fig. 5 . Also, the configuration of the inter-pixel isolation region 31 is different. The other configurations are generally similar to those of the first embodiment.

[0167] <Configuration of Shutter Layer> As shown in Fig. 25, the shutter layer 51D basically has the same configuration as the liquid crystal layer 51 of the first embodiment shown in Fig. 5, and includes an upper electrode 60D and a lower electrode 56D instead of the upper electrode 60 and the lower electrode 56 shown in Fig. 5. That is, the shutter layer 51D has a polarizer 54, an insulating film 55, a lower electrode 56D, an alignment film 57, a liquid crystal layer 58, an alignment film 59, the upper electrode 60D, an insulating film 61, a polarizer 62, and an insulating film 63, which are provided in this order from the second surface S2 side of the semiconductor layer 21.

[0168] 26 and 27 , the upper electrode 60D extends over a wide area across the multiple shutter sections 52 and is shared by the multiple shutter sections. The lower electrode 56D is provided for each shutter section 52. Each of the upper electrode 60D and the lower electrode 56D is made of a transparent conductive film such as ITO (Indium Tin Oxide).

[0169] The shutter section 52 of this fourth embodiment includes an upper electrode 60D and a lower electrode 56D. The shutter section 52 controls the incidence of light on the photoelectric conversion region 22 by applying a voltage to the upper electrode 60D and the lower electrode 56D, generating an electric field between the upper electrode 60D and the lower electrode 56D and driving the liquid crystal molecules in the liquid crystal layer 56 to an open state (transmitting state) or a closed state (blocking state). A voltage is applied to the lower electrode 56D by a drive transistor DR provided for each lower electrode 56. That is, the shutter layer 51D is configured, for example, using an active matrix system, although this is not limited thereto. In the active matrix system, the desired shutter section 52 is selected by a drive transistor DR electrically connected to the lower electrode 56.

[0170] The configurations of the shutter section and shutter block of the fourth embodiment are generally similar to the shutter section 52 and shutter block 53 of the first embodiment, except for the upper electrode 60D and lower electrode 56D.

[0171] 25 , the drive transistor DR is provided in the photoelectric conversion region 22 on the first surface S1 side of the semiconductor layer 21. The drive transistor DR has a gate electrode 43 d provided outside the first surface S1 of the semiconductor layer 21, and a gate insulating film 42 provided between the gate electrode 43 d and the first surface S1 of the semiconductor layer 21. The drive transistor DR is also provided in a surface layer portion on the first surface S1 side of the semiconductor layer 21, and further has a pair of main electrode regions 49 a and 49 b functioning as a source region and a drain region, and a p-type well region 23 functioning as a channel formation region. Each of the pair of main electrode regions 49 a and 49 b is composed of an n-type semiconductor region having a higher impurity concentration than the n-type semiconductor region 24.

[0172] 25 , one main electrode region 49a of the drive transistor DR is electrically connected to a wiring 48m provided in the wiring layer 48 via a contact electrode 47m provided in the interlayer insulating film 46. The other main electrode region 49b of the drive transistor DR is electrically connected to a wiring 48n provided in the wiring layer 48 via a contact electrode 47n provided in the interlayer insulating film 46.

[0173] 25 , the inter-pixel isolation region 31 of the fourth embodiment includes a relay electrode 35. That is, the inter-pixel isolation region 31 of the fourth embodiment includes a dug portion 32 extending in the thickness direction (Z direction) of the semiconductor layer 21, an isolation insulating film 34 provided along the sidewall of the dug portion 32, and a relay electrode 35 provided in the dug portion 32 with the isolation insulating film 34 interposed therebetween.

[0174] 25 , one end of the relay electrode 35 protrudes from the second surface S2 of the semiconductor layer 21 to the shutter layer 51D and is electrically and mechanically connected to the lower electrode 56D. The other end of the relay electrode 35 is electrically and mechanically connected to a contact electrode 47p provided in the interlayer insulating film 46. The contact electrode 47p is then electrically and mechanically connected to a wiring 48n provided in the wiring layer 48. That is, the lower electrode 56D is electrically connected to the main electrode region 49b of the drive transistor DR via the relay electrode 35, the contact electrode 47p, the wiring 48n, and the contact electrode 47n.

[0175] 28 , the relay electrode 35 is provided for each shutter section 52, and is electrically and structurally isolated from adjacent relay electrodes 35. Although not limited to this, the relay electrode 35 has a cross shape in a plan view, and is provided between four photoelectric conversion regions adjacent to each other in each of the X direction and the Y direction.

[0176] The relay electrodes 35 may be configured with individually separated dot patterns. In this case, the relay electrodes 35 are electrically connected to each liquid crystal shutter layer 52.

[0177] As described above, the present technology can be applied to the active matrix shutter layer 51D, and the solid-state imaging device 1D according to the fourth embodiment also provides the same effects as those of the first embodiment.

[0178] The color filter layer 65 of the second embodiment and modified example 2-5 can be applied to the solid-state imaging device 1D of the fourth embodiment. Also, the techniques related to the separation walls 64 and 67 of modified examples 2-1 to 2-4 can be applied to the solid-state imaging device 1D of the fourth embodiment.

[0179] <Modifications of Fourth Embodiment> <Modifications 4-1 and 4-2> Polarizing plates having linear polarizers of "0°", "45°", "90°", and "135°" may be combined as the polarizing plates 54 and 62. The overlapping manner of the polarizing plates 54 and 62 with the shutter section 52 (lower electrode 56D) and the photoelectric conversion region 22 (pixel 3) allows for the same use in transmission every quarter size, but can be used as a different sensor when used in transmission of all pixels.

[0180] Fig. 29 is a plan view schematically showing a modified example 4-1 of the fourth embodiment of the present technology. Fig. 30 is a plan view schematically showing a modified example 4-2 of the fourth embodiment of the present technology. Modified example 4-1 shown in Fig. 29 is a case where the polarizing plates 54, 62 and the shutter section 52 (lower electrode 56D) are overlapped at the same position. In this modified example 4-1, all pixels are transparent and four polarized lights are mixed, so it can be used like a normal sensor.

[0181] 30 shows a modified example 4-2 in which the polarizing plates 54 and 62 and the photoelectric conversion region 22 (pixel 3) overlap at the same position. In this modified example 4-2, all pixels are transparent, and the sensor can be used as a polarization sensor having a linear polarizer in one direction for each pixel.

[0182] <Modifications 4-3 and 4-4> Fig. 31 is a longitudinal cross-sectional view schematically illustrating Modification 4-3 of the fourth embodiment of the present technology. Fig. 32 is a plan view schematically illustrating Modification 4-3 of the fourth embodiment of the present technology. Fig. 33 is a plan view schematically illustrating Modification 4-4 of the fourth embodiment of the present technology. As shown in Fig. 31, in a solid-state imaging device in which the color filter layer 65 and the liquid crystal layer 58 shown in Fig. 16 of Modification 2-3 described above are applied to the fourth embodiment, Modification 4-3 of Fig. 32 is a case in which the polarizing plates 54 and 62 and the shutter section 52 (lower electrode 56D) overlap at the same position, and the filter section 66 and the photoelectric conversion region 22 (pixel 3) overlap at the same position. In the case of Modification 4-3, when all pixels are transmitted, the device can be used as a polarization sensor that separates light into RGB, similar to when light is transmitted in quarter-size increments.

[0183] 31, the polarizing plates 54, 62 and the photoelectric conversion region 22 (pixel 3) overlap at the same position, and the filter section 66 and the shutter section 52 (lower electrode 56D) overlap at the same position. In the case of this variation 4-4, all pixels are transparent, and the device can be used as a polarization sensor that mixes R+G+B light.

[0184] Fifth Embodiment This fifth embodiment is an example of a case where an electrochromic material layer 58E is used as a material layer that can be electrically switched between transmitting and blocking light. Fig. 34 is a longitudinal sectional view schematically showing a longitudinal sectional structure of a solid-state imaging device 1E according to a fifth embodiment of the present technology.

[0185] A solid-state imaging device 1E according to the fifth embodiment of the present technology has basically the same configuration as the solid-state imaging device 1A according to the first embodiment described above, but differs in the following configuration.

[0186] That is, as shown in Fig. 34 , a solid-state imaging device 1E according to the fifth embodiment of the present technology includes an electrochromic material layer 58E instead of the liquid crystal layer 58 of the first embodiment shown in Fig. 5 described above. The solid-state imaging device 1E according to the fifth embodiment of the present technology does not include the polarizing plates 54 and 62, the alignment films 57 and 59, and the insulating film 63 shown in Fig. 5. The other configurations and driving methods are generally similar to those of the first embodiment described above.

[0187] In the fifth embodiment, the shutter unit 52 controls light transmission and light blocking by applying a voltage to change the transmittance of the electrochromic material layer 58E. In other words, the shutter unit 52 of the fifth embodiment controls light incidence on the photoelectric conversion region 22 by applying a voltage to change the transmittance of the electrochromic material layer 58E. In other words, the shutter unit 52 of the fifth embodiment is a chromic shutter unit that controls light transmission and light blocking by applying a voltage to change the transmittance of the electrochromic material layer 58E.

[0188] The solid-state imaging device 1E according to the fifth embodiment also provides the same effects as the solid-state imaging device 1A according to the first embodiment.

[0189] Furthermore, when an electrochromic material layer 58E is used as a material layer that can be electrically switched between transmitting and blocking light, signals can be extracted without polarization, compared to when a liquid crystal layer 58 is used.

[0190] The electrochromic material layer 58E can also be applied to the second to fourth embodiments and their modifications.

[0191] Sixth Embodiment Example of Application to Electronic Devices The present technology (technology related to the present disclosure) can be applied to various electronic devices, such as imaging devices such as digital still cameras and digital video cameras, mobile phones with imaging functions, or other devices with imaging functions.

[0192] FIG. 35 is a diagram showing a schematic configuration of an electronic device (for example, a camera) according to a sixth embodiment of the present technology.

[0193] 35 , the electronic device 100 includes a solid-state imaging device 101, an optical lens 102, a shutter device 103, a drive circuit 104, and a signal processing circuit 105. The electronic device 100 illustrates an embodiment in which the solid-state imaging devices 1A to 1E according to the first to fifth embodiments of the present technology are used as the solid-state imaging device 101 in an electronic device (for example, a camera).

[0194] The optical lens 102 focuses image light (incident light 106) from the subject on the imaging surface of the solid-state imaging device 101. This causes signal charges to accumulate in the solid-state imaging device 101 for a certain period of time. The shutter device 103 controls the light irradiation period and light blocking period of the solid-state imaging device 101. The drive circuit 104 supplies drive signals that control the transfer operation of the solid-state imaging device 101 and the shutter operation of the shutter device 103. The drive signals (timing signals) supplied from the drive circuit 104 cause charge transfer in the solid-state imaging device 101. The signal processing circuit 105 performs various signal processing on signals (pixel signals (image signals)) output from the solid-state imaging device 101. The processed video signals are stored in a storage medium such as a memory or output to a monitor.

[0195] With this configuration, the solid-state imaging device 101 has a high resolution, and therefore the image quality performance of the electronic device 100 of the sixth embodiment can be improved.

[0196] The electronic device 100 to which the solid-state imaging device of the above-described embodiment can be applied is not limited to a camera, but can also be applied to other electronic devices. For example, the solid-state imaging device may be applied to an imaging device such as a camera module for a mobile device such as a mobile phone or a tablet terminal.

[0197] Furthermore, the present technology can be applied to not only the solid-state imaging device as the image sensor described above, but also to photodetection devices in general, including distance measurement sensors called ToF (Time of Flight) sensors that measure distance. A distance measurement sensor emits light toward an object, detects the light reflected from the surface of the object, and calculates the distance to the object based on the time of flight between when the light is emitted and when the reflected light is received. The pixel transistor described above can also be used in this distance measurement sensor.

[0198] The present technology may be configured as follows: (1) A photodetector comprising: a semiconductor layer having a light incident surface portion, and having photoelectric conversion regions arranged in a matrix, which photoelectrically convert light incident from the light incident surface portion side into signal charges; a shutter layer provided on the light incident surface portion side of the semiconductor layer, and having shutter portions arranged in a matrix at the same arrangement pitch as the photoelectric conversion regions, which control light incidence on the photoelectric conversion regions by transmission and blocking; and a shutter block including a plurality of the shutter portions, each of which partially overlaps with one of the photoelectric conversion regions in a planar view. (2) The photodetector according to (1), wherein the plurality of shutter portions included in the shutter block are two of the shutter portions lined up adjacent to each other in either an X direction or a Y direction that are orthogonal to each other in the same plane. (3) The photodetector according to (2), wherein each of the two shutter units is shifted in position relative to the photoelectric conversion region by half the arrangement pitch of the photoelectric conversion region in the one direction. (4) The photodetector according to (1), wherein the plurality of shutter units included in the shutter block are four shutter units arranged adjacent to each other in each of the X direction and the Y direction which are orthogonal to each other in the same plane. (5) The photodetector according to (4), wherein each of the four shutter units is shifted in position relative to the photoelectric conversion region by half the arrangement pitch of the photoelectric conversion region in each of the X direction and the Y direction. (6) The photodetector according to any of (1) to (5), wherein the shutter unit is a liquid crystal shutter unit that controls transmission and blocking of light by generating an electric field to drive liquid crystal molecules in a liquid crystal layer. (7) The photodetector according to any one of (1) to (5), wherein the shutter section is a chromic shutter section that controls light transmission and blocking by changing the transmittance of an electrochromic material layer by applying a voltage. (8) The photodetector according to any one of (1) to (7), wherein a separation wall is provided between the shutter sections adjacent to each other. (9) The photodetector according to (8), wherein the shutter section is divided into a plurality of sub-regions by the separation wall.(10) The photodetector according to any one of claims 1 to 9, further comprising a color filter layer including a plurality of color filter portions and provided on the semiconductor layer side of the shutter layer or on the side opposite to the semiconductor layer side. (11) The photodetector according to any one of claims 1 to 10 above, further comprising a lens layer provided on the side opposite to the semiconductor layer side of the shutter layer and including a microlens provided for each overlapping region where one photoelectric conversion region and a portion of one of the shutter portions overlap. (12) An electronic device comprising: a photodetector; an optical lens that focuses image light from a subject on an imaging surface of the photodetector; and a signal processing circuit that processes a signal output from the photodetector, wherein the photodetector comprises: a semiconductor layer having a light incident surface and having photoelectric conversion regions arranged in a matrix that photoelectrically convert light incident from the light incident surface side into signal charges; a shutter layer provided on the light incident surface side of the semiconductor layer and having shutter sections that control the incidence of light on the photoelectric conversion regions by transmission and blocking, and that are arranged in a matrix at the same arrangement pitch as the photoelectric conversion regions; and a shutter block including a plurality of the shutter sections, each of which has a portion that overlaps with one of the photoelectric conversion regions in a planar view.

[0199] The scope of the present technology is not limited to the exemplary embodiments shown and described, but includes all embodiments that achieve equivalent effects to those intended by the present technology. Furthermore, the scope of the present technology is not limited to the combination of the features of the invention defined by the claims, but may be defined by any desired combination of specific features among all the respective disclosed features.

[0200] DESCRIPTION OF SYMBOLS 1A, 1B, 1C, 1D, 1E...Solid-state imaging device 2...Semiconductor chip 2A...Pixel array section 2B...Peripheral section 3...Pixel 4...Vertical drive circuit 5...Column signal processing circuit 6...Horizontal drive circuit 7...Output circuit 8...Control circuit 10...Pixel drive line 11...Vertical signal line 12...Horizontal signal line 13...Logic circuit 14...Bonding pad 15...Pixel circuit (readout circuit) 21...Semiconductor layer 22...Photoelectric conversion region 22Px, 22Py...Array pitch 23...P-type well region (p-type semiconductor region) 24...N-type semiconductor region 25...Photoelectric conversion section (PD) 27, 27a, 27b, 27c, 27d...Overlapping region (pseudo pixel) 31...Inter-pixel isolation region 32...Dug-in portion 34...Isolation insulating film 35...Relay electrode 42...Gate insulating film 43, 43d...Gate electrode 46... Interlayer insulating film 47f, 47m, 47n, 47p, 47t... Contact electrodes (conductive plugs) 48... Wiring layer 48f, 48m, 48n, 48p, 48t... Wirings 51, 51D... Shutter layers 52, 52a, 52b, 52c, 52d... Shutter portions 52Px, 52Py... Arrangement pitch 53, 53C ２ . . . shutter block 54 polarizer 55 insulating film 56, 56D lower electrode 57 alignment film 58 liquid crystal layer 58E electrochromic material layer 59 alignment film 60, 60D upper electrode 61 insulating film 62 polarizer 63 insulating film 64 separation wall (shutter separation wall) 65 color filter layer 66 filter portion 67 separation wall (filter separation wall) 71 lens layer 72 microlens DR drive transistor

Claims

1. A photodetection device comprising: a semiconductor layer having a light incident surface, and in which photoelectric conversion regions that photoelectrically convert light incident from the light incident surface side into signal charges are arranged in a matrix; a shutter layer provided on the light incident surface side of the semiconductor layer, and in which shutter sections that control the incidence of light to the photoelectric conversion regions by transmission and blocking are arranged in a matrix at the same arrangement pitch as the photoelectric conversion regions; and a shutter block including a plurality of the shutter sections, each of which has a portion overlapping with one of the photoelectric conversion regions in a planar view.

2. The optical detection device according to claim 1, wherein the plurality of shutter sections included in the shutter block are two of the shutter sections arranged adjacent to each other in either the X direction or the Y direction which are perpendicular to each other within the same plane.

3. The optical detection device according to claim 2, wherein each of the two shutter sections is shifted in position relative to the photoelectric conversion regions by half the arrangement pitch of the photoelectric conversion regions in the one direction.

4. The optical detection device according to claim 1, wherein the plurality of shutter sections included in the shutter block are four shutter sections arranged adjacent to each other in each of the X direction and the Y direction which are perpendicular to each other within the same plane.

5. The optical detection device according to claim 4, wherein each of the four shutter elements is shifted in position relative to the photoelectric conversion regions by half the arrangement pitch of the photoelectric conversion regions in each of the X and Y directions.

6. The photodetector according to claim 1, wherein the shutter section is a liquid crystal shutter section which controls the transmission and blocking of light by generating an electric field to drive liquid crystal molecules in a liquid crystal layer.

7. The photodetector according to claim 1, wherein said shutter section is an electrochromic shutter section which controls the transmission and blocking of light by changing the transmittance of an electrochromic material layer by applying a voltage thereto.

8. The light detection device according to claim 1, wherein a separation wall is provided between adjacent shutter portions.

9. The light detection device according to claim 8, wherein the shutter portion is divided into a plurality of sub-regions by the separation wall.

10. The light detection device according to claim 1, further comprising a color filter layer including a plurality of color filter portions and provided on the semiconductor layer side of the shutter layer or on the side opposite to the semiconductor layer side.

11. The photodetection device of claim 1, further comprising a lens layer provided on the opposite side of the shutter layer from the semiconductor layer side, the lens layer including a microlens provided for each overlap region where one photoelectric conversion region overlaps with a portion of one of the shutter sections.

12. An electronic device comprising: a photodetector; an optical lens that focuses image light from a subject on an imaging surface of the photodetector; and a signal processing circuit that performs signal processing on a signal output from the photodetector, wherein the photodetector comprises: a semiconductor layer having a light incident surface and having photoelectric conversion regions arranged in a matrix that photoelectrically converts light incident from the light incident surface side into a signal charge; a shutter layer provided on the light incident surface side of the semiconductor layer and having shutter sections arranged in a matrix at the same arrangement pitch as the photoelectric conversion regions that control the incidence of light on the photoelectric conversion regions by transmission and blocking; and a shutter block including a plurality of the shutter sections, each of which has a portion that overlaps with one of the photoelectric conversion regions in a planar view.

Images